Unified Coverage Report :: Module :: alert_handler_accu

Module : alert_handler_accu

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[1].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[2].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[3].u_accu	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_classes[0].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[1].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[2].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[3].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

Line Coverage for Module : alert_handler_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	55	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
55	1	1

---

Cond Coverage for Module : alert_handler_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T6
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T45,T196,T197
1	1	Covered	T1,T2,T3

 LINE       55
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T6

---

Assert Coverage for Module : alert_handler_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	2147483647	16355	0	0
DisabledNoTrigBkwd_A	2147483647	882074	0	0
DisabledNoTrigFwd_A	2147483647	1731865698	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	16355	0	0
T32	727196	0	0	0
T45	0	964	0	0
T67	326231	0	0	0
T87	704551	0	0	0
T113	484898	0	0	0
T196	1206	358	0	0
T197	2678	592	0	0
T198	0	343	0	0
T199	0	1025	0	0
T200	0	214	0	0
T201	4740	1219	0	0
T202	0	899	0	0
T203	0	531	0	0
T204	0	753	0	0
T205	0	1701	0	0
T206	0	1294	0	0
T207	0	929	0	0
T208	0	611	0	0
T209	0	287	0	0
T210	0	490	0	0
T211	0	1034	0	0
T212	0	495	0	0
T213	0	1465	0	0
T214	0	1151	0	0
T215	157746	0	0	0
T216	1402574	0	0	0
T217	19934	0	0	0
T218	182550	0	0	0
T219	451356	0	0	0
T220	136508	0	0	0
T221	5043	0	0	0
T222	180249	0	0	0
T223	17068	0	0	0
T224	27926	0	0	0
T225	20313	0	0	0
T226	396439	0	0	0
T227	361464	0	0	0
T228	69680	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	882074	0	0
T2	49644	45	0	0
T3	581382	848	0	0
T4	2113608	2051	0	0
T5	685356	1241	0	0
T6	277212	14	0	0
T7	2982432	2265	0	0
T8	630048	0	0	0
T9	3919132	0	0	0
T10	0	7	0	0
T15	3045220	22511	0	0
T16	0	12103	0	0
T18	601600	101	0	0
T19	437514	172	0	0
T20	0	5051	0	0
T50	0	51	0	0
T51	0	58	0	0
T52	0	11	0	0
T53	0	486	0	0
T54	0	851	0	0
T56	149786	0	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1731865698	0	0
T1	70000	62845	0	0
T2	198576	151236	0	0
T3	1162764	872546	0	0
T4	2113608	603855	0	0
T5	685356	525200	0	0
T6	277212	177859	0	0
T7	2982432	1947148	0	0
T8	630048	475826	0	0
T15	3045220	1512441	0	0
T18	601600	537991	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	55	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
55	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Covered	T1,T3,T6
1	1	Covered	T2,T3,T6

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T197,T198,T202
1	1	Covered	T2,T3,T6

 LINE       55
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T6

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	774255058	3050	0	0
DisabledNoTrigBkwd_A	774255058	243849	0	0
DisabledNoTrigFwd_A	774255058	388050195	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	774255058	3050	0	0
T32	363598	0	0	0
T197	1339	592	0	0
T198	0	343	0	0
T202	0	899	0	0
T207	0	929	0	0
T209	0	287	0	0
T215	78873	0	0	0
T216	701287	0	0	0
T217	9967	0	0	0
T218	91275	0	0	0
T219	225678	0	0	0
T220	136508	0	0	0
T221	5043	0	0	0
T222	180249	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	774255058	243849	0	0
T2	49644	45	0	0
T3	290691	845	0	0
T4	528402	13	0	0
T5	171339	0	0	0
T6	69303	3	0	0
T7	745608	302	0	0
T8	157512	0	0	0
T9	979783	0	0	0
T15	761305	1757	0	0
T16	0	143	0	0
T18	150400	89	0	0
T19	0	172	0	0
T20	0	4311	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	774255058	388050195	0	0
T1	17500	17409	0	0
T2	49644	2520	0	0
T3	290691	8501	0	0
T4	528402	519605	0	0
T5	171339	170442	0	0
T6	69303	44941	0	0
T7	745608	610788	0	0
T8	157512	157504	0	0
T15	761305	485555	0	0
T18	150400	141692	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	55	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
55	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T3,T6,T4
1	0	Covered	T1,T3,T6
1	1	Covered	T3,T6,T4

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T196,T199,T200
1	1	Covered	T3,T6,T4

 LINE       55
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T18
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T6,T5

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	774255058	3121	0	0
DisabledNoTrigBkwd_A	774255058	214825	0	0
DisabledNoTrigFwd_A	774255058	452883843	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	774255058	3121	0	0
T32	363598	0	0	0
T87	704551	0	0	0
T113	484898	0	0	0
T196	1206	358	0	0
T197	1339	0	0	0
T199	0	1025	0	0
T200	0	214	0	0
T210	0	490	0	0
T211	0	1034	0	0
T215	78873	0	0	0
T216	701287	0	0	0
T217	9967	0	0	0
T218	91275	0	0	0
T219	225678	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	774255058	214825	0	0
T3	290691	3	0	0
T4	528402	0	0	0
T5	171339	3	0	0
T6	69303	1	0	0
T7	745608	244	0	0
T8	157512	0	0	0
T9	979783	0	0	0
T10	0	2	0	0
T15	761305	1691	0	0
T16	0	3070	0	0
T18	150400	0	0	0
T19	145838	0	0	0
T20	0	285	0	0
T50	0	29	0	0
T51	0	37	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	774255058	452883843	0	0
T1	17500	17409	0	0
T2	49644	49572	0	0
T3	290691	284113	0	0
T4	528402	15326	0	0
T5	171339	170442	0	0
T6	69303	61931	0	0
T7	745608	601481	0	0
T8	157512	3314	0	0
T15	761305	453286	0	0
T18	150400	125415	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	55	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
55	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T3,T6
1	1	Covered	T1,T3,T6

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T201,T203,T204
1	1	Covered	T1,T3,T6

 LINE       55
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T6,T4,T18

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	774255058	4579	0	0
DisabledNoTrigBkwd_A	774255058	200815	0	0
DisabledNoTrigFwd_A	774255058	453502636	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	774255058	4579	0	0
T67	326231	0	0	0
T201	4740	1219	0	0
T203	0	531	0	0
T204	0	753	0	0
T208	0	611	0	0
T213	0	1465	0	0
T223	17068	0	0	0
T224	27926	0	0	0
T225	20313	0	0	0
T226	396439	0	0	0
T227	361464	0	0	0
T228	69680	0	0	0
T229	66189	0	0	0
T230	70932	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	774255058	200815	0	0
T4	528402	444	0	0
T5	171339	1238	0	0
T6	69303	5	0	0
T7	745608	1300	0	0
T8	157512	0	0	0
T9	979783	0	0	0
T10	0	5	0	0
T15	761305	3070	0	0
T16	0	2453	0	0
T18	150400	7	0	0
T19	145838	0	0	0
T20	0	455	0	0
T52	0	11	0	0
T56	74893	0	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	774255058	453502636	0	0
T1	17500	10618	0	0
T2	49644	49572	0	0
T3	290691	289248	0	0
T4	528402	58588	0	0
T5	171339	12986	0	0
T6	69303	32162	0	0
T7	745608	200130	0	0
T8	157512	157504	0	0
T15	761305	307391	0	0
T18	150400	144704	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	55	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
55	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T4,T18
1	0	Covered	T1,T3,T6
1	1	Covered	T6,T4,T18

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T45,T205,T206
1	1	Covered	T6,T4,T18

 LINE       55
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T18,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T6,T4,T18

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	774255058	5605	0	0
DisabledNoTrigBkwd_A	774255058	222585	0	0
DisabledNoTrigFwd_A	774255058	437429024	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	774255058	5605	0	0
T45	3651	964	0	0
T46	498399	0	0	0
T47	8806	0	0	0
T48	899739	0	0	0
T49	150874	0	0	0
T205	0	1701	0	0
T206	0	1294	0	0
T212	0	495	0	0
T214	0	1151	0	0
T231	37937	0	0	0
T232	11876	0	0	0
T233	226550	0	0	0
T234	20495	0	0	0
T235	27361	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	774255058	222585	0	0
T4	528402	1594	0	0
T5	171339	0	0	0
T6	69303	5	0	0
T7	745608	419	0	0
T8	157512	0	0	0
T9	979783	0	0	0
T15	761305	15993	0	0
T16	0	6437	0	0
T18	150400	5	0	0
T19	145838	0	0	0
T50	0	22	0	0
T51	0	21	0	0
T53	0	486	0	0
T54	0	851	0	0
T56	74893	0	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	774255058	437429024	0	0
T1	17500	17409	0	0
T2	49644	49572	0	0
T3	290691	290684	0	0
T4	528402	10336	0	0
T5	171339	171330	0	0
T6	69303	38825	0	0
T7	745608	534749	0	0
T8	157512	157504	0	0
T15	761305	266209	0	0
T18	150400	126180	0	0