Unified Coverage Report :: Module :: alert_handler_esc_timer

Module : alert_handler_esc_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.30	100.00	91.49		70.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[1].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[2].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[3].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[0].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00

---

Module Instance : tb.dut.gen_classes[1].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[2].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[3].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[0].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.26	100.00	95.56	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	79	1	1	100.00
ALWAYS	128	89	89	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
ALWAYS	299	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
79	1	1
128	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
138	1	1
142	1	1
143	1	1
145	1	1
146	1	1
147	1	1
148	1	1
151	1	1
152	1	1
153	1	1
			MISSING_ELSE
163	1	1
165	1	1
166	1	1
167	1	1
168	1	1
169	1	1
172	1	1
173	1	1
175	1	1
176	1	1
181	1	1
182	1	1
183	1	1
184	1	1
185	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
198	1	1
199	1	1
200	1	1
201	1	1
202	1	1
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
222	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
			MISSING_ELSE
232	1	1
233	1	1
234	1	1
235	1	1
236	1	1
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
			MISSING_ELSE
252	1	1
253	1	1
254	1	1
255	1	1
			MISSING_ELSE
262	1	1
263	1	1
277	1	1
278	1	1
279	1	1
			MISSING_ELSE
286	4	4
289	4	4
299	3	3

---

Cond Coverage for Module : alert_handler_esc_timer

	Total	Covered	Percent
Conditions	47	43	91.49
Logical	47	43	91.49
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       145
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Covered	T30
1	1	1	Covered	T2,T3,T6

 LINE       151
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T6,T18
1	0	1	Covered	T3,T4,T18
1	1	0	Covered	T1,T6,T18
1	1	1	Covered	T1,T6,T18

 LINE       165
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T18
0	1	Covered	T7,T15,T20
1	0	Covered	T6,T18,T7

 LINE       165
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T6,T18
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T6,T18,T7

 LINE       165
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T18
1	0	Not Covered
1	1	Covered	T7,T15,T20

 LINE       185
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T6
1	Covered	T3,T6,T18

 LINE       202
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T6
1	Covered	T6,T18,T7

 LINE       219
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T6
1	Covered	T3,T6,T4

 LINE       236
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T3,T6,T4
1	Covered	T2,T4,T18

 LINE       277
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13

 LINE       289
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T3,T6

 LINE       289
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T6,T4

 LINE       289
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T3,T6

 LINE       289
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T3,T6,T4

---

FSM Coverage for Module : alert_handler_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	20	14	70.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	278	Covered	T14
IdleSt	175	Covered	T14
Phase0St	146	Covered	T14
Phase1St	192	Covered	T14
Phase2St	209	Covered	T14
Phase3St	227	Covered	T14
TerminalSt	243	Covered	T14
TimeoutSt	153	Covered	T14

transitions	Line No.	Covered	Tests
IdleSt->FsmErrorSt	278	Covered	T14
IdleSt->Phase0St	146	Covered	T14
IdleSt->TimeoutSt	153	Covered	T14
Phase0St->FsmErrorSt	278	Not Covered
Phase0St->IdleSt	188	Covered	T14
Phase0St->Phase1St	192	Covered	T14
Phase1St->FsmErrorSt	278	Not Covered
Phase1St->IdleSt	205	Covered	T14
Phase1St->Phase2St	209	Covered	T14
Phase2St->FsmErrorSt	278	Not Covered
Phase2St->IdleSt	223	Covered	T14
Phase2St->Phase3St	227	Covered	T14
Phase3St->FsmErrorSt	278	Not Covered
Phase3St->IdleSt	239	Covered	T14
Phase3St->TerminalSt	243	Covered	T14
TerminalSt->FsmErrorSt	278	Not Covered
TerminalSt->IdleSt	255	Covered	T14
TimeoutSt->FsmErrorSt	278	Not Covered
TimeoutSt->IdleSt	175	Covered	T14
TimeoutSt->Phase0St	166	Covered	T14

---

Branch Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	138	22	22	100.00
IF	277	2	2	100.00
IF	299	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	case (state_q)
-2-:	145	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	151	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	165	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	172	if (timeout_en_i)
-6-:	187	if (clr_i)
-7-:	191	if (cnt_ge)
-8-:	204	if (clr_i)
-9-:	208	if (cnt_ge)
-10-:	222	if (clr_i)
-11-:	226	if (cnt_ge)
-12-:	238	if (clr_i)
-13-:	242	if (cnt_ge)
-14-:	254	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T6
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T6,T18
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T6,T18,T7
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T6,T18
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T18,T5
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T20,T31,T32
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T3,T6
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T3,T6
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T33,T34,T35
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T3,T6
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T3,T6
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T36,T37,T38
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T2,T3,T6
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T3,T6
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T18,T33,T36
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T2,T3,T6
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T3,T6
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T18,T7,T15
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T3,T6
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	277	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	299	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	2147483647	870	0	0
CheckAccumTrig0_A	2147483647	2540	0	0
CheckAccumTrig1_A	2147483647	130	0	0
CheckClr_A	2147483647	1134	0	0
CheckEn_A	2147483647	1332765703	0	0
CheckPhase0_A	2147483647	2928	0	0
CheckPhase1_A	2147483647	2889	0	0
CheckPhase2_A	2147483647	2839	0	0
CheckPhase3_A	2147483647	2783	0	0
CheckTimeout0_A	2147483647	8000	0	0
CheckTimeoutSt1_A	2147483647	801021	0	0
CheckTimeoutSt2_A	2147483647	7583	0	0
CheckTimeoutStTrig_A	2147483647	287	0	0
ErrorStAllEscAsserted_A	2147483647	5120	0	0
ErrorStIsTerminal_A	2147483647	4280	0	0
u_state_regs_A	2147483647	2147483647	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	870	0	0
T11	84784	126	0	0
T12	0	248	0	0
T13	0	131	0	0
T39	0	118	0	0
T40	0	247	0	0
T41	390276	0	0	0
T42	112112	0	0	0
T43	464952	0	0	0
T44	1994600	0	0	0
T45	14604	0	0	0
T46	1993596	0	0	0
T47	35224	0	0	0
T48	3598956	0	0	0
T49	603496	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2540	0	0
T2	49644	1	0	0
T3	581382	2	0	0
T4	2113608	3	0	0
T5	685356	2	0	0
T6	207909	3	0	0
T7	2982432	20	0	0
T8	630048	0	0	0
T9	3919132	0	0	0
T10	0	2	0	0
T15	3045220	23	0	0
T16	179021	22	0	0
T18	601600	8	0	0
T19	437514	1	0	0
T20	0	14	0	0
T50	0	3	0	0
T51	0	5	0	0
T52	0	1	0	0
T53	0	3	0	0
T54	0	2	0	0
T55	0	1	0	0
T56	149786	0	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	130	0	0
T4	528402	0	0	0
T5	342678	0	0	0
T6	69303	1	0	0
T7	2236824	3	0	0
T8	472536	0	0	0
T9	2939349	0	0	0
T10	110271	0	0	0
T15	2283915	0	0	0
T16	358042	1	0	0
T17	12165	0	0	0
T18	300800	2	0	0
T19	437514	0	0	0
T20	1559866	2	0	0
T33	0	2	0	0
T35	0	1	0	0
T36	0	2	0	0
T50	224550	0	0	0
T51	165184	0	0	0
T56	224679	0	0	0
T57	0	1	0	0
T58	0	1	0	0
T59	0	1	0	0
T60	0	2	0	0
T61	0	2	0	0
T62	0	1	0	0
T63	333182	2	0	0
T64	0	1	0	0
T65	0	1	0	0
T66	0	1	0	0
T67	0	2	0	0
T68	0	1	0	0
T69	0	1	0	0
T70	8464	0	0	0
T71	552330	0	0	0
T72	112917	0	0	0
T73	430165	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1134	0	0
T5	342678	0	0	0
T7	2982432	9	0	0
T8	630048	0	0	0
T9	3919132	0	0	0
T15	3045220	11	0	0
T16	716084	8	0	0
T18	300800	5	0	0
T19	583352	0	0	0
T20	1559866	8	0	0
T31	0	3	0	0
T33	0	7	0	0
T36	0	18	0	0
T50	299400	4	0	0
T51	165184	3	0	0
T53	0	1	0	0
T54	0	4	0	0
T56	299572	0	0	0
T58	0	2	0	0
T60	0	1	0	0
T74	0	1	0	0
T75	0	1	0	0
T76	0	4	0	0
T77	0	1	0	0
T78	0	1	0	0
T79	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1332765703	0	0
T1	70000	62841	0	0
T2	198576	151233	0	0
T3	1162764	614463	0	0
T4	2113608	92826	0	0
T5	685356	356884	0	0
T6	277212	43008	0	0
T7	2982432	650868	0	0
T8	630048	475826	0	0
T15	3045220	1786523	0	0
T18	601600	532719	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2928	0	0
T2	49644	1	0	0
T3	581382	2	0	0
T4	2113608	3	0	0
T5	685356	2	0	0
T6	277212	4	0	0
T7	2982432	24	0	0
T8	630048	0	0	0
T9	3919132	0	0	0
T10	0	2	0	0
T15	3045220	24	0	0
T16	0	23	0	0
T18	601600	11	0	0
T19	437514	1	0	0
T20	0	22	0	0
T50	0	6	0	0
T51	0	5	0	0
T52	0	1	0	0
T56	149786	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2889	0	0
T2	49644	1	0	0
T3	581382	2	0	0
T4	2113608	3	0	0
T5	685356	2	0	0
T6	277212	4	0	0
T7	2982432	23	0	0
T8	630048	0	0	0
T9	3919132	0	0	0
T10	0	2	0	0
T15	3045220	24	0	0
T16	0	23	0	0
T18	601600	10	0	0
T19	437514	1	0	0
T20	0	22	0	0
T50	0	6	0	0
T51	0	5	0	0
T52	0	1	0	0
T56	149786	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2839	0	0
T2	49644	1	0	0
T3	581382	2	0	0
T4	2113608	3	0	0
T5	685356	2	0	0
T6	277212	4	0	0
T7	2982432	23	0	0
T8	630048	0	0	0
T9	3919132	0	0	0
T10	0	2	0	0
T15	3045220	24	0	0
T16	0	23	0	0
T18	601600	9	0	0
T19	437514	1	0	0
T20	0	22	0	0
T50	0	6	0	0
T51	0	5	0	0
T52	0	1	0	0
T56	149786	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2783	0	0
T2	49644	1	0	0
T3	581382	2	0	0
T4	2113608	3	0	0
T5	685356	2	0	0
T6	277212	4	0	0
T7	2982432	23	0	0
T8	630048	0	0	0
T9	3919132	0	0	0
T10	0	2	0	0
T15	3045220	24	0	0
T16	0	23	0	0
T18	601600	8	0	0
T19	437514	1	0	0
T20	0	22	0	0
T50	0	6	0	0
T51	0	5	0	0
T52	0	1	0	0
T56	149786	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8000	0	0
T1	17500	1	0	0
T2	49644	0	0	0
T3	290691	0	0	0
T4	528402	0	0	0
T5	685356	3	0	0
T6	69303	1	0	0
T7	2982432	84	0	0
T8	630048	0	0	0
T9	2939349	0	0	0
T15	3045220	4	0	0
T16	537063	34	0	0
T18	601600	742	0	0
T19	437514	1	0	0
T20	0	28	0	0
T33	0	3	0	0
T36	0	414	0	0
T38	0	4	0	0
T50	224550	6	0	0
T56	224679	9	0	0
T57	0	1	0	0
T59	0	1	0	0
T60	0	86	0	0
T76	0	3	0	0
T79	0	6	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	801021	0	0
T1	17500	160	0	0
T2	49644	0	0	0
T3	290691	0	0	0
T4	528402	0	0	0
T5	685356	235	0	0
T6	69303	1	0	0
T7	2982432	9980	0	0
T8	630048	0	0	0
T9	2939349	0	0	0
T15	3045220	418	0	0
T16	537063	4844	0	0
T18	601600	41709	0	0
T19	437514	19	0	0
T20	0	5471	0	0
T33	0	95	0	0
T36	0	25478	0	0
T38	0	280	0	0
T50	224550	609	0	0
T56	224679	2328	0	0
T57	0	3	0	0
T59	0	516	0	0
T60	0	6906	0	0
T76	0	209	0	0
T79	0	993	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7583	0	0
T1	17500	1	0	0
T2	49644	0	0	0
T3	290691	0	0	0
T4	528402	0	0	0
T5	685356	3	0	0
T6	69303	0	0	0
T7	2982432	80	0	0
T8	630048	0	0	0
T9	2939349	0	0	0
T15	3045220	3	0	0
T16	537063	33	0	0
T18	451200	739	0	0
T19	437514	1	0	0
T20	779933	19	0	0
T36	0	563	0	0
T38	0	4	0	0
T50	224550	3	0	0
T56	224679	8	0	0
T59	0	1	0	0
T60	0	85	0	0
T76	0	3	0	0
T77	0	1	0	0
T79	0	18	0	0
T80	0	10	0	0
T81	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	287	0	0
T5	171339	0	0	0
T7	1491216	1	0	0
T8	472536	0	0	0
T9	2939349	0	0	0
T10	220542	0	0	0
T15	2283915	1	0	0
T16	537063	0	0	0
T17	12165	0	0	0
T18	150400	0	0	0
T19	437514	0	0	0
T20	2339799	6	0	0
T32	0	1	0	0
T33	281829	1	0	0
T35	0	1	0	0
T36	416985	2	0	0
T46	0	3	0	0
T50	224550	0	0	0
T51	247776	0	0	0
T56	224679	0	0	0
T58	55494	0	0	0
T59	25550	0	0	0
T60	0	2	0	0
T62	0	2	0	0
T63	0	2	0	0
T65	0	5	0	0
T70	8464	0	0	0
T71	0	1	0	0
T75	176017	0	0	0
T79	0	3	0	0
T82	0	1	0	0
T83	0	1	0	0
T84	0	1	0	0
T85	0	5	0	0
T86	0	1	0	0
T87	0	2	0	0
T88	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5120	0	0
T11	84784	765	0	0
T12	0	1418	0	0
T13	0	714	0	0
T39	0	744	0	0
T40	0	1479	0	0
T41	390276	0	0	0
T42	112112	0	0	0
T43	464952	0	0	0
T44	1994600	0	0	0
T45	14604	0	0	0
T46	1993596	0	0	0
T47	35224	0	0	0
T48	3598956	0	0	0
T49	603496	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4280	0	0
T11	84784	645	0	0
T12	0	1178	0	0
T13	0	594	0	0
T39	0	624	0	0
T40	0	1239	0	0
T41	390276	0	0	0
T42	112112	0	0	0
T43	464952	0	0	0
T44	1994600	0	0	0
T45	14604	0	0	0
T46	1993596	0	0	0
T47	35224	0	0	0
T48	3598956	0	0	0
T49	603496	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	70000	69636	0	0
T2	198576	198288	0	0
T3	1162764	1162736	0	0
T4	2113608	2113580	0	0
T5	685356	685320	0	0
T6	277212	276908	0	0
T7	2982432	2982384	0	0
T8	630048	630016	0	0
T15	3045220	3045188	0	0
T18	601600	601388	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	79	1	1	100.00
ALWAYS	128	89	89	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
ALWAYS	299	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
79	1	1
128	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
138	1	1
142	1	1
143	1	1
145	1	1
146	1	1
147	1	1
148	1	1
151	1	1
152	1	1
153	1	1
			MISSING_ELSE
163	1	1
165	1	1
166	1	1
167	1	1
168	1	1
169	1	1
172	1	1
173	1	1
175	1	1
176	1	1
181	1	1
182	1	1
183	1	1
184	1	1
185	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
198	1	1
199	1	1
200	1	1
201	1	1
202	1	1
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
222	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
			MISSING_ELSE
232	1	1
233	1	1
234	1	1
235	1	1
236	1	1
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
			MISSING_ELSE
252	1	1
253	1	1
254	1	1
255	1	1
			MISSING_ELSE
262	1	1
263	1	1
277	1	1
278	1	1
279	1	1
			MISSING_ELSE
286	4	4
289	4	4
299	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T3,T6,T18
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T3,T6,T18
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T6,T18

 LINE       145
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T3,T6,T4
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T3,T6,T5

 LINE       151
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T6,T18,T5
1	0	1	Covered	T7,T15,T8
1	1	0	Covered	T18,T7,T15
1	1	1	Covered	T18,T7,T15

 LINE       165
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T18,T7,T15
0	1	Covered	T15,T36,T79
1	0	Covered	T7,T16,T36

 LINE       165
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T18,T7,T15
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T7,T16,T36

 LINE       165
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T18,T7,T15
1	0	Not Covered
1	1	Covered	T15,T36,T79

 LINE       185
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T3,T5,T7
1	Covered	T6,T7,T15

 LINE       202
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T3,T6,T5
1	Covered	T54,T36,T89

 LINE       219
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T6,T5,T7
1	Covered	T3,T7,T15

 LINE       236
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T3,T6,T7
1	Covered	T5,T7,T16

 LINE       277
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13

 LINE       289
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T3,T15,T16

 LINE       289
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T7,T15,T16

 LINE       289
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T6,T7,T15

 LINE       289
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T3,T6,T5

---

FSM Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	278	Covered	T14
IdleSt	175	Covered	T14
Phase0St	146	Covered	T14
Phase1St	192	Covered	T14
Phase2St	209	Covered	T14
Phase3St	227	Covered	T14
TerminalSt	243	Covered	T14
TimeoutSt	153	Covered	T14

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	278	Covered	T14
IdleSt->Phase0St	146	Covered	T14
IdleSt->TimeoutSt	153	Covered	T14
Phase0St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	188	Covered	T14
Phase0St->Phase1St	192	Covered	T14
Phase1St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	205	Covered	T14
Phase1St->Phase2St	209	Covered	T14
Phase2St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	223	Covered	T14
Phase2St->Phase3St	227	Covered	T14
Phase3St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	239	Covered	T14
Phase3St->TerminalSt	243	Covered	T14
TerminalSt->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	255	Covered	T14
TimeoutSt->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	175	Covered	T14
TimeoutSt->Phase0St	166	Covered	T14

---

Branch Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	138	22	22	100.00
IF	277	2	2	100.00
IF	299	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	case (state_q)
-2-:	145	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	151	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	165	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	172	if (timeout_en_i)
-6-:	187	if (clr_i)
-7-:	191	if (cnt_ge)
-8-:	204	if (clr_i)
-9-:	208	if (cnt_ge)
-10-:	222	if (clr_i)
-11-:	226	if (cnt_ge)
-12-:	238	if (clr_i)
-13-:	242	if (cnt_ge)
-14-:	254	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T6,T5
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T18,T7,T15
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T7,T15,T16
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T18,T7,T15
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T18,T7,T15
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T90,T91,T92
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T3,T6,T5
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T3,T6,T5
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T33,T35,T88
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T3,T6,T5
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T3,T6,T5
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T93,T94,T95
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T3,T6,T5
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T3,T6,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T33,T88,T91
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T3,T6,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T3,T6,T5
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T7,T15,T16
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T3,T6,T5
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	277	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	299	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	774255058	241	0	0
CheckAccumTrig0_A	774255058	553	0	0
CheckAccumTrig1_A	774255058	25	0	0
CheckClr_A	774255058	226	0	0
CheckEn_A	774122133	351800275	0	0
CheckPhase0_A	774255058	646	0	0
CheckPhase1_A	774255058	638	0	0
CheckPhase2_A	774255058	628	0	0
CheckPhase3_A	774255058	616	0	0
CheckTimeout0_A	774255058	2616	0	0
CheckTimeoutSt1_A	774255058	235211	0	0
CheckTimeoutSt2_A	774255058	2517	0	0
CheckTimeoutStTrig_A	774255058	74	0	0
ErrorStAllEscAsserted_A	774255058	1272	0	0
ErrorStIsTerminal_A	774255058	1062	0	0
u_state_regs_A	774255058	774090866	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	774255058	241	0	0
T11	21196	36	0	0
T12	0	67	0	0
T13	0	46	0	0
T39	0	43	0	0
T40	0	49	0	0
T41	97569	0	0	0
T42	28028	0	0	0
T43	116238	0	0	0
T44	498650	0	0	0
T45	3651	0	0	0
T46	498399	0	0	0
T47	8806	0	0	0
T48	899739	0	0	0
T49	150874	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	774255058	553	0	0
T3	290691	1	0	0
T4	528402	0	0	0
T5	171339	1	0	0
T6	69303	1	0	0
T7	745608	2	0	0
T8	157512	0	0	0
T9	979783	0	0	0
T10	0	1	0	0
T15	761305	5	0	0
T16	0	3	0	0
T18	150400	0	0	0
T19	145838	0	0	0
T20	0	3	0	0
T50	0	3	0	0
T51	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	774255058	25	0	0
T7	745608	2	0	0
T8	157512	0	0	0
T9	979783	0	0	0
T15	761305	0	0	0
T16	179021	1	0	0
T19	145838	0	0	0
T20	779933	0	0	0
T35	0	1	0	0
T36	0	1	0	0
T50	74850	0	0	0
T51	82592	0	0	0
T56	74893	0	0	0
T60	0	1	0	0
T65	0	1	0	0
T66	0	1	0	0
T67	0	2	0	0
T68	0	1	0	0
T69	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	774255058	226	0	0
T7	745608	1	0	0
T8	157512	0	0	0
T9	979783	0	0	0
T15	761305	3	0	0
T16	179021	1	0	0
T19	145838	0	0	0
T20	779933	1	0	0
T33	0	5	0	0
T36	0	7	0	0
T50	74850	2	0	0
T51	82592	0	0	0
T54	0	2	0	0
T56	74893	0	0	0
T75	0	1	0	0
T76	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	774122133	351800275	0	0
T1	17500	17408	0	0
T2	49644	49571	0	0
T3	290691	26030	0	0
T4	528402	15326	0	0
T5	171339	2126	0	0
T6	69303	3275	0	0
T7	745608	169185	0	0
T8	157512	3314	0	0
T15	761305	453285	0	0
T18	150400	125411	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	774255058	646	0	0
T3	290691	1	0	0
T4	528402	0	0	0
T5	171339	1	0	0
T6	69303	1	0	0
T7	745608	4	0	0
T8	157512	0	0	0
T9	979783	0	0	0
T10	0	1	0	0
T15	761305	6	0	0
T16	0	4	0	0
T18	150400	0	0	0
T19	145838	0	0	0
T20	0	3	0	0
T50	0	3	0	0
T51	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	774255058	638	0	0
T3	290691	1	0	0
T4	528402	0	0	0
T5	171339	1	0	0
T6	69303	1	0	0
T7	745608	4	0	0
T8	157512	0	0	0
T9	979783	0	0	0
T10	0	1	0	0
T15	761305	6	0	0
T16	0	4	0	0
T18	150400	0	0	0
T19	145838	0	0	0
T20	0	3	0	0
T50	0	3	0	0
T51	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	774255058	628	0	0
T3	290691	1	0	0
T4	528402	0	0	0
T5	171339	1	0	0
T6	69303	1	0	0
T7	745608	4	0	0
T8	157512	0	0	0
T9	979783	0	0	0
T10	0	1	0	0
T15	761305	6	0	0
T16	0	4	0	0
T18	150400	0	0	0
T19	145838	0	0	0
T20	0	3	0	0
T50	0	3	0	0
T51	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	774255058	616	0	0
T3	290691	1	0	0
T4	528402	0	0	0
T5	171339	1	0	0
T6	69303	1	0	0
T7	745608	4	0	0
T8	157512	0	0	0
T9	979783	0	0	0
T10	0	1	0	0
T15	761305	6	0	0
T16	0	4	0	0
T18	150400	0	0	0
T19	145838	0	0	0
T20	0	3	0	0
T50	0	3	0	0
T51	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	774255058	2616	0	0
T5	171339	0	0	0
T7	745608	27	0	0
T8	157512	0	0	0
T9	979783	0	0	0
T15	761305	3	0	0
T16	179021	10	0	0
T18	150400	386	0	0
T19	145838	0	0	0
T20	0	8	0	0
T36	0	124	0	0
T50	74850	1	0	0
T56	74893	4	0	0
T59	0	1	0	0
T76	0	3	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	774255058	235211	0	0
T5	171339	0	0	0
T7	745608	3781	0	0
T8	157512	0	0	0
T9	979783	0	0	0
T15	761305	360	0	0
T16	179021	1225	0	0
T18	150400	21217	0	0
T19	145838	0	0	0
T20	0	1420	0	0
T36	0	7894	0	0
T50	74850	36	0	0
T56	74893	985	0	0
T59	0	516	0	0
T76	0	209	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	774255058	2517	0	0
T5	171339	0	0	0
T7	745608	25	0	0
T8	157512	0	0	0
T9	979783	0	0	0
T15	761305	2	0	0
T16	179021	9	0	0
T18	150400	386	0	0
T19	145838	0	0	0
T20	0	8	0	0
T36	0	121	0	0
T50	74850	1	0	0
T56	74893	4	0	0
T59	0	1	0	0
T76	0	3	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	774255058	74	0	0
T8	157512	0	0	0
T9	979783	0	0	0
T10	110271	0	0	0
T15	761305	1	0	0
T16	179021	0	0	0
T19	145838	0	0	0
T20	779933	0	0	0
T35	0	1	0	0
T36	0	2	0	0
T46	0	1	0	0
T50	74850	0	0	0
T51	82592	0	0	0
T56	74893	0	0	0
T60	0	1	0	0
T63	0	1	0	0
T65	0	2	0	0
T79	0	2	0	0
T84	0	1	0	0
T85	0	3	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	774255058	1272	0	0
T11	21196	188	0	0
T12	0	373	0	0
T13	0	164	0	0
T39	0	202	0	0
T40	0	345	0	0
T41	97569	0	0	0
T42	28028	0	0	0
T43	116238	0	0	0
T44	498650	0	0	0
T45	3651	0	0	0
T46	498399	0	0	0
T47	8806	0	0	0
T48	899739	0	0	0
T49	150874	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	774255058	1062	0	0
T11	21196	158	0	0
T12	0	313	0	0
T13	0	134	0	0
T39	0	172	0	0
T40	0	285	0	0
T41	97569	0	0	0
T42	28028	0	0	0
T43	116238	0	0	0
T44	498650	0	0	0
T45	3651	0	0	0
T46	498399	0	0	0
T47	8806	0	0	0
T48	899739	0	0	0
T49	150874	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	774255058	774090866	0	0
T1	17500	17409	0	0
T2	49644	49572	0	0
T3	290691	290684	0	0
T4	528402	528395	0	0
T5	171339	171330	0	0
T6	69303	69227	0	0
T7	745608	745596	0	0
T8	157512	157504	0	0
T15	761305	761297	0	0
T18	150400	150347	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	79	1	1	100.00
ALWAYS	128	89	89	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
ALWAYS	299	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
79	1	1
128	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
138	1	1
142	1	1
143	1	1
145	1	1
146	1	1
147	1	1
148	1	1
151	1	1
152	1	1
153	1	1
			MISSING_ELSE
163	1	1
165	1	1
166	1	1
167	1	1
168	1	1
169	1	1
172	1	1
173	1	1
175	1	1
176	1	1
181	1	1
182	1	1
183	1	1
184	1	1
185	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
198	1	1
199	1	1
200	1	1
201	1	1
202	1	1
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
222	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
			MISSING_ELSE
232	1	1
233	1	1
234	1	1
235	1	1
236	1	1
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
			MISSING_ELSE
252	1	1
253	1	1
254	1	1
255	1	1
			MISSING_ELSE
262	1	1
263	1	1
277	1	1
278	1	1
279	1	1
			MISSING_ELSE
286	4	4
289	4	4
299	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T6,T4
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T6,T4

 LINE       145
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T3,T6
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T4,T5,T7

 LINE       151
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T6,T18
1	0	1	Covered	T3,T4,T7
1	1	0	Covered	T1,T18,T5
1	1	1	Covered	T1,T6,T18

 LINE       165
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T18
0	1	Covered	T20,T33,T60
1	0	Covered	T6,T18,T33

 LINE       165
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T6,T18
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T6,T18,T33

 LINE       165
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T18
1	0	Not Covered
1	1	Covered	T20,T33,T60

 LINE       185
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T6,T4,T18
1	Covered	T7,T15,T16

 LINE       202
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T4,T18,T5
1	Covered	T6,T7,T15

 LINE       219
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T6,T4,T18
1	Covered	T5,T7,T15

 LINE       236
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T6,T5,T7
1	Covered	T4,T18,T15

 LINE       277
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13

 LINE       289
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T4,T18,T15

 LINE       289
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T6,T5,T7

 LINE       289
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T18,T5,T7

 LINE       289
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T6,T4,T5

---

FSM Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	278	Covered	T14
IdleSt	175	Covered	T14
Phase0St	146	Covered	T14
Phase1St	192	Covered	T14
Phase2St	209	Covered	T14
Phase3St	227	Covered	T14
TerminalSt	243	Covered	T14
TimeoutSt	153	Covered	T14

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	278	Covered	T14
IdleSt->Phase0St	146	Covered	T14
IdleSt->TimeoutSt	153	Covered	T14
Phase0St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	188	Covered	T14
Phase0St->Phase1St	192	Covered	T14
Phase1St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	205	Covered	T14
Phase1St->Phase2St	209	Covered	T14
Phase2St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	223	Covered	T14
Phase2St->Phase3St	227	Covered	T14
Phase3St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	239	Covered	T14
Phase3St->TerminalSt	243	Covered	T14
TerminalSt->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	255	Covered	T14
TimeoutSt->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	175	Covered	T14
TimeoutSt->Phase0St	166	Covered	T14

---

Branch Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	138	22	22	100.00
IF	277	2	2	100.00
IF	299	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	case (state_q)
-2-:	145	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	151	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	165	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	172	if (timeout_en_i)
-6-:	187	if (clr_i)
-7-:	191	if (cnt_ge)
-8-:	204	if (clr_i)
-9-:	208	if (cnt_ge)
-10-:	222	if (clr_i)
-11-:	226	if (cnt_ge)
-12-:	238	if (clr_i)
-13-:	242	if (cnt_ge)
-14-:	254	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T7
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T6,T18
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T6,T18,T20
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T6,T18
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T18,T5
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T20,T96,T68
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T6,T4,T18
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T6,T4,T18
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T87,T97,T98
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T6,T4,T18
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T6,T4,T18
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T63,T72,T99
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T6,T4,T18
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T6,T4,T18
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T36,T47,T100
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T6,T4,T18
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T6,T4,T18
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T7,T15,T16
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T6,T4,T18
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	277	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	299	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	774255058	218	0	0
CheckAccumTrig0_A	774255058	535	0	0
CheckAccumTrig1_A	774255058	27	0	0
CheckClr_A	774255058	232	0	0
CheckEn_A	774122133	365282318	0	0
CheckPhase0_A	774255058	623	0	0
CheckPhase1_A	774255058	614	0	0
CheckPhase2_A	774255058	603	0	0
CheckPhase3_A	774255058	593	0	0
CheckTimeout0_A	774255058	1167	0	0
CheckTimeoutSt1_A	774255058	142981	0	0
CheckTimeoutSt2_A	774255058	1072	0	0
CheckTimeoutStTrig_A	774255058	68	0	0
ErrorStAllEscAsserted_A	774255058	1334	0	0
ErrorStIsTerminal_A	774255058	1124	0	0
u_state_regs_A	774255058	774090866	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	774255058	218	0	0
T11	21196	19	0	0
T12	0	69	0	0
T13	0	30	0	0
T39	0	25	0	0
T40	0	75	0	0
T41	97569	0	0	0
T42	28028	0	0	0
T43	116238	0	0	0
T44	498650	0	0	0
T45	3651	0	0	0
T46	498399	0	0	0
T47	8806	0	0	0
T48	899739	0	0	0
T49	150874	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	774255058	535	0	0
T4	528402	1	0	0
T5	171339	1	0	0
T7	745608	4	0	0
T8	157512	0	0	0
T9	979783	0	0	0
T10	0	1	0	0
T15	761305	6	0	0
T16	179021	6	0	0
T18	150400	0	0	0
T19	145838	0	0	0
T20	0	2	0	0
T52	0	1	0	0
T53	0	2	0	0
T54	0	1	0	0
T56	74893	0	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	774255058	27	0	0
T4	528402	0	0	0
T5	171339	0	0	0
T6	69303	1	0	0
T7	745608	0	0	0
T8	157512	0	0	0
T9	979783	0	0	0
T15	761305	0	0	0
T18	150400	1	0	0
T19	145838	0	0	0
T33	0	1	0	0
T56	74893	0	0	0
T59	0	1	0	0
T60	0	1	0	0
T63	0	2	0	0
T97	0	1	0	0
T99	0	1	0	0
T101	0	1	0	0
T102	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	774255058	232	0	0
T7	745608	1	0	0
T8	157512	0	0	0
T9	979783	0	0	0
T15	761305	2	0	0
T16	179021	1	0	0
T19	145838	0	0	0
T20	779933	1	0	0
T33	0	2	0	0
T36	0	3	0	0
T50	74850	0	0	0
T51	82592	0	0	0
T53	0	1	0	0
T54	0	1	0	0
T56	74893	0	0	0
T76	0	1	0	0
T78	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	774122133	365282318	0	0
T1	17500	10617	0	0
T2	49644	49571	0	0
T3	290691	289248	0	0
T4	528402	58588	0	0
T5	171339	12986	0	0
T6	69303	3295	0	0
T7	745608	196789	0	0
T8	157512	157504	0	0
T15	761305	803052	0	0
T18	150400	144703	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	774255058	623	0	0
T4	528402	1	0	0
T5	171339	1	0	0
T6	69303	1	0	0
T7	745608	4	0	0
T8	157512	0	0	0
T9	979783	0	0	0
T10	0	1	0	0
T15	761305	6	0	0
T16	0	6	0	0
T18	150400	1	0	0
T19	145838	0	0	0
T20	0	5	0	0
T52	0	1	0	0
T56	74893	0	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	774255058	614	0	0
T4	528402	1	0	0
T5	171339	1	0	0
T6	69303	1	0	0
T7	745608	4	0	0
T8	157512	0	0	0
T9	979783	0	0	0
T10	0	1	0	0
T15	761305	6	0	0
T16	0	6	0	0
T18	150400	1	0	0
T19	145838	0	0	0
T20	0	5	0	0
T52	0	1	0	0
T56	74893	0	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	774255058	603	0	0
T4	528402	1	0	0
T5	171339	1	0	0
T6	69303	1	0	0
T7	745608	4	0	0
T8	157512	0	0	0
T9	979783	0	0	0
T10	0	1	0	0
T15	761305	6	0	0
T16	0	6	0	0
T18	150400	1	0	0
T19	145838	0	0	0
T20	0	5	0	0
T52	0	1	0	0
T56	74893	0	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	774255058	593	0	0
T4	528402	1	0	0
T5	171339	1	0	0
T6	69303	1	0	0
T7	745608	4	0	0
T8	157512	0	0	0
T9	979783	0	0	0
T10	0	1	0	0
T15	761305	6	0	0
T16	0	6	0	0
T18	150400	1	0	0
T19	145838	0	0	0
T20	0	5	0	0
T52	0	1	0	0
T56	74893	0	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	774255058	1167	0	0
T1	17500	1	0	0
T2	49644	0	0	0
T3	290691	0	0	0
T4	528402	0	0	0
T5	171339	2	0	0
T6	69303	1	0	0
T7	745608	24	0	0
T8	157512	0	0	0
T15	761305	1	0	0
T16	0	9	0	0
T18	150400	13	0	0
T20	0	6	0	0
T33	0	2	0	0
T56	0	2	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	774255058	142981	0	0
T1	17500	160	0	0
T2	49644	0	0	0
T3	290691	0	0	0
T4	528402	0	0	0
T5	171339	71	0	0
T6	69303	1	0	0
T7	745608	3093	0	0
T8	157512	0	0	0
T15	761305	58	0	0
T16	0	1259	0	0
T18	150400	833	0	0
T20	0	1708	0	0
T33	0	93	0	0
T56	0	512	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	774255058	1072	0	0
T1	17500	1	0	0
T2	49644	0	0	0
T3	290691	0	0	0
T4	528402	0	0	0
T5	171339	2	0	0
T6	69303	0	0	0
T7	745608	24	0	0
T8	157512	0	0	0
T15	761305	1	0	0
T16	0	9	0	0
T18	150400	12	0	0
T20	0	2	0	0
T36	0	154	0	0
T56	0	2	0	0
T79	0	12	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	774255058	68	0	0
T10	110271	0	0	0
T17	12165	0	0	0
T20	779933	4	0	0
T32	0	1	0	0
T33	281829	1	0	0
T36	416985	0	0	0
T46	0	1	0	0
T51	82592	0	0	0
T58	55494	0	0	0
T59	25550	0	0	0
T60	0	1	0	0
T63	0	1	0	0
T70	8464	0	0	0
T75	176017	0	0	0
T85	0	2	0	0
T86	0	1	0	0
T87	0	1	0	0
T88	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	774255058	1334	0	0
T11	21196	202	0	0
T12	0	359	0	0
T13	0	189	0	0
T39	0	176	0	0
T40	0	408	0	0
T41	97569	0	0	0
T42	28028	0	0	0
T43	116238	0	0	0
T44	498650	0	0	0
T45	3651	0	0	0
T46	498399	0	0	0
T47	8806	0	0	0
T48	899739	0	0	0
T49	150874	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	774255058	1124	0	0
T11	21196	172	0	0
T12	0	299	0	0
T13	0	159	0	0
T39	0	146	0	0
T40	0	348	0	0
T41	97569	0	0	0
T42	28028	0	0	0
T43	116238	0	0	0
T44	498650	0	0	0
T45	3651	0	0	0
T46	498399	0	0	0
T47	8806	0	0	0
T48	899739	0	0	0
T49	150874	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	774255058	774090866	0	0
T1	17500	17409	0	0
T2	49644	49572	0	0
T3	290691	290684	0	0
T4	528402	528395	0	0
T5	171339	171330	0	0
T6	69303	69227	0	0
T7	745608	745596	0	0
T8	157512	157504	0	0
T15	761305	761297	0	0
T18	150400	150347	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	79	1	1	100.00
ALWAYS	128	89	89	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
ALWAYS	299	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
79	1	1
128	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
138	1	1
142	1	1
143	1	1
145	1	1
146	1	1
147	1	1
148	1	1
151	1	1
152	1	1
153	1	1
			MISSING_ELSE
163	1	1
165	1	1
166	1	1
167	1	1
168	1	1
169	1	1
172	1	1
173	1	1
175	1	1
176	1	1
181	1	1
182	1	1
183	1	1
184	1	1
185	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
198	1	1
199	1	1
200	1	1
201	1	1
202	1	1
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
222	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
			MISSING_ELSE
232	1	1
233	1	1
234	1	1
235	1	1
236	1	1
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
			MISSING_ELSE
252	1	1
253	1	1
254	1	1
255	1	1
			MISSING_ELSE
262	1	1
263	1	1
277	1	1
278	1	1
279	1	1
			MISSING_ELSE
286	4	4
289	4	4
299	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T6,T4,T18
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T6,T4,T18
1	0	Covered	T1,T2,T3
1	1	Covered	T6,T4,T18

 LINE       145
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T6,T4,T18
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T6,T4,T18

 LINE       151
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T6,T18,T7
1	0	1	Covered	T7,T15,T16
1	1	0	Covered	T6,T18,T5
1	1	1	Covered	T18,T7,T56

 LINE       165
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T18,T7,T56
0	1	Covered	T18,T56,T50
1	0	Covered	T16,T50,T71

 LINE       165
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T18,T7,T56
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T16,T50,T71

 LINE       165
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T18,T7,T56
1	0	Not Covered
1	1	Covered	T18,T56,T50

 LINE       185
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T6,T4,T18
1	Covered	T16,T51,T53

 LINE       202
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T6,T4,T18
1	Covered	T7,T16,T51

 LINE       219
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T6,T18,T7
1	Covered	T4,T7,T15

 LINE       236
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T4,T7,T15
1	Covered	T6,T18,T15

 LINE       277
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13

 LINE       289
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T6,T4,T18

 LINE       289
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T6,T18,T7

 LINE       289
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T6,T4,T7

 LINE       289
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T6,T18,T7

---

FSM Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	278	Covered	T14
IdleSt	175	Covered	T14
Phase0St	146	Covered	T14
Phase1St	192	Covered	T14
Phase2St	209	Covered	T14
Phase3St	227	Covered	T14
TerminalSt	243	Covered	T14
TimeoutSt	153	Covered	T14

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	278	Covered	T14
IdleSt->Phase0St	146	Covered	T14
IdleSt->TimeoutSt	153	Covered	T14
Phase0St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	188	Covered	T14
Phase0St->Phase1St	192	Covered	T14
Phase1St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	205	Covered	T14
Phase1St->Phase2St	209	Covered	T14
Phase2St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	223	Covered	T14
Phase2St->Phase3St	227	Covered	T14
Phase3St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	239	Covered	T14
Phase3St->TerminalSt	243	Covered	T14
TerminalSt->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	255	Covered	T14
TimeoutSt->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	175	Covered	T14
TimeoutSt->Phase0St	166	Covered	T14

---

Branch Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	138	22	22	100.00
IF	277	2	2	100.00
IF	299	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	case (state_q)
-2-:	145	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	151	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	165	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	172	if (timeout_en_i)
-6-:	187	if (clr_i)
-7-:	191	if (cnt_ge)
-8-:	204	if (clr_i)
-9-:	208	if (cnt_ge)
-10-:	222	if (clr_i)
-11-:	226	if (cnt_ge)
-12-:	238	if (clr_i)
-13-:	242	if (cnt_ge)
-14-:	254	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T4,T18
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T18,T7,T56
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T18,T56,T16
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T18,T7,T56
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T18,T7,T16
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T31,T69,T98
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T6,T4,T18
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T6,T4,T18
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T18,T79,T87
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T6,T4,T18
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T6,T4,T18
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T18,T65,T46
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T6,T4,T18
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T6,T4,T18
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T65,T103,T92
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T6,T4,T18
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T6,T4,T18
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T7,T15,T16
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T6,T4,T18
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	277	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	299	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	774255058	207	0	0
CheckAccumTrig0_A	774255058	556	0	0
CheckAccumTrig1_A	774255058	15	0	0
CheckClr_A	774255058	244	0	0
CheckEn_A	774122133	330005281	0	0
CheckPhase0_A	774255058	642	0	0
CheckPhase1_A	774255058	634	0	0
CheckPhase2_A	774255058	620	0	0
CheckPhase3_A	774255058	607	0	0
CheckTimeout0_A	774255058	2533	0	0
CheckTimeoutSt1_A	774255058	244326	0	0
CheckTimeoutSt2_A	774255058	2440	0	0
CheckTimeoutStTrig_A	774255058	78	0	0
ErrorStAllEscAsserted_A	774255058	1301	0	0
ErrorStIsTerminal_A	774255058	1091	0	0
u_state_regs_A	774255058	774090866	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	774255058	207	0	0
T11	21196	44	0	0
T12	0	57	0	0
T13	0	28	0	0
T39	0	18	0	0
T40	0	60	0	0
T41	97569	0	0	0
T42	28028	0	0	0
T43	116238	0	0	0
T44	498650	0	0	0
T45	3651	0	0	0
T46	498399	0	0	0
T47	8806	0	0	0
T48	899739	0	0	0
T49	150874	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	774255058	556	0	0
T4	528402	1	0	0
T5	171339	0	0	0
T6	69303	1	0	0
T7	745608	6	0	0
T8	157512	0	0	0
T9	979783	0	0	0
T15	761305	6	0	0
T16	0	7	0	0
T18	150400	2	0	0
T19	145838	0	0	0
T51	0	4	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	74893	0	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	774255058	15	0	0
T10	110271	0	0	0
T17	12165	0	0	0
T20	779933	0	0	0
T50	74850	1	0	0
T51	82592	0	0	0
T63	333182	0	0	0
T70	8464	0	0	0
T71	552330	1	0	0
T72	112917	0	0	0
T73	430165	0	0	0
T87	0	2	0	0
T104	0	1	0	0
T105	0	1	0	0
T106	0	1	0	0
T107	0	1	0	0
T108	0	1	0	0
T109	0	1	0	0
T110	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	774255058	244	0	0
T5	171339	0	0	0
T7	745608	2	0	0
T8	157512	0	0	0
T9	979783	0	0	0
T15	761305	3	0	0
T16	179021	4	0	0
T18	150400	2	0	0
T19	145838	0	0	0
T31	0	3	0	0
T50	74850	2	0	0
T51	0	3	0	0
T56	74893	0	0	0
T60	0	1	0	0
T76	0	2	0	0
T79	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	774122133	330005281	0	0
T1	17500	17408	0	0
T2	49644	49571	0	0
T3	290691	290684	0	0
T4	528402	10336	0	0
T5	171339	171330	0	0
T6	69303	16065	0	0
T7	745608	106405	0	0
T8	157512	157504	0	0
T15	761305	265130	0	0
T18	150400	123835	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	774255058	642	0	0
T4	528402	1	0	0
T5	171339	0	0	0
T6	69303	1	0	0
T7	745608	6	0	0
T8	157512	0	0	0
T9	979783	0	0	0
T15	761305	6	0	0
T16	0	7	0	0
T18	150400	3	0	0
T19	145838	0	0	0
T20	0	1	0	0
T50	0	3	0	0
T51	0	4	0	0
T56	74893	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	774255058	634	0	0
T4	528402	1	0	0
T5	171339	0	0	0
T6	69303	1	0	0
T7	745608	6	0	0
T8	157512	0	0	0
T9	979783	0	0	0
T15	761305	6	0	0
T16	0	7	0	0
T18	150400	2	0	0
T19	145838	0	0	0
T20	0	1	0	0
T50	0	3	0	0
T51	0	4	0	0
T56	74893	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	774255058	620	0	0
T4	528402	1	0	0
T5	171339	0	0	0
T6	69303	1	0	0
T7	745608	6	0	0
T8	157512	0	0	0
T9	979783	0	0	0
T15	761305	6	0	0
T16	0	7	0	0
T18	150400	1	0	0
T19	145838	0	0	0
T20	0	1	0	0
T50	0	3	0	0
T51	0	4	0	0
T56	74893	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	774255058	607	0	0
T4	528402	1	0	0
T5	171339	0	0	0
T6	69303	1	0	0
T7	745608	6	0	0
T8	157512	0	0	0
T9	979783	0	0	0
T15	761305	6	0	0
T16	0	7	0	0
T18	150400	1	0	0
T19	145838	0	0	0
T20	0	1	0	0
T50	0	3	0	0
T51	0	4	0	0
T56	74893	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	774255058	2533	0	0
T5	171339	0	0	0
T7	745608	24	0	0
T8	157512	0	0	0
T9	979783	0	0	0
T15	761305	0	0	0
T16	179021	11	0	0
T18	150400	342	0	0
T19	145838	0	0	0
T20	0	4	0	0
T36	0	142	0	0
T38	0	4	0	0
T50	74850	5	0	0
T56	74893	1	0	0
T60	0	86	0	0
T79	0	6	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	774255058	244326	0	0
T5	171339	0	0	0
T7	745608	2374	0	0
T8	157512	0	0	0
T9	979783	0	0	0
T15	761305	0	0	0
T16	179021	1308	0	0
T18	150400	19654	0	0
T19	145838	0	0	0
T20	0	519	0	0
T36	0	8652	0	0
T38	0	280	0	0
T50	74850	573	0	0
T56	74893	241	0	0
T60	0	6906	0	0
T79	0	993	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	774255058	2440	0	0
T5	171339	0	0	0
T7	745608	24	0	0
T8	157512	0	0	0
T9	979783	0	0	0
T15	761305	0	0	0
T16	179021	11	0	0
T18	150400	341	0	0
T19	145838	0	0	0
T20	0	3	0	0
T36	0	141	0	0
T38	0	4	0	0
T50	74850	2	0	0
T56	74893	0	0	0
T60	0	85	0	0
T79	0	5	0	0
T81	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	774255058	78	0	0
T5	171339	0	0	0
T7	745608	0	0	0
T8	157512	0	0	0
T9	979783	0	0	0
T15	761305	0	0	0
T16	179021	0	0	0
T18	150400	1	0	0
T19	145838	0	0	0
T20	0	1	0	0
T36	0	1	0	0
T50	74850	2	0	0
T56	74893	1	0	0
T60	0	1	0	0
T62	0	2	0	0
T71	0	1	0	0
T79	0	1	0	0
T83	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	774255058	1301	0	0
T11	21196	198	0	0
T12	0	332	0	0
T13	0	182	0	0
T39	0	198	0	0
T40	0	391	0	0
T41	97569	0	0	0
T42	28028	0	0	0
T43	116238	0	0	0
T44	498650	0	0	0
T45	3651	0	0	0
T46	498399	0	0	0
T47	8806	0	0	0
T48	899739	0	0	0
T49	150874	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	774255058	1091	0	0
T11	21196	168	0	0
T12	0	272	0	0
T13	0	152	0	0
T39	0	168	0	0
T40	0	331	0	0
T41	97569	0	0	0
T42	28028	0	0	0
T43	116238	0	0	0
T44	498650	0	0	0
T45	3651	0	0	0
T46	498399	0	0	0
T47	8806	0	0	0
T48	899739	0	0	0
T49	150874	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	774255058	774090866	0	0
T1	17500	17409	0	0
T2	49644	49572	0	0
T3	290691	290684	0	0
T4	528402	528395	0	0
T5	171339	171330	0	0
T6	69303	69227	0	0
T7	745608	745596	0	0
T8	157512	157504	0	0
T15	761305	761297	0	0
T18	150400	150347	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	79	1	1	100.00
ALWAYS	128	89	89	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
ALWAYS	299	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
79	1	1
128	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
138	1	1
142	1	1
143	1	1
145	1	1
146	1	1
147	1	1
148	1	1
151	1	1
152	1	1
153	1	1
			MISSING_ELSE
163	1	1
165	1	1
166	1	1
167	1	1
168	1	1
169	1	1
172	1	1
173	1	1
175	1	1
176	1	1
181	1	1
182	1	1
183	1	1
184	1	1
185	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
198	1	1
199	1	1
200	1	1
201	1	1
202	1	1
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
222	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
			MISSING_ELSE
232	1	1
233	1	1
234	1	1
235	1	1
236	1	1
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
			MISSING_ELSE
252	1	1
253	1	1
254	1	1
255	1	1
			MISSING_ELSE
262	1	1
263	1	1
277	1	1
278	1	1
279	1	1
			MISSING_ELSE
286	4	4
289	4	4
299	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T3,T6
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T6

 LINE       145
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T3,T6
1	0	1	Excluded		VC_COV_UNR
1	1	0	Covered	T30
1	1	1	Covered	T2,T3,T6

 LINE       151
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T6,T18,T5
1	0	1	Covered	T3,T4,T18
1	1	0	Covered	T1,T6,T18
1	1	1	Covered	T18,T5,T7

 LINE       165
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T18,T5,T7
0	1	Covered	T7,T20,T82
1	0	Covered	T18,T7,T20

 LINE       165
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T18,T5,T7
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T18,T7,T20

 LINE       165
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T18,T5,T7
1	0	Not Covered
1	1	Covered	T7,T20,T82

 LINE       185
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T6,T4
1	Covered	T3,T18,T7

 LINE       202
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T6
1	Covered	T18,T15,T20

 LINE       219
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T18
1	Covered	T6,T4,T18

 LINE       236
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T3,T6,T4
1	Covered	T2,T7,T19

 LINE       277
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13

 LINE       289
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T3,T18

 LINE       289
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T6,T4

 LINE       289
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T3,T18

 LINE       289
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T4,T18,T7

---

FSM Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	278	Covered	T14
IdleSt	175	Covered	T14
Phase0St	146	Covered	T14
Phase1St	192	Covered	T14
Phase2St	209	Covered	T14
Phase3St	227	Covered	T14
TerminalSt	243	Covered	T14
TimeoutSt	153	Covered	T14

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	278	Covered	T14
IdleSt->Phase0St	146	Covered	T14
IdleSt->TimeoutSt	153	Covered	T14
Phase0St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	188	Covered	T14
Phase0St->Phase1St	192	Covered	T14
Phase1St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	205	Covered	T14
Phase1St->Phase2St	209	Covered	T14
Phase2St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	223	Covered	T14
Phase2St->Phase3St	227	Covered	T14
Phase3St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	239	Covered	T14
Phase3St->TerminalSt	243	Covered	T14
TerminalSt->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	255	Covered	T14
TimeoutSt->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	175	Covered	T14
TimeoutSt->Phase0St	166	Covered	T14

---

Branch Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	138	22	22	100.00
IF	277	2	2	100.00
IF	299	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	case (state_q)
-2-:	145	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	151	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	165	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	172	if (timeout_en_i)
-6-:	187	if (clr_i)
-7-:	191	if (cnt_ge)
-8-:	204	if (clr_i)
-9-:	208	if (cnt_ge)
-10-:	222	if (clr_i)
-11-:	226	if (cnt_ge)
-12-:	238	if (clr_i)
-13-:	242	if (cnt_ge)
-14-:	254	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T6
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T18,T5,T7
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T18,T7,T20
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T18,T5,T7
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T5,T7,T19
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T32,T111,T112
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T3,T6
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T3,T6
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T34,T85,T113
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T3,T6
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T3,T6
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T36,T37,T38
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T2,T3,T6
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T3,T6
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T18,T60,T61
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T2,T3,T6
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T3,T6
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T18,T7,T15
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T3,T6
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	277	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	299	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	774255058	204	0	0
CheckAccumTrig0_A	774255058	896	0	0
CheckAccumTrig1_A	774255058	63	0	0
CheckClr_A	774255058	432	0	0
CheckEn_A	774122133	285677829	0	0
CheckPhase0_A	774255058	1017	0	0
CheckPhase1_A	774255058	1003	0	0
CheckPhase2_A	774255058	988	0	0
CheckPhase3_A	774255058	967	0	0
CheckTimeout0_A	774255058	1684	0	0
CheckTimeoutSt1_A	774255058	178503	0	0
CheckTimeoutSt2_A	774255058	1554	0	0
CheckTimeoutStTrig_A	774255058	67	0	0
ErrorStAllEscAsserted_A	774255058	1213	0	0
ErrorStIsTerminal_A	774255058	1003	0	0
u_state_regs_A	774255058	774090866	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	774255058	204	0	0
T11	21196	27	0	0
T12	0	55	0	0
T13	0	27	0	0
T39	0	32	0	0
T40	0	63	0	0
T41	97569	0	0	0
T42	28028	0	0	0
T43	116238	0	0	0
T44	498650	0	0	0
T45	3651	0	0	0
T46	498399	0	0	0
T47	8806	0	0	0
T48	899739	0	0	0
T49	150874	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	774255058	896	0	0
T2	49644	1	0	0
T3	290691	1	0	0
T4	528402	1	0	0
T5	171339	0	0	0
T6	69303	1	0	0
T7	745608	8	0	0
T8	157512	0	0	0
T9	979783	0	0	0
T15	761305	6	0	0
T16	0	6	0	0
T18	150400	6	0	0
T19	0	1	0	0
T20	0	9	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	774255058	63	0	0
T5	171339	0	0	0
T7	745608	1	0	0
T8	157512	0	0	0
T9	979783	0	0	0
T15	761305	0	0	0
T16	179021	0	0	0
T18	150400	1	0	0
T19	145838	0	0	0
T20	0	2	0	0
T33	0	1	0	0
T36	0	1	0	0
T50	74850	0	0	0
T56	74893	0	0	0
T57	0	1	0	0
T58	0	1	0	0
T61	0	2	0	0
T62	0	1	0	0
T64	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	774255058	432	0	0
T5	171339	0	0	0
T7	745608	5	0	0
T8	157512	0	0	0
T9	979783	0	0	0
T15	761305	3	0	0
T16	179021	2	0	0
T18	150400	3	0	0
T19	145838	0	0	0
T20	0	6	0	0
T36	0	8	0	0
T50	74850	0	0	0
T54	0	1	0	0
T56	74893	0	0	0
T58	0	2	0	0
T74	0	1	0	0
T77	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	774122133	285677829	0	0
T1	17500	17408	0	0
T2	49644	2520	0	0
T3	290691	8501	0	0
T4	528402	8576	0	0
T5	171339	170442	0	0
T6	69303	20373	0	0
T7	745608	178489	0	0
T8	157512	157504	0	0
T15	761305	265056	0	0
T18	150400	138770	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	774255058	1017	0	0
T2	49644	1	0	0
T3	290691	1	0	0
T4	528402	1	0	0
T5	171339	0	0	0
T6	69303	1	0	0
T7	745608	10	0	0
T8	157512	0	0	0
T9	979783	0	0	0
T15	761305	6	0	0
T16	0	6	0	0
T18	150400	7	0	0
T19	0	1	0	0
T20	0	13	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	774255058	1003	0	0
T2	49644	1	0	0
T3	290691	1	0	0
T4	528402	1	0	0
T5	171339	0	0	0
T6	69303	1	0	0
T7	745608	9	0	0
T8	157512	0	0	0
T9	979783	0	0	0
T15	761305	6	0	0
T16	0	6	0	0
T18	150400	7	0	0
T19	0	1	0	0
T20	0	13	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	774255058	988	0	0
T2	49644	1	0	0
T3	290691	1	0	0
T4	528402	1	0	0
T5	171339	0	0	0
T6	69303	1	0	0
T7	745608	9	0	0
T8	157512	0	0	0
T9	979783	0	0	0
T15	761305	6	0	0
T16	0	6	0	0
T18	150400	7	0	0
T19	0	1	0	0
T20	0	13	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	774255058	967	0	0
T2	49644	1	0	0
T3	290691	1	0	0
T4	528402	1	0	0
T5	171339	0	0	0
T6	69303	1	0	0
T7	745608	9	0	0
T8	157512	0	0	0
T9	979783	0	0	0
T15	761305	6	0	0
T16	0	6	0	0
T18	150400	6	0	0
T19	0	1	0	0
T20	0	13	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	774255058	1684	0	0
T5	171339	1	0	0
T7	745608	9	0	0
T8	157512	0	0	0
T9	979783	0	0	0
T15	761305	0	0	0
T16	179021	4	0	0
T18	150400	1	0	0
T19	145838	1	0	0
T20	0	10	0	0
T33	0	1	0	0
T36	0	148	0	0
T50	74850	0	0	0
T56	74893	2	0	0
T57	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	774255058	178503	0	0
T5	171339	164	0	0
T7	745608	732	0	0
T8	157512	0	0	0
T9	979783	0	0	0
T15	761305	0	0	0
T16	179021	1052	0	0
T18	150400	5	0	0
T19	145838	19	0	0
T20	0	1824	0	0
T33	0	2	0	0
T36	0	8932	0	0
T50	74850	0	0	0
T56	74893	590	0	0
T57	0	3	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	774255058	1554	0	0
T5	171339	1	0	0
T7	745608	7	0	0
T8	157512	0	0	0
T9	979783	0	0	0
T15	761305	0	0	0
T16	179021	4	0	0
T19	145838	1	0	0
T20	779933	6	0	0
T36	0	147	0	0
T50	74850	0	0	0
T56	74893	2	0	0
T77	0	1	0	0
T79	0	1	0	0
T80	0	10	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	774255058	67	0	0
T7	745608	1	0	0
T8	157512	0	0	0
T9	979783	0	0	0
T15	761305	0	0	0
T16	179021	0	0	0
T19	145838	0	0	0
T20	779933	2	0	0
T46	0	1	0	0
T50	74850	0	0	0
T51	82592	0	0	0
T56	74893	0	0	0
T62	0	2	0	0
T65	0	3	0	0
T71	0	1	0	0
T79	0	1	0	0
T82	0	1	0	0
T83	0	1	0	0
T87	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	774255058	1213	0	0
T11	21196	177	0	0
T12	0	354	0	0
T13	0	179	0	0
T39	0	168	0	0
T40	0	335	0	0
T41	97569	0	0	0
T42	28028	0	0	0
T43	116238	0	0	0
T44	498650	0	0	0
T45	3651	0	0	0
T46	498399	0	0	0
T47	8806	0	0	0
T48	899739	0	0	0
T49	150874	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	774255058	1003	0	0
T11	21196	147	0	0
T12	0	294	0	0
T13	0	149	0	0
T39	0	138	0	0
T40	0	275	0	0
T41	97569	0	0	0
T42	28028	0	0	0
T43	116238	0	0	0
T44	498650	0	0	0
T45	3651	0	0	0
T46	498399	0	0	0
T47	8806	0	0	0
T48	899739	0	0	0
T49	150874	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	774255058	774090866	0	0
T1	17500	17409	0	0
T2	49644	49572	0	0
T3	290691	290684	0	0
T4	528402	528395	0	0
T5	171339	171330	0	0
T6	69303	69227	0	0
T7	745608	745596	0	0
T8	157512	157504	0	0
T15	761305	761297	0	0
T18	150400	150347	0	0