Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
esc_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	8	0	8	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	80738	1			T2	9		T4	3617		T13	1717
class_i[0x1]	72737	1			T2	1		T5	12		T8	1
class_i[0x2]	48645	1			T13	37		T8	24		T14	5
class_i[0x3]	63277	1			T7	4		T13	16		T34	13

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Summary for Variable esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	65754	1			T2	4		T4	901		T7	1
alert[0x1]	66497	1			T2	1		T5	5		T4	839
alert[0x2]	67915	1			T2	2		T5	7		T4	1001
alert[0x3]	65231	1			T2	3		T4	876		T7	1

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Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

esc_integrity_fail

265119

1

T5

12

T4

3617

T13

1770

esc_ping_fail

278

1

T2

10

T7

4

T8

9

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Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	esc_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	alert[0x0]	65675	1			T4	901		T13	31		T8	2
esc_integrity_fail	alert[0x1]	66428	1			T5	5		T4	839		T13	1524
esc_integrity_fail	alert[0x2]	67847	1			T5	7		T4	1001		T13	204
esc_integrity_fail	alert[0x3]	65169	1			T4	876		T13	11		T8	11
esc_ping_fail	alert[0x0]	79	1			T2	4		T7	1		T8	1
esc_ping_fail	alert[0x1]	69	1			T2	1		T7	1		T8	3
esc_ping_fail	alert[0x2]	68	1			T2	2		T7	1		T8	1
esc_ping_fail	alert[0x3]	62	1			T2	3		T7	1		T8	4

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Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	class_i[0x0]	80677	1			T4	3617		T13	1717		T16	294
esc_integrity_fail	class_i[0x1]	72664	1			T5	12		T14	2		T16	1391
esc_integrity_fail	class_i[0x2]	48566	1			T13	37		T8	17		T14	5
esc_integrity_fail	class_i[0x3]	63212	1			T13	16		T34	13		T54	60
esc_ping_fail	class_i[0x0]	61	1			T2	9		T8	1		T14	4
esc_ping_fail	class_i[0x1]	73	1			T2	1		T8	1		T297	1
esc_ping_fail	class_i[0x2]	79	1			T8	7		T36	1		T123	1
esc_ping_fail	class_i[0x3]	65	1			T7	4		T36	2		T297	1