Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_edn_req.u_prim_packer_fifo.DataOStableWhenPending_A	0	0	741519896	0	0	635
tb.dut.u_edn_req.u_prim_packer_fifo.ValidOPairedWithReadyI_A	0	0	741519896	0	0	0

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.AckPKnownO_A	0	0	741519896	741332080	0	0
tb.dut.CheckAccuCntDw	0	0	635	635	0	0
tb.dut.CheckEscCntDw	0	0	635	635	0	0
tb.dut.CheckNAlerts	0	0	635	635	0	0
tb.dut.CheckNClasses	0	0	635	635	0	0
tb.dut.CheckNEscSev	0	0	635	635	0	0
tb.dut.CrashdumpKnownO_A	0	0	741519896	741332080	0	0
tb.dut.EdnKnownO_A	0	0	741519896	741332080	0	0
tb.dut.EscPKnownO_A	0	0	741519896	741332080	0	0
tb.dut.FpvSecCmPingTimerCnterCheck_A	0	0	741519896	90	0	0
tb.dut.FpvSecCmPingTimerDoubleLfsrCheck_A	0	0	741519896	90	0	0
tb.dut.FpvSecCmPingTimerEscCnterCheck_A	0	0	741519896	90	0	0
tb.dut.FpvSecCmPingTimerFsmCheck_A	0	0	741519896	90	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	741519896	90	0	0
tb.dut.IrqAKnownO_A	0	0	741519896	741332080	0	0
tb.dut.IrqBKnownO_A	0	0	741519896	741332080	0	0
tb.dut.IrqCKnownO_A	0	0	741519896	741332080	0	0
tb.dut.IrqDKnownO_A	0	0	741519896	741332080	0	0
tb.dut.TlAReadyKnownO_A	0	0	741519896	741332080	0	0
tb.dut.TlDValidKnownO_A	0	0	741519896	741332080	0	0
tb.dut.alert_handler_csr_assert.TlulOOBAddrErr_A	0	0	766211914	4053729	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_0_rd_A	0	0	766211914	18551	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_10_rd_A	0	0	766211914	17029	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_11_rd_A	0	0	766211914	17864	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_12_rd_A	0	0	766211914	17135	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_13_rd_A	0	0	766211914	16930	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_14_rd_A	0	0	766211914	18191	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_15_rd_A	0	0	766211914	18266	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_16_rd_A	0	0	766211914	19510	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_17_rd_A	0	0	766211914	18900	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_18_rd_A	0	0	766211914	17035	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_19_rd_A	0	0	766211914	16717	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_1_rd_A	0	0	766211914	16810	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_20_rd_A	0	0	766211914	17781	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_21_rd_A	0	0	766211914	16943	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_22_rd_A	0	0	766211914	16879	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_23_rd_A	0	0	766211914	16672	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_24_rd_A	0	0	766211914	17213	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_25_rd_A	0	0	766211914	17047	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_26_rd_A	0	0	766211914	18328	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_27_rd_A	0	0	766211914	17936	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_28_rd_A	0	0	766211914	18382	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_29_rd_A	0	0	766211914	16967	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_2_rd_A	0	0	766211914	17144	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_30_rd_A	0	0	766211914	18168	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_31_rd_A	0	0	766211914	18400	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_32_rd_A	0	0	766211914	17875	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_33_rd_A	0	0	766211914	17675	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_34_rd_A	0	0	766211914	17699	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_35_rd_A	0	0	766211914	16974	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_36_rd_A	0	0	766211914	17930	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_37_rd_A	0	0	766211914	16424	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_38_rd_A	0	0	766211914	17014	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_39_rd_A	0	0	766211914	18175	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_3_rd_A	0	0	766211914	17688	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_40_rd_A	0	0	766211914	17084	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_41_rd_A	0	0	766211914	16859	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_42_rd_A	0	0	766211914	16886	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_43_rd_A	0	0	766211914	19455	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_44_rd_A	0	0	766211914	16815	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_45_rd_A	0	0	766211914	18042	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_46_rd_A	0	0	766211914	17075	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_47_rd_A	0	0	766211914	16563	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_48_rd_A	0	0	766211914	16818	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_49_rd_A	0	0	766211914	18037	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_4_rd_A	0	0	766211914	16819	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_50_rd_A	0	0	766211914	17259	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_51_rd_A	0	0	766211914	16628	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_52_rd_A	0	0	766211914	18423	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_53_rd_A	0	0	766211914	18004	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_54_rd_A	0	0	766211914	18012	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_55_rd_A	0	0	766211914	17258	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_56_rd_A	0	0	766211914	17523	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_57_rd_A	0	0	766211914	16578	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_58_rd_A	0	0	766211914	17102	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_59_rd_A	0	0	766211914	16378	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_5_rd_A	0	0	766211914	18323	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_60_rd_A	0	0	766211914	16921	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_61_rd_A	0	0	766211914	19340	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_62_rd_A	0	0	766211914	18335	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_63_rd_A	0	0	766211914	16406	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_64_rd_A	0	0	766211914	17013	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_6_rd_A	0	0	766211914	18213	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_7_rd_A	0	0	766211914	18084	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_8_rd_A	0	0	766211914	19343	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_9_rd_A	0	0	766211914	17158	0	0
tb.dut.alert_handler_csr_assert.classa_regwen_rd_A	0	0	766211914	18327	0	0
tb.dut.alert_handler_csr_assert.classb_regwen_rd_A	0	0	766211914	19379	0	0
tb.dut.alert_handler_csr_assert.classc_regwen_rd_A	0	0	766211914	18094	0	0
tb.dut.alert_handler_csr_assert.classd_regwen_rd_A	0	0	766211914	17859	0	0
tb.dut.alert_handler_csr_assert.intr_enable_rd_A	0	0	766211914	33750	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_0_rd_A	0	0	766211914	16865	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_1_rd_A	0	0	766211914	16888	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_2_rd_A	0	0	766211914	18120	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_3_rd_A	0	0	766211914	18387	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_4_rd_A	0	0	766211914	18001	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_5_rd_A	0	0	766211914	18193	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_6_rd_A	0	0	766211914	17369	0	0
tb.dut.alert_handler_csr_assert.ping_timer_regwen_rd_A	0	0	766211914	17186	0	0
tb.dut.gen_classes[0].FpvSecCmAccuCnterCheck_A	0	0	741519896	90	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerCnterCheck_A	0	0	741519896	90	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerFsmCheck_A	0	0	741519896	90	0	0
tb.dut.gen_classes[0].u_accu.CountSaturateStable_A	0	0	741519896	4254	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigBkwd_A	0	0	741519896	259832	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigFwd_A	0	0	741519896	339603642	0	0
tb.dut.gen_classes[0].u_esc_timer.AccuFailToFsmError_A	0	0	741519896	293	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig0_A	0	0	741519896	879	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig1_A	0	0	741519896	51	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckClr_A	0	0	741519896	410	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckEn_A	0	0	741343977	255430212	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase0_A	0	0	741519896	1000	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase1_A	0	0	741519896	979	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase2_A	0	0	741519896	963	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase3_A	0	0	741519896	949	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeout0_A	0	0	741519896	1226	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt1_A	0	0	741519896	120126	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt2_A	0	0	741519896	1083	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutStTrig_A	0	0	741519896	92	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStAllEscAsserted_A	0	0	741519896	1616	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStIsTerminal_A	0	0	741519896	1346	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs.AssertConnected_A	0	0	635	635	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs_A	0	0	741519896	741332080	0	0
tb.dut.gen_classes[1].FpvSecCmAccuCnterCheck_A	0	0	741519896	90	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerCnterCheck_A	0	0	741519896	90	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerFsmCheck_A	0	0	741519896	90	0	0
tb.dut.gen_classes[1].u_accu.CountSaturateStable_A	0	0	741519896	1573	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigBkwd_A	0	0	741519896	166037	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigFwd_A	0	0	741519896	435021886	0	0
tb.dut.gen_classes[1].u_esc_timer.AccuFailToFsmError_A	0	0	741519896	349	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig0_A	0	0	741519896	546	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig1_A	0	0	741519896	22	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckClr_A	0	0	741519896	257	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckEn_A	0	0	741343977	332891933	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase0_A	0	0	741519896	623	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase1_A	0	0	741519896	611	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase2_A	0	0	741519896	602	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase3_A	0	0	741519896	587	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeout0_A	0	0	741519896	495	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt1_A	0	0	741519896	70150	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt2_A	0	0	741519896	407	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutStTrig_A	0	0	741519896	66	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStAllEscAsserted_A	0	0	741519896	1644	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStIsTerminal_A	0	0	741519896	1374	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs.AssertConnected_A	0	0	635	635	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs_A	0	0	741519896	741332080	0	0
tb.dut.gen_classes[2].FpvSecCmAccuCnterCheck_A	0	0	741519896	90	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerCnterCheck_A	0	0	741519896	90	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerFsmCheck_A	0	0	741519896	90	0	0
tb.dut.gen_classes[2].u_accu.CountSaturateStable_A	0	0	741519896	3370	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigBkwd_A	0	0	741519896	181420	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigFwd_A	0	0	741519896	430430158	0	0
tb.dut.gen_classes[2].u_esc_timer.AccuFailToFsmError_A	0	0	741519896	323	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig0_A	0	0	741519896	547	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig1_A	0	0	741519896	24	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckClr_A	0	0	741519896	232	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckEn_A	0	0	741343977	342239532	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase0_A	0	0	741519896	612	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase1_A	0	0	741519896	595	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase2_A	0	0	741519896	584	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase3_A	0	0	741519896	575	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeout0_A	0	0	741519896	788	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt1_A	0	0	741519896	100382	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt2_A	0	0	741519896	719	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutStTrig_A	0	0	741519896	45	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStAllEscAsserted_A	0	0	741519896	1608	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStIsTerminal_A	0	0	741519896	1338	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs.AssertConnected_A	0	0	635	635	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs_A	0	0	741519896	741332080	0	0
tb.dut.gen_classes[3].FpvSecCmAccuCnterCheck_A	0	0	741519896	90	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerCnterCheck_A	0	0	741519896	90	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerFsmCheck_A	0	0	741519896	90	0	0
tb.dut.gen_classes[3].u_accu.CountSaturateStable_A	0	0	741519896	4757	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigBkwd_A	0	0	741519896	183908	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigFwd_A	0	0	741519896	414291187	0	0
tb.dut.gen_classes[3].u_esc_timer.AccuFailToFsmError_A	0	0	741519896	309	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig0_A	0	0	741519896	491	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig1_A	0	0	741519896	18	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckClr_A	0	0	741519896	202	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckEn_A	0	0	741343977	341323970	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase0_A	0	0	741519896	565	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase1_A	0	0	741519896	553	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase2_A	0	0	741519896	539	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase3_A	0	0	741519896	530	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeout0_A	0	0	741519896	1216	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt1_A	0	0	741519896	128009	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt2_A	0	0	741519896	1136	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutStTrig_A	0	0	741519896	62	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStAllEscAsserted_A	0	0	741519896	1567	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStIsTerminal_A	0	0	741519896	1297	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs.AssertConnected_A	0	0	635	635	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs_A	0	0	741519896	741332080	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	766211914	145890845	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	766211914	765532312	0	0
tb.dut.tlul_assert_device.aReadyKnown_A	0	0	766211914	765532312	0	0
tb.dut.tlul_assert_device.dKnown_A	0	0	766211914	205053605	0	0
tb.dut.tlul_assert_device.dKnown_AKnownEnable	0	0	766211914	765532312	0	0
tb.dut.tlul_assert_device.dReadyKnown_A	0	0	766211914	765532312	0	0
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tb.dut.tlul_assert_device.gen_assert_final[179].noOutstandingReqsAtEndOfSim_A	0	0	840	840	0	0
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tb.dut.tlul_assert_device.gen_assert_final[180].noOutstandingReqsAtEndOfSim_A	0	0	840	840	0	0
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tb.dut.tlul_assert_device.gen_assert_final[183].noOutstandingReqsAtEndOfSim_A	0	0	840	840	0	0
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tb.dut.tlul_assert_device.gen_assert_final[185].noOutstandingReqsAtEndOfSim_A	0	0	840	840	0	0
tb.dut.tlul_assert_device.gen_assert_final[186].noOutstandingReqsAtEndOfSim_A	0	0	840	840	0	0
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tb.dut.tlul_assert_device.gen_assert_final[190].noOutstandingReqsAtEndOfSim_A	0	0	840	840	0	0
tb.dut.tlul_assert_device.gen_assert_final[191].noOutstandingReqsAtEndOfSim_A	0	0	840	840	0	0
tb.dut.tlul_assert_device.gen_assert_final[192].noOutstandingReqsAtEndOfSim_A	0	0	840	840	0	0
tb.dut.tlul_assert_device.gen_assert_final[193].noOutstandingReqsAtEndOfSim_A	0	0	840	840	0	0
tb.dut.tlul_assert_device.gen_assert_final[194].noOutstandingReqsAtEndOfSim_A	0	0	840	840	0	0
tb.dut.tlul_assert_device.gen_assert_final[195].noOutstandingReqsAtEndOfSim_A	0	0	840	840	0	0
tb.dut.tlul_assert_device.gen_assert_final[196].noOutstandingReqsAtEndOfSim_A	0	0	840	840	0	0
tb.dut.tlul_assert_device.gen_assert_final[197].noOutstandingReqsAtEndOfSim_A	0	0	840	840	0	0
tb.dut.tlul_assert_device.gen_assert_final[198].noOutstandingReqsAtEndOfSim_A	0	0	840	840	0	0
tb.dut.tlul_assert_device.gen_assert_final[199].noOutstandingReqsAtEndOfSim_A	0	0	840	840	0	0

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