Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
92.59	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	40	4	36	90.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
intr_timeout_cnt_cp	10	0	10	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	40	4	36	90.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	92	1			T5	1		T13	1		T34	1
class_index[0x1]	66	1			T19	1		T21	1		T86	1
class_index[0x2]	45	1			T13	1		T75	1		T83	2
class_index[0x3]	62	1			T1	1		T13	1		T34	1

---

Summary for Variable intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for intr_timeout_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
intr_timeout_cnt[0]	94	1			T1	1		T19	1		T13	2
intr_timeout_cnt[1]	64	1			T5	1		T21	1		T13	1
intr_timeout_cnt[2]	26	1			T83	3		T35	1		T123	1
intr_timeout_cnt[3]	19	1			T79	1		T35	1		T96	1
intr_timeout_cnt[4]	10	1			T34	1		T86	1		T79	1
intr_timeout_cnt[5]	15	1			T83	1		T93	2		T244	1
intr_timeout_cnt[6]	11	1			T62	1		T63	3		T257	1
intr_timeout_cnt[7]	7	1			T263	2		T273	1		T274	1
intr_timeout_cnt[8]	10	1			T86	1		T62	2		T93	1
intr_timeout_cnt[9]	9	1			T97	1		T68	1		T275	1

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	4	36	90.00	4

Automatically Generated Cross Bins for class_cnt_cross

Uncovered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	NUMBER	STATUS
[class_index[0x1]]	[intr_timeout_cnt[9]]	0	1	1
[class_index[0x2]]	[intr_timeout_cnt[3] , intr_timeout_cnt[4]]	--	--	2
[class_index[0x2]]	[intr_timeout_cnt[7]]	0	1	1

Covered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	intr_timeout_cnt[0]	29	1			T75	1		T83	2		T92	1
class_index[0x0]	intr_timeout_cnt[1]	27	1			T5	1		T13	1		T41	1
class_index[0x0]	intr_timeout_cnt[2]	10	1			T83	2		T35	1		T123	1
class_index[0x0]	intr_timeout_cnt[3]	6	1			T96	1		T116	1		T276	4
class_index[0x0]	intr_timeout_cnt[4]	4	1			T34	1		T277	3		-	-
class_index[0x0]	intr_timeout_cnt[5]	3	1			T83	1		T93	1		T244	1
class_index[0x0]	intr_timeout_cnt[6]	2	1			T257	1		T278	1		-	-
class_index[0x0]	intr_timeout_cnt[7]	3	1			T274	1		T279	1		T280	1
class_index[0x0]	intr_timeout_cnt[8]	2	1			T210	1		T281	1		-	-
class_index[0x0]	intr_timeout_cnt[9]	6	1			T97	1		T68	1		T282	1
class_index[0x1]	intr_timeout_cnt[0]	25	1			T19	1		T62	1		T93	1
class_index[0x1]	intr_timeout_cnt[1]	11	1			T21	1		T83	2		T102	1
class_index[0x1]	intr_timeout_cnt[2]	9	1			T83	1		T110	1		T283	1
class_index[0x1]	intr_timeout_cnt[3]	6	1			T35	1		T113	1		T68	1
class_index[0x1]	intr_timeout_cnt[4]	3	1			T79	1		T102	1		T284	1
class_index[0x1]	intr_timeout_cnt[5]	5	1			T257	1		T285	2		T286	1
class_index[0x1]	intr_timeout_cnt[6]	1	1			T287	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[7]	3	1			T263	1		T273	1		T116	1
class_index[0x1]	intr_timeout_cnt[8]	3	1			T86	1		T93	1		T282	1
class_index[0x2]	intr_timeout_cnt[0]	19	1			T13	1		T87	1		T41	1
class_index[0x2]	intr_timeout_cnt[1]	10	1			T75	1		T83	2		T112	1
class_index[0x2]	intr_timeout_cnt[2]	3	1			T288	1		T242	1		T289	1
class_index[0x2]	intr_timeout_cnt[5]	2	1			T93	1		T290	1		-	-
class_index[0x2]	intr_timeout_cnt[6]	5	1			T63	2		T208	1		T291	1
class_index[0x2]	intr_timeout_cnt[8]	4	1			T62	2		T292	1		T286	1
class_index[0x2]	intr_timeout_cnt[9]	2	1			T275	1		T212	1		-	-
class_index[0x3]	intr_timeout_cnt[0]	21	1			T1	1		T13	1		T54	1
class_index[0x3]	intr_timeout_cnt[1]	16	1			T34	1		T95	1		T112	2
class_index[0x3]	intr_timeout_cnt[2]	4	1			T63	1		T282	1		T289	1
class_index[0x3]	intr_timeout_cnt[3]	7	1			T79	1		T63	1		T293	1
class_index[0x3]	intr_timeout_cnt[4]	3	1			T86	1		T60	1		T285	1
class_index[0x3]	intr_timeout_cnt[5]	5	1			T257	1		T290	1		T292	2
class_index[0x3]	intr_timeout_cnt[6]	3	1			T62	1		T63	1		T290	1
class_index[0x3]	intr_timeout_cnt[7]	1	1			T263	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[8]	1	1			T68	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[9]	1	1			T292	1		-	-		-	-