Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	356854	1			T22	5		T174	5		T175	8
all_values[1]	356854	1			T22	5		T174	5		T175	8
all_values[2]	356854	1			T22	5		T174	5		T175	8
all_values[3]	356854	1			T22	5		T174	5		T175	8

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

710292

1

T22

11

T174

13

T175

12

auto[1]

717124

1

T22

9

T174

7

T175

20

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

849440

1

T22

12

T174

12

T175

23

auto[1]

577976

1

T22

8

T174

8

T175

9

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	102392	1			T22	3		T174	1		T175	4
all_values[0]	auto[0]	auto[1]	74805	1			T22	1		T174	2		T250	1
all_values[0]	auto[1]	auto[0]	104356	1			T174	1		T175	3		T250	2
all_values[0]	auto[1]	auto[1]	75301	1			T22	1		T174	1		T175	1
all_values[1]	auto[0]	auto[0]	106555	1			T22	1		T174	4		T175	3
all_values[1]	auto[0]	auto[1]	71430	1			T22	1		T202	3		T194	3
all_values[1]	auto[1]	auto[0]	107555	1			T22	3		T174	1		T175	5
all_values[1]	auto[1]	auto[1]	71314	1			T202	3		T190	1		T194	1
all_values[2]	auto[0]	auto[0]	106375	1			T174	2		T175	3		T250	3
all_values[2]	auto[0]	auto[1]	71214	1			T22	1		T174	2		T175	1
all_values[2]	auto[1]	auto[0]	107820	1			T22	1		T175	4		T250	1
all_values[2]	auto[1]	auto[1]	71445	1			T22	3		T174	1		T202	1
all_values[3]	auto[0]	auto[0]	106368	1			T22	3		T174	2		T250	1
all_values[3]	auto[0]	auto[1]	71153	1			T22	1		T175	1		T250	2
all_values[3]	auto[1]	auto[0]	108019	1			T22	1		T174	1		T175	1
all_values[3]	auto[1]	auto[1]	71314	1			T174	2		T175	6		T202	2