Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	4	0	4	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	356854	1			T22	5		T174	5		T175	8
all_pins[1]	356854	1			T22	5		T174	5		T175	8
all_pins[2]	356854	1			T22	5		T174	5		T175	8
all_pins[3]	356854	1			T22	5		T174	5		T175	8

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1138042	1			T22	16		T174	16		T175	25
values[0x1]	289374	1			T22	4		T174	4		T175	7
transitions[0x0=>0x1]	192576	1			T22	4		T174	4		T175	6
transitions[0x1=>0x0]	192839	1			T22	4		T174	4		T175	6

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	281553	1			T22	4		T174	4		T175	7
all_pins[0]	values[0x1]	75301	1			T22	1		T174	1		T175	1
all_pins[0]	transitions[0x0=>0x1]	74495	1			T22	1		T174	1		T250	2
all_pins[0]	transitions[0x1=>0x0]	70771	1			T174	2		T175	5		T202	1
all_pins[1]	values[0x0]	285540	1			T22	5		T174	5		T175	8
all_pins[1]	values[0x1]	71314	1			T202	3		T190	1		T194	1
all_pins[1]	transitions[0x0=>0x1]	39139	1			T202	2		T190	1		T194	1
all_pins[1]	transitions[0x1=>0x0]	43126	1			T22	1		T174	1		T175	1
all_pins[2]	values[0x0]	285409	1			T22	2		T174	4		T175	8
all_pins[2]	values[0x1]	71445	1			T22	3		T174	1		T202	1
all_pins[2]	transitions[0x0=>0x1]	39545	1			T22	3		T174	1		T202	1
all_pins[2]	transitions[0x1=>0x0]	39414	1			T202	3		T190	1		T196	4
all_pins[3]	values[0x0]	285540	1			T22	5		T174	3		T175	2
all_pins[3]	values[0x1]	71314	1			T174	2		T175	6		T202	2
all_pins[3]	transitions[0x0=>0x1]	39397	1			T174	2		T175	6		T202	2
all_pins[3]	transitions[0x1=>0x0]	39528	1			T22	3		T174	1		T202	1