Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	278	1			T22	4		T174	4		T175	7
all_values[1]	278	1			T22	4		T174	4		T175	7
all_values[2]	278	1			T22	4		T174	4		T175	7
all_values[3]	278	1			T22	4		T174	4		T175	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

624

1

T22

9

T174

9

T175

15

auto[1]

488

1

T22

7

T174

7

T175

13

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

409

1

T22

5

T174

8

T175

16

auto[1]

703

1

T22

11

T174

8

T175

12

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

648

1

T22

7

T174

12

T175

19

auto[1]

464

1

T22

9

T174

4

T175

9

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	24	0	24	100.00
Automatically Generated Cross Bins	24	0	24	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr

cp_intr_test

cp_intr_en

cp_intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_values[0]

auto[0]

auto[0]

auto[0]

55

1

T22

1

T174

1

T175

3

all_values[0]

auto[0]

auto[0]

auto[1]

26

1

T174

1

T202

2

T190

1

all_values[0]

auto[0]

auto[1]

auto[0]

34

1

T175

2

T190

1

T194

1

all_values[0]

auto[0]

auto[1]

auto[1]

36

1

T250

2

T202

1

T194

1

all_values[0]

auto[1]

auto[0]

auto[1]

74

1

T22

2

T175

2

T250

1

all_values[0]

auto[1]

auto[1]

auto[1]

53

1

T22

1

T174

2

T202

1

all_values[1]

auto[0]

auto[0]

auto[0]

65

1

T22

1

T174

2

T175

4

all_values[1]

auto[0]

auto[0]

auto[1]

21

1

T202

1

T194

2

T196

1

all_values[1]

auto[0]

auto[1]

auto[0]

57

1

T22

1

T174

2

T175

2

all_values[1]

auto[0]

auto[1]

auto[1]

28

1

T202

1

T196

2

T344

1

all_values[1]

auto[1]

auto[0]

auto[1]

61

1

T22

2

T175

1

T202

3

all_values[1]

auto[1]

auto[1]

auto[1]

46

1

T202

1

T190

2

T196

1

all_values[2]

auto[0]

auto[0]

auto[0]

58

1

T174

1

T175

2

T250

3

all_values[2]

auto[0]

auto[0]

auto[1]

32

1

T174

1

T194

1

T345

1

all_values[2]

auto[0]

auto[1]

auto[0]

44

1

T175

3

T202

3

T190

2

all_values[2]

auto[0]

auto[1]

auto[1]

37

1

T22

1

T174

1

T202

1

all_values[2]

auto[1]

auto[0]

auto[1]

67

1

T22

1

T250

1

T202

2

all_values[2]

auto[1]

auto[1]

auto[1]

40

1

T22

2

T174

1

T175

2

all_values[3]

auto[0]

auto[0]

auto[0]

61

1

T22

1

T174

2

T250

1

all_values[3]

auto[0]

auto[0]

auto[1]

32

1

T22

1

T175

2

T250

1

all_values[3]

auto[0]

auto[1]

auto[0]

35

1

T22

1

T250

1

T190

2

all_values[3]

auto[0]

auto[1]

auto[1]

27

1

T174

1

T175

1

T202

2

all_values[3]

auto[1]

auto[0]

auto[1]

72

1

T174

1

T175

1

T250

1

all_values[3]

auto[1]

auto[1]

auto[1]

51

1

T22

1

T175

3

T202

2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal