Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
accum_cnt_cp	6	0	6	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	24	0	24	100.00	100	1	1	0

Summary for Variable accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for accum_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
accum_cnt_2000	90727	1			T4	384		T6	745		T13	417
accum_cnt_1000	247628	1			T4	610		T6	1507		T13	2234
accum_cnt_100	31332	1			T4	34		T6	86		T13	243
accum_cnt_50	69288	1			T1	2		T2	10		T3	20
accum_cnt_10	174813	1			T1	34		T2	25		T3	30
accum_cnt_0	400139	1			T1	12		T2	133		T3	62

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Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	263310	1			T1	12		T2	42		T3	28
class_index[0x1]	263309	1			T1	12		T2	42		T3	28
class_index[0x2]	263309	1			T1	12		T2	42		T3	28
class_index[0x3]	263309	1			T1	12		T2	42		T3	28

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Summary for Cross class_cnt_cross

Samples crossed: class_index_cp accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for class_cnt_cross

Bins

class_index_cp	accum_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	accum_cnt_2000	28771	1			T6	520		T13	123		T54	140
class_index[0x0]	accum_cnt_1000	67117	1			T6	461		T13	537		T15	350
class_index[0x0]	accum_cnt_100	8501	1			T6	22		T13	45		T15	161
class_index[0x0]	accum_cnt_50	19496	1			T3	20		T19	2		T20	13
class_index[0x0]	accum_cnt_10	43686	1			T1	6		T2	2		T3	7
class_index[0x0]	accum_cnt_0	81749	1			T1	6		T2	40		T3	1
class_index[0x1]	accum_cnt_2000	16073	1			T13	73		T54	412		T57	192
class_index[0x1]	accum_cnt_1000	56689	1			T13	582		T15	414		T16	104
class_index[0x1]	accum_cnt_100	8825	1			T13	77		T15	142		T16	1
class_index[0x1]	accum_cnt_50	16905	1			T2	10		T19	8		T20	8
class_index[0x1]	accum_cnt_10	54245	1			T1	9		T2	23		T5	2
class_index[0x1]	accum_cnt_0	102942	1			T1	3		T2	9		T3	28
class_index[0x2]	accum_cnt_2000	22561	1			T6	225		T13	143		T34	292
class_index[0x2]	accum_cnt_1000	64812	1			T6	1046		T13	530		T52	29
class_index[0x2]	accum_cnt_100	7397	1			T6	64		T13	82		T16	55
class_index[0x2]	accum_cnt_50	16196	1			T1	2		T4	1057		T6	43
class_index[0x2]	accum_cnt_10	39493	1			T1	9		T3	1		T5	2
class_index[0x2]	accum_cnt_0	104922	1			T1	1		T2	42		T3	27
class_index[0x3]	accum_cnt_2000	23322	1			T4	384		T13	78		T34	329
class_index[0x3]	accum_cnt_1000	59010	1			T4	610		T13	585		T15	369
class_index[0x3]	accum_cnt_100	6609	1			T4	34		T13	39		T15	168
class_index[0x3]	accum_cnt_50	16691	1			T4	27		T20	11		T13	69
class_index[0x3]	accum_cnt_10	37389	1			T1	10		T3	22		T4	7
class_index[0x3]	accum_cnt_0	110526	1			T1	2		T2	42		T3	6