Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	71	0	71	100.00
Crosses	138	0	138	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
alert_index_cp	65	0	65	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	130	0	130	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for alert_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	5171	1			T2	1		T7	1		T54	163
alert[0x1]	4107	1			T2	1		T16	2		T54	1302
alert[0x2]	5279	1			T2	2		T54	89		T38	1
alert[0x3]	5840	1			T2	1		T54	1278		T75	33
alert[0x4]	3896	1			T2	1		T13	1		T8	1
alert[0x5]	6700	1			T78	1		T248	1570		T49	20
alert[0x6]	5067	1			T5	1		T8	1		T51	112
alert[0x7]	5666	1			T75	22		T248	8		T49	15
alert[0x8]	7102	1			T8	1		T16	6		T79	59
alert[0x9]	12206	1			T2	1		T14	1		T36	1
alert[0xa]	4225	1			T2	2		T13	2		T8	1
alert[0xb]	2074	1			T79	10		T248	153		T38	5
alert[0xc]	17253	1			T13	1		T8	1		T54	432
alert[0xd]	5984	1			T5	2		T13	31		T51	9
alert[0xe]	2488	1			T7	1		T8	1		T54	49
alert[0xf]	8792	1			T51	2		T54	364		T79	7
alert[0x10]	3596	1			T2	1		T79	102		T37	243
alert[0x11]	6086	1			T2	1		T8	1		T54	91
alert[0x12]	5378	1			T13	1		T54	1379		T75	54
alert[0x13]	5416	1			T51	1		T75	60		T81	2
alert[0x14]	3316	1			T16	2		T79	90		T118	1
alert[0x15]	5691	1			T13	17		T16	3		T75	1
alert[0x16]	4909	1			T79	878		T37	25		T248	3
alert[0x17]	5108	1			T79	164		T248	313		T132	1
alert[0x18]	9420	1			T7	1		T37	9		T39	281
alert[0x19]	4195	1			T16	3		T75	13		T86	2
alert[0x1a]	4714	1			T51	2		T75	128		T49	130
alert[0x1b]	11033	1			T75	2		T59	2		T37	394
alert[0x1c]	3864	1			T13	2		T248	67		T35	4
alert[0x1d]	2734	1			T7	1		T40	1		T54	528
alert[0x1e]	10366	1			T7	1		T8	2		T16	50
alert[0x1f]	15650	1			T13	2		T73	1		T248	46
alert[0x20]	3591	1			T13	1		T54	740		T79	3
alert[0x21]	5646	1			T13	1		T8	1		T51	1
alert[0x22]	4684	1			T7	2		T14	1		T16	1
alert[0x23]	10804	1			T7	1		T13	1		T8	1
alert[0x24]	5583	1			T75	118		T49	6		T35	10
alert[0x25]	4402	1			T51	3		T75	9		T79	1
alert[0x26]	4806	1			T37	2		T248	1800		T49	23
alert[0x27]	5346	1			T7	1		T8	1		T14	1
alert[0x28]	3783	1			T8	1		T15	1		T75	205
alert[0x29]	4971	1			T2	1		T13	21		T51	9
alert[0x2a]	2233	1			T2	1		T14	1		T15	1
alert[0x2b]	3832	1			T75	633		T79	97		T36	1
alert[0x2c]	3981	1			T2	2		T37	179		T248	160
alert[0x2d]	2444	1			T14	1		T79	132		T83	13
alert[0x2e]	6265	1			T2	1		T7	1		T13	1
alert[0x2f]	4863	1			T2	1		T75	54		T78	1
alert[0x30]	6837	1			T7	1		T34	3		T78	1
alert[0x31]	6252	1			T8	1		T16	2		T54	551
alert[0x32]	1883	1			T7	1		T8	1		T79	11
alert[0x33]	3620	1			T7	1		T13	2		T54	44
alert[0x34]	9373	1			T34	1		T54	21		T75	50
alert[0x35]	1639	1			T13	3		T54	16		T75	38
alert[0x36]	3951	1			T13	1		T75	83		T83	132
alert[0x37]	4252	1			T51	21		T54	46		T79	43
alert[0x38]	5719	1			T16	90		T75	13		T79	10
alert[0x39]	3493	1			T13	6		T8	1		T14	1
alert[0x3a]	7553	1			T2	1		T14	1		T83	3
alert[0x3b]	4500	1			T2	1		T54	29		T75	24
alert[0x3c]	6798	1			T7	1		T51	3		T59	47
alert[0x3d]	3698	1			T16	2		T54	40		T79	92
alert[0x3e]	3187	1			T8	1		T16	5		T34	9
alert[0x3f]	4217	1			T13	12		T8	1		T54	317
alert[0x40]	2348	1			T2	1		T54	219		T79	6

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	84247	1			T2	2		T8	2		T16	8
class_i[0x1]	54576	1			T2	18		T7	1		T13	7
class_i[0x2]	119170	1			T5	3		T13	82		T8	12
class_i[0x3]	101887	1			T7	13		T13	17		T8	4

---

Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

alert_integrity_fail

359241

1

T5

3

T13

106

T51

172

alert_ping_fail

639

1

T2

20

T7

14

T8

19

---

Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	0	130	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	alert_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	alert[0x0]	5165	1			T54	163		T133	1		T83	29
alert_integrity_fail	alert[0x1]	4098	1			T16	2		T54	1302		T75	6
alert_integrity_fail	alert[0x2]	5271	1			T54	89		T38	1		T49	10
alert_integrity_fail	alert[0x3]	5835	1			T54	1278		T75	33		T248	1
alert_integrity_fail	alert[0x4]	3889	1			T13	1		T54	170		T248	84
alert_integrity_fail	alert[0x5]	6693	1			T248	1570		T49	20		T35	16
alert_integrity_fail	alert[0x6]	5055	1			T5	1		T51	112		T248	89
alert_integrity_fail	alert[0x7]	5655	1			T75	22		T248	8		T49	15
alert_integrity_fail	alert[0x8]	7091	1			T16	6		T79	59		T49	55
alert_integrity_fail	alert[0x9]	12192	1			T37	26		T49	234		T39	74
alert_integrity_fail	alert[0xa]	4213	1			T13	2		T54	32		T79	25
alert_integrity_fail	alert[0xb]	2072	1			T79	10		T248	153		T38	5
alert_integrity_fail	alert[0xc]	17245	1			T13	1		T54	432		T75	399
alert_integrity_fail	alert[0xd]	5968	1			T5	2		T13	31		T51	9
alert_integrity_fail	alert[0xe]	2478	1			T54	49		T79	13		T81	6
alert_integrity_fail	alert[0xf]	8781	1			T51	2		T54	364		T79	7
alert_integrity_fail	alert[0x10]	3585	1			T79	102		T37	243		T38	3
alert_integrity_fail	alert[0x11]	6079	1			T54	91		T75	420		T79	2
alert_integrity_fail	alert[0x12]	5370	1			T13	1		T54	1379		T75	54
alert_integrity_fail	alert[0x13]	5404	1			T51	1		T75	60		T81	2
alert_integrity_fail	alert[0x14]	3298	1			T16	2		T79	90		T37	89
alert_integrity_fail	alert[0x15]	5682	1			T13	17		T16	3		T75	1
alert_integrity_fail	alert[0x16]	4893	1			T79	878		T37	25		T248	3
alert_integrity_fail	alert[0x17]	5101	1			T79	164		T248	313		T91	2
alert_integrity_fail	alert[0x18]	9409	1			T37	9		T39	281		T62	5361
alert_integrity_fail	alert[0x19]	4187	1			T16	3		T75	13		T86	2
alert_integrity_fail	alert[0x1a]	4705	1			T51	2		T75	128		T49	130
alert_integrity_fail	alert[0x1b]	11021	1			T75	2		T59	2		T37	394
alert_integrity_fail	alert[0x1c]	3852	1			T13	2		T248	67		T35	4
alert_integrity_fail	alert[0x1d]	2723	1			T54	528		T49	149		T35	85
alert_integrity_fail	alert[0x1e]	10355	1			T16	50		T54	57		T79	108
alert_integrity_fail	alert[0x1f]	15635	1			T13	2		T248	46		T296	3062
alert_integrity_fail	alert[0x20]	3582	1			T13	1		T54	740		T79	3
alert_integrity_fail	alert[0x21]	5631	1			T13	1		T51	1		T54	264
alert_integrity_fail	alert[0x22]	4669	1			T16	1		T54	369		T59	1
alert_integrity_fail	alert[0x23]	10799	1			T13	1		T51	8		T54	468
alert_integrity_fail	alert[0x24]	5575	1			T75	118		T49	6		T35	10
alert_integrity_fail	alert[0x25]	4392	1			T51	3		T75	9		T79	1
alert_integrity_fail	alert[0x26]	4797	1			T37	2		T248	1800		T49	23
alert_integrity_fail	alert[0x27]	5336	1			T16	2		T54	305		T79	1
alert_integrity_fail	alert[0x28]	3768	1			T75	205		T49	14		T35	36
alert_integrity_fail	alert[0x29]	4964	1			T13	21		T51	9		T34	5
alert_integrity_fail	alert[0x2a]	2220	1			T75	364		T79	7		T59	2
alert_integrity_fail	alert[0x2b]	3824	1			T75	633		T79	97		T248	100
alert_integrity_fail	alert[0x2c]	3963	1			T37	179		T248	160		T35	4
alert_integrity_fail	alert[0x2d]	2436	1			T79	132		T83	13		T49	394
alert_integrity_fail	alert[0x2e]	6251	1			T13	1		T54	654		T248	164
alert_integrity_fail	alert[0x2f]	4857	1			T75	54		T79	188		T49	237
alert_integrity_fail	alert[0x30]	6822	1			T34	3		T248	281		T35	3
alert_integrity_fail	alert[0x31]	6243	1			T16	2		T54	551		T49	11
alert_integrity_fail	alert[0x32]	1871	1			T79	11		T107	308		T123	55
alert_integrity_fail	alert[0x33]	3610	1			T13	2		T54	44		T133	4
alert_integrity_fail	alert[0x34]	9369	1			T34	1		T54	21		T75	50
alert_integrity_fail	alert[0x35]	1630	1			T13	3		T54	16		T75	38
alert_integrity_fail	alert[0x36]	3942	1			T13	1		T75	83		T83	132
alert_integrity_fail	alert[0x37]	4246	1			T51	21		T54	46		T79	43
alert_integrity_fail	alert[0x38]	5710	1			T16	90		T75	13		T79	10
alert_integrity_fail	alert[0x39]	3483	1			T13	6		T51	1		T54	551
alert_integrity_fail	alert[0x3a]	7545	1			T83	3		T37	10		T49	8
alert_integrity_fail	alert[0x3b]	4492	1			T54	29		T75	24		T49	7
alert_integrity_fail	alert[0x3c]	6784	1			T51	3		T59	47		T62	4
alert_integrity_fail	alert[0x3d]	3690	1			T16	2		T54	40		T79	92
alert_integrity_fail	alert[0x3e]	3182	1			T16	5		T34	9		T75	651
alert_integrity_fail	alert[0x3f]	4214	1			T13	12		T54	317		T49	9
alert_integrity_fail	alert[0x40]	2344	1			T54	219		T79	6		T91	1
alert_ping_fail	alert[0x0]	6	1			T2	1		T7	1		T297	1
alert_ping_fail	alert[0x1]	9	1			T2	1		T270	1		T298	1
alert_ping_fail	alert[0x2]	8	1			T2	2		T270	1		T299	1
alert_ping_fail	alert[0x3]	5	1			T2	1		T300	2		T301	1
alert_ping_fail	alert[0x4]	7	1			T2	1		T8	1		T132	1
alert_ping_fail	alert[0x5]	7	1			T78	1		T302	1		T299	1
alert_ping_fail	alert[0x6]	12	1			T8	1		T269	1		T298	1
alert_ping_fail	alert[0x7]	11	1			T301	1		T303	1		T304	1
alert_ping_fail	alert[0x8]	11	1			T8	1		T262	2		T270	2
alert_ping_fail	alert[0x9]	14	1			T2	1		T14	1		T36	1
alert_ping_fail	alert[0xa]	12	1			T2	2		T8	1		T295	1
alert_ping_fail	alert[0xb]	2	1			T304	1		T305	1		-	-
alert_ping_fail	alert[0xc]	8	1			T8	1		T270	1		T298	1
alert_ping_fail	alert[0xd]	16	1			T300	2		T270	1		T306	2
alert_ping_fail	alert[0xe]	10	1			T7	1		T8	1		T270	1
alert_ping_fail	alert[0xf]	11	1			T270	2		T307	1		T308	1
alert_ping_fail	alert[0x10]	11	1			T2	1		T298	1		T304	1
alert_ping_fail	alert[0x11]	7	1			T2	1		T8	1		T300	1
alert_ping_fail	alert[0x12]	8	1			T298	1		T301	1		T304	1
alert_ping_fail	alert[0x13]	12	1			T300	1		T301	1		T303	1
alert_ping_fail	alert[0x14]	18	1			T118	1		T298	1		T309	2
alert_ping_fail	alert[0x15]	9	1			T300	1		T310	1		T311	1
alert_ping_fail	alert[0x16]	16	1			T312	1		T304	1		T313	1
alert_ping_fail	alert[0x17]	7	1			T132	1		T298	1		T294	1
alert_ping_fail	alert[0x18]	11	1			T7	1		T294	1		T299	1
alert_ping_fail	alert[0x19]	8	1			T298	1		T301	1		T306	1
alert_ping_fail	alert[0x1a]	9	1			T314	1		T315	1		T316	1
alert_ping_fail	alert[0x1b]	12	1			T132	2		T298	1		T301	1
alert_ping_fail	alert[0x1c]	12	1			T301	1		T304	1		T313	1
alert_ping_fail	alert[0x1d]	11	1			T7	1		T40	1		T317	1
alert_ping_fail	alert[0x1e]	11	1			T7	1		T8	2		T36	1
alert_ping_fail	alert[0x1f]	15	1			T73	1		T298	1		T302	1
alert_ping_fail	alert[0x20]	9	1			T300	1		T307	1		T304	2
alert_ping_fail	alert[0x21]	15	1			T8	1		T118	1		T270	1
alert_ping_fail	alert[0x22]	15	1			T7	2		T14	1		T301	1
alert_ping_fail	alert[0x23]	5	1			T7	1		T8	1		T318	2
alert_ping_fail	alert[0x24]	8	1			T300	1		T301	1		T319	1
alert_ping_fail	alert[0x25]	10	1			T298	1		T301	1		T307	1
alert_ping_fail	alert[0x26]	9	1			T132	1		T299	1		T317	2
alert_ping_fail	alert[0x27]	10	1			T7	1		T8	1		T14	1
alert_ping_fail	alert[0x28]	15	1			T8	1		T15	1		T132	1
alert_ping_fail	alert[0x29]	7	1			T2	1		T297	1		T132	1
alert_ping_fail	alert[0x2a]	13	1			T2	1		T14	1		T15	1
alert_ping_fail	alert[0x2b]	8	1			T36	1		T300	1		T270	1
alert_ping_fail	alert[0x2c]	18	1			T2	2		T312	1		T299	1
alert_ping_fail	alert[0x2d]	8	1			T14	1		T319	1		T320	1
alert_ping_fail	alert[0x2e]	14	1			T2	1		T7	1		T8	1
alert_ping_fail	alert[0x2f]	6	1			T2	1		T78	1		T301	2
alert_ping_fail	alert[0x30]	15	1			T7	1		T78	1		T249	1
alert_ping_fail	alert[0x31]	9	1			T8	1		T300	1		T299	1
alert_ping_fail	alert[0x32]	12	1			T7	1		T8	1		T36	1
alert_ping_fail	alert[0x33]	10	1			T7	1		T300	1		T302	1
alert_ping_fail	alert[0x34]	4	1			T321	1		T322	2		T323	1
alert_ping_fail	alert[0x35]	9	1			T299	1		T324	1		T308	1
alert_ping_fail	alert[0x36]	9	1			T299	1		T319	1		T304	1
alert_ping_fail	alert[0x37]	6	1			T298	1		T319	1		T308	1
alert_ping_fail	alert[0x38]	9	1			T307	1		T304	1		T320	1
alert_ping_fail	alert[0x39]	10	1			T8	1		T14	1		T308	1
alert_ping_fail	alert[0x3a]	8	1			T2	1		T14	1		T300	1
alert_ping_fail	alert[0x3b]	8	1			T2	1		T298	1		T317	2
alert_ping_fail	alert[0x3c]	14	1			T7	1		T36	1		T300	1
alert_ping_fail	alert[0x3d]	8	1			T300	1		T298	1		T324	1
alert_ping_fail	alert[0x3e]	5	1			T8	1		T321	1		T325	1
alert_ping_fail	alert[0x3f]	3	1			T8	1		T302	1		T314	1
alert_ping_fail	alert[0x40]	4	1			T2	1		T270	1		T316	1

---

Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	class_i[0x0]	84110	1			T16	8		T34	8		T54	10686
alert_integrity_fail	class_i[0x1]	54430	1			T13	7		T16	158		T133	3
alert_integrity_fail	class_i[0x2]	119010	1			T5	3		T13	82		T34	10
alert_integrity_fail	class_i[0x3]	101691	1			T13	17		T51	172		T16	2
alert_ping_fail	class_i[0x0]	137	1			T2	2		T8	2		T40	1
alert_ping_fail	class_i[0x1]	146	1			T2	18		T7	1		T8	1
alert_ping_fail	class_i[0x2]	160	1			T8	12		T14	1		T73	1
alert_ping_fail	class_i[0x3]	196	1			T7	13		T8	4		T14	6