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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.64 99.99 98.69 99.97 100.00 100.00 99.38 99.48


Total test records in report: 840
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T775 /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.3083473524 Jan 24 01:10:00 PM PST 24 Jan 24 01:10:40 PM PST 24 164512143 ps
T776 /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.1613683541 Jan 24 01:10:13 PM PST 24 Jan 24 01:10:50 PM PST 24 30742633 ps
T777 /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.69086360 Jan 24 01:11:31 PM PST 24 Jan 24 01:12:13 PM PST 24 9584810 ps
T178 /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.1776339583 Jan 24 01:09:55 PM PST 24 Jan 24 01:10:40 PM PST 24 305245671 ps
T778 /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.2992952510 Jan 24 01:09:30 PM PST 24 Jan 24 01:16:10 PM PST 24 11843561699 ps
T779 /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.1747002755 Jan 24 01:11:17 PM PST 24 Jan 24 01:11:52 PM PST 24 16340692 ps
T150 /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.3233929763 Jan 24 01:10:14 PM PST 24 Jan 24 01:20:28 PM PST 24 8585788572 ps
T780 /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.3063199804 Jan 24 01:09:56 PM PST 24 Jan 24 01:10:31 PM PST 24 8664477 ps
T781 /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.1114369775 Jan 24 01:10:49 PM PST 24 Jan 24 01:12:15 PM PST 24 723246571 ps
T782 /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.1679136236 Jan 24 01:10:05 PM PST 24 Jan 24 01:10:46 PM PST 24 495033007 ps
T783 /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.328042374 Jan 24 01:09:35 PM PST 24 Jan 24 01:12:36 PM PST 24 4329361482 ps
T162 /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.2747700887 Jan 24 01:09:25 PM PST 24 Jan 24 01:25:19 PM PST 24 12414247068 ps
T784 /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.3868964703 Jan 24 01:10:30 PM PST 24 Jan 24 01:11:15 PM PST 24 30706992 ps
T785 /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.1510676744 Jan 24 01:09:50 PM PST 24 Jan 24 01:10:28 PM PST 24 9731981 ps
T152 /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.3944502108 Jan 24 01:09:50 PM PST 24 Jan 24 01:13:29 PM PST 24 6011233110 ps
T786 /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.21661058 Jan 24 01:10:06 PM PST 24 Jan 24 01:10:55 PM PST 24 1081416456 ps
T787 /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.1124620682 Jan 24 01:09:31 PM PST 24 Jan 24 01:10:25 PM PST 24 1741976018 ps
T788 /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.2906532246 Jan 24 01:10:59 PM PST 24 Jan 24 01:11:37 PM PST 24 17611058 ps
T789 /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.1344820679 Jan 24 01:10:42 PM PST 24 Jan 24 01:11:30 PM PST 24 82851458 ps
T165 /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.3072833514 Jan 24 01:10:50 PM PST 24 Jan 24 01:14:10 PM PST 24 2329985018 ps
T164 /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.377410961 Jan 24 01:10:14 PM PST 24 Jan 24 01:12:44 PM PST 24 1602134957 ps
T790 /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.2744004732 Jan 24 01:11:11 PM PST 24 Jan 24 01:11:45 PM PST 24 20183576 ps
T168 /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.744223819 Jan 24 01:10:32 PM PST 24 Jan 24 01:18:47 PM PST 24 12329428867 ps
T791 /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.2747785484 Jan 24 01:10:13 PM PST 24 Jan 24 01:10:50 PM PST 24 15686709 ps
T792 /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.1112540441 Jan 24 01:28:51 PM PST 24 Jan 24 01:29:12 PM PST 24 9523271 ps
T793 /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.3964598012 Jan 24 01:11:03 PM PST 24 Jan 24 01:11:45 PM PST 24 960399107 ps
T794 /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.2270325175 Jan 24 01:10:15 PM PST 24 Jan 24 01:10:58 PM PST 24 50380790 ps
T348 /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.96770711 Jan 24 01:35:47 PM PST 24 Jan 24 01:41:44 PM PST 24 2481387830 ps
T795 /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.1345067354 Jan 24 01:10:30 PM PST 24 Jan 24 01:11:13 PM PST 24 11817552 ps
T796 /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.1309550005 Jan 24 01:11:11 PM PST 24 Jan 24 01:11:45 PM PST 24 12114670 ps
T160 /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.3194545592 Jan 24 01:47:12 PM PST 24 Jan 24 01:52:08 PM PST 24 3968350434 ps
T169 /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.321984937 Jan 24 01:10:59 PM PST 24 Jan 24 01:16:21 PM PST 24 4924399264 ps
T797 /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.4269445917 Jan 24 01:11:18 PM PST 24 Jan 24 01:11:53 PM PST 24 10362582 ps
T798 /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.1220804817 Jan 24 01:10:30 PM PST 24 Jan 24 01:11:17 PM PST 24 66309885 ps
T185 /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.1542805206 Jan 24 01:09:43 PM PST 24 Jan 24 01:10:23 PM PST 24 64511915 ps
T799 /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.2455269618 Jan 24 01:09:39 PM PST 24 Jan 24 01:10:35 PM PST 24 258220839 ps
T800 /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.3153759853 Jan 24 01:11:05 PM PST 24 Jan 24 01:11:46 PM PST 24 73940387 ps
T801 /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.4147917771 Jan 24 01:10:20 PM PST 24 Jan 24 01:11:16 PM PST 24 486482861 ps
T802 /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.3551971740 Jan 24 01:09:30 PM PST 24 Jan 24 01:11:23 PM PST 24 569306199 ps
T347 /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.2436842069 Jan 24 01:10:13 PM PST 24 Jan 24 01:15:38 PM PST 24 8996288781 ps
T803 /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.1841652576 Jan 24 01:11:14 PM PST 24 Jan 24 01:11:48 PM PST 24 9470407 ps
T804 /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.3558981812 Jan 24 01:10:41 PM PST 24 Jan 24 01:11:26 PM PST 24 19622526 ps
T805 /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.4258292446 Jan 24 01:11:18 PM PST 24 Jan 24 01:11:54 PM PST 24 14134963 ps
T806 /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.2548126026 Jan 24 01:09:31 PM PST 24 Jan 24 01:10:15 PM PST 24 262907340 ps
T172 /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.3117928202 Jan 24 01:10:16 PM PST 24 Jan 24 01:13:36 PM PST 24 9468618412 ps
T807 /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.3225921143 Jan 24 01:09:31 PM PST 24 Jan 24 01:10:19 PM PST 24 397440923 ps
T808 /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.2817101339 Jan 24 01:10:58 PM PST 24 Jan 24 01:11:40 PM PST 24 30709501 ps
T809 /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.3868029758 Jan 24 01:11:01 PM PST 24 Jan 24 01:11:38 PM PST 24 12192751 ps
T170 /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.4046860966 Jan 24 01:11:02 PM PST 24 Jan 24 01:29:24 PM PST 24 15725364381 ps
T171 /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.964399814 Jan 24 01:09:31 PM PST 24 Jan 24 01:28:28 PM PST 24 15544500714 ps
T810 /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.2486048595 Jan 24 01:10:08 PM PST 24 Jan 24 01:10:44 PM PST 24 15554053 ps
T811 /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.1422092723 Jan 24 01:09:54 PM PST 24 Jan 24 01:10:34 PM PST 24 32773256 ps
T812 /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.3669514126 Jan 24 01:11:12 PM PST 24 Jan 24 01:11:45 PM PST 24 15968357 ps
T813 /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.3947816137 Jan 24 01:09:39 PM PST 24 Jan 24 01:14:17 PM PST 24 18199243546 ps
T814 /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.722050613 Jan 24 01:10:16 PM PST 24 Jan 24 01:11:01 PM PST 24 186172301 ps
T815 /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.2685901878 Jan 24 01:10:00 PM PST 24 Jan 24 01:10:55 PM PST 24 1034860014 ps
T179 /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.1751920431 Jan 24 01:10:58 PM PST 24 Jan 24 01:11:38 PM PST 24 93220953 ps
T816 /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.1848956404 Jan 24 01:09:26 PM PST 24 Jan 24 01:10:14 PM PST 24 133051029 ps
T182 /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.1619847774 Jan 24 01:10:17 PM PST 24 Jan 24 01:11:39 PM PST 24 1291140301 ps
T817 /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.2787258205 Jan 24 01:10:30 PM PST 24 Jan 24 01:11:53 PM PST 24 1288455598 ps
T818 /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.3703103397 Jan 24 01:10:39 PM PST 24 Jan 24 01:11:41 PM PST 24 515194868 ps
T819 /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.1699290840 Jan 24 01:10:01 PM PST 24 Jan 24 01:10:38 PM PST 24 37425045 ps
T820 /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.3744838258 Jan 24 01:11:18 PM PST 24 Jan 24 01:11:53 PM PST 24 18096583 ps
T821 /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.763996287 Jan 24 01:11:12 PM PST 24 Jan 24 01:11:45 PM PST 24 6436808 ps
T822 /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.2770370948 Jan 24 03:20:47 PM PST 24 Jan 24 03:21:06 PM PST 24 124182943 ps
T187 /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.1588123640 Jan 24 01:09:22 PM PST 24 Jan 24 01:10:03 PM PST 24 129485923 ps
T823 /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.601242351 Jan 24 01:09:52 PM PST 24 Jan 24 01:10:54 PM PST 24 1460139384 ps
T824 /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.1858626863 Jan 24 01:10:41 PM PST 24 Jan 24 01:13:06 PM PST 24 1072537851 ps
T825 /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.2929272285 Jan 24 01:10:40 PM PST 24 Jan 24 01:11:29 PM PST 24 141550123 ps
T826 /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.3830859086 Jan 24 01:10:29 PM PST 24 Jan 24 01:11:23 PM PST 24 332121737 ps
T827 /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.1753514335 Jan 24 01:10:15 PM PST 24 Jan 24 01:11:04 PM PST 24 87001086 ps
T828 /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.3907856634 Jan 24 01:09:39 PM PST 24 Jan 24 01:10:19 PM PST 24 107629056 ps
T829 /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.2015914891 Jan 24 01:10:14 PM PST 24 Jan 24 01:10:56 PM PST 24 70110572 ps
T166 /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.644664663 Jan 24 01:09:21 PM PST 24 Jan 24 01:18:53 PM PST 24 97416246941 ps
T830 /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.3369051329 Jan 24 01:09:39 PM PST 24 Jan 24 01:10:18 PM PST 24 7223320 ps
T831 /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.3765623615 Jan 24 01:11:00 PM PST 24 Jan 24 01:12:21 PM PST 24 1436609730 ps
T832 /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.316780257 Jan 24 01:10:01 PM PST 24 Jan 24 01:10:36 PM PST 24 14547828 ps
T833 /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.4167416089 Jan 24 01:11:02 PM PST 24 Jan 24 01:11:42 PM PST 24 912032348 ps
T834 /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.1894707081 Jan 24 01:10:39 PM PST 24 Jan 24 01:11:27 PM PST 24 243648918 ps
T181 /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.1564861837 Jan 24 01:10:39 PM PST 24 Jan 24 01:11:25 PM PST 24 170725407 ps
T835 /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.2363739166 Jan 24 01:10:42 PM PST 24 Jan 24 01:11:25 PM PST 24 11058349 ps
T836 /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.734070045 Jan 24 01:42:55 PM PST 24 Jan 24 01:48:05 PM PST 24 8572528220 ps
T183 /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.2982259332 Jan 24 01:10:40 PM PST 24 Jan 24 01:12:29 PM PST 24 3717836240 ps
T346 /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.24574529 Jan 24 01:10:01 PM PST 24 Jan 24 01:26:25 PM PST 24 28285304373 ps
T837 /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.1395248137 Jan 24 01:11:00 PM PST 24 Jan 24 01:11:37 PM PST 24 11416015 ps
T838 /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.2541474169 Jan 24 01:10:13 PM PST 24 Jan 24 01:10:59 PM PST 24 147010661 ps
T180 /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.3951006792 Jan 24 01:11:06 PM PST 24 Jan 24 01:12:23 PM PST 24 1199974327 ps
T159 /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.105999183 Jan 24 01:10:16 PM PST 24 Jan 24 01:13:29 PM PST 24 4073929492 ps
T839 /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.2925111694 Jan 24 01:10:49 PM PST 24 Jan 24 01:11:39 PM PST 24 271067460 ps
T840 /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.115435194 Jan 24 01:10:16 PM PST 24 Jan 24 01:11:21 PM PST 24 1605761112 ps

Test location /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.1243270348
Short name T12
Test name
Test status
Simulation time 378960253 ps
CPU time 14.16 seconds
Started Jan 24 01:10:07 PM PST 24
Finished Jan 24 01:10:55 PM PST 24
Peak memory 244708 kb
Host smart-b9ec76e0-534f-4132-b62d-2a18abe4dc57
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1243270348 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_same_csr_out
standing.1243270348
Directory /workspace/8.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/default/43.alert_handler_entropy.1476935137
Short name T4
Test name
Test status
Simulation time 56632962880 ps
CPU time 2028.53 seconds
Started Jan 24 01:49:32 PM PST 24
Finished Jan 24 02:23:22 PM PST 24
Peak memory 281364 kb
Host smart-96b94305-1372-414d-ba34-fda623dfbeaa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476935137 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_entropy.1476935137
Directory /workspace/43.alert_handler_entropy/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.4147547988
Short name T23
Test name
Test status
Simulation time 2726101007 ps
CPU time 70.57 seconds
Started Jan 24 01:10:29 PM PST 24
Finished Jan 24 01:12:21 PM PST 24
Peak memory 240716 kb
Host smart-a45a599d-c5bb-4c05-b42a-d90614eadab5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4147547988 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_intg_err.4147547988
Directory /workspace/14.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all.795633080
Short name T13
Test name
Test status
Simulation time 14615831245 ps
CPU time 1241.24 seconds
Started Jan 24 01:44:15 PM PST 24
Finished Jan 24 02:05:15 PM PST 24
Peak memory 288516 kb
Host smart-6a27d512-b6c5-4903-a88c-061fae3b8b60
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795633080 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_han
dler_stress_all.795633080
Directory /workspace/28.alert_handler_stress_all/latest

Test location /workspace/coverage/default/3.alert_handler_sec_cm.752072762
Short name T42
Test name
Test status
Simulation time 1499074516 ps
CPU time 20.94 seconds
Started Jan 24 01:39:22 PM PST 24
Finished Jan 24 01:39:48 PM PST 24
Peak memory 272552 kb
Host smart-6f11d3b9-fc7e-411c-a9f4-45927476f944
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=752072762 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sec_cm.752072762
Directory /workspace/3.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/14.alert_handler_entropy_stress.3073597104
Short name T213
Test name
Test status
Simulation time 306252392 ps
CPU time 9.47 seconds
Started Jan 24 02:23:47 PM PST 24
Finished Jan 24 02:24:16 PM PST 24
Peak memory 239844 kb
Host smart-0b334061-e0b0-4d92-92bc-38546eb33e4e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3073597104 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy_stress.3073597104
Directory /workspace/14.alert_handler_entropy_stress/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.125279712
Short name T138
Test name
Test status
Simulation time 14798879762 ps
CPU time 189.54 seconds
Started Jan 24 01:26:02 PM PST 24
Finished Jan 24 01:30:04 PM PST 24
Peak memory 273400 kb
Host smart-d3f26094-5eda-4bbd-b87f-94a7627d4f2e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=125279712 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shadow_reg_error
s.125279712
Directory /workspace/4.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all_with_rand_reset.3596375276
Short name T16
Test name
Test status
Simulation time 26387590675 ps
CPU time 1929.79 seconds
Started Jan 24 01:46:57 PM PST 24
Finished Jan 24 02:19:10 PM PST 24
Peak memory 289288 kb
Host smart-417bc007-2fec-4551-8e2e-f239ecb3fdfe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596375276 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 37.alert_handler_stress_all_with_rand_reset.3596375276
Directory /workspace/37.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.alert_handler_lpg.2891323034
Short name T249
Test name
Test status
Simulation time 24813330302 ps
CPU time 1474.11 seconds
Started Jan 24 01:42:47 PM PST 24
Finished Jan 24 02:08:00 PM PST 24
Peak memory 264516 kb
Host smart-141ea104-421c-4a6d-a8ec-936de10b5265
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891323034 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg.2891323034
Directory /workspace/24.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.1125784309
Short name T26
Test name
Test status
Simulation time 5339748392 ps
CPU time 655.76 seconds
Started Jan 24 01:09:43 PM PST 24
Finished Jan 24 01:21:15 PM PST 24
Peak memory 273152 kb
Host smart-f611a981-9bbf-4a88-a623-1a1abb830d13
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125784309 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.alert_handler_shadow_reg_errors_with_csr_rw.1125784309
Directory /workspace/3.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.2811076255
Short name T196
Test name
Test status
Simulation time 11361518 ps
CPU time 1.37 seconds
Started Jan 24 01:09:26 PM PST 24
Finished Jan 24 01:10:07 PM PST 24
Peak memory 236520 kb
Host smart-55fb1a83-4ec6-4239-b86b-8b84d8190fcb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2811076255 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_intr_test.2811076255
Directory /workspace/1.alert_handler_intr_test/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all.1331688486
Short name T62
Test name
Test status
Simulation time 57959980465 ps
CPU time 3331.35 seconds
Started Jan 24 01:42:53 PM PST 24
Finished Jan 24 02:39:02 PM PST 24
Peak memory 297336 kb
Host smart-47cd6dcb-08d1-4bce-b138-b8a49f8e19cc
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331688486 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_ha
ndler_stress_all.1331688486
Directory /workspace/24.alert_handler_stress_all/latest

Test location /workspace/coverage/default/32.alert_handler_ping_timeout.1575562736
Short name T8
Test name
Test status
Simulation time 167696577900 ps
CPU time 699.33 seconds
Started Jan 24 01:45:06 PM PST 24
Finished Jan 24 01:56:57 PM PST 24
Peak memory 246600 kb
Host smart-7c1ce090-3642-4595-a22e-d06792ce24ef
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575562736 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_ping_timeout.1575562736
Directory /workspace/32.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.2926829010
Short name T149
Test name
Test status
Simulation time 59135890289 ps
CPU time 1086.72 seconds
Started Jan 24 01:10:37 PM PST 24
Finished Jan 24 01:29:26 PM PST 24
Peak memory 265536 kb
Host smart-9c68d45a-f141-48e6-886c-65541a775273
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926829010 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 15.alert_handler_shadow_reg_errors_with_csr_rw.2926829010
Directory /workspace/15.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.4190821103
Short name T158
Test name
Test status
Simulation time 8883031182 ps
CPU time 601.69 seconds
Started Jan 24 01:10:37 PM PST 24
Finished Jan 24 01:21:21 PM PST 24
Peak memory 265580 kb
Host smart-c41820e5-ff8b-48e0-892b-deba578b6ccb
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190821103 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 16.alert_handler_shadow_reg_errors_with_csr_rw.4190821103
Directory /workspace/16.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all_with_rand_reset.1916390373
Short name T79
Test name
Test status
Simulation time 38727283256 ps
CPU time 2876.43 seconds
Started Jan 24 02:46:50 PM PST 24
Finished Jan 24 03:35:00 PM PST 24
Peak memory 304884 kb
Host smart-3cc075a8-18ef-4f21-a985-6b7d0cb3fd67
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916390373 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 26.alert_handler_stress_all_with_rand_reset.1916390373
Directory /workspace/26.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.alert_handler_lpg.2395552896
Short name T78
Test name
Test status
Simulation time 243613083593 ps
CPU time 2647.13 seconds
Started Jan 24 01:42:07 PM PST 24
Finished Jan 24 02:26:18 PM PST 24
Peak memory 287504 kb
Host smart-598180fd-0cd9-4fa2-aa30-1c4e28d04fb4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395552896 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg.2395552896
Directory /workspace/19.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.2626457656
Short name T140
Test name
Test status
Simulation time 3270880764 ps
CPU time 95.04 seconds
Started Jan 24 01:10:28 PM PST 24
Finished Jan 24 01:12:43 PM PST 24
Peak memory 257308 kb
Host smart-e5798969-a591-48a6-8e1a-19c94e4ffc01
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2626457656 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shadow_reg_err
ors.2626457656
Directory /workspace/15.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.964399814
Short name T171
Test name
Test status
Simulation time 15544500714 ps
CPU time 1099.86 seconds
Started Jan 24 01:09:31 PM PST 24
Finished Jan 24 01:28:28 PM PST 24
Peak memory 270632 kb
Host smart-c7135d92-fda8-4aab-b1c5-595ac9c1107a
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964399814 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.alert_handler_shadow_reg_errors_with_csr_rw.964399814
Directory /workspace/1.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/31.alert_handler_ping_timeout.2410258095
Short name T2
Test name
Test status
Simulation time 53394816038 ps
CPU time 573.89 seconds
Started Jan 24 01:44:52 PM PST 24
Finished Jan 24 01:54:31 PM PST 24
Peak memory 246588 kb
Host smart-918b5cef-410b-4e71-8147-fb710ef75063
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2410258095 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_ping_timeout.2410258095
Directory /workspace/31.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all_with_rand_reset.3065504926
Short name T123
Test name
Test status
Simulation time 71721520429 ps
CPU time 6103.25 seconds
Started Jan 24 01:42:34 PM PST 24
Finished Jan 24 03:24:53 PM PST 24
Peak memory 354612 kb
Host smart-4608f3e5-e27b-4f5c-898b-5291f6a85025
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065504926 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.alert_handler_stress_all_with_rand_reset.3065504926
Directory /workspace/21.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.3944502108
Short name T152
Test name
Test status
Simulation time 6011233110 ps
CPU time 182.65 seconds
Started Jan 24 01:09:50 PM PST 24
Finished Jan 24 01:13:29 PM PST 24
Peak memory 265588 kb
Host smart-bd5dd38a-df29-4572-b1cd-39e043cab5d9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3944502108 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shadow_reg_erro
rs.3944502108
Directory /workspace/5.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/11.alert_handler_lpg.2041586962
Short name T294
Test name
Test status
Simulation time 94555705764 ps
CPU time 1895.52 seconds
Started Jan 24 01:40:31 PM PST 24
Finished Jan 24 02:13:00 PM PST 24
Peak memory 270740 kb
Host smart-fba88082-6d00-40b8-8787-37aae7b81151
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041586962 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg.2041586962
Directory /workspace/11.alert_handler_lpg/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all_with_rand_reset.2023749901
Short name T110
Test name
Test status
Simulation time 213027684927 ps
CPU time 3875.78 seconds
Started Jan 24 01:44:36 PM PST 24
Finished Jan 24 02:49:23 PM PST 24
Peak memory 304004 kb
Host smart-9ad5981e-71b8-4659-a211-592839a92081
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023749901 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.alert_handler_stress_all_with_rand_reset.2023749901
Directory /workspace/30.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.alert_handler_ping_timeout.1822934534
Short name T304
Test name
Test status
Simulation time 9643289092 ps
CPU time 426.77 seconds
Started Jan 24 01:40:54 PM PST 24
Finished Jan 24 01:48:41 PM PST 24
Peak memory 250348 kb
Host smart-f7f3fabf-95c2-4479-a24b-128b3856cc7c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822934534 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_ping_timeout.1822934534
Directory /workspace/14.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all.139087520
Short name T263
Test name
Test status
Simulation time 427315180937 ps
CPU time 2707.85 seconds
Started Jan 24 01:46:44 PM PST 24
Finished Jan 24 02:31:56 PM PST 24
Peak memory 288356 kb
Host smart-fa86862d-66bc-49c8-88f0-605f67bc6e42
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139087520 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_han
dler_stress_all.139087520
Directory /workspace/37.alert_handler_stress_all/latest

Test location /workspace/coverage/default/15.alert_handler_lpg.2907356684
Short name T118
Test name
Test status
Simulation time 710489632352 ps
CPU time 2114 seconds
Started Jan 24 02:01:28 PM PST 24
Finished Jan 24 02:36:46 PM PST 24
Peak memory 272568 kb
Host smart-8aa976a6-7ed3-4666-a36c-c0480df73b01
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2907356684 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg.2907356684
Directory /workspace/15.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.3896735629
Short name T145
Test name
Test status
Simulation time 13883601726 ps
CPU time 931.72 seconds
Started Jan 24 01:10:04 PM PST 24
Finished Jan 24 01:26:08 PM PST 24
Peak memory 265536 kb
Host smart-1d7ee930-8164-452a-aa2b-edc0104cf7a0
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896735629 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 10.alert_handler_shadow_reg_errors_with_csr_rw.3896735629
Directory /workspace/10.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.2112825753
Short name T144
Test name
Test status
Simulation time 2100400383 ps
CPU time 216.11 seconds
Started Jan 24 01:09:43 PM PST 24
Finished Jan 24 01:13:55 PM PST 24
Peak memory 270548 kb
Host smart-def57735-634a-4c83-bc47-dc76834e6cd0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2112825753 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shadow_reg_erro
rs.2112825753
Directory /workspace/3.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/4.alert_handler_lpg.2022315709
Short name T269
Test name
Test status
Simulation time 74545636775 ps
CPU time 1443.28 seconds
Started Jan 24 01:39:37 PM PST 24
Finished Jan 24 02:04:50 PM PST 24
Peak memory 288268 kb
Host smart-92277b90-f7ff-41af-8b1e-f115b2262044
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022315709 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg.2022315709
Directory /workspace/4.alert_handler_lpg/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all_with_rand_reset.3084413849
Short name T39
Test name
Test status
Simulation time 119994444074 ps
CPU time 3913.8 seconds
Started Jan 24 01:42:29 PM PST 24
Finished Jan 24 02:48:11 PM PST 24
Peak memory 301692 kb
Host smart-49374947-e8be-4020-ad74-c52c8d55bda0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084413849 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 22.alert_handler_stress_all_with_rand_reset.3084413849
Directory /workspace/22.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all_with_rand_reset.445463287
Short name T285
Test name
Test status
Simulation time 82963568681 ps
CPU time 5386.89 seconds
Started Jan 24 01:42:51 PM PST 24
Finished Jan 24 03:13:17 PM PST 24
Peak memory 302396 kb
Host smart-6eb3b312-9690-47ea-9119-b44e47ca6a08
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445463287 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 24.alert_handler_stress_all_with_rand_reset.445463287
Directory /workspace/24.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.alert_handler_ping_timeout.4257905678
Short name T316
Test name
Test status
Simulation time 31586862647 ps
CPU time 369.91 seconds
Started Jan 24 01:44:40 PM PST 24
Finished Jan 24 01:50:59 PM PST 24
Peak memory 246596 kb
Host smart-29f7c2f9-581c-4569-a54b-53827243a6ac
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257905678 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_ping_timeout.4257905678
Directory /workspace/30.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_lpg.1512776798
Short name T665
Test name
Test status
Simulation time 56108522868 ps
CPU time 3107.86 seconds
Started Jan 24 02:30:27 PM PST 24
Finished Jan 24 03:22:26 PM PST 24
Peak memory 288796 kb
Host smart-7e1c29db-db10-4df7-81b9-75649c7fe615
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512776798 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg.1512776798
Directory /workspace/43.alert_handler_lpg/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all.1601960212
Short name T112
Test name
Test status
Simulation time 143504097222 ps
CPU time 3976.71 seconds
Started Jan 24 01:53:57 PM PST 24
Finished Jan 24 03:00:16 PM PST 24
Peak memory 298640 kb
Host smart-ee1116a2-3600-4df5-935c-53fb8aae4d62
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601960212 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_ha
ndler_stress_all.1601960212
Directory /workspace/49.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.352064260
Short name T174
Test name
Test status
Simulation time 10966189 ps
CPU time 1.41 seconds
Started Jan 24 01:10:50 PM PST 24
Finished Jan 24 01:11:32 PM PST 24
Peak memory 234688 kb
Host smart-4a5537f7-2f66-4313-bad2-b2e232c0aa3c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=352064260 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_intr_test.352064260
Directory /workspace/17.alert_handler_intr_test/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all.2974570841
Short name T114
Test name
Test status
Simulation time 156596721585 ps
CPU time 2723.09 seconds
Started Jan 24 01:39:00 PM PST 24
Finished Jan 24 02:24:30 PM PST 24
Peak memory 297596 kb
Host smart-758b1278-f0d7-48ae-bd12-7cb7d4395068
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974570841 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_han
dler_stress_all.2974570841
Directory /workspace/1.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.2020855212
Short name T186
Test name
Test status
Simulation time 608934135 ps
CPU time 42.1 seconds
Started Jan 24 01:10:07 PM PST 24
Finished Jan 24 01:11:23 PM PST 24
Peak memory 240528 kb
Host smart-5a065c62-8e77-442e-af3c-6b043f69afaa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2020855212 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_intg_err.2020855212
Directory /workspace/8.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/21.alert_handler_lpg.2171420435
Short name T128
Test name
Test status
Simulation time 74203903780 ps
CPU time 2114.59 seconds
Started Jan 24 01:42:20 PM PST 24
Finished Jan 24 02:18:03 PM PST 24
Peak memory 271888 kb
Host smart-a26997a8-2791-4484-ab2f-283ce928ec85
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171420435 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg.2171420435
Directory /workspace/21.alert_handler_lpg/latest

Test location /workspace/coverage/default/25.alert_handler_ping_timeout.253988119
Short name T319
Test name
Test status
Simulation time 13517501284 ps
CPU time 310.85 seconds
Started Jan 24 03:58:17 PM PST 24
Finished Jan 24 04:03:30 PM PST 24
Peak memory 246748 kb
Host smart-f87e36a1-c345-4a03-b58e-53092591f047
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253988119 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_ping_timeout.253988119
Directory /workspace/25.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_ping_timeout.383106064
Short name T300
Test name
Test status
Simulation time 10854859861 ps
CPU time 449.76 seconds
Started Jan 24 01:43:36 PM PST 24
Finished Jan 24 01:51:21 PM PST 24
Peak memory 246632 kb
Host smart-a42aeed4-a403-4ae8-83f0-15595128d481
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383106064 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_ping_timeout.383106064
Directory /workspace/27.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all.1627884089
Short name T34
Test name
Test status
Simulation time 34420755109 ps
CPU time 2209.16 seconds
Started Jan 24 01:39:22 PM PST 24
Finished Jan 24 02:16:17 PM PST 24
Peak memory 286260 kb
Host smart-b3df633e-f6d2-4bdb-9c15-5be9fde8ced4
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627884089 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_han
dler_stress_all.1627884089
Directory /workspace/3.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.748687544
Short name T143
Test name
Test status
Simulation time 2484709369 ps
CPU time 193.67 seconds
Started Jan 24 01:10:53 PM PST 24
Finished Jan 24 01:14:45 PM PST 24
Peak memory 265548 kb
Host smart-9eec526a-32c9-4451-8094-2cc237424ed6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=748687544 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shadow_reg_erro
rs.748687544
Directory /workspace/18.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.3194545592
Short name T160
Test name
Test status
Simulation time 3968350434 ps
CPU time 294.72 seconds
Started Jan 24 01:47:12 PM PST 24
Finished Jan 24 01:52:08 PM PST 24
Peak memory 269820 kb
Host smart-90bc9a90-e9d1-485e-94dc-b22393fe82ae
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3194545592 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shadow_reg_erro
rs.3194545592
Directory /workspace/1.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.349187558
Short name T151
Test name
Test status
Simulation time 11826077142 ps
CPU time 501.06 seconds
Started Jan 24 01:10:07 PM PST 24
Finished Jan 24 01:19:01 PM PST 24
Peak memory 270468 kb
Host smart-b2753202-1410-4710-985a-29b33014da01
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349187558 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.alert_handler_shadow_reg_errors_with_csr_rw.349187558
Directory /workspace/8.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.546411407
Short name T250
Test name
Test status
Simulation time 49728337 ps
CPU time 2.94 seconds
Started Jan 24 01:09:36 PM PST 24
Finished Jan 24 01:10:17 PM PST 24
Peak memory 236512 kb
Host smart-502a192c-0b38-4bb7-b8c6-0322ad867f72
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=546411407 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_intr_test.546411407
Directory /workspace/0.alert_handler_intr_test/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all.91651761
Short name T93
Test name
Test status
Simulation time 7204747740 ps
CPU time 462.26 seconds
Started Jan 24 01:40:42 PM PST 24
Finished Jan 24 01:49:12 PM PST 24
Peak memory 253524 kb
Host smart-ef30bf84-764b-4f0b-8f01-26aa1b6ebea7
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91651761 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_hand
ler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_hand
ler_stress_all.91651761
Directory /workspace/13.alert_handler_stress_all/latest

Test location /workspace/coverage/default/26.alert_handler_lpg.476120601
Short name T326
Test name
Test status
Simulation time 27500044082 ps
CPU time 1476.07 seconds
Started Jan 24 01:50:48 PM PST 24
Finished Jan 24 02:15:26 PM PST 24
Peak memory 271932 kb
Host smart-dba815b8-1f7f-4823-abb3-ec84ccb53b95
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476120601 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg.476120601
Directory /workspace/26.alert_handler_lpg/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all_with_rand_reset.3842920814
Short name T276
Test name
Test status
Simulation time 70410279578 ps
CPU time 2461.91 seconds
Started Jan 24 01:40:11 PM PST 24
Finished Jan 24 02:22:09 PM PST 24
Peak memory 288368 kb
Host smart-f28eeba3-25ed-4e10-8bf2-39a0771c814a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842920814 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 9.alert_handler_stress_all_with_rand_reset.3842920814
Directory /workspace/9.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.3677835181
Short name T163
Test name
Test status
Simulation time 4280829841 ps
CPU time 302.52 seconds
Started Jan 24 01:10:27 PM PST 24
Finished Jan 24 01:16:10 PM PST 24
Peak memory 267456 kb
Host smart-e2303f12-c9fd-47ad-abd6-1bd3e1a288d7
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677835181 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 13.alert_handler_shadow_reg_errors_with_csr_rw.3677835181
Directory /workspace/13.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.1751920431
Short name T179
Test name
Test status
Simulation time 93220953 ps
CPU time 3.75 seconds
Started Jan 24 01:10:58 PM PST 24
Finished Jan 24 01:11:38 PM PST 24
Peak memory 237536 kb
Host smart-d15d7883-5c72-4d43-b1f2-273922c00745
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1751920431 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_intg_err.1751920431
Directory /workspace/17.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/0.alert_handler_alert_accum_saturation.3847596258
Short name T226
Test name
Test status
Simulation time 46971206 ps
CPU time 2.32 seconds
Started Jan 24 01:38:52 PM PST 24
Finished Jan 24 01:39:05 PM PST 24
Peak memory 248316 kb
Host smart-abf30b4c-6c74-4234-a015-616423f26b05
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3847596258 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_alert_accum_saturation.3847596258
Directory /workspace/0.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/12.alert_handler_alert_accum_saturation.370141333
Short name T224
Test name
Test status
Simulation time 103361536 ps
CPU time 3.17 seconds
Started Jan 24 01:40:31 PM PST 24
Finished Jan 24 01:41:28 PM PST 24
Peak memory 249460 kb
Host smart-c9dcc990-b86e-4a66-8d68-e00ade36b0b2
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=370141333 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_alert_accum_saturation.370141333
Directory /workspace/12.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/16.alert_handler_alert_accum_saturation.1079422292
Short name T228
Test name
Test status
Simulation time 12696559 ps
CPU time 2.59 seconds
Started Jan 24 01:41:17 PM PST 24
Finished Jan 24 01:41:43 PM PST 24
Peak memory 249344 kb
Host smart-275a50ea-ff2f-43c2-8cbc-c5d6deb3a994
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1079422292 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_alert_accum_saturation.1079422292
Directory /workspace/16.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/17.alert_handler_alert_accum_saturation.3535730043
Short name T223
Test name
Test status
Simulation time 19161695 ps
CPU time 2.84 seconds
Started Jan 24 02:19:59 PM PST 24
Finished Jan 24 02:20:11 PM PST 24
Peak memory 248288 kb
Host smart-2e237e0a-7bc2-4074-8595-15accd264626
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3535730043 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_alert_accum_saturation.3535730043
Directory /workspace/17.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/17.alert_handler_sig_int_fail.509438475
Short name T68
Test name
Test status
Simulation time 1205992570 ps
CPU time 72.99 seconds
Started Jan 24 01:41:25 PM PST 24
Finished Jan 24 01:42:55 PM PST 24
Peak memory 250236 kb
Host smart-ef5632b7-52e2-4768-9fbc-fc9ad9030f6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50943
8475 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_sig_int_fail.509438475
Directory /workspace/17.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all.1259102187
Short name T257
Test name
Test status
Simulation time 53527543888 ps
CPU time 3075.75 seconds
Started Jan 24 01:43:54 PM PST 24
Finished Jan 24 02:35:15 PM PST 24
Peak memory 288932 kb
Host smart-362f70ac-76f2-4e5d-a387-cb5ce8df434a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259102187 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_ha
ndler_stress_all.1259102187
Directory /workspace/27.alert_handler_stress_all/latest

Test location /workspace/coverage/default/31.alert_handler_sig_int_fail.4098452813
Short name T289
Test name
Test status
Simulation time 635241409 ps
CPU time 40.16 seconds
Started Jan 24 01:44:54 PM PST 24
Finished Jan 24 01:45:46 PM PST 24
Peak memory 248068 kb
Host smart-89753cb0-20b6-4998-a340-c2d883e78db4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40984
52813 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_sig_int_fail.4098452813
Directory /workspace/31.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all.319950099
Short name T261
Test name
Test status
Simulation time 16835115278 ps
CPU time 1707.56 seconds
Started Jan 24 01:39:38 PM PST 24
Finished Jan 24 02:09:15 PM PST 24
Peak memory 297644 kb
Host smart-26e352b3-f238-4e13-a58f-6b7b096a519b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319950099 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_hand
ler_stress_all.319950099
Directory /workspace/7.alert_handler_stress_all/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all.2665922636
Short name T41
Test name
Test status
Simulation time 74625561774 ps
CPU time 1185.82 seconds
Started Jan 24 01:41:06 PM PST 24
Finished Jan 24 02:01:23 PM PST 24
Peak memory 271332 kb
Host smart-79a3fafb-a60c-4c5c-aa68-df774c1cad42
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665922636 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_ha
ndler_stress_all.2665922636
Directory /workspace/15.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.2747700887
Short name T162
Test name
Test status
Simulation time 12414247068 ps
CPU time 913.51 seconds
Started Jan 24 01:09:25 PM PST 24
Finished Jan 24 01:25:19 PM PST 24
Peak memory 265524 kb
Host smart-04f2cbb4-3a59-45d7-8e2b-e6b1090f9623
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747700887 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.alert_handler_shadow_reg_errors_with_csr_rw.2747700887
Directory /workspace/2.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.1121054628
Short name T154
Test name
Test status
Simulation time 24909725604 ps
CPU time 425.48 seconds
Started Jan 24 01:10:17 PM PST 24
Finished Jan 24 01:18:01 PM PST 24
Peak memory 269552 kb
Host smart-5c1c09a4-3fae-4a33-8bbb-31c811665bb6
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121054628 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 11.alert_handler_shadow_reg_errors_with_csr_rw.1121054628
Directory /workspace/11.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all_with_rand_reset.2380388412
Short name T279
Test name
Test status
Simulation time 287927778085 ps
CPU time 6031.95 seconds
Started Jan 24 01:38:51 PM PST 24
Finished Jan 24 03:19:35 PM PST 24
Peak memory 321824 kb
Host smart-20a3fe1e-0bf1-4e91-93b1-087ad6e81d9c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380388412 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.alert_handler_stress_all_with_rand_reset.2380388412
Directory /workspace/1.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all.2395255137
Short name T260
Test name
Test status
Simulation time 233474085844 ps
CPU time 3317.45 seconds
Started Jan 24 01:40:31 PM PST 24
Finished Jan 24 02:36:43 PM PST 24
Peak memory 296252 kb
Host smart-d046dcb7-963e-4a31-b764-3b1ee2c3103e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395255137 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_ha
ndler_stress_all.2395255137
Directory /workspace/10.alert_handler_stress_all/latest

Test location /workspace/coverage/default/11.alert_handler_ping_timeout.583439399
Short name T592
Test name
Test status
Simulation time 72396963970 ps
CPU time 628.38 seconds
Started Jan 24 02:02:47 PM PST 24
Finished Jan 24 02:13:25 PM PST 24
Peak memory 245652 kb
Host smart-cea10ce6-572c-4ca3-9b79-bc15c4c47eee
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583439399 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_ping_timeout.583439399
Directory /workspace/11.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_lpg.2824391922
Short name T337
Test name
Test status
Simulation time 51664946362 ps
CPU time 1070.92 seconds
Started Jan 24 01:40:39 PM PST 24
Finished Jan 24 01:59:19 PM PST 24
Peak memory 272044 kb
Host smart-bc599450-9902-48a5-b738-ebe4e7a45333
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824391922 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg.2824391922
Directory /workspace/12.alert_handler_lpg/latest

Test location /workspace/coverage/default/13.alert_handler_ping_timeout.2443224880
Short name T323
Test name
Test status
Simulation time 11758253948 ps
CPU time 438.23 seconds
Started Jan 24 01:40:49 PM PST 24
Finished Jan 24 01:48:51 PM PST 24
Peak memory 246704 kb
Host smart-8f768d65-7acb-44f4-afd7-02a6a5e76369
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2443224880 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_ping_timeout.2443224880
Directory /workspace/13.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all_with_rand_reset.236073883
Short name T210
Test name
Test status
Simulation time 191136642190 ps
CPU time 3125.24 seconds
Started Jan 24 01:41:09 PM PST 24
Finished Jan 24 02:33:43 PM PST 24
Peak memory 304412 kb
Host smart-5d5927e1-4ac0-449d-8951-c8cb0dc858a9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236073883 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 15.alert_handler_stress_all_with_rand_reset.236073883
Directory /workspace/15.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.alert_handler_lpg_stub_clk.3086889401
Short name T255
Test name
Test status
Simulation time 168108398129 ps
CPU time 2846.17 seconds
Started Jan 24 01:42:08 PM PST 24
Finished Jan 24 02:29:39 PM PST 24
Peak memory 288204 kb
Host smart-e328d283-627a-4fa9-845b-32c8c6c8f850
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086889401 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg_stub_clk.3086889401
Directory /workspace/20.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all_with_rand_reset.2189817451
Short name T212
Test name
Test status
Simulation time 63320113963 ps
CPU time 4448.08 seconds
Started Jan 24 01:45:53 PM PST 24
Finished Jan 24 03:00:23 PM PST 24
Peak memory 304900 kb
Host smart-b52be8d3-5f24-4fb3-bf3b-4b0a5137f0f1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189817451 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.alert_handler_stress_all_with_rand_reset.2189817451
Directory /workspace/34.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all_with_rand_reset.3861018238
Short name T292
Test name
Test status
Simulation time 64735580501 ps
CPU time 1963.84 seconds
Started Jan 24 02:30:27 PM PST 24
Finished Jan 24 03:03:22 PM PST 24
Peak memory 283520 kb
Host smart-5fb5af8b-b542-4bfa-941f-1486764264ba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861018238 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.alert_handler_stress_all_with_rand_reset.3861018238
Directory /workspace/38.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all_with_rand_reset.1636371817
Short name T287
Test name
Test status
Simulation time 81687648102 ps
CPU time 8327.79 seconds
Started Jan 24 01:51:42 PM PST 24
Finished Jan 24 04:10:35 PM PST 24
Peak memory 362980 kb
Host smart-9106e639-06a7-419b-855d-af4d827f15d7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636371817 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 48.alert_handler_stress_all_with_rand_reset.1636371817
Directory /workspace/48.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.alert_handler_lpg.199746589
Short name T40
Test name
Test status
Simulation time 40491153916 ps
CPU time 1009.69 seconds
Started Jan 24 01:42:45 PM PST 24
Finished Jan 24 02:00:13 PM PST 24
Peak memory 272440 kb
Host smart-14d0bae9-c9ac-46cb-8944-8c2b793f03fa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=199746589 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg.199746589
Directory /workspace/23.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.105999183
Short name T159
Test name
Test status
Simulation time 4073929492 ps
CPU time 156.26 seconds
Started Jan 24 01:10:16 PM PST 24
Finished Jan 24 01:13:29 PM PST 24
Peak memory 267200 kb
Host smart-589e550c-69e9-4f24-8980-4e4005849283
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=105999183 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shadow_reg_erro
rs.105999183
Directory /workspace/11.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.1619847774
Short name T182
Test name
Test status
Simulation time 1291140301 ps
CPU time 45.43 seconds
Started Jan 24 01:10:17 PM PST 24
Finished Jan 24 01:11:39 PM PST 24
Peak memory 236800 kb
Host smart-54c3ea2c-bf5c-4eb1-889a-8f65adae48b4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1619847774 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_intg_err.1619847774
Directory /workspace/11.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.1721289546
Short name T184
Test name
Test status
Simulation time 54577025 ps
CPU time 3.75 seconds
Started Jan 24 01:09:54 PM PST 24
Finished Jan 24 01:10:32 PM PST 24
Peak memory 235624 kb
Host smart-5830565a-004c-48a3-95f2-f1302c1f568c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1721289546 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_intg_err.1721289546
Directory /workspace/4.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.1776339583
Short name T178
Test name
Test status
Simulation time 305245671 ps
CPU time 11.05 seconds
Started Jan 24 01:09:55 PM PST 24
Finished Jan 24 01:10:40 PM PST 24
Peak memory 237072 kb
Host smart-1c8693ed-b1ec-4a58-ae09-a217553ac835
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1776339583 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_intg_err.1776339583
Directory /workspace/5.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.1564861837
Short name T181
Test name
Test status
Simulation time 170725407 ps
CPU time 3.66 seconds
Started Jan 24 01:10:39 PM PST 24
Finished Jan 24 01:11:25 PM PST 24
Peak memory 236524 kb
Host smart-ab3302a4-b66d-4739-a03a-693ce532a922
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1564861837 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_intg_err.1564861837
Directory /workspace/13.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.2924690139
Short name T177
Test name
Test status
Simulation time 1181519862 ps
CPU time 44.03 seconds
Started Jan 24 01:10:04 PM PST 24
Finished Jan 24 01:11:20 PM PST 24
Peak memory 239372 kb
Host smart-860a2240-cdf8-433e-aa0b-22e83b50ed27
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2924690139 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_intg_err.2924690139
Directory /workspace/9.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.1588123640
Short name T187
Test name
Test status
Simulation time 129485923 ps
CPU time 2.66 seconds
Started Jan 24 01:09:22 PM PST 24
Finished Jan 24 01:10:03 PM PST 24
Peak memory 237056 kb
Host smart-675571b0-13cb-40a2-9396-b0f6d24b03a1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1588123640 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_intg_err.1588123640
Directory /workspace/1.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.3233929763
Short name T150
Test name
Test status
Simulation time 8585788572 ps
CPU time 577.86 seconds
Started Jan 24 01:10:14 PM PST 24
Finished Jan 24 01:20:28 PM PST 24
Peak memory 265532 kb
Host smart-831217d0-cb40-4bc8-9430-485961a0cd87
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233929763 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 12.alert_handler_shadow_reg_errors_with_csr_rw.3233929763
Directory /workspace/12.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.2271357579
Short name T135
Test name
Test status
Simulation time 92419817 ps
CPU time 3.79 seconds
Started Jan 24 01:11:02 PM PST 24
Finished Jan 24 01:11:41 PM PST 24
Peak memory 236544 kb
Host smart-f9e29d27-65dd-4d72-8380-f6f1e4993486
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2271357579 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_intg_err.2271357579
Directory /workspace/18.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.3951006792
Short name T180
Test name
Test status
Simulation time 1199974327 ps
CPU time 44.08 seconds
Started Jan 24 01:11:06 PM PST 24
Finished Jan 24 01:12:23 PM PST 24
Peak memory 236700 kb
Host smart-6a29c9d3-f604-4106-a79d-63bac8184d12
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3951006792 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_intg_err.3951006792
Directory /workspace/19.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.1542805206
Short name T185
Test name
Test status
Simulation time 64511915 ps
CPU time 3.84 seconds
Started Jan 24 01:09:43 PM PST 24
Finished Jan 24 01:10:23 PM PST 24
Peak memory 236392 kb
Host smart-8349adbd-9cd6-44f2-b4ab-575d408d7e69
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1542805206 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_intg_err.1542805206
Directory /workspace/2.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.1419191119
Short name T176
Test name
Test status
Simulation time 29425578 ps
CPU time 2.6 seconds
Started Jan 24 01:10:01 PM PST 24
Finished Jan 24 01:10:37 PM PST 24
Peak memory 235720 kb
Host smart-9f3f3ded-0acf-4bff-b3fa-7762a2cafda0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1419191119 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_intg_err.1419191119
Directory /workspace/7.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.3974451826
Short name T173
Test name
Test status
Simulation time 914891900 ps
CPU time 64.28 seconds
Started Jan 24 01:09:54 PM PST 24
Finished Jan 24 01:11:33 PM PST 24
Peak memory 239404 kb
Host smart-b0a9178f-9dfe-4369-90a1-c59fc8945d46
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3974451826 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_intg_err.3974451826
Directory /workspace/6.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/27.alert_handler_entropy.1560590990
Short name T31
Test name
Test status
Simulation time 57124173371 ps
CPU time 3268.18 seconds
Started Jan 24 01:43:41 PM PST 24
Finished Jan 24 02:38:22 PM PST 24
Peak memory 288168 kb
Host smart-20c3a597-7611-4043-b1fe-fc52c6bbc9ac
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560590990 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_entropy.1560590990
Directory /workspace/27.alert_handler_entropy/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.3551971740
Short name T802
Test name
Test status
Simulation time 569306199 ps
CPU time 74.63 seconds
Started Jan 24 01:09:30 PM PST 24
Finished Jan 24 01:11:23 PM PST 24
Peak memory 236388 kb
Host smart-6e60df8f-c11f-4bd5-835a-4214d1f18eca
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3551971740 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_aliasing.3551971740
Directory /workspace/0.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.678353610
Short name T30
Test name
Test status
Simulation time 8558510746 ps
CPU time 533.02 seconds
Started Jan 24 01:46:44 PM PST 24
Finished Jan 24 01:55:41 PM PST 24
Peak memory 236608 kb
Host smart-6d20d7c7-673b-4dad-93c6-6c7c9d025912
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=678353610 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_bit_bash.678353610
Directory /workspace/0.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.2548126026
Short name T806
Test name
Test status
Simulation time 262907340 ps
CPU time 5.85 seconds
Started Jan 24 01:09:31 PM PST 24
Finished Jan 24 01:10:15 PM PST 24
Peak memory 240448 kb
Host smart-8d8cf53e-2910-49e3-a358-2de64eff56d2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2548126026 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_hw_reset.2548126026
Directory /workspace/0.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.4126490286
Short name T733
Test name
Test status
Simulation time 35438159 ps
CPU time 4.03 seconds
Started Jan 24 01:09:22 PM PST 24
Finished Jan 24 01:10:05 PM PST 24
Peak memory 240640 kb
Host smart-2dfc19e0-5460-4fd0-ab18-bfe9fab72951
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126490286 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 0.alert_handler_csr_mem_rw_with_rand_reset.4126490286
Directory /workspace/0.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.2770370948
Short name T822
Test name
Test status
Simulation time 124182943 ps
CPU time 10.14 seconds
Started Jan 24 03:20:47 PM PST 24
Finished Jan 24 03:21:06 PM PST 24
Peak memory 240520 kb
Host smart-1f5765fd-fe2e-41bf-bedb-455b79ec03b3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2770370948 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_rw.2770370948
Directory /workspace/0.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.1029091265
Short name T198
Test name
Test status
Simulation time 2098299270 ps
CPU time 33.11 seconds
Started Jan 24 01:09:30 PM PST 24
Finished Jan 24 01:10:41 PM PST 24
Peak memory 240140 kb
Host smart-1130df4a-10f1-45f8-99ee-692d4758da78
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1029091265 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_same_csr_out
standing.1029091265
Directory /workspace/0.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.860008814
Short name T146
Test name
Test status
Simulation time 1773836011 ps
CPU time 186.07 seconds
Started Jan 24 01:09:36 PM PST 24
Finished Jan 24 01:13:20 PM PST 24
Peak memory 265500 kb
Host smart-03e8bc13-d5a9-416b-8324-c4b6fb6c3095
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=860008814 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shadow_reg_error
s.860008814
Directory /workspace/0.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.644664663
Short name T166
Test name
Test status
Simulation time 97416246941 ps
CPU time 534.27 seconds
Started Jan 24 01:09:21 PM PST 24
Finished Jan 24 01:18:53 PM PST 24
Peak memory 265556 kb
Host smart-07fb99c9-3ea0-415a-b116-8614aaf8f484
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644664663 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.alert_handler_shadow_reg_errors_with_csr_rw.644664663
Directory /workspace/0.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.1124620682
Short name T787
Test name
Test status
Simulation time 1741976018 ps
CPU time 15.3 seconds
Started Jan 24 01:09:31 PM PST 24
Finished Jan 24 01:10:25 PM PST 24
Peak memory 247988 kb
Host smart-c94409c7-243a-4cf5-9982-005ee133e593
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1124620682 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_errors.1124620682
Directory /workspace/0.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.445212983
Short name T189
Test name
Test status
Simulation time 582212908 ps
CPU time 21.93 seconds
Started Jan 24 01:09:25 PM PST 24
Finished Jan 24 01:10:26 PM PST 24
Peak memory 244864 kb
Host smart-acb00fc2-a655-4890-a7c7-754a76c7bdcd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=445212983 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_intg_err.445212983
Directory /workspace/0.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.589607855
Short name T167
Test name
Test status
Simulation time 3804557618 ps
CPU time 245.7 seconds
Started Jan 24 01:09:36 PM PST 24
Finished Jan 24 01:14:20 PM PST 24
Peak memory 240616 kb
Host smart-1722dc79-49f6-4f8a-9b6a-7061cbb44316
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=589607855 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_aliasing.589607855
Directory /workspace/1.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.2992952510
Short name T778
Test name
Test status
Simulation time 11843561699 ps
CPU time 361.61 seconds
Started Jan 24 01:09:30 PM PST 24
Finished Jan 24 01:16:10 PM PST 24
Peak memory 236616 kb
Host smart-ceb7e282-60a1-41da-9131-dcce95d29ee7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2992952510 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_bit_bash.2992952510
Directory /workspace/1.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.3831419387
Short name T740
Test name
Test status
Simulation time 294409319 ps
CPU time 7.77 seconds
Started Jan 24 01:09:25 PM PST 24
Finished Jan 24 01:10:12 PM PST 24
Peak memory 240484 kb
Host smart-bdd4e6da-9157-4626-b568-5ba0265a860a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3831419387 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_hw_reset.3831419387
Directory /workspace/1.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.3788891516
Short name T767
Test name
Test status
Simulation time 78685494 ps
CPU time 7.24 seconds
Started Jan 24 01:09:36 PM PST 24
Finished Jan 24 01:10:21 PM PST 24
Peak memory 256820 kb
Host smart-86823dc9-14cb-42a1-90e0-c5c5e7818401
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788891516 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 1.alert_handler_csr_mem_rw_with_rand_reset.3788891516
Directory /workspace/1.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.1704694103
Short name T754
Test name
Test status
Simulation time 24461992 ps
CPU time 3.78 seconds
Started Jan 24 01:09:30 PM PST 24
Finished Jan 24 01:10:12 PM PST 24
Peak memory 236396 kb
Host smart-d8fec4fb-0286-4ba0-9ed6-7b3f7b3fe594
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1704694103 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_rw.1704694103
Directory /workspace/1.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.1028465561
Short name T729
Test name
Test status
Simulation time 354167447 ps
CPU time 13.2 seconds
Started Jan 24 01:09:31 PM PST 24
Finished Jan 24 01:10:22 PM PST 24
Peak memory 245052 kb
Host smart-d18f61d9-0ebf-4752-9861-182b6f7038b9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1028465561 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_same_csr_out
standing.1028465561
Directory /workspace/1.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.3225921143
Short name T807
Test name
Test status
Simulation time 397440923 ps
CPU time 8.97 seconds
Started Jan 24 01:09:31 PM PST 24
Finished Jan 24 01:10:19 PM PST 24
Peak memory 248796 kb
Host smart-9ee13b76-8e4f-468e-84fe-6f86cefa2eab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3225921143 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_errors.3225921143
Directory /workspace/1.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.2015583002
Short name T136
Test name
Test status
Simulation time 42037792 ps
CPU time 4.66 seconds
Started Jan 24 01:10:14 PM PST 24
Finished Jan 24 01:10:54 PM PST 24
Peak memory 240632 kb
Host smart-595a909a-4561-4488-8d90-74a0e857c903
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015583002 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 10.alert_handler_csr_mem_rw_with_rand_reset.2015583002
Directory /workspace/10.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.2270325175
Short name T794
Test name
Test status
Simulation time 50380790 ps
CPU time 4.79 seconds
Started Jan 24 01:10:15 PM PST 24
Finished Jan 24 01:10:58 PM PST 24
Peak memory 240288 kb
Host smart-eab1dfd0-c98f-4787-addd-d45fd5d3d152
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2270325175 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_rw.2270325175
Directory /workspace/10.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.937081473
Short name T22
Test name
Test status
Simulation time 9134687 ps
CPU time 1.33 seconds
Started Jan 24 01:10:05 PM PST 24
Finished Jan 24 01:10:38 PM PST 24
Peak memory 236560 kb
Host smart-01e95b49-f92b-4ca2-922b-2d3769caf247
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=937081473 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_intr_test.937081473
Directory /workspace/10.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.21661058
Short name T786
Test name
Test status
Simulation time 1081416456 ps
CPU time 16.32 seconds
Started Jan 24 01:10:06 PM PST 24
Finished Jan 24 01:10:55 PM PST 24
Peak memory 243884 kb
Host smart-1b0badce-d722-4669-98ed-3a61a12e7574
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=21661058 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_same_csr_outs
tanding.21661058
Directory /workspace/10.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.3918023988
Short name T142
Test name
Test status
Simulation time 2325381871 ps
CPU time 154.18 seconds
Started Jan 24 01:10:06 PM PST 24
Finished Jan 24 01:13:13 PM PST 24
Peak memory 257340 kb
Host smart-9faa7e76-46ad-4d0c-a1c7-be306ab86683
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3918023988 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shadow_reg_err
ors.3918023988
Directory /workspace/10.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.2541474169
Short name T838
Test name
Test status
Simulation time 147010661 ps
CPU time 10.15 seconds
Started Jan 24 01:10:13 PM PST 24
Finished Jan 24 01:10:59 PM PST 24
Peak memory 254184 kb
Host smart-79b9d52c-c8dc-40e9-a538-37305cebaf78
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2541474169 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_errors.2541474169
Directory /workspace/10.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.1233735198
Short name T201
Test name
Test status
Simulation time 182931976 ps
CPU time 2.41 seconds
Started Jan 24 01:10:08 PM PST 24
Finished Jan 24 01:10:43 PM PST 24
Peak memory 236580 kb
Host smart-53df6e16-5bb0-424b-8a1a-1dd21cfac05d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1233735198 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_intg_err.1233735198
Directory /workspace/10.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.2015914891
Short name T829
Test name
Test status
Simulation time 70110572 ps
CPU time 7.1 seconds
Started Jan 24 01:10:14 PM PST 24
Finished Jan 24 01:10:56 PM PST 24
Peak memory 256988 kb
Host smart-86d806b8-b906-4ab1-a110-c8b263e729ba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015914891 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 11.alert_handler_csr_mem_rw_with_rand_reset.2015914891
Directory /workspace/11.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.200084559
Short name T24
Test name
Test status
Simulation time 107209277 ps
CPU time 8.66 seconds
Started Jan 24 01:10:16 PM PST 24
Finished Jan 24 01:11:02 PM PST 24
Peak memory 236532 kb
Host smart-89615c20-37fa-4d9f-9171-deb7c5cb5c95
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=200084559 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_rw.200084559
Directory /workspace/11.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.1613683541
Short name T776
Test name
Test status
Simulation time 30742633 ps
CPU time 1.38 seconds
Started Jan 24 01:10:13 PM PST 24
Finished Jan 24 01:10:50 PM PST 24
Peak memory 235688 kb
Host smart-9ec703be-5066-47ac-829b-06043b974fdd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1613683541 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_intr_test.1613683541
Directory /workspace/11.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.1753514335
Short name T827
Test name
Test status
Simulation time 87001086 ps
CPU time 12.76 seconds
Started Jan 24 01:10:15 PM PST 24
Finished Jan 24 01:11:04 PM PST 24
Peak memory 240476 kb
Host smart-ae5de8c5-c4bc-445d-88c9-a2252e3963ba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1753514335 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_same_csr_ou
tstanding.1753514335
Directory /workspace/11.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.115435194
Short name T840
Test name
Test status
Simulation time 1605761112 ps
CPU time 27.52 seconds
Started Jan 24 01:10:16 PM PST 24
Finished Jan 24 01:11:21 PM PST 24
Peak memory 248288 kb
Host smart-3800afbb-b3c4-4da1-bc60-1ff22fedcf89
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=115435194 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_errors.115435194
Directory /workspace/11.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.1848698213
Short name T728
Test name
Test status
Simulation time 21874963 ps
CPU time 4.19 seconds
Started Jan 24 01:10:38 PM PST 24
Finished Jan 24 01:11:24 PM PST 24
Peak memory 241500 kb
Host smart-ade9d940-d015-4da2-99e7-680e16b17620
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848698213 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 12.alert_handler_csr_mem_rw_with_rand_reset.1848698213
Directory /workspace/12.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.722050613
Short name T814
Test name
Test status
Simulation time 186172301 ps
CPU time 7.7 seconds
Started Jan 24 01:10:16 PM PST 24
Finished Jan 24 01:11:01 PM PST 24
Peak memory 236544 kb
Host smart-e34650fe-3117-4b82-a1a5-40d996c9b21d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=722050613 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_rw.722050613
Directory /workspace/12.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.2371818538
Short name T765
Test name
Test status
Simulation time 24483516 ps
CPU time 1.42 seconds
Started Jan 24 01:10:13 PM PST 24
Finished Jan 24 01:10:50 PM PST 24
Peak memory 236596 kb
Host smart-530578c5-b961-43a2-9b73-4dfd6f28b980
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2371818538 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_intr_test.2371818538
Directory /workspace/12.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.754588680
Short name T748
Test name
Test status
Simulation time 593825344 ps
CPU time 33.1 seconds
Started Jan 24 01:10:33 PM PST 24
Finished Jan 24 01:11:48 PM PST 24
Peak memory 243896 kb
Host smart-e0eb7226-5c50-4ed9-ba65-413524cd15fa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=754588680 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_same_csr_out
standing.754588680
Directory /workspace/12.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.3117928202
Short name T172
Test name
Test status
Simulation time 9468618412 ps
CPU time 163.17 seconds
Started Jan 24 01:10:16 PM PST 24
Finished Jan 24 01:13:36 PM PST 24
Peak memory 256976 kb
Host smart-360ff351-d7aa-4a74-be75-bcbca788d992
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3117928202 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shadow_reg_err
ors.3117928202
Directory /workspace/12.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.4147917771
Short name T801
Test name
Test status
Simulation time 486482861 ps
CPU time 17.34 seconds
Started Jan 24 01:10:20 PM PST 24
Finished Jan 24 01:11:16 PM PST 24
Peak memory 248832 kb
Host smart-01e4c9cb-caee-41c1-8eaf-2aadfda5de69
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4147917771 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_errors.4147917771
Directory /workspace/12.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.3885281303
Short name T29
Test name
Test status
Simulation time 487627676 ps
CPU time 31 seconds
Started Jan 24 01:10:13 PM PST 24
Finished Jan 24 01:11:20 PM PST 24
Peak memory 244804 kb
Host smart-ac27fc84-a1e4-4ab5-a9df-3cc1d1fb1706
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3885281303 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_intg_err.3885281303
Directory /workspace/12.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.402314737
Short name T25
Test name
Test status
Simulation time 74169083 ps
CPU time 4.1 seconds
Started Jan 24 01:10:39 PM PST 24
Finished Jan 24 01:11:26 PM PST 24
Peak memory 237596 kb
Host smart-409149ad-f772-4282-945a-630cbfa1c1de
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402314737 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 13.alert_handler_csr_mem_rw_with_rand_reset.402314737
Directory /workspace/13.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.1220804817
Short name T798
Test name
Test status
Simulation time 66309885 ps
CPU time 5.49 seconds
Started Jan 24 01:10:30 PM PST 24
Finished Jan 24 01:11:17 PM PST 24
Peak memory 240240 kb
Host smart-ed636bbb-9a69-469d-af2d-4a9eefae7e9f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1220804817 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_rw.1220804817
Directory /workspace/13.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.1345067354
Short name T795
Test name
Test status
Simulation time 11817552 ps
CPU time 1.61 seconds
Started Jan 24 01:10:30 PM PST 24
Finished Jan 24 01:11:13 PM PST 24
Peak memory 236600 kb
Host smart-746132e9-dbd2-45e8-91df-033b6e7b4f9d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1345067354 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_intr_test.1345067354
Directory /workspace/13.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.2787258205
Short name T817
Test name
Test status
Simulation time 1288455598 ps
CPU time 42.11 seconds
Started Jan 24 01:10:30 PM PST 24
Finished Jan 24 01:11:53 PM PST 24
Peak memory 244804 kb
Host smart-5bbe3d19-83b7-430d-af46-8640f2974086
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2787258205 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_same_csr_ou
tstanding.2787258205
Directory /workspace/13.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.4060207143
Short name T161
Test name
Test status
Simulation time 4408100966 ps
CPU time 323.27 seconds
Started Jan 24 01:10:27 PM PST 24
Finished Jan 24 01:16:31 PM PST 24
Peak memory 265448 kb
Host smart-9bb61c38-1703-47ba-87e4-c13a86ca369e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4060207143 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shadow_reg_err
ors.4060207143
Directory /workspace/13.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.3830859086
Short name T826
Test name
Test status
Simulation time 332121737 ps
CPU time 12.33 seconds
Started Jan 24 01:10:29 PM PST 24
Finished Jan 24 01:11:23 PM PST 24
Peak memory 253012 kb
Host smart-33588c42-bc71-4217-a074-8353177e5900
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3830859086 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_errors.3830859086
Directory /workspace/13.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.1500350278
Short name T721
Test name
Test status
Simulation time 275083277 ps
CPU time 4.07 seconds
Started Jan 24 01:10:37 PM PST 24
Finished Jan 24 01:11:23 PM PST 24
Peak memory 240604 kb
Host smart-06179f17-1a45-404f-afd3-70534dbce062
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500350278 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 14.alert_handler_csr_mem_rw_with_rand_reset.1500350278
Directory /workspace/14.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.3359387352
Short name T200
Test name
Test status
Simulation time 34468256 ps
CPU time 5.56 seconds
Started Jan 24 01:10:37 PM PST 24
Finished Jan 24 01:11:24 PM PST 24
Peak memory 236496 kb
Host smart-cd178271-6f23-4a57-8c5c-bc982f904222
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3359387352 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_rw.3359387352
Directory /workspace/14.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.199287088
Short name T190
Test name
Test status
Simulation time 20551591 ps
CPU time 1.48 seconds
Started Jan 24 01:10:28 PM PST 24
Finished Jan 24 01:11:09 PM PST 24
Peak memory 235732 kb
Host smart-3b499678-6336-4cbc-a70a-80d20e08d14a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=199287088 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_intr_test.199287088
Directory /workspace/14.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.989047480
Short name T199
Test name
Test status
Simulation time 256093648 ps
CPU time 17.53 seconds
Started Jan 24 01:10:33 PM PST 24
Finished Jan 24 01:11:33 PM PST 24
Peak memory 243896 kb
Host smart-566e061c-6105-4a95-84c2-7eb67ef90d7a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=989047480 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_same_csr_out
standing.989047480
Directory /workspace/14.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.4108661101
Short name T141
Test name
Test status
Simulation time 4077622639 ps
CPU time 284.72 seconds
Started Jan 24 01:10:29 PM PST 24
Finished Jan 24 01:15:55 PM PST 24
Peak memory 271912 kb
Host smart-d7321756-8cde-4beb-a580-151c3144e414
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4108661101 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shadow_reg_err
ors.4108661101
Directory /workspace/14.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.744223819
Short name T168
Test name
Test status
Simulation time 12329428867 ps
CPU time 452.75 seconds
Started Jan 24 01:10:32 PM PST 24
Finished Jan 24 01:18:47 PM PST 24
Peak memory 265580 kb
Host smart-cb11fe2d-052a-4002-8c8e-8f86f79c3d15
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744223819 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 14.alert_handler_shadow_reg_errors_with_csr_rw.744223819
Directory /workspace/14.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.3868964703
Short name T784
Test name
Test status
Simulation time 30706992 ps
CPU time 4.07 seconds
Started Jan 24 01:10:30 PM PST 24
Finished Jan 24 01:11:15 PM PST 24
Peak memory 248732 kb
Host smart-deb7d72f-3f63-4fcf-a3c2-ee7741e07e4d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3868964703 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_errors.3868964703
Directory /workspace/14.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.2929272285
Short name T825
Test name
Test status
Simulation time 141550123 ps
CPU time 6.98 seconds
Started Jan 24 01:10:40 PM PST 24
Finished Jan 24 01:11:29 PM PST 24
Peak memory 253404 kb
Host smart-1be28ca0-ea50-4143-adad-675225d1ac8f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929272285 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 15.alert_handler_csr_mem_rw_with_rand_reset.2929272285
Directory /workspace/15.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.3558981812
Short name T804
Test name
Test status
Simulation time 19622526 ps
CPU time 3.42 seconds
Started Jan 24 01:10:41 PM PST 24
Finished Jan 24 01:11:26 PM PST 24
Peak memory 240316 kb
Host smart-82a7315e-1191-4f66-bb8a-ad4818a72b4e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3558981812 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_rw.3558981812
Directory /workspace/15.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.2363739166
Short name T835
Test name
Test status
Simulation time 11058349 ps
CPU time 1.22 seconds
Started Jan 24 01:10:42 PM PST 24
Finished Jan 24 01:11:25 PM PST 24
Peak memory 236528 kb
Host smart-6c9341f6-91a3-444a-ad32-98c988fd6f8a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2363739166 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_intr_test.2363739166
Directory /workspace/15.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.3703103397
Short name T818
Test name
Test status
Simulation time 515194868 ps
CPU time 19.61 seconds
Started Jan 24 01:10:39 PM PST 24
Finished Jan 24 01:11:41 PM PST 24
Peak memory 244796 kb
Host smart-3d164467-aa76-4ba2-bd9b-6b9c5707df89
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3703103397 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_same_csr_ou
tstanding.3703103397
Directory /workspace/15.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.1420296437
Short name T753
Test name
Test status
Simulation time 384451544 ps
CPU time 6.88 seconds
Started Jan 24 01:10:42 PM PST 24
Finished Jan 24 01:11:31 PM PST 24
Peak memory 248912 kb
Host smart-c62e5e9e-073e-483a-b73d-6e8629de4a48
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1420296437 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_errors.1420296437
Directory /workspace/15.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.1976887608
Short name T188
Test name
Test status
Simulation time 261910328 ps
CPU time 23.79 seconds
Started Jan 24 01:10:40 PM PST 24
Finished Jan 24 01:11:46 PM PST 24
Peak memory 248744 kb
Host smart-91f2be92-e70b-49d7-99e5-83e54f7517fa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1976887608 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_intg_err.1976887608
Directory /workspace/15.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.2817101339
Short name T808
Test name
Test status
Simulation time 30709501 ps
CPU time 6.04 seconds
Started Jan 24 01:10:58 PM PST 24
Finished Jan 24 01:11:40 PM PST 24
Peak memory 251820 kb
Host smart-23c86fc6-bb58-4d8f-a331-293c4d40ef43
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817101339 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 16.alert_handler_csr_mem_rw_with_rand_reset.2817101339
Directory /workspace/16.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.1344820679
Short name T789
Test name
Test status
Simulation time 82851458 ps
CPU time 5.86 seconds
Started Jan 24 01:10:42 PM PST 24
Finished Jan 24 01:11:30 PM PST 24
Peak memory 240416 kb
Host smart-2cb9ffe0-d90c-42ac-82f3-e96b4b3368fc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1344820679 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_rw.1344820679
Directory /workspace/16.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.696580509
Short name T761
Test name
Test status
Simulation time 10113745 ps
CPU time 1.38 seconds
Started Jan 24 01:10:42 PM PST 24
Finished Jan 24 01:11:25 PM PST 24
Peak memory 236536 kb
Host smart-c1c1e55a-53a6-4bd0-b773-752780da3e48
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=696580509 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_intr_test.696580509
Directory /workspace/16.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.3172061726
Short name T759
Test name
Test status
Simulation time 4014256893 ps
CPU time 19.33 seconds
Started Jan 24 01:10:49 PM PST 24
Finished Jan 24 01:11:49 PM PST 24
Peak memory 244756 kb
Host smart-2ef1fbe4-ce8c-4c07-92e9-058483f3d684
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3172061726 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_same_csr_ou
tstanding.3172061726
Directory /workspace/16.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.1858626863
Short name T824
Test name
Test status
Simulation time 1072537851 ps
CPU time 102.65 seconds
Started Jan 24 01:10:41 PM PST 24
Finished Jan 24 01:13:06 PM PST 24
Peak memory 257168 kb
Host smart-fc45d2f8-b1b8-48b6-a935-e646d50e858b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1858626863 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shadow_reg_err
ors.1858626863
Directory /workspace/16.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.1894707081
Short name T834
Test name
Test status
Simulation time 243648918 ps
CPU time 7.3 seconds
Started Jan 24 01:10:39 PM PST 24
Finished Jan 24 01:11:27 PM PST 24
Peak memory 248652 kb
Host smart-2e682c70-8db2-4e86-b38f-da2bffd22320
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1894707081 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_errors.1894707081
Directory /workspace/16.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.2982259332
Short name T183
Test name
Test status
Simulation time 3717836240 ps
CPU time 67.02 seconds
Started Jan 24 01:10:40 PM PST 24
Finished Jan 24 01:12:29 PM PST 24
Peak memory 245264 kb
Host smart-41c52bdd-99bc-4bae-9086-d60dcd08c6a2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2982259332 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_intg_err.2982259332
Directory /workspace/16.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.679816809
Short name T774
Test name
Test status
Simulation time 66536606 ps
CPU time 3.7 seconds
Started Jan 24 01:10:47 PM PST 24
Finished Jan 24 01:11:32 PM PST 24
Peak memory 237644 kb
Host smart-943efeb4-2036-4a9a-8053-d289b10b6b25
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679816809 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 17.alert_handler_csr_mem_rw_with_rand_reset.679816809
Directory /workspace/17.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.2460953420
Short name T747
Test name
Test status
Simulation time 567949727 ps
CPU time 9.21 seconds
Started Jan 24 01:10:59 PM PST 24
Finished Jan 24 01:11:43 PM PST 24
Peak memory 236444 kb
Host smart-50730359-4b15-4dc4-b6ca-682f6dc171b9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2460953420 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_rw.2460953420
Directory /workspace/17.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.1114369775
Short name T781
Test name
Test status
Simulation time 723246571 ps
CPU time 45.53 seconds
Started Jan 24 01:10:49 PM PST 24
Finished Jan 24 01:12:15 PM PST 24
Peak memory 244804 kb
Host smart-e1778413-3520-41bf-93c1-af189977339f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1114369775 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_same_csr_ou
tstanding.1114369775
Directory /workspace/17.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.3072833514
Short name T165
Test name
Test status
Simulation time 2329985018 ps
CPU time 160.3 seconds
Started Jan 24 01:10:50 PM PST 24
Finished Jan 24 01:14:10 PM PST 24
Peak memory 257388 kb
Host smart-ed255e5d-d433-4c8b-aafd-be8b24889046
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3072833514 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shadow_reg_err
ors.3072833514
Directory /workspace/17.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.850053620
Short name T147
Test name
Test status
Simulation time 2517901259 ps
CPU time 329.09 seconds
Started Jan 24 01:10:59 PM PST 24
Finished Jan 24 01:17:03 PM PST 24
Peak memory 265744 kb
Host smart-da12c86f-fdde-4a2f-87b0-37af9417dc07
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850053620 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 17.alert_handler_shadow_reg_errors_with_csr_rw.850053620
Directory /workspace/17.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.2925111694
Short name T839
Test name
Test status
Simulation time 271067460 ps
CPU time 9.49 seconds
Started Jan 24 01:10:49 PM PST 24
Finished Jan 24 01:11:39 PM PST 24
Peak memory 248784 kb
Host smart-25e9a4ef-15c9-41c5-8b07-be03533d5fee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2925111694 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_errors.2925111694
Directory /workspace/17.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.3153759853
Short name T800
Test name
Test status
Simulation time 73940387 ps
CPU time 6.77 seconds
Started Jan 24 01:11:05 PM PST 24
Finished Jan 24 01:11:46 PM PST 24
Peak memory 253880 kb
Host smart-05f0e0dc-154e-41a1-af12-bce44589376c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153759853 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 18.alert_handler_csr_mem_rw_with_rand_reset.3153759853
Directory /workspace/18.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.2942260664
Short name T766
Test name
Test status
Simulation time 63984998 ps
CPU time 5.36 seconds
Started Jan 24 01:48:43 PM PST 24
Finished Jan 24 01:48:52 PM PST 24
Peak memory 235640 kb
Host smart-e175e36b-638b-47de-9289-bfde541939da
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2942260664 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_rw.2942260664
Directory /workspace/18.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.3671718132
Short name T757
Test name
Test status
Simulation time 9835522 ps
CPU time 1.56 seconds
Started Jan 24 01:11:06 PM PST 24
Finished Jan 24 01:11:41 PM PST 24
Peak memory 236600 kb
Host smart-5a08be95-a0bf-43cd-948e-db66afe644be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3671718132 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_intr_test.3671718132
Directory /workspace/18.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.3765623615
Short name T831
Test name
Test status
Simulation time 1436609730 ps
CPU time 45.27 seconds
Started Jan 24 01:11:00 PM PST 24
Finished Jan 24 01:12:21 PM PST 24
Peak memory 248756 kb
Host smart-983b5bf4-4fa3-4faf-88f4-6c5fa2ae78f0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3765623615 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_same_csr_ou
tstanding.3765623615
Directory /workspace/18.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.321984937
Short name T169
Test name
Test status
Simulation time 4924399264 ps
CPU time 286.99 seconds
Started Jan 24 01:10:59 PM PST 24
Finished Jan 24 01:16:21 PM PST 24
Peak memory 271012 kb
Host smart-0e3c3da1-4932-4252-9888-6ed5906b82fd
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321984937 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 18.alert_handler_shadow_reg_errors_with_csr_rw.321984937
Directory /workspace/18.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.3964598012
Short name T793
Test name
Test status
Simulation time 960399107 ps
CPU time 6.97 seconds
Started Jan 24 01:11:03 PM PST 24
Finished Jan 24 01:11:45 PM PST 24
Peak memory 248280 kb
Host smart-be8c920f-2d9b-4e27-a629-9e1e8783e2ee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3964598012 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_errors.3964598012
Directory /workspace/18.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.199905823
Short name T722
Test name
Test status
Simulation time 110802845 ps
CPU time 6.25 seconds
Started Jan 24 01:33:58 PM PST 24
Finished Jan 24 01:34:44 PM PST 24
Peak memory 251592 kb
Host smart-e57b0bdc-6de0-4a80-9585-429ec4681789
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199905823 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 19.alert_handler_csr_mem_rw_with_rand_reset.199905823
Directory /workspace/19.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.1931755846
Short name T763
Test name
Test status
Simulation time 178874687 ps
CPU time 8.23 seconds
Started Jan 24 01:11:04 PM PST 24
Finished Jan 24 01:11:47 PM PST 24
Peak memory 235640 kb
Host smart-ae59646d-a1cc-4147-b9d1-6e754e633837
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1931755846 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_rw.1931755846
Directory /workspace/19.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.1395248137
Short name T837
Test name
Test status
Simulation time 11416015 ps
CPU time 1.32 seconds
Started Jan 24 01:11:00 PM PST 24
Finished Jan 24 01:11:37 PM PST 24
Peak memory 234640 kb
Host smart-49e3d6ee-18aa-4ab1-a6f9-412936ce1a07
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1395248137 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_intr_test.1395248137
Directory /workspace/19.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.2438197146
Short name T746
Test name
Test status
Simulation time 8831292490 ps
CPU time 39.02 seconds
Started Jan 24 01:11:06 PM PST 24
Finished Jan 24 01:12:18 PM PST 24
Peak memory 244036 kb
Host smart-675a2715-fb07-4d14-b94d-fcb587ef3a62
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2438197146 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_same_csr_ou
tstanding.2438197146
Directory /workspace/19.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.1647059860
Short name T157
Test name
Test status
Simulation time 4107081457 ps
CPU time 148.62 seconds
Started Jan 24 01:11:02 PM PST 24
Finished Jan 24 01:14:05 PM PST 24
Peak memory 265476 kb
Host smart-8291bf67-c5f7-47c2-a83b-d28cf8dc1598
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1647059860 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shadow_reg_err
ors.1647059860
Directory /workspace/19.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.4046860966
Short name T170
Test name
Test status
Simulation time 15725364381 ps
CPU time 1066.62 seconds
Started Jan 24 01:11:02 PM PST 24
Finished Jan 24 01:29:24 PM PST 24
Peak memory 265484 kb
Host smart-e5bbe5c6-c4fe-4545-bff4-60fa5157f190
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046860966 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 19.alert_handler_shadow_reg_errors_with_csr_rw.4046860966
Directory /workspace/19.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.4167416089
Short name T833
Test name
Test status
Simulation time 912032348 ps
CPU time 5.53 seconds
Started Jan 24 01:11:02 PM PST 24
Finished Jan 24 01:11:42 PM PST 24
Peak memory 248776 kb
Host smart-dabba490-4359-41fe-a370-780fa80412c1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4167416089 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_errors.4167416089
Directory /workspace/19.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.328042374
Short name T783
Test name
Test status
Simulation time 4329361482 ps
CPU time 142.42 seconds
Started Jan 24 01:09:35 PM PST 24
Finished Jan 24 01:12:36 PM PST 24
Peak memory 240648 kb
Host smart-a0be1dee-a126-4f09-b144-47710551dbda
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=328042374 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_aliasing.328042374
Directory /workspace/2.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.734070045
Short name T836
Test name
Test status
Simulation time 8572528220 ps
CPU time 274.25 seconds
Started Jan 24 01:42:55 PM PST 24
Finished Jan 24 01:48:05 PM PST 24
Peak memory 236636 kb
Host smart-565856fb-e5c7-4c36-a8ee-be9305f08666
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=734070045 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_bit_bash.734070045
Directory /workspace/2.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.3907856634
Short name T828
Test name
Test status
Simulation time 107629056 ps
CPU time 3.66 seconds
Started Jan 24 01:09:39 PM PST 24
Finished Jan 24 01:10:19 PM PST 24
Peak memory 240504 kb
Host smart-98c5a55a-e7a0-4761-bcac-62c38929ee57
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3907856634 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_hw_reset.3907856634
Directory /workspace/2.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.1325007609
Short name T725
Test name
Test status
Simulation time 260708136 ps
CPU time 7.05 seconds
Started Jan 24 02:16:17 PM PST 24
Finished Jan 24 02:17:01 PM PST 24
Peak memory 251560 kb
Host smart-67f4e1c0-7f09-430b-9314-c1fd62cf6d08
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325007609 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 2.alert_handler_csr_mem_rw_with_rand_reset.1325007609
Directory /workspace/2.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.3466792222
Short name T195
Test name
Test status
Simulation time 346029418 ps
CPU time 7.38 seconds
Started Jan 24 01:09:34 PM PST 24
Finished Jan 24 01:10:20 PM PST 24
Peak memory 236512 kb
Host smart-d9033138-0208-4836-a5c7-a310ee6e4b1b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3466792222 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_rw.3466792222
Directory /workspace/2.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.3369051329
Short name T830
Test name
Test status
Simulation time 7223320 ps
CPU time 1.44 seconds
Started Jan 24 01:09:39 PM PST 24
Finished Jan 24 01:10:18 PM PST 24
Peak memory 235704 kb
Host smart-a5dc02f2-725d-44db-ada3-d8cc6cbe9f92
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3369051329 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_intr_test.3369051329
Directory /workspace/2.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.2455269618
Short name T799
Test name
Test status
Simulation time 258220839 ps
CPU time 18.47 seconds
Started Jan 24 01:09:39 PM PST 24
Finished Jan 24 01:10:35 PM PST 24
Peak memory 243880 kb
Host smart-e466c383-8f96-4fff-b3ef-71ad9355a5cf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2455269618 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_same_csr_out
standing.2455269618
Directory /workspace/2.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.1298519
Short name T156
Test name
Test status
Simulation time 2301404767 ps
CPU time 114.68 seconds
Started Jan 24 01:09:36 PM PST 24
Finished Jan 24 01:12:09 PM PST 24
Peak memory 257328 kb
Host smart-8e01a4c2-505e-45ed-804b-1c7cab88d02f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1298519 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shadow_reg_errors.1298519
Directory /workspace/2.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.1848956404
Short name T816
Test name
Test status
Simulation time 133051029 ps
CPU time 8.52 seconds
Started Jan 24 01:09:26 PM PST 24
Finished Jan 24 01:10:14 PM PST 24
Peak memory 252636 kb
Host smart-8b92ed75-d6f8-47f6-88cb-8422bdf09d5e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1848956404 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_errors.1848956404
Directory /workspace/2.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.3389775748
Short name T723
Test name
Test status
Simulation time 9445932 ps
CPU time 1.34 seconds
Started Jan 24 01:10:59 PM PST 24
Finished Jan 24 01:11:36 PM PST 24
Peak memory 236596 kb
Host smart-7d847337-a42a-4775-a850-023b3f9f678b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3389775748 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.alert_handler_intr_test.3389775748
Directory /workspace/20.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.3868029758
Short name T809
Test name
Test status
Simulation time 12192751 ps
CPU time 1.32 seconds
Started Jan 24 01:11:01 PM PST 24
Finished Jan 24 01:11:38 PM PST 24
Peak memory 236604 kb
Host smart-7cffaf45-a594-4d31-b32a-bf94e17d3ff1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3868029758 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.alert_handler_intr_test.3868029758
Directory /workspace/21.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.2906532246
Short name T788
Test name
Test status
Simulation time 17611058 ps
CPU time 1.34 seconds
Started Jan 24 01:10:59 PM PST 24
Finished Jan 24 01:11:37 PM PST 24
Peak memory 235724 kb
Host smart-d76ba46c-95cc-43d8-b736-d0c57687d7dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2906532246 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.alert_handler_intr_test.2906532246
Directory /workspace/22.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.3667121613
Short name T764
Test name
Test status
Simulation time 18295092 ps
CPU time 1.45 seconds
Started Jan 24 01:11:11 PM PST 24
Finished Jan 24 01:11:45 PM PST 24
Peak memory 236604 kb
Host smart-af452014-3a10-46db-9b08-abd4ad410e71
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3667121613 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.alert_handler_intr_test.3667121613
Directory /workspace/23.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.1309550005
Short name T796
Test name
Test status
Simulation time 12114670 ps
CPU time 1.62 seconds
Started Jan 24 01:11:11 PM PST 24
Finished Jan 24 01:11:45 PM PST 24
Peak memory 236604 kb
Host smart-cbd3033a-a4db-412c-852d-35c9ceb0bbc7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1309550005 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.alert_handler_intr_test.1309550005
Directory /workspace/24.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.119389361
Short name T773
Test name
Test status
Simulation time 8846540 ps
CPU time 1.58 seconds
Started Jan 24 01:11:13 PM PST 24
Finished Jan 24 01:11:47 PM PST 24
Peak memory 235720 kb
Host smart-af0ae16e-e49c-4da6-8f4f-d2713444248c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=119389361 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.alert_handler_intr_test.119389361
Directory /workspace/25.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.3912170550
Short name T726
Test name
Test status
Simulation time 11381242 ps
CPU time 1.46 seconds
Started Jan 24 01:11:13 PM PST 24
Finished Jan 24 01:11:47 PM PST 24
Peak memory 235840 kb
Host smart-010b8678-6358-4bf3-9b13-f7a447503501
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3912170550 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.alert_handler_intr_test.3912170550
Directory /workspace/26.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.3248008600
Short name T758
Test name
Test status
Simulation time 11404243 ps
CPU time 1.32 seconds
Started Jan 24 01:11:13 PM PST 24
Finished Jan 24 01:11:47 PM PST 24
Peak memory 235712 kb
Host smart-44fccce5-3e43-4b1f-9ecf-ef527cfd4ada
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3248008600 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.alert_handler_intr_test.3248008600
Directory /workspace/27.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.1841652576
Short name T803
Test name
Test status
Simulation time 9470407 ps
CPU time 1.6 seconds
Started Jan 24 01:11:14 PM PST 24
Finished Jan 24 01:11:48 PM PST 24
Peak memory 235732 kb
Host smart-38e105f1-af0d-4640-8699-4e8b7bf48e2a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1841652576 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.alert_handler_intr_test.1841652576
Directory /workspace/28.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.2744004732
Short name T790
Test name
Test status
Simulation time 20183576 ps
CPU time 1.24 seconds
Started Jan 24 01:11:11 PM PST 24
Finished Jan 24 01:11:45 PM PST 24
Peak memory 235708 kb
Host smart-4d5ad8c3-a993-49a9-9181-00dd770a385f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2744004732 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.alert_handler_intr_test.2744004732
Directory /workspace/29.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.3947816137
Short name T813
Test name
Test status
Simulation time 18199243546 ps
CPU time 240.67 seconds
Started Jan 24 01:09:39 PM PST 24
Finished Jan 24 01:14:17 PM PST 24
Peak memory 239828 kb
Host smart-f0c0e8cb-bbf2-4a6c-8da0-fdc9ce598a42
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3947816137 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_aliasing.3947816137
Directory /workspace/3.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.511127395
Short name T762
Test name
Test status
Simulation time 1779682559 ps
CPU time 102.33 seconds
Started Jan 24 01:27:03 PM PST 24
Finished Jan 24 01:29:23 PM PST 24
Peak memory 236504 kb
Host smart-345b4a63-d3ac-4fc7-a2fc-f6a96f33306d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=511127395 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_bit_bash.511127395
Directory /workspace/3.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.3398847302
Short name T724
Test name
Test status
Simulation time 133831941 ps
CPU time 10 seconds
Started Jan 24 01:09:39 PM PST 24
Finished Jan 24 01:10:27 PM PST 24
Peak memory 240468 kb
Host smart-9a03a7b6-d7ad-4b71-bf26-f79bed354b19
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3398847302 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_hw_reset.3398847302
Directory /workspace/3.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.3467454620
Short name T772
Test name
Test status
Simulation time 116908296 ps
CPU time 5.85 seconds
Started Jan 24 01:09:43 PM PST 24
Finished Jan 24 01:10:25 PM PST 24
Peak memory 252296 kb
Host smart-af68b68f-4e1f-47e4-be8e-d2a698b80814
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467454620 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 3.alert_handler_csr_mem_rw_with_rand_reset.3467454620
Directory /workspace/3.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.1060290275
Short name T751
Test name
Test status
Simulation time 177291049 ps
CPU time 7.41 seconds
Started Jan 24 01:09:37 PM PST 24
Finished Jan 24 01:10:23 PM PST 24
Peak memory 240508 kb
Host smart-620b8de1-e0ab-4283-8f3d-597b0adb254a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1060290275 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_rw.1060290275
Directory /workspace/3.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.1112540441
Short name T792
Test name
Test status
Simulation time 9523271 ps
CPU time 1.46 seconds
Started Jan 24 01:28:51 PM PST 24
Finished Jan 24 01:29:12 PM PST 24
Peak memory 236604 kb
Host smart-5a3aa134-2d24-4e54-8ac8-427f9660a970
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1112540441 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_intr_test.1112540441
Directory /workspace/3.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.442057011
Short name T736
Test name
Test status
Simulation time 627208510 ps
CPU time 22.13 seconds
Started Jan 24 01:09:39 PM PST 24
Finished Jan 24 01:10:38 PM PST 24
Peak memory 244808 kb
Host smart-471fc57f-4c39-49e8-a7e2-cc7656854739
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=442057011 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_same_csr_outs
tanding.442057011
Directory /workspace/3.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.1535124869
Short name T731
Test name
Test status
Simulation time 304215549 ps
CPU time 20.4 seconds
Started Jan 24 01:09:36 PM PST 24
Finished Jan 24 01:10:35 PM PST 24
Peak memory 248812 kb
Host smart-5e7ea4b8-eb0b-4856-8c74-a61d32c26469
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1535124869 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_errors.1535124869
Directory /workspace/3.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.2849341299
Short name T738
Test name
Test status
Simulation time 40233368 ps
CPU time 3.01 seconds
Started Jan 24 01:09:36 PM PST 24
Finished Jan 24 01:10:18 PM PST 24
Peak memory 236600 kb
Host smart-8b0c100b-c45e-4790-a60a-b93fc122ad5c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2849341299 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_intg_err.2849341299
Directory /workspace/3.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.1763152014
Short name T344
Test name
Test status
Simulation time 6581216 ps
CPU time 1.46 seconds
Started Jan 24 01:11:13 PM PST 24
Finished Jan 24 01:11:47 PM PST 24
Peak memory 235688 kb
Host smart-e026245a-3979-4622-a3bf-3a7982d5f121
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1763152014 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.alert_handler_intr_test.1763152014
Directory /workspace/30.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.763996287
Short name T821
Test name
Test status
Simulation time 6436808 ps
CPU time 1.45 seconds
Started Jan 24 01:11:12 PM PST 24
Finished Jan 24 01:11:45 PM PST 24
Peak memory 236616 kb
Host smart-ff8b2590-3efb-4537-a94a-53dc4d31d002
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=763996287 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.alert_handler_intr_test.763996287
Directory /workspace/31.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.3669514126
Short name T812
Test name
Test status
Simulation time 15968357 ps
CPU time 1.4 seconds
Started Jan 24 01:11:12 PM PST 24
Finished Jan 24 01:11:45 PM PST 24
Peak memory 236580 kb
Host smart-b1804074-306c-4e03-83d0-597d4f4eb457
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3669514126 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.alert_handler_intr_test.3669514126
Directory /workspace/32.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.1132621697
Short name T752
Test name
Test status
Simulation time 10102090 ps
CPU time 1.24 seconds
Started Jan 24 01:11:10 PM PST 24
Finished Jan 24 01:11:44 PM PST 24
Peak memory 235672 kb
Host smart-42e3cc12-be84-4e2c-b8f1-9f8ada2eb1c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1132621697 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.alert_handler_intr_test.1132621697
Directory /workspace/33.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.164567700
Short name T345
Test name
Test status
Simulation time 11470677 ps
CPU time 1.62 seconds
Started Jan 24 01:11:11 PM PST 24
Finished Jan 24 01:11:45 PM PST 24
Peak memory 235732 kb
Host smart-a80049d6-c78e-441a-8ec3-303bba2f2a96
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=164567700 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.alert_handler_intr_test.164567700
Directory /workspace/34.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.2780227602
Short name T745
Test name
Test status
Simulation time 10863498 ps
CPU time 1.29 seconds
Started Jan 24 01:11:31 PM PST 24
Finished Jan 24 01:12:12 PM PST 24
Peak memory 236556 kb
Host smart-314a77f5-0492-4c1c-b62c-c078ea6a4dc4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2780227602 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.alert_handler_intr_test.2780227602
Directory /workspace/35.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.1702529617
Short name T349
Test name
Test status
Simulation time 7983780 ps
CPU time 1.34 seconds
Started Jan 24 01:11:31 PM PST 24
Finished Jan 24 01:12:12 PM PST 24
Peak memory 236596 kb
Host smart-76b69a66-8943-456e-b67d-76afe4fe392c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1702529617 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.alert_handler_intr_test.1702529617
Directory /workspace/36.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.3744838258
Short name T820
Test name
Test status
Simulation time 18096583 ps
CPU time 1.44 seconds
Started Jan 24 01:11:18 PM PST 24
Finished Jan 24 01:11:53 PM PST 24
Peak memory 235740 kb
Host smart-69967659-83f0-4d57-bee4-7d32e694addf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3744838258 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.alert_handler_intr_test.3744838258
Directory /workspace/37.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.1747002755
Short name T779
Test name
Test status
Simulation time 16340692 ps
CPU time 1.47 seconds
Started Jan 24 01:11:17 PM PST 24
Finished Jan 24 01:11:52 PM PST 24
Peak memory 236612 kb
Host smart-6d85fcc0-a8ba-4478-92fc-572b7f827569
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1747002755 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.alert_handler_intr_test.1747002755
Directory /workspace/38.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.489618100
Short name T739
Test name
Test status
Simulation time 6721392 ps
CPU time 1.5 seconds
Started Jan 24 01:11:31 PM PST 24
Finished Jan 24 01:12:13 PM PST 24
Peak memory 236600 kb
Host smart-e85880cb-8552-4a6f-9251-4bd8006343be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=489618100 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.alert_handler_intr_test.489618100
Directory /workspace/39.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.2497005164
Short name T744
Test name
Test status
Simulation time 17185904573 ps
CPU time 294.41 seconds
Started Jan 24 01:09:54 PM PST 24
Finished Jan 24 01:15:23 PM PST 24
Peak memory 240608 kb
Host smart-cc5778f3-b77c-4fd2-8413-675ba48600bb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2497005164 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_aliasing.2497005164
Directory /workspace/4.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.3661862233
Short name T197
Test name
Test status
Simulation time 821688335 ps
CPU time 105.07 seconds
Started Jan 24 01:09:54 PM PST 24
Finished Jan 24 01:12:14 PM PST 24
Peak memory 236428 kb
Host smart-d3bc2128-3bdd-416e-90e7-8288ddb48417
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3661862233 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_bit_bash.3661862233
Directory /workspace/4.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.1698998595
Short name T749
Test name
Test status
Simulation time 57422238 ps
CPU time 5.37 seconds
Started Jan 24 01:09:53 PM PST 24
Finished Jan 24 01:10:34 PM PST 24
Peak memory 240440 kb
Host smart-a4efb704-c8aa-4e58-9301-cd5cc6bdd480
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1698998595 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_hw_reset.1698998595
Directory /workspace/4.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.1440624281
Short name T741
Test name
Test status
Simulation time 53436252 ps
CPU time 6.32 seconds
Started Jan 24 01:09:54 PM PST 24
Finished Jan 24 01:10:35 PM PST 24
Peak memory 248812 kb
Host smart-47a23b65-1651-41bc-9261-0a5e6e58747f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440624281 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 4.alert_handler_csr_mem_rw_with_rand_reset.1440624281
Directory /workspace/4.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.3371311915
Short name T760
Test name
Test status
Simulation time 35286751 ps
CPU time 3.35 seconds
Started Jan 24 01:09:52 PM PST 24
Finished Jan 24 01:10:31 PM PST 24
Peak memory 240264 kb
Host smart-bd67d301-80f8-4eb8-8daa-7c03c2498ac3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3371311915 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_rw.3371311915
Directory /workspace/4.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.1510676744
Short name T785
Test name
Test status
Simulation time 9731981 ps
CPU time 1.56 seconds
Started Jan 24 01:09:50 PM PST 24
Finished Jan 24 01:10:28 PM PST 24
Peak memory 235744 kb
Host smart-6a13df3f-3b8d-4a74-b26a-bffa4d68541b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1510676744 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_intr_test.1510676744
Directory /workspace/4.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.3847411837
Short name T743
Test name
Test status
Simulation time 173076294 ps
CPU time 22.49 seconds
Started Jan 24 01:09:55 PM PST 24
Finished Jan 24 01:10:52 PM PST 24
Peak memory 248744 kb
Host smart-c353ef4c-d7b1-401d-a461-6962fd23f607
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3847411837 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_same_csr_out
standing.3847411837
Directory /workspace/4.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.96770711
Short name T348
Test name
Test status
Simulation time 2481387830 ps
CPU time 330.23 seconds
Started Jan 24 01:35:47 PM PST 24
Finished Jan 24 01:41:44 PM PST 24
Peak memory 265544 kb
Host smart-c4960997-4de8-448d-8750-a1b8a54cf379
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96770711 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_
TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -
cm_name 4.alert_handler_shadow_reg_errors_with_csr_rw.96770711
Directory /workspace/4.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.601242351
Short name T823
Test name
Test status
Simulation time 1460139384 ps
CPU time 25.78 seconds
Started Jan 24 01:09:52 PM PST 24
Finished Jan 24 01:10:54 PM PST 24
Peak memory 248828 kb
Host smart-a58db741-94cd-4984-99dc-e3e86cb7c9ba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=601242351 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_errors.601242351
Directory /workspace/4.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.4269445917
Short name T797
Test name
Test status
Simulation time 10362582 ps
CPU time 1.37 seconds
Started Jan 24 01:11:18 PM PST 24
Finished Jan 24 01:11:53 PM PST 24
Peak memory 236596 kb
Host smart-bbf36878-3f20-4d2f-ba35-fc71de8cea43
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4269445917 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.alert_handler_intr_test.4269445917
Directory /workspace/40.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.3912089966
Short name T194
Test name
Test status
Simulation time 9653805 ps
CPU time 1.26 seconds
Started Jan 24 01:11:31 PM PST 24
Finished Jan 24 01:12:13 PM PST 24
Peak memory 235720 kb
Host smart-8bc4e301-8467-4bb9-83f7-36f0ae1d300c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3912089966 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.alert_handler_intr_test.3912089966
Directory /workspace/41.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.3307677118
Short name T735
Test name
Test status
Simulation time 19507059 ps
CPU time 1.36 seconds
Started Jan 24 01:11:18 PM PST 24
Finished Jan 24 01:11:54 PM PST 24
Peak memory 234628 kb
Host smart-8c3a1342-3c95-41c8-b26c-55f598ca7a39
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3307677118 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.alert_handler_intr_test.3307677118
Directory /workspace/42.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.2468093610
Short name T175
Test name
Test status
Simulation time 44853932 ps
CPU time 1.46 seconds
Started Jan 24 01:11:31 PM PST 24
Finished Jan 24 01:12:13 PM PST 24
Peak memory 235708 kb
Host smart-97b253e6-dd43-4714-ba7c-48e4b431bd0e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2468093610 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.alert_handler_intr_test.2468093610
Directory /workspace/43.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.4258292446
Short name T805
Test name
Test status
Simulation time 14134963 ps
CPU time 1.59 seconds
Started Jan 24 01:11:18 PM PST 24
Finished Jan 24 01:11:54 PM PST 24
Peak memory 236596 kb
Host smart-3f9e5518-ece6-409e-a0c6-d11aea4442da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4258292446 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.alert_handler_intr_test.4258292446
Directory /workspace/44.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.1828716650
Short name T742
Test name
Test status
Simulation time 10297856 ps
CPU time 1.36 seconds
Started Jan 24 01:11:20 PM PST 24
Finished Jan 24 01:11:55 PM PST 24
Peak memory 235652 kb
Host smart-2aae6e20-307f-4e75-b78b-6b3c1e1e1bcd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1828716650 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.alert_handler_intr_test.1828716650
Directory /workspace/45.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.442160485
Short name T755
Test name
Test status
Simulation time 13205124 ps
CPU time 1.69 seconds
Started Jan 24 01:11:19 PM PST 24
Finished Jan 24 01:11:54 PM PST 24
Peak memory 236556 kb
Host smart-2c86c20c-c0f3-4a09-9454-9425a4415d76
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=442160485 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.alert_handler_intr_test.442160485
Directory /workspace/46.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.1287049679
Short name T768
Test name
Test status
Simulation time 12610508 ps
CPU time 1.29 seconds
Started Jan 24 01:11:18 PM PST 24
Finished Jan 24 01:11:54 PM PST 24
Peak memory 236592 kb
Host smart-1150ebc0-42af-4a0e-826e-7fb5adc25e9d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1287049679 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.alert_handler_intr_test.1287049679
Directory /workspace/47.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.495504804
Short name T727
Test name
Test status
Simulation time 8287239 ps
CPU time 1.45 seconds
Started Jan 24 01:11:20 PM PST 24
Finished Jan 24 01:11:57 PM PST 24
Peak memory 235712 kb
Host smart-b7ed72fa-7be9-4636-91e8-3e8ddeafbedf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=495504804 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.alert_handler_intr_test.495504804
Directory /workspace/48.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.69086360
Short name T777
Test name
Test status
Simulation time 9584810 ps
CPU time 1.27 seconds
Started Jan 24 01:11:31 PM PST 24
Finished Jan 24 01:12:13 PM PST 24
Peak memory 235720 kb
Host smart-c36fa1fc-7c68-4f06-a73b-bf4b395b8618
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=69086360 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.alert_handler_intr_test.69086360
Directory /workspace/49.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.1922192587
Short name T137
Test name
Test status
Simulation time 77751441 ps
CPU time 4.2 seconds
Started Jan 24 01:10:01 PM PST 24
Finished Jan 24 01:10:39 PM PST 24
Peak memory 239240 kb
Host smart-b18c926d-4362-4d8f-8971-9e507f7c5de1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922192587 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 5.alert_handler_csr_mem_rw_with_rand_reset.1922192587
Directory /workspace/5.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.1422092723
Short name T811
Test name
Test status
Simulation time 32773256 ps
CPU time 5.24 seconds
Started Jan 24 01:09:54 PM PST 24
Finished Jan 24 01:10:34 PM PST 24
Peak memory 236504 kb
Host smart-825536f9-6832-4a59-9cd5-8e3cf38a9ad4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1422092723 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_rw.1422092723
Directory /workspace/5.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.1310756503
Short name T202
Test name
Test status
Simulation time 8477475 ps
CPU time 1.44 seconds
Started Jan 24 01:09:55 PM PST 24
Finished Jan 24 01:10:30 PM PST 24
Peak memory 236616 kb
Host smart-fe801ce0-3511-45ef-9c92-c60969802ff3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1310756503 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_intr_test.1310756503
Directory /workspace/5.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.1094954665
Short name T732
Test name
Test status
Simulation time 527322189 ps
CPU time 19.58 seconds
Started Jan 24 01:09:54 PM PST 24
Finished Jan 24 01:10:48 PM PST 24
Peak memory 244800 kb
Host smart-7bad5c18-850a-4409-ad8c-c715ded62dc6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1094954665 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_same_csr_out
standing.1094954665
Directory /workspace/5.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.1916232950
Short name T155
Test name
Test status
Simulation time 17350500813 ps
CPU time 596.94 seconds
Started Jan 24 01:09:54 PM PST 24
Finished Jan 24 01:20:25 PM PST 24
Peak memory 265768 kb
Host smart-33f4a791-3308-4d42-8734-53a5abbde3a1
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916232950 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.alert_handler_shadow_reg_errors_with_csr_rw.1916232950
Directory /workspace/5.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.2619190760
Short name T769
Test name
Test status
Simulation time 941673097 ps
CPU time 20.38 seconds
Started Jan 24 01:10:00 PM PST 24
Finished Jan 24 01:10:54 PM PST 24
Peak memory 248744 kb
Host smart-b7637be6-0f28-4e58-8e32-c58c43538f74
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2619190760 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_errors.2619190760
Directory /workspace/5.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.3083473524
Short name T775
Test name
Test status
Simulation time 164512143 ps
CPU time 6.41 seconds
Started Jan 24 01:10:00 PM PST 24
Finished Jan 24 01:10:40 PM PST 24
Peak memory 250692 kb
Host smart-4a647c20-4f9f-4119-8ed0-4607c68030cc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083473524 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 6.alert_handler_csr_mem_rw_with_rand_reset.3083473524
Directory /workspace/6.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.3208112439
Short name T730
Test name
Test status
Simulation time 91298925 ps
CPU time 4.58 seconds
Started Jan 24 01:10:00 PM PST 24
Finished Jan 24 01:10:38 PM PST 24
Peak memory 236528 kb
Host smart-9a93b299-037d-4c76-be58-8e8d4e1ec991
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3208112439 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_rw.3208112439
Directory /workspace/6.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.3063199804
Short name T780
Test name
Test status
Simulation time 8664477 ps
CPU time 1.39 seconds
Started Jan 24 01:09:56 PM PST 24
Finished Jan 24 01:10:31 PM PST 24
Peak memory 235684 kb
Host smart-f4b41978-b345-4b96-9d92-4543c9e664dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3063199804 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_intr_test.3063199804
Directory /workspace/6.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.1294567871
Short name T191
Test name
Test status
Simulation time 5100834342 ps
CPU time 20.59 seconds
Started Jan 24 01:09:55 PM PST 24
Finished Jan 24 01:10:50 PM PST 24
Peak memory 244784 kb
Host smart-3bca8222-de75-471d-b79f-ca072252c73d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1294567871 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_same_csr_out
standing.1294567871
Directory /workspace/6.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.451628768
Short name T148
Test name
Test status
Simulation time 2367929033 ps
CPU time 143.29 seconds
Started Jan 24 01:10:01 PM PST 24
Finished Jan 24 01:12:58 PM PST 24
Peak memory 257348 kb
Host smart-ec1dd28c-817f-4cc1-91e8-18e48dbd16f1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=451628768 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shadow_reg_error
s.451628768
Directory /workspace/6.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.24574529
Short name T346
Test name
Test status
Simulation time 28285304373 ps
CPU time 949.7 seconds
Started Jan 24 01:10:01 PM PST 24
Finished Jan 24 01:26:25 PM PST 24
Peak memory 265704 kb
Host smart-2a0352b2-b0f4-413d-a31c-31d334f5a354
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24574529 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_
TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -
cm_name 6.alert_handler_shadow_reg_errors_with_csr_rw.24574529
Directory /workspace/6.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.2745076031
Short name T734
Test name
Test status
Simulation time 202751407 ps
CPU time 12.69 seconds
Started Jan 24 01:10:00 PM PST 24
Finished Jan 24 01:10:46 PM PST 24
Peak memory 248472 kb
Host smart-631e9d1c-2231-4a51-86d8-14738ff9e796
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2745076031 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_errors.2745076031
Directory /workspace/6.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.1699290840
Short name T819
Test name
Test status
Simulation time 37425045 ps
CPU time 3.88 seconds
Started Jan 24 01:10:01 PM PST 24
Finished Jan 24 01:10:38 PM PST 24
Peak memory 236448 kb
Host smart-2685b223-31e5-44de-a886-c27db75a5a70
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699290840 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 7.alert_handler_csr_mem_rw_with_rand_reset.1699290840
Directory /workspace/7.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.2451509875
Short name T28
Test name
Test status
Simulation time 111999304 ps
CPU time 8.31 seconds
Started Jan 24 01:10:13 PM PST 24
Finished Jan 24 01:10:57 PM PST 24
Peak memory 236460 kb
Host smart-1d595295-e9d8-4e75-8bf7-7aca4ef9d2ae
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2451509875 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_rw.2451509875
Directory /workspace/7.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.316780257
Short name T832
Test name
Test status
Simulation time 14547828 ps
CPU time 1.34 seconds
Started Jan 24 01:10:01 PM PST 24
Finished Jan 24 01:10:36 PM PST 24
Peak memory 234480 kb
Host smart-11478d49-2fd5-4f65-b20d-22c20fa3146f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=316780257 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_intr_test.316780257
Directory /workspace/7.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.1057998876
Short name T750
Test name
Test status
Simulation time 2025916852 ps
CPU time 34.19 seconds
Started Jan 24 01:10:06 PM PST 24
Finished Jan 24 01:11:13 PM PST 24
Peak memory 248736 kb
Host smart-67848a12-1cc3-40de-85a0-b5d82db46fae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1057998876 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_same_csr_out
standing.1057998876
Directory /workspace/7.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.975429316
Short name T27
Test name
Test status
Simulation time 2177982336 ps
CPU time 151.63 seconds
Started Jan 24 01:09:55 PM PST 24
Finished Jan 24 01:13:01 PM PST 24
Peak memory 257336 kb
Host smart-dfcd8f1d-5c57-4d23-999f-8da7d3f5a84e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=975429316 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shadow_reg_error
s.975429316
Directory /workspace/7.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.2436842069
Short name T347
Test name
Test status
Simulation time 8996288781 ps
CPU time 289.68 seconds
Started Jan 24 01:10:13 PM PST 24
Finished Jan 24 01:15:38 PM PST 24
Peak memory 265688 kb
Host smart-ae3d5a5c-a23b-4ce6-b7b7-081d913a4eb0
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436842069 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.alert_handler_shadow_reg_errors_with_csr_rw.2436842069
Directory /workspace/7.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.2685901878
Short name T815
Test name
Test status
Simulation time 1034860014 ps
CPU time 21.79 seconds
Started Jan 24 01:10:00 PM PST 24
Finished Jan 24 01:10:55 PM PST 24
Peak memory 253328 kb
Host smart-6d902df9-0c00-45fb-9886-84269efabb60
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2685901878 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_errors.2685901878
Directory /workspace/7.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.1433703848
Short name T770
Test name
Test status
Simulation time 36080046 ps
CPU time 4.33 seconds
Started Jan 24 01:10:08 PM PST 24
Finished Jan 24 01:10:45 PM PST 24
Peak memory 239312 kb
Host smart-8f5b6deb-c7a7-4d71-a6bc-c1aaa3bf2629
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433703848 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 8.alert_handler_csr_mem_rw_with_rand_reset.1433703848
Directory /workspace/8.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.822090349
Short name T737
Test name
Test status
Simulation time 22397680 ps
CPU time 3.65 seconds
Started Jan 24 01:10:07 PM PST 24
Finished Jan 24 01:10:42 PM PST 24
Peak memory 236468 kb
Host smart-00447977-1f3c-4974-a1d2-0dedb57258a8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=822090349 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_rw.822090349
Directory /workspace/8.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.2964937469
Short name T771
Test name
Test status
Simulation time 40978826 ps
CPU time 1.34 seconds
Started Jan 24 01:10:07 PM PST 24
Finished Jan 24 01:10:40 PM PST 24
Peak memory 235624 kb
Host smart-c0936bbe-dad8-469d-beff-9621d43cdca5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2964937469 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_intr_test.2964937469
Directory /workspace/8.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.377410961
Short name T164
Test name
Test status
Simulation time 1602134957 ps
CPU time 114.37 seconds
Started Jan 24 01:10:14 PM PST 24
Finished Jan 24 01:12:44 PM PST 24
Peak memory 257240 kb
Host smart-55d1f8d5-45fd-4e0b-965e-1431d60f777e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=377410961 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shadow_reg_error
s.377410961
Directory /workspace/8.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.765591662
Short name T756
Test name
Test status
Simulation time 1460255802 ps
CPU time 12.24 seconds
Started Jan 24 01:10:13 PM PST 24
Finished Jan 24 01:11:01 PM PST 24
Peak memory 248832 kb
Host smart-d27224ce-707a-4000-a88a-6151656be9ad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=765591662 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_errors.765591662
Directory /workspace/8.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.2486048595
Short name T810
Test name
Test status
Simulation time 15554053 ps
CPU time 3.29 seconds
Started Jan 24 01:10:08 PM PST 24
Finished Jan 24 01:10:44 PM PST 24
Peak memory 240272 kb
Host smart-65d3b271-1228-431b-8033-c2a94b352563
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486048595 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 9.alert_handler_csr_mem_rw_with_rand_reset.2486048595
Directory /workspace/9.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.1592317671
Short name T193
Test name
Test status
Simulation time 36908057 ps
CPU time 5.44 seconds
Started Jan 24 01:10:08 PM PST 24
Finished Jan 24 01:10:47 PM PST 24
Peak memory 240456 kb
Host smart-4f566e38-d39b-475c-83e1-25d005128627
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1592317671 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_rw.1592317671
Directory /workspace/9.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.2747785484
Short name T791
Test name
Test status
Simulation time 15686709 ps
CPU time 1.3 seconds
Started Jan 24 01:10:13 PM PST 24
Finished Jan 24 01:10:50 PM PST 24
Peak memory 235728 kb
Host smart-c41044d8-cee3-4f9a-949a-e194a363ed19
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2747785484 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_intr_test.2747785484
Directory /workspace/9.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.2055480592
Short name T192
Test name
Test status
Simulation time 5037895297 ps
CPU time 46.8 seconds
Started Jan 24 01:10:13 PM PST 24
Finished Jan 24 01:11:35 PM PST 24
Peak memory 244232 kb
Host smart-bbf01d29-48e8-4227-82c6-bfab65ddfbec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2055480592 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_same_csr_out
standing.2055480592
Directory /workspace/9.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.3041328242
Short name T139
Test name
Test status
Simulation time 23305112870 ps
CPU time 366.51 seconds
Started Jan 24 01:10:05 PM PST 24
Finished Jan 24 01:16:44 PM PST 24
Peak memory 265512 kb
Host smart-0063200e-36cb-49f6-93ab-04e0b2543f9b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3041328242 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shadow_reg_erro
rs.3041328242
Directory /workspace/9.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.3921073798
Short name T153
Test name
Test status
Simulation time 8724326552 ps
CPU time 586.63 seconds
Started Jan 24 01:10:13 PM PST 24
Finished Jan 24 01:20:35 PM PST 24
Peak memory 264920 kb
Host smart-b6d75125-049c-4a58-9f38-466fa198fe44
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921073798 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.alert_handler_shadow_reg_errors_with_csr_rw.3921073798
Directory /workspace/9.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.1679136236
Short name T782
Test name
Test status
Simulation time 495033007 ps
CPU time 9.4 seconds
Started Jan 24 01:10:05 PM PST 24
Finished Jan 24 01:10:46 PM PST 24
Peak memory 252684 kb
Host smart-82165fa1-6f30-418f-8366-5e44740ff55b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1679136236 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_errors.1679136236
Directory /workspace/9.alert_handler_tl_errors/latest

Test location /workspace/coverage/default/0.alert_handler_entropy.128102500
Short name T129
Test name
Test status
Simulation time 14815913424 ps
CPU time 714.12 seconds
Started Jan 24 01:38:34 PM PST 24
Finished Jan 24 01:50:50 PM PST 24
Peak memory 271312 kb
Host smart-a1bd78ea-76c0-48ce-ae69-2a036d9ccb84
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128102500 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy.128102500
Directory /workspace/0.alert_handler_entropy/latest

Test location /workspace/coverage/default/0.alert_handler_entropy_stress.3473439155
Short name T385
Test name
Test status
Simulation time 2340292493 ps
CPU time 27.89 seconds
Started Jan 24 02:54:16 PM PST 24
Finished Jan 24 02:55:08 PM PST 24
Peak memory 248204 kb
Host smart-d7d806ef-6638-4c26-8dd4-bae9f2272afc
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3473439155 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy_stress.3473439155
Directory /workspace/0.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/0.alert_handler_esc_alert_accum.1330820773
Short name T403
Test name
Test status
Simulation time 2370797290 ps
CPU time 14 seconds
Started Jan 24 02:29:50 PM PST 24
Finished Jan 24 02:30:18 PM PST 24
Peak memory 252656 kb
Host smart-9031f826-0765-4fce-8491-9e80750451bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13308
20773 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_alert_accum.1330820773
Directory /workspace/0.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/0.alert_handler_esc_intr_timeout.3431381824
Short name T704
Test name
Test status
Simulation time 172351727 ps
CPU time 4.57 seconds
Started Jan 24 01:38:33 PM PST 24
Finished Jan 24 01:39:00 PM PST 24
Peak memory 239832 kb
Host smart-758cde42-e737-4fd8-9627-95098268323c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34313
81824 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_intr_timeout.3431381824
Directory /workspace/0.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_lpg_stub_clk.3641249305
Short name T106
Test name
Test status
Simulation time 28534675539 ps
CPU time 1758.98 seconds
Started Jan 24 01:38:36 PM PST 24
Finished Jan 24 02:08:16 PM PST 24
Peak memory 271464 kb
Host smart-baa577bb-9fdb-4e91-ba1f-fe5d63c7cd47
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641249305 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg_stub_clk.3641249305
Directory /workspace/0.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/0.alert_handler_ping_timeout.3890605060
Short name T696
Test name
Test status
Simulation time 3162401684 ps
CPU time 133.91 seconds
Started Jan 24 01:38:46 PM PST 24
Finished Jan 24 01:41:14 PM PST 24
Peak memory 246560 kb
Host smart-157800b4-db28-4fd2-9bee-cc7ec4306ca5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3890605060 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_ping_timeout.3890605060
Directory /workspace/0.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_random_alerts.1910747795
Short name T539
Test name
Test status
Simulation time 268438622 ps
CPU time 16.75 seconds
Started Jan 24 02:33:17 PM PST 24
Finished Jan 24 02:34:01 PM PST 24
Peak memory 256228 kb
Host smart-0969cbef-636d-40f9-90ba-13f1ea06985d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19107
47795 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_alerts.1910747795
Directory /workspace/0.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/0.alert_handler_random_classes.2307967586
Short name T525
Test name
Test status
Simulation time 593575466 ps
CPU time 36.77 seconds
Started Jan 24 01:38:39 PM PST 24
Finished Jan 24 01:39:35 PM PST 24
Peak memory 254308 kb
Host smart-2aedaa00-5a52-4a22-9e52-88d7ad84a845
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23079
67586 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_classes.2307967586
Directory /workspace/0.alert_handler_random_classes/latest

Test location /workspace/coverage/default/0.alert_handler_sec_cm.1369994738
Short name T10
Test name
Test status
Simulation time 969334005 ps
CPU time 24.94 seconds
Started Jan 24 01:38:45 PM PST 24
Finished Jan 24 01:39:25 PM PST 24
Peak memory 269868 kb
Host smart-f0967ebc-9171-4a80-a0c7-e407e8e083a0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1369994738 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sec_cm.1369994738
Directory /workspace/0.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/0.alert_handler_sig_int_fail.613031405
Short name T714
Test name
Test status
Simulation time 386839326 ps
CPU time 30.46 seconds
Started Jan 24 01:43:52 PM PST 24
Finished Jan 24 01:44:26 PM PST 24
Peak memory 248040 kb
Host smart-e9f83b5b-4859-445f-946f-0e9473e00798
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61303
1405 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sig_int_fail.613031405
Directory /workspace/0.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/0.alert_handler_smoke.542384303
Short name T355
Test name
Test status
Simulation time 226535480 ps
CPU time 18.32 seconds
Started Jan 24 01:38:38 PM PST 24
Finished Jan 24 01:39:16 PM PST 24
Peak memory 250396 kb
Host smart-a558a6bd-0be5-42a1-9bf8-25405a05b0d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54238
4303 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_smoke.542384303
Directory /workspace/0.alert_handler_smoke/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all.2925815694
Short name T209
Test name
Test status
Simulation time 53041226698 ps
CPU time 1346.09 seconds
Started Jan 24 01:38:52 PM PST 24
Finished Jan 24 02:01:29 PM PST 24
Peak memory 285068 kb
Host smart-541a080f-01f3-44c9-8d49-c630278ce4f3
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925815694 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_han
dler_stress_all.2925815694
Directory /workspace/0.alert_handler_stress_all/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all_with_rand_reset.1454273909
Short name T37
Test name
Test status
Simulation time 55366377122 ps
CPU time 3760.74 seconds
Started Jan 24 01:38:51 PM PST 24
Finished Jan 24 02:41:43 PM PST 24
Peak memory 297240 kb
Host smart-ccadfd25-0458-409e-b36e-dd01c8234585
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454273909 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.alert_handler_stress_all_with_rand_reset.1454273909
Directory /workspace/0.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.alert_handler_alert_accum_saturation.3046376346
Short name T221
Test name
Test status
Simulation time 142198764 ps
CPU time 2.97 seconds
Started Jan 24 01:38:50 PM PST 24
Finished Jan 24 01:39:05 PM PST 24
Peak memory 248256 kb
Host smart-74867228-f655-4cfd-917c-aae05f669a6b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3046376346 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_alert_accum_saturation.3046376346
Directory /workspace/1.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/1.alert_handler_entropy.4052304801
Short name T133
Test name
Test status
Simulation time 39197833319 ps
CPU time 2446.6 seconds
Started Jan 24 01:38:48 PM PST 24
Finished Jan 24 02:19:48 PM PST 24
Peak memory 271348 kb
Host smart-4e31d888-49a7-4c3d-80cf-4cbaf2e1eee5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052304801 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy.4052304801
Directory /workspace/1.alert_handler_entropy/latest

Test location /workspace/coverage/default/1.alert_handler_entropy_stress.277708454
Short name T435
Test name
Test status
Simulation time 156270034 ps
CPU time 9.68 seconds
Started Jan 24 01:38:52 PM PST 24
Finished Jan 24 01:39:12 PM PST 24
Peak memory 239860 kb
Host smart-30a0089d-7327-4014-b992-592048e4ba77
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=277708454 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy_stress.277708454
Directory /workspace/1.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/1.alert_handler_esc_alert_accum.1944473123
Short name T72
Test name
Test status
Simulation time 764307050 ps
CPU time 50.4 seconds
Started Jan 24 01:38:47 PM PST 24
Finished Jan 24 01:39:51 PM PST 24
Peak memory 248024 kb
Host smart-6f165370-709e-41d6-b25b-6155f6cc905e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19444
73123 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_alert_accum.1944473123
Directory /workspace/1.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/1.alert_handler_esc_intr_timeout.3262809417
Short name T238
Test name
Test status
Simulation time 2826799864 ps
CPU time 29.54 seconds
Started Jan 24 01:38:51 PM PST 24
Finished Jan 24 01:39:32 PM PST 24
Peak memory 250220 kb
Host smart-92567442-4e91-462a-b719-5ca2f551002a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32628
09417 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_intr_timeout.3262809417
Directory /workspace/1.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_lpg.2701675037
Short name T530
Test name
Test status
Simulation time 20394400897 ps
CPU time 898.32 seconds
Started Jan 24 01:38:47 PM PST 24
Finished Jan 24 01:53:59 PM PST 24
Peak memory 271448 kb
Host smart-9357dc8a-2d1c-40a2-b665-ec745a69be2b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701675037 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg.2701675037
Directory /workspace/1.alert_handler_lpg/latest

Test location /workspace/coverage/default/1.alert_handler_lpg_stub_clk.1513734344
Short name T648
Test name
Test status
Simulation time 41269961323 ps
CPU time 1499.27 seconds
Started Jan 24 01:38:49 PM PST 24
Finished Jan 24 02:04:01 PM PST 24
Peak memory 265600 kb
Host smart-85fc2edb-c3a5-42c5-8452-75073e1855e6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513734344 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg_stub_clk.1513734344
Directory /workspace/1.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/1.alert_handler_ping_timeout.389686522
Short name T299
Test name
Test status
Simulation time 85346160362 ps
CPU time 464.42 seconds
Started Jan 24 01:38:51 PM PST 24
Finished Jan 24 01:46:47 PM PST 24
Peak memory 246616 kb
Host smart-0f9c0e83-2970-48aa-9010-008b726dfebc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389686522 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_ping_timeout.389686522
Directory /workspace/1.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_random_alerts.703226250
Short name T571
Test name
Test status
Simulation time 4323345914 ps
CPU time 60.27 seconds
Started Jan 24 01:38:52 PM PST 24
Finished Jan 24 01:40:03 PM PST 24
Peak memory 248204 kb
Host smart-4ad2b4ad-9a0e-46c3-849e-05e904cb1ad9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70322
6250 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_alerts.703226250
Directory /workspace/1.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/1.alert_handler_random_classes.2116503657
Short name T681
Test name
Test status
Simulation time 3454565531 ps
CPU time 19.91 seconds
Started Jan 24 01:38:50 PM PST 24
Finished Jan 24 01:39:22 PM PST 24
Peak memory 254288 kb
Host smart-5522aff5-fce8-4208-b62d-1dc5b9936342
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21165
03657 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_classes.2116503657
Directory /workspace/1.alert_handler_random_classes/latest

Test location /workspace/coverage/default/1.alert_handler_sec_cm.2611055020
Short name T43
Test name
Test status
Simulation time 1694138494 ps
CPU time 25.37 seconds
Started Jan 24 01:39:00 PM PST 24
Finished Jan 24 01:39:32 PM PST 24
Peak memory 275184 kb
Host smart-0b0d34a2-2d9b-4cfa-9fbd-98e7e0047310
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2611055020 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sec_cm.2611055020
Directory /workspace/1.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/1.alert_handler_sig_int_fail.1247057227
Short name T441
Test name
Test status
Simulation time 976052612 ps
CPU time 30.46 seconds
Started Jan 24 01:38:46 PM PST 24
Finished Jan 24 01:39:31 PM PST 24
Peak memory 248052 kb
Host smart-d04f1bc7-d7e6-477a-b9a0-7f1926c05231
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12470
57227 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sig_int_fail.1247057227
Directory /workspace/1.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/1.alert_handler_smoke.3648673808
Short name T48
Test name
Test status
Simulation time 317118072 ps
CPU time 14.83 seconds
Started Jan 24 01:38:45 PM PST 24
Finished Jan 24 01:39:15 PM PST 24
Peak memory 251120 kb
Host smart-88a1ec35-f3dd-43fc-91cf-166fecdec7d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36486
73808 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_smoke.3648673808
Directory /workspace/1.alert_handler_smoke/latest

Test location /workspace/coverage/default/10.alert_handler_alert_accum_saturation.3223092207
Short name T233
Test name
Test status
Simulation time 21194008 ps
CPU time 2.34 seconds
Started Jan 24 02:03:15 PM PST 24
Finished Jan 24 02:03:33 PM PST 24
Peak memory 248288 kb
Host smart-ab9b9b9e-60de-4d14-bccd-0384ffc0a524
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3223092207 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_alert_accum_saturation.3223092207
Directory /workspace/10.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/10.alert_handler_entropy.2052936753
Short name T600
Test name
Test status
Simulation time 289015415772 ps
CPU time 1481.68 seconds
Started Jan 24 02:05:30 PM PST 24
Finished Jan 24 02:31:05 PM PST 24
Peak memory 264600 kb
Host smart-b5cf5bf0-6440-4c31-a568-5f4c7e2eb441
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052936753 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy.2052936753
Directory /workspace/10.alert_handler_entropy/latest

Test location /workspace/coverage/default/10.alert_handler_entropy_stress.3087446482
Short name T362
Test name
Test status
Simulation time 253401088 ps
CPU time 13.18 seconds
Started Jan 24 01:40:09 PM PST 24
Finished Jan 24 01:41:17 PM PST 24
Peak memory 239808 kb
Host smart-f576c55c-5231-42f9-8c98-0d875b4abe64
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3087446482 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy_stress.3087446482
Directory /workspace/10.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/10.alert_handler_esc_alert_accum.2508381223
Short name T392
Test name
Test status
Simulation time 2557070141 ps
CPU time 75.6 seconds
Started Jan 24 01:40:15 PM PST 24
Finished Jan 24 01:42:28 PM PST 24
Peak memory 248148 kb
Host smart-0c6c3ebb-71c8-4b40-b078-94702216e2e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25083
81223 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_alert_accum.2508381223
Directory /workspace/10.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/10.alert_handler_esc_intr_timeout.4128890715
Short name T241
Test name
Test status
Simulation time 809712274 ps
CPU time 55.07 seconds
Started Jan 24 01:40:11 PM PST 24
Finished Jan 24 01:42:02 PM PST 24
Peak memory 254156 kb
Host smart-d99382a0-e282-4aa8-ab84-3d9dd038907c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41288
90715 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_intr_timeout.4128890715
Directory /workspace/10.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_lpg.460737929
Short name T343
Test name
Test status
Simulation time 28726522174 ps
CPU time 2023.57 seconds
Started Jan 24 01:40:11 PM PST 24
Finished Jan 24 02:14:51 PM PST 24
Peak memory 270960 kb
Host smart-157723ad-b89e-46d1-8e7d-10ddd49f0d83
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460737929 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg.460737929
Directory /workspace/10.alert_handler_lpg/latest

Test location /workspace/coverage/default/10.alert_handler_lpg_stub_clk.59348582
Short name T646
Test name
Test status
Simulation time 26006000386 ps
CPU time 881.52 seconds
Started Jan 24 01:40:14 PM PST 24
Finished Jan 24 01:55:52 PM PST 24
Peak memory 266948 kb
Host smart-c5ee1422-fd3a-442c-b930-fbbae2d4e244
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59348582 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg_stub_clk.59348582
Directory /workspace/10.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/10.alert_handler_ping_timeout.2046181053
Short name T270
Test name
Test status
Simulation time 36576999929 ps
CPU time 367.25 seconds
Started Jan 24 01:40:15 PM PST 24
Finished Jan 24 01:47:19 PM PST 24
Peak memory 245604 kb
Host smart-716f40f2-1c5a-40fe-8605-b3d4ecd24c28
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046181053 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_ping_timeout.2046181053
Directory /workspace/10.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_random_alerts.1250330722
Short name T397
Test name
Test status
Simulation time 137732278 ps
CPU time 5.53 seconds
Started Jan 24 01:40:12 PM PST 24
Finished Jan 24 01:41:14 PM PST 24
Peak memory 239876 kb
Host smart-7fb4e270-27d1-494a-bc69-a4c723a85fb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12503
30722 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_alerts.1250330722
Directory /workspace/10.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/10.alert_handler_random_classes.1563134362
Short name T503
Test name
Test status
Simulation time 1623500505 ps
CPU time 40.71 seconds
Started Jan 24 02:24:25 PM PST 24
Finished Jan 24 02:25:15 PM PST 24
Peak memory 250276 kb
Host smart-e7db5187-cb53-47c2-89f7-b0e7f3edb4c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15631
34362 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_classes.1563134362
Directory /workspace/10.alert_handler_random_classes/latest

Test location /workspace/coverage/default/10.alert_handler_sig_int_fail.1244134227
Short name T514
Test name
Test status
Simulation time 418333667 ps
CPU time 11.49 seconds
Started Jan 24 01:40:21 PM PST 24
Finished Jan 24 01:41:30 PM PST 24
Peak memory 250352 kb
Host smart-81bead49-4b96-4b72-a080-95449c95f296
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12441
34227 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_sig_int_fail.1244134227
Directory /workspace/10.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/10.alert_handler_smoke.4189854932
Short name T56
Test name
Test status
Simulation time 86700611 ps
CPU time 5.41 seconds
Started Jan 24 01:40:15 PM PST 24
Finished Jan 24 01:41:18 PM PST 24
Peak memory 239848 kb
Host smart-d79f6f17-7146-4ce6-95c7-19760a5e8ae9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41898
54932 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_smoke.4189854932
Directory /workspace/10.alert_handler_smoke/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all_with_rand_reset.3969792530
Short name T411
Test name
Test status
Simulation time 148377262976 ps
CPU time 4806.92 seconds
Started Jan 24 01:40:17 PM PST 24
Finished Jan 24 03:01:22 PM PST 24
Peak memory 304828 kb
Host smart-65663e25-799a-4a3d-bac7-74f45b061e6c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969792530 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 10.alert_handler_stress_all_with_rand_reset.3969792530
Directory /workspace/10.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.alert_handler_alert_accum_saturation.1245680320
Short name T229
Test name
Test status
Simulation time 119885089 ps
CPU time 3.47 seconds
Started Jan 24 01:40:19 PM PST 24
Finished Jan 24 01:41:18 PM PST 24
Peak memory 249316 kb
Host smart-7a628497-76d8-4d70-ae35-ad60299515b0
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1245680320 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_alert_accum_saturation.1245680320
Directory /workspace/11.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/11.alert_handler_entropy.3185281827
Short name T107
Test name
Test status
Simulation time 73212826212 ps
CPU time 2336.95 seconds
Started Jan 24 01:40:31 PM PST 24
Finished Jan 24 02:20:22 PM PST 24
Peak memory 288168 kb
Host smart-442435df-8cad-43d2-ab75-5c890c001c61
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185281827 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy.3185281827
Directory /workspace/11.alert_handler_entropy/latest

Test location /workspace/coverage/default/11.alert_handler_entropy_stress.3330089139
Short name T720
Test name
Test status
Simulation time 522703372 ps
CPU time 7.74 seconds
Started Jan 24 01:40:17 PM PST 24
Finished Jan 24 01:41:22 PM PST 24
Peak memory 239780 kb
Host smart-854e6fdc-c593-40aa-9595-c68133413eaa
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3330089139 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy_stress.3330089139
Directory /workspace/11.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/11.alert_handler_esc_alert_accum.2010106923
Short name T252
Test name
Test status
Simulation time 5130606587 ps
CPU time 262.86 seconds
Started Jan 24 01:45:06 PM PST 24
Finished Jan 24 01:49:41 PM PST 24
Peak memory 250236 kb
Host smart-c25736a5-d2f6-4acb-aa39-a6fcbcad48e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20101
06923 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_alert_accum.2010106923
Directory /workspace/11.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/11.alert_handler_lpg_stub_clk.61230565
Short name T569
Test name
Test status
Simulation time 101413603047 ps
CPU time 1589.33 seconds
Started Jan 24 01:40:31 PM PST 24
Finished Jan 24 02:07:54 PM PST 24
Peak memory 271976 kb
Host smart-b41de70c-9719-4e93-bda5-cd1d64e53adf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61230565 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg_stub_clk.61230565
Directory /workspace/11.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/11.alert_handler_random_alerts.4021335447
Short name T425
Test name
Test status
Simulation time 856750567 ps
CPU time 48.7 seconds
Started Jan 24 02:15:58 PM PST 24
Finished Jan 24 02:17:25 PM PST 24
Peak memory 248060 kb
Host smart-f619732d-8fce-4012-b187-2b612ae16c1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40213
35447 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_alerts.4021335447
Directory /workspace/11.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/11.alert_handler_random_classes.812960044
Short name T521
Test name
Test status
Simulation time 274743449 ps
CPU time 22.86 seconds
Started Jan 24 02:37:22 PM PST 24
Finished Jan 24 02:38:15 PM PST 24
Peak memory 251116 kb
Host smart-09b7fee3-d65f-4746-9842-8738c4f3dff9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81296
0044 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_classes.812960044
Directory /workspace/11.alert_handler_random_classes/latest

Test location /workspace/coverage/default/11.alert_handler_sig_int_fail.792493088
Short name T593
Test name
Test status
Simulation time 626569944 ps
CPU time 20.63 seconds
Started Jan 24 02:29:39 PM PST 24
Finished Jan 24 02:30:14 PM PST 24
Peak memory 250400 kb
Host smart-7c10dd40-fe81-4003-bf19-3b1340205d9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79249
3088 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_sig_int_fail.792493088
Directory /workspace/11.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/11.alert_handler_smoke.2365364652
Short name T382
Test name
Test status
Simulation time 1425765340 ps
CPU time 41.17 seconds
Started Jan 24 01:40:23 PM PST 24
Finished Jan 24 01:42:00 PM PST 24
Peak memory 248028 kb
Host smart-70cbf29e-5cd4-408f-a823-50e2736f55de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23653
64652 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_smoke.2365364652
Directory /workspace/11.alert_handler_smoke/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all.2597175158
Short name T87
Test name
Test status
Simulation time 41309687916 ps
CPU time 183.93 seconds
Started Jan 24 01:40:19 PM PST 24
Finished Jan 24 01:44:19 PM PST 24
Peak memory 256376 kb
Host smart-4bf4dae4-ced1-4839-a3dc-da58a29afcae
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597175158 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_ha
ndler_stress_all.2597175158
Directory /workspace/11.alert_handler_stress_all/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all_with_rand_reset.2885208036
Short name T477
Test name
Test status
Simulation time 16725190998 ps
CPU time 1206.6 seconds
Started Jan 24 01:40:18 PM PST 24
Finished Jan 24 02:01:22 PM PST 24
Peak memory 272832 kb
Host smart-c2dd529f-86b5-4d50-81da-deace20bce75
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885208036 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 11.alert_handler_stress_all_with_rand_reset.2885208036
Directory /workspace/11.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.alert_handler_entropy.4004508408
Short name T264
Test name
Test status
Simulation time 133731286029 ps
CPU time 2275.36 seconds
Started Jan 24 02:09:58 PM PST 24
Finished Jan 24 02:48:05 PM PST 24
Peak memory 288472 kb
Host smart-c35ae87c-39f5-4ecb-923e-02231e647a40
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004508408 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy.4004508408
Directory /workspace/12.alert_handler_entropy/latest

Test location /workspace/coverage/default/12.alert_handler_entropy_stress.1445004440
Short name T484
Test name
Test status
Simulation time 277677835 ps
CPU time 12.98 seconds
Started Jan 24 01:40:33 PM PST 24
Finished Jan 24 01:41:40 PM PST 24
Peak memory 239852 kb
Host smart-447222ad-fe27-4c8d-a2d0-88a920aaa9c3
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1445004440 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy_stress.1445004440
Directory /workspace/12.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/12.alert_handler_esc_alert_accum.545985685
Short name T488
Test name
Test status
Simulation time 1578955467 ps
CPU time 108.24 seconds
Started Jan 24 01:40:36 PM PST 24
Finished Jan 24 01:43:16 PM PST 24
Peak memory 247152 kb
Host smart-202a69db-92bf-4280-9056-0d6bebb0a24b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54598
5685 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_alert_accum.545985685
Directory /workspace/12.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/12.alert_handler_esc_intr_timeout.248997985
Short name T652
Test name
Test status
Simulation time 1034984704 ps
CPU time 56.55 seconds
Started Jan 24 01:40:31 PM PST 24
Finished Jan 24 01:42:21 PM PST 24
Peak memory 254404 kb
Host smart-a564fda6-5f26-4d3f-8333-932e281da18f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24899
7985 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_intr_timeout.248997985
Directory /workspace/12.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_lpg_stub_clk.160708442
Short name T542
Test name
Test status
Simulation time 14916586734 ps
CPU time 1303.28 seconds
Started Jan 24 01:40:35 PM PST 24
Finished Jan 24 02:03:10 PM PST 24
Peak memory 288216 kb
Host smart-61e9a102-34c2-4437-9f0b-dbb026995cd8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160708442 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg_stub_clk.160708442
Directory /workspace/12.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/12.alert_handler_ping_timeout.877495651
Short name T628
Test name
Test status
Simulation time 52646626965 ps
CPU time 540.55 seconds
Started Jan 24 01:40:35 PM PST 24
Finished Jan 24 01:50:28 PM PST 24
Peak memory 250180 kb
Host smart-e7792569-ab6a-459a-ba37-7e0503db6a52
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877495651 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_ping_timeout.877495651
Directory /workspace/12.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_random_alerts.2119101987
Short name T625
Test name
Test status
Simulation time 395222550 ps
CPU time 13.49 seconds
Started Jan 24 02:38:27 PM PST 24
Finished Jan 24 02:38:53 PM PST 24
Peak memory 248048 kb
Host smart-4abb0aae-3bbd-40f5-9f8f-0009e070ab7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21191
01987 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_alerts.2119101987
Directory /workspace/12.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/12.alert_handler_random_classes.681092756
Short name T468
Test name
Test status
Simulation time 2123462564 ps
CPU time 37.74 seconds
Started Jan 24 01:40:19 PM PST 24
Finished Jan 24 01:41:53 PM PST 24
Peak memory 247968 kb
Host smart-219c5331-75fe-4516-822b-8b2c4d099b3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68109
2756 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_classes.681092756
Directory /workspace/12.alert_handler_random_classes/latest

Test location /workspace/coverage/default/12.alert_handler_sig_int_fail.3085172697
Short name T450
Test name
Test status
Simulation time 421285774 ps
CPU time 4 seconds
Started Jan 24 01:40:38 PM PST 24
Finished Jan 24 01:41:32 PM PST 24
Peak memory 237724 kb
Host smart-532a4e9e-172b-49be-9b0f-18c017bde8ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30851
72697 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_sig_int_fail.3085172697
Directory /workspace/12.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/12.alert_handler_smoke.2418722101
Short name T676
Test name
Test status
Simulation time 134306277 ps
CPU time 2.83 seconds
Started Jan 24 01:40:31 PM PST 24
Finished Jan 24 01:41:28 PM PST 24
Peak memory 239832 kb
Host smart-a2123ba1-acee-4f88-b048-e0291232cac0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24187
22101 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_smoke.2418722101
Directory /workspace/12.alert_handler_smoke/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all.18332176
Short name T471
Test name
Test status
Simulation time 375147725182 ps
CPU time 2258.33 seconds
Started Jan 24 01:40:38 PM PST 24
Finished Jan 24 02:19:06 PM PST 24
Peak memory 288400 kb
Host smart-60d3a0e7-f318-4035-bc16-d366080171a1
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18332176 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_hand
ler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_hand
ler_stress_all.18332176
Directory /workspace/12.alert_handler_stress_all/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all_with_rand_reset.887891990
Short name T97
Test name
Test status
Simulation time 31019100253 ps
CPU time 493.54 seconds
Started Jan 24 01:40:36 PM PST 24
Finished Jan 24 01:49:41 PM PST 24
Peak memory 272828 kb
Host smart-32b95be8-2400-44d7-a1ba-11c8b2ec376f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887891990 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 12.alert_handler_stress_all_with_rand_reset.887891990
Directory /workspace/12.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.alert_handler_alert_accum_saturation.558764469
Short name T222
Test name
Test status
Simulation time 109042750 ps
CPU time 2.79 seconds
Started Jan 24 01:40:53 PM PST 24
Finished Jan 24 01:41:36 PM PST 24
Peak memory 248296 kb
Host smart-c3590ad7-9284-424d-802e-70c754bd83fa
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=558764469 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_alert_accum_saturation.558764469
Directory /workspace/13.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/13.alert_handler_entropy.2102905800
Short name T215
Test name
Test status
Simulation time 134954330868 ps
CPU time 2253.71 seconds
Started Jan 24 01:40:39 PM PST 24
Finished Jan 24 02:19:02 PM PST 24
Peak memory 272716 kb
Host smart-8bd51840-1ef9-4931-84bc-9c3ef60c842f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102905800 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy.2102905800
Directory /workspace/13.alert_handler_entropy/latest

Test location /workspace/coverage/default/13.alert_handler_entropy_stress.1248385650
Short name T651
Test name
Test status
Simulation time 1344198226 ps
CPU time 17.16 seconds
Started Jan 24 01:40:43 PM PST 24
Finished Jan 24 01:41:47 PM PST 24
Peak memory 239820 kb
Host smart-89ff5639-6dc1-48bb-8a32-e6d5a42b1b02
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1248385650 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy_stress.1248385650
Directory /workspace/13.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/13.alert_handler_esc_alert_accum.2105418478
Short name T76
Test name
Test status
Simulation time 918452703 ps
CPU time 14.91 seconds
Started Jan 24 01:40:36 PM PST 24
Finished Jan 24 01:41:42 PM PST 24
Peak memory 250344 kb
Host smart-6394bc31-a62f-4f03-866e-edd9763fb1a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21054
18478 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_alert_accum.2105418478
Directory /workspace/13.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/13.alert_handler_esc_intr_timeout.2506574827
Short name T528
Test name
Test status
Simulation time 1401767705 ps
CPU time 27.77 seconds
Started Jan 24 01:40:33 PM PST 24
Finished Jan 24 01:41:54 PM PST 24
Peak memory 254448 kb
Host smart-5ad1dc91-4ac3-44dc-8ee0-6fcaf52e046d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25065
74827 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_intr_timeout.2506574827
Directory /workspace/13.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_lpg.2392197219
Short name T342
Test name
Test status
Simulation time 134017430658 ps
CPU time 2003.84 seconds
Started Jan 24 01:40:53 PM PST 24
Finished Jan 24 02:14:58 PM PST 24
Peak memory 282264 kb
Host smart-a58fb582-fa64-489e-8fb6-bb6396ffff43
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392197219 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg.2392197219
Directory /workspace/13.alert_handler_lpg/latest

Test location /workspace/coverage/default/13.alert_handler_lpg_stub_clk.3963202538
Short name T674
Test name
Test status
Simulation time 127876481646 ps
CPU time 1400.4 seconds
Started Jan 24 01:40:53 PM PST 24
Finished Jan 24 02:04:54 PM PST 24
Peak memory 271732 kb
Host smart-36b8c5c8-c463-4e48-b251-cfcc8bcc08bd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963202538 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg_stub_clk.3963202538
Directory /workspace/13.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/13.alert_handler_random_alerts.2186754170
Short name T524
Test name
Test status
Simulation time 7175221060 ps
CPU time 60.54 seconds
Started Jan 24 01:40:35 PM PST 24
Finished Jan 24 01:42:28 PM PST 24
Peak memory 256312 kb
Host smart-fda57425-8d93-414b-a9a2-ddc5058fcd92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21867
54170 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_alerts.2186754170
Directory /workspace/13.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/13.alert_handler_random_classes.421676345
Short name T430
Test name
Test status
Simulation time 161868200 ps
CPU time 6.85 seconds
Started Jan 24 01:40:36 PM PST 24
Finished Jan 24 01:41:34 PM PST 24
Peak memory 249424 kb
Host smart-fcf22904-916c-4a35-ad74-56065aa1c5cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42167
6345 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_classes.421676345
Directory /workspace/13.alert_handler_random_classes/latest

Test location /workspace/coverage/default/13.alert_handler_sig_int_fail.2920867138
Short name T439
Test name
Test status
Simulation time 220759637 ps
CPU time 25.44 seconds
Started Jan 24 01:40:38 PM PST 24
Finished Jan 24 01:41:53 PM PST 24
Peak memory 248012 kb
Host smart-0d723344-4d12-4a5d-bd2e-15f89ca24fe1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29208
67138 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_sig_int_fail.2920867138
Directory /workspace/13.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/13.alert_handler_smoke.2666895271
Short name T46
Test name
Test status
Simulation time 99920396 ps
CPU time 4.92 seconds
Started Jan 24 01:40:34 PM PST 24
Finished Jan 24 01:41:32 PM PST 24
Peak memory 239852 kb
Host smart-62b3245b-3a78-44e6-b0dc-69f84638a8b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26668
95271 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_smoke.2666895271
Directory /workspace/13.alert_handler_smoke/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all_with_rand_reset.3672420593
Short name T685
Test name
Test status
Simulation time 62374830870 ps
CPU time 607.85 seconds
Started Jan 24 04:29:17 PM PST 24
Finished Jan 24 04:39:26 PM PST 24
Peak memory 272928 kb
Host smart-2fa1a736-8ba9-4330-9e35-78f90f4b26f9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672420593 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.alert_handler_stress_all_with_rand_reset.3672420593
Directory /workspace/13.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.alert_handler_alert_accum_saturation.3757061004
Short name T230
Test name
Test status
Simulation time 45710190 ps
CPU time 3.5 seconds
Started Jan 24 01:40:54 PM PST 24
Finished Jan 24 01:41:38 PM PST 24
Peak memory 248220 kb
Host smart-436f5998-fdc9-46f3-909a-6eb0b1eb62fc
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3757061004 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_alert_accum_saturation.3757061004
Directory /workspace/14.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/14.alert_handler_entropy.421602168
Short name T122
Test name
Test status
Simulation time 967511414375 ps
CPU time 3174.84 seconds
Started Jan 24 06:07:00 PM PST 24
Finished Jan 24 06:59:56 PM PST 24
Peak memory 281012 kb
Host smart-b63afc2a-3851-42e9-bc90-fbcd0ca99333
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421602168 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy.421602168
Directory /workspace/14.alert_handler_entropy/latest

Test location /workspace/coverage/default/14.alert_handler_esc_alert_accum.1026539498
Short name T699
Test name
Test status
Simulation time 2559715079 ps
CPU time 145.29 seconds
Started Jan 24 01:59:23 PM PST 24
Finished Jan 24 02:01:50 PM PST 24
Peak memory 249212 kb
Host smart-abf339c7-6229-4416-bf28-556afbbcd923
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10265
39498 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_alert_accum.1026539498
Directory /workspace/14.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/14.alert_handler_esc_intr_timeout.678816717
Short name T365
Test name
Test status
Simulation time 310689009 ps
CPU time 34.11 seconds
Started Jan 24 04:55:37 PM PST 24
Finished Jan 24 04:56:20 PM PST 24
Peak memory 248124 kb
Host smart-cb881a14-58c3-4059-bfc3-8739525b1eb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67881
6717 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_intr_timeout.678816717
Directory /workspace/14.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_lpg.2721360936
Short name T340
Test name
Test status
Simulation time 209238609719 ps
CPU time 3122.65 seconds
Started Jan 24 01:40:58 PM PST 24
Finished Jan 24 02:33:38 PM PST 24
Peak memory 280940 kb
Host smart-b23f99cf-88cc-4ed1-a795-01b281e0a4e7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721360936 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg.2721360936
Directory /workspace/14.alert_handler_lpg/latest

Test location /workspace/coverage/default/14.alert_handler_random_alerts.2888194858
Short name T416
Test name
Test status
Simulation time 232439922 ps
CPU time 5.3 seconds
Started Jan 24 01:40:56 PM PST 24
Finished Jan 24 01:41:40 PM PST 24
Peak memory 239804 kb
Host smart-7d43b873-b732-4c2c-915b-fc17771bc290
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28881
94858 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_alerts.2888194858
Directory /workspace/14.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/14.alert_handler_random_classes.2802717243
Short name T460
Test name
Test status
Simulation time 29994251 ps
CPU time 4.48 seconds
Started Jan 24 02:12:42 PM PST 24
Finished Jan 24 02:13:08 PM PST 24
Peak memory 239844 kb
Host smart-659ec213-9157-4715-a4a6-e2744f3c7df8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28027
17243 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_classes.2802717243
Directory /workspace/14.alert_handler_random_classes/latest

Test location /workspace/coverage/default/14.alert_handler_sig_int_fail.215209892
Short name T277
Test name
Test status
Simulation time 803714283 ps
CPU time 50.17 seconds
Started Jan 24 02:19:28 PM PST 24
Finished Jan 24 02:20:25 PM PST 24
Peak memory 248052 kb
Host smart-851d34c7-de6f-4ce9-8c40-ecdb16db3224
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21520
9892 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_sig_int_fail.215209892
Directory /workspace/14.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/14.alert_handler_smoke.3913348703
Short name T359
Test name
Test status
Simulation time 2169176630 ps
CPU time 37.74 seconds
Started Jan 24 02:06:08 PM PST 24
Finished Jan 24 02:07:35 PM PST 24
Peak memory 250144 kb
Host smart-3750f2fc-f64b-4cfb-984b-cc20677be39f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39133
48703 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_smoke.3913348703
Directory /workspace/14.alert_handler_smoke/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all.3905210124
Short name T98
Test name
Test status
Simulation time 16154214542 ps
CPU time 1063.67 seconds
Started Jan 24 01:40:58 PM PST 24
Finished Jan 24 01:59:19 PM PST 24
Peak memory 272764 kb
Host smart-1b7a6ca0-69cd-4c3c-b535-bbcd5d6d83a5
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905210124 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_ha
ndler_stress_all.3905210124
Directory /workspace/14.alert_handler_stress_all/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all_with_rand_reset.952672596
Short name T204
Test name
Test status
Simulation time 120436742516 ps
CPU time 3314.6 seconds
Started Jan 24 01:40:59 PM PST 24
Finished Jan 24 02:36:50 PM PST 24
Peak memory 317900 kb
Host smart-68597bc1-f725-4c0d-993a-fa298f345659
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952672596 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 14.alert_handler_stress_all_with_rand_reset.952672596
Directory /workspace/14.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.alert_handler_alert_accum_saturation.380195778
Short name T225
Test name
Test status
Simulation time 16025707 ps
CPU time 2.65 seconds
Started Jan 24 01:41:04 PM PST 24
Finished Jan 24 01:41:39 PM PST 24
Peak memory 248296 kb
Host smart-baa7775c-b1f3-4bf2-aaa6-094d91372fd0
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=380195778 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_alert_accum_saturation.380195778
Directory /workspace/15.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/15.alert_handler_entropy.96305450
Short name T248
Test name
Test status
Simulation time 130179293522 ps
CPU time 1290.75 seconds
Started Jan 24 01:40:58 PM PST 24
Finished Jan 24 02:03:06 PM PST 24
Peak memory 288124 kb
Host smart-5c66ade1-cbd3-4f42-81a9-a40bd41304c0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96305450 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy.96305450
Directory /workspace/15.alert_handler_entropy/latest

Test location /workspace/coverage/default/15.alert_handler_entropy_stress.2694103161
Short name T381
Test name
Test status
Simulation time 6923753974 ps
CPU time 57.76 seconds
Started Jan 24 01:53:16 PM PST 24
Finished Jan 24 01:54:27 PM PST 24
Peak memory 239968 kb
Host smart-ef0e1dbc-94d3-4145-853b-ba8e6b02ab26
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2694103161 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy_stress.2694103161
Directory /workspace/15.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/15.alert_handler_esc_alert_accum.3461912244
Short name T438
Test name
Test status
Simulation time 3809924873 ps
CPU time 212.7 seconds
Started Jan 24 02:23:57 PM PST 24
Finished Jan 24 02:27:46 PM PST 24
Peak memory 255752 kb
Host smart-462d8aff-c44a-4226-9826-31abf6849d86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34619
12244 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_alert_accum.3461912244
Directory /workspace/15.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/15.alert_handler_esc_intr_timeout.2166219793
Short name T90
Test name
Test status
Simulation time 347923943 ps
CPU time 7.51 seconds
Started Jan 24 01:41:01 PM PST 24
Finished Jan 24 01:41:43 PM PST 24
Peak memory 250024 kb
Host smart-251d5e3d-0024-4813-8033-d28f3c6cb3ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21662
19793 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_intr_timeout.2166219793
Directory /workspace/15.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_lpg_stub_clk.4217501311
Short name T531
Test name
Test status
Simulation time 34374127766 ps
CPU time 981.28 seconds
Started Jan 24 01:41:04 PM PST 24
Finished Jan 24 01:57:58 PM PST 24
Peak memory 266600 kb
Host smart-013f7514-49ff-46f9-849b-3049b5df80a5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217501311 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg_stub_clk.4217501311
Directory /workspace/15.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/15.alert_handler_ping_timeout.802444691
Short name T313
Test name
Test status
Simulation time 4218653573 ps
CPU time 178.12 seconds
Started Jan 24 01:40:58 PM PST 24
Finished Jan 24 01:44:33 PM PST 24
Peak memory 248172 kb
Host smart-3c9dbe40-80e1-4b34-a737-1110f18d48e1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=802444691 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_ping_timeout.802444691
Directory /workspace/15.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_random_alerts.1095202232
Short name T595
Test name
Test status
Simulation time 4089036587 ps
CPU time 62.72 seconds
Started Jan 24 02:43:31 PM PST 24
Finished Jan 24 02:45:04 PM PST 24
Peak memory 248256 kb
Host smart-5cff8fe4-9bb0-49c9-a62b-8345eaea9ab5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10952
02232 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_alerts.1095202232
Directory /workspace/15.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/15.alert_handler_sig_int_fail.3270947376
Short name T240
Test name
Test status
Simulation time 3672483044 ps
CPU time 56.47 seconds
Started Jan 24 01:40:54 PM PST 24
Finished Jan 24 01:42:31 PM PST 24
Peak memory 248092 kb
Host smart-cbe8fd6b-6e6e-4d96-bdcb-2a4ce3f432c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32709
47376 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_sig_int_fail.3270947376
Directory /workspace/15.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/15.alert_handler_smoke.614728614
Short name T442
Test name
Test status
Simulation time 859258657 ps
CPU time 51.76 seconds
Started Jan 24 01:40:54 PM PST 24
Finished Jan 24 01:42:25 PM PST 24
Peak memory 250244 kb
Host smart-f5147781-c5a7-4b2d-94ad-cbe2b5691abd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61472
8614 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_smoke.614728614
Directory /workspace/15.alert_handler_smoke/latest

Test location /workspace/coverage/default/16.alert_handler_entropy.1679994406
Short name T621
Test name
Test status
Simulation time 11860302707 ps
CPU time 933.45 seconds
Started Jan 24 01:41:23 PM PST 24
Finished Jan 24 01:57:15 PM PST 24
Peak memory 268784 kb
Host smart-40e74c87-ec80-4d38-a60d-1beee1c08305
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679994406 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy.1679994406
Directory /workspace/16.alert_handler_entropy/latest

Test location /workspace/coverage/default/16.alert_handler_entropy_stress.3584270451
Short name T214
Test name
Test status
Simulation time 964477959 ps
CPU time 43.29 seconds
Started Jan 24 01:41:18 PM PST 24
Finished Jan 24 01:42:23 PM PST 24
Peak memory 239868 kb
Host smart-d2623d52-9b19-4c76-aeb9-77fbafa51372
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3584270451 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy_stress.3584270451
Directory /workspace/16.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/16.alert_handler_esc_alert_accum.1426813447
Short name T501
Test name
Test status
Simulation time 22776556697 ps
CPU time 342.36 seconds
Started Jan 24 01:41:10 PM PST 24
Finished Jan 24 01:47:20 PM PST 24
Peak memory 250180 kb
Host smart-bf0084d1-6887-4622-80c4-9ff0824918c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14268
13447 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_alert_accum.1426813447
Directory /workspace/16.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/16.alert_handler_esc_intr_timeout.1588171451
Short name T520
Test name
Test status
Simulation time 1519435807 ps
CPU time 22.46 seconds
Started Jan 24 01:41:12 PM PST 24
Finished Jan 24 01:42:00 PM PST 24
Peak memory 248016 kb
Host smart-9e159772-6004-481f-a833-2b8df161e72f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15881
71451 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_intr_timeout.1588171451
Directory /workspace/16.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_lpg.3546924704
Short name T73
Test name
Test status
Simulation time 12611169408 ps
CPU time 735.27 seconds
Started Jan 24 01:41:24 PM PST 24
Finished Jan 24 01:53:57 PM PST 24
Peak memory 271920 kb
Host smart-72c9b635-c2a6-4eb3-94ca-52d8020fc24c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546924704 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg.3546924704
Directory /workspace/16.alert_handler_lpg/latest

Test location /workspace/coverage/default/16.alert_handler_lpg_stub_clk.1250149318
Short name T236
Test name
Test status
Simulation time 225124962237 ps
CPU time 1748.14 seconds
Started Jan 24 01:41:23 PM PST 24
Finished Jan 24 02:10:50 PM PST 24
Peak memory 271884 kb
Host smart-8c34925d-121c-46be-8acc-4846e387e6ca
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250149318 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg_stub_clk.1250149318
Directory /workspace/16.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/16.alert_handler_ping_timeout.3251499271
Short name T602
Test name
Test status
Simulation time 7092185688 ps
CPU time 301.34 seconds
Started Jan 24 01:41:24 PM PST 24
Finished Jan 24 01:46:43 PM PST 24
Peak memory 245652 kb
Host smart-bdb55fde-0e94-440d-b97d-bb1461f7494e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251499271 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_ping_timeout.3251499271
Directory /workspace/16.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_random_alerts.106515943
Short name T690
Test name
Test status
Simulation time 1543443024 ps
CPU time 25.95 seconds
Started Jan 24 01:41:05 PM PST 24
Finished Jan 24 01:42:02 PM PST 24
Peak memory 250120 kb
Host smart-c6b7944f-022c-45c3-925a-94b2e72446be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10651
5943 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_alerts.106515943
Directory /workspace/16.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/16.alert_handler_random_classes.2758768363
Short name T506
Test name
Test status
Simulation time 2425366176 ps
CPU time 38.71 seconds
Started Jan 24 03:14:39 PM PST 24
Finished Jan 24 03:15:30 PM PST 24
Peak memory 248244 kb
Host smart-c77dc85a-318f-4c58-8d95-0a30ced84f64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27587
68363 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_classes.2758768363
Directory /workspace/16.alert_handler_random_classes/latest

Test location /workspace/coverage/default/16.alert_handler_sig_int_fail.22801103
Short name T282
Test name
Test status
Simulation time 3102569601 ps
CPU time 60.38 seconds
Started Jan 24 01:41:13 PM PST 24
Finished Jan 24 01:42:39 PM PST 24
Peak memory 254712 kb
Host smart-62ff30d9-18e4-46d9-8816-f7eef10dc4da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22801
103 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_sig_int_fail.22801103
Directory /workspace/16.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all.3759435760
Short name T453
Test name
Test status
Simulation time 8792669667 ps
CPU time 462.21 seconds
Started Jan 24 01:41:23 PM PST 24
Finished Jan 24 01:49:24 PM PST 24
Peak memory 256164 kb
Host smart-8f4d8b0c-93a9-4167-a619-55a4e0b1c076
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759435760 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_ha
ndler_stress_all.3759435760
Directory /workspace/16.alert_handler_stress_all/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all_with_rand_reset.4103995014
Short name T203
Test name
Test status
Simulation time 40162752850 ps
CPU time 2375.56 seconds
Started Jan 24 01:41:16 PM PST 24
Finished Jan 24 02:21:16 PM PST 24
Peak memory 281088 kb
Host smart-e554f6ce-18b1-4a3d-8183-a0a771116bb5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103995014 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 16.alert_handler_stress_all_with_rand_reset.4103995014
Directory /workspace/16.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.alert_handler_entropy.467560218
Short name T115
Test name
Test status
Simulation time 53625846734 ps
CPU time 1498.66 seconds
Started Jan 24 01:41:30 PM PST 24
Finished Jan 24 02:06:42 PM PST 24
Peak memory 288708 kb
Host smart-149ef1be-e944-49af-be14-5e9e302df9bb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=467560218 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy.467560218
Directory /workspace/17.alert_handler_entropy/latest

Test location /workspace/coverage/default/17.alert_handler_entropy_stress.1268993132
Short name T412
Test name
Test status
Simulation time 2300140687 ps
CPU time 52.2 seconds
Started Jan 24 01:41:34 PM PST 24
Finished Jan 24 01:42:36 PM PST 24
Peak memory 239912 kb
Host smart-9b1e7303-5a19-4d1e-9a63-9721a4132ff4
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1268993132 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy_stress.1268993132
Directory /workspace/17.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/17.alert_handler_esc_alert_accum.2278193060
Short name T390
Test name
Test status
Simulation time 705303695 ps
CPU time 14.58 seconds
Started Jan 24 01:41:21 PM PST 24
Finished Jan 24 01:41:56 PM PST 24
Peak memory 248028 kb
Host smart-84fa561f-823e-4e60-80e4-693c0e63ce36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22781
93060 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_alert_accum.2278193060
Directory /workspace/17.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/17.alert_handler_esc_intr_timeout.1106474765
Short name T19
Test name
Test status
Simulation time 183568807 ps
CPU time 24.26 seconds
Started Jan 24 01:41:24 PM PST 24
Finished Jan 24 01:42:06 PM PST 24
Peak memory 250268 kb
Host smart-bc033787-c689-4542-8dc4-bd9c892f0c08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11064
74765 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_intr_timeout.1106474765
Directory /workspace/17.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_lpg.2149983413
Short name T338
Test name
Test status
Simulation time 65176567904 ps
CPU time 2149.04 seconds
Started Jan 24 01:41:30 PM PST 24
Finished Jan 24 02:17:32 PM PST 24
Peak memory 280940 kb
Host smart-c9a55a8a-0e13-4dc8-ac91-5e9c7ea21d97
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2149983413 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg.2149983413
Directory /workspace/17.alert_handler_lpg/latest

Test location /workspace/coverage/default/17.alert_handler_lpg_stub_clk.1954539963
Short name T103
Test name
Test status
Simulation time 392357842118 ps
CPU time 1360.3 seconds
Started Jan 24 01:41:29 PM PST 24
Finished Jan 24 02:04:24 PM PST 24
Peak memory 272076 kb
Host smart-9684f8c4-4e1d-498d-9150-4a9ccd38c5ff
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954539963 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg_stub_clk.1954539963
Directory /workspace/17.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/17.alert_handler_ping_timeout.2271037889
Short name T132
Test name
Test status
Simulation time 43057324456 ps
CPU time 132.35 seconds
Started Jan 24 01:41:35 PM PST 24
Finished Jan 24 01:43:56 PM PST 24
Peak memory 246596 kb
Host smart-caec21b3-8285-4219-ab0a-6bfd316ce53c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271037889 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_ping_timeout.2271037889
Directory /workspace/17.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_random_alerts.143760507
Short name T398
Test name
Test status
Simulation time 137443714 ps
CPU time 14.15 seconds
Started Jan 24 01:41:25 PM PST 24
Finished Jan 24 01:41:56 PM PST 24
Peak memory 248036 kb
Host smart-0610647b-ad4b-4483-bba6-509477e92fd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14376
0507 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_alerts.143760507
Directory /workspace/17.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/17.alert_handler_random_classes.3668306928
Short name T479
Test name
Test status
Simulation time 449308504 ps
CPU time 34.44 seconds
Started Jan 24 01:41:24 PM PST 24
Finished Jan 24 01:42:16 PM PST 24
Peak memory 253984 kb
Host smart-f6f42517-8744-40e3-8933-8d69c35fc7b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36683
06928 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_classes.3668306928
Directory /workspace/17.alert_handler_random_classes/latest

Test location /workspace/coverage/default/17.alert_handler_smoke.1510300338
Short name T88
Test name
Test status
Simulation time 164218531 ps
CPU time 16.18 seconds
Started Jan 24 01:41:19 PM PST 24
Finished Jan 24 01:41:57 PM PST 24
Peak memory 248032 kb
Host smart-0aeeaefe-1ca2-4b8f-81de-17fc67602121
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15103
00338 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_smoke.1510300338
Directory /workspace/17.alert_handler_smoke/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all.1976209457
Short name T384
Test name
Test status
Simulation time 12756576856 ps
CPU time 301.42 seconds
Started Jan 24 01:41:34 PM PST 24
Finished Jan 24 01:46:45 PM PST 24
Peak memory 254408 kb
Host smart-cfeebbb5-1e10-4f7a-88a8-3520e1c86fa1
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976209457 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_ha
ndler_stress_all.1976209457
Directory /workspace/17.alert_handler_stress_all/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all_with_rand_reset.3529930333
Short name T457
Test name
Test status
Simulation time 233999854681 ps
CPU time 4900.25 seconds
Started Jan 24 02:01:57 PM PST 24
Finished Jan 24 03:23:56 PM PST 24
Peak memory 289272 kb
Host smart-1ca189bd-8da1-405d-a805-fb39fb7a0725
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529930333 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 17.alert_handler_stress_all_with_rand_reset.3529930333
Directory /workspace/17.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.alert_handler_alert_accum_saturation.2523629329
Short name T220
Test name
Test status
Simulation time 53352094 ps
CPU time 3.85 seconds
Started Jan 24 01:42:01 PM PST 24
Finished Jan 24 01:42:06 PM PST 24
Peak memory 248296 kb
Host smart-90aecaee-78ac-4a42-a3ed-e3feba8b9f89
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2523629329 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_alert_accum_saturation.2523629329
Directory /workspace/18.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/18.alert_handler_entropy.1747046416
Short name T38
Test name
Test status
Simulation time 26699655941 ps
CPU time 1435.91 seconds
Started Jan 24 01:41:49 PM PST 24
Finished Jan 24 02:05:48 PM PST 24
Peak memory 282080 kb
Host smart-8204999b-f107-42d4-aab4-b1978dbf0e17
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747046416 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy.1747046416
Directory /workspace/18.alert_handler_entropy/latest

Test location /workspace/coverage/default/18.alert_handler_entropy_stress.539528372
Short name T556
Test name
Test status
Simulation time 903245165 ps
CPU time 10.31 seconds
Started Jan 24 01:42:02 PM PST 24
Finished Jan 24 01:42:14 PM PST 24
Peak memory 239768 kb
Host smart-2743ef5d-44f9-4a0d-b5fe-8976050ccc43
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=539528372 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy_stress.539528372
Directory /workspace/18.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/18.alert_handler_esc_alert_accum.221622512
Short name T670
Test name
Test status
Simulation time 6085929287 ps
CPU time 181.34 seconds
Started Jan 24 02:05:30 PM PST 24
Finished Jan 24 02:09:24 PM PST 24
Peak memory 249256 kb
Host smart-7f1b35e5-ac42-4487-89e8-4b7cdb0e72e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22162
2512 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_alert_accum.221622512
Directory /workspace/18.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/18.alert_handler_esc_intr_timeout.3619708241
Short name T532
Test name
Test status
Simulation time 369916050 ps
CPU time 26.2 seconds
Started Jan 24 03:33:34 PM PST 24
Finished Jan 24 03:34:05 PM PST 24
Peak memory 254324 kb
Host smart-4f7304cf-ee08-45fd-a13f-b0f56734d4af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36197
08241 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_intr_timeout.3619708241
Directory /workspace/18.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_lpg.3045894693
Short name T327
Test name
Test status
Simulation time 155266227675 ps
CPU time 2266.21 seconds
Started Jan 24 01:41:49 PM PST 24
Finished Jan 24 02:19:38 PM PST 24
Peak memory 271968 kb
Host smart-2c8296dd-21ab-4421-989a-5a64910dd55d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045894693 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg.3045894693
Directory /workspace/18.alert_handler_lpg/latest

Test location /workspace/coverage/default/18.alert_handler_lpg_stub_clk.2387499700
Short name T612
Test name
Test status
Simulation time 97786846742 ps
CPU time 2899.24 seconds
Started Jan 24 01:41:48 PM PST 24
Finished Jan 24 02:30:10 PM PST 24
Peak memory 280864 kb
Host smart-2f5720f3-51dd-4c0c-b721-cc034a5418f7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2387499700 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg_stub_clk.2387499700
Directory /workspace/18.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/18.alert_handler_ping_timeout.3326063051
Short name T36
Test name
Test status
Simulation time 6589961357 ps
CPU time 144.98 seconds
Started Jan 24 01:41:46 PM PST 24
Finished Jan 24 01:44:14 PM PST 24
Peak memory 245660 kb
Host smart-fbb16aaf-8919-4506-a4cd-805cd71a75b9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3326063051 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_ping_timeout.3326063051
Directory /workspace/18.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_random_alerts.2439852588
Short name T459
Test name
Test status
Simulation time 1580598235 ps
CPU time 48.41 seconds
Started Jan 24 01:41:36 PM PST 24
Finished Jan 24 01:42:33 PM PST 24
Peak memory 250052 kb
Host smart-4aac59bc-5739-4549-9ce0-41071113dcdb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24398
52588 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_alerts.2439852588
Directory /workspace/18.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/18.alert_handler_random_classes.1233919778
Short name T354
Test name
Test status
Simulation time 91780047 ps
CPU time 4.24 seconds
Started Jan 24 01:41:37 PM PST 24
Finished Jan 24 01:41:49 PM PST 24
Peak memory 237704 kb
Host smart-4eaf92d0-e81b-409b-978e-9793d0eac397
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12339
19778 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_classes.1233919778
Directory /workspace/18.alert_handler_random_classes/latest

Test location /workspace/coverage/default/18.alert_handler_sig_int_fail.725949628
Short name T383
Test name
Test status
Simulation time 1044347177 ps
CPU time 31.48 seconds
Started Jan 24 01:41:47 PM PST 24
Finished Jan 24 01:42:20 PM PST 24
Peak memory 248040 kb
Host smart-5f9fa5f3-dbeb-4941-8efa-63bcc51bc611
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72594
9628 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_sig_int_fail.725949628
Directory /workspace/18.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/18.alert_handler_smoke.1598750909
Short name T395
Test name
Test status
Simulation time 41500070 ps
CPU time 5.81 seconds
Started Jan 24 01:41:39 PM PST 24
Finished Jan 24 01:41:51 PM PST 24
Peak memory 248028 kb
Host smart-d5a29926-b88e-4d82-833f-017c1712b07d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15987
50909 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_smoke.1598750909
Directory /workspace/18.alert_handler_smoke/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all.342017866
Short name T63
Test name
Test status
Simulation time 100834972727 ps
CPU time 1876.69 seconds
Started Jan 24 01:42:07 PM PST 24
Finished Jan 24 02:13:28 PM PST 24
Peak memory 283132 kb
Host smart-182cb5ea-017b-4b94-b7b2-7a36571961f6
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342017866 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_han
dler_stress_all.342017866
Directory /workspace/18.alert_handler_stress_all/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all_with_rand_reset.762197693
Short name T251
Test name
Test status
Simulation time 35286501936 ps
CPU time 1909.32 seconds
Started Jan 24 01:42:05 PM PST 24
Finished Jan 24 02:13:58 PM PST 24
Peak memory 299500 kb
Host smart-7560e43f-e852-4ac7-b1cf-d5194d6a464d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762197693 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 18.alert_handler_stress_all_with_rand_reset.762197693
Directory /workspace/18.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.alert_handler_alert_accum_saturation.450752591
Short name T18
Test name
Test status
Simulation time 20167396 ps
CPU time 3.03 seconds
Started Jan 24 01:42:11 PM PST 24
Finished Jan 24 01:42:20 PM PST 24
Peak memory 249372 kb
Host smart-cf3b454a-ad2f-442e-bec5-19304a47ec06
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=450752591 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_alert_accum_saturation.450752591
Directory /workspace/19.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/19.alert_handler_entropy.1540148236
Short name T66
Test name
Test status
Simulation time 19630430480 ps
CPU time 1041.58 seconds
Started Jan 24 01:42:09 PM PST 24
Finished Jan 24 01:59:37 PM PST 24
Peak memory 272564 kb
Host smart-fa68434d-55fd-4dcd-9ec2-a84da6f2a34f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540148236 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy.1540148236
Directory /workspace/19.alert_handler_entropy/latest

Test location /workspace/coverage/default/19.alert_handler_entropy_stress.339389377
Short name T487
Test name
Test status
Simulation time 91724508 ps
CPU time 6.78 seconds
Started Jan 24 01:42:11 PM PST 24
Finished Jan 24 01:42:23 PM PST 24
Peak memory 238832 kb
Host smart-cef7eb15-778c-4f79-9fdf-98e7a53ee885
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=339389377 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy_stress.339389377
Directory /workspace/19.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/19.alert_handler_esc_alert_accum.1684261246
Short name T20
Test name
Test status
Simulation time 252683276 ps
CPU time 25.01 seconds
Started Jan 24 01:42:13 PM PST 24
Finished Jan 24 01:42:51 PM PST 24
Peak memory 250120 kb
Host smart-a463d5f6-7923-44b2-8a97-4ddc2bdfec06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16842
61246 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_alert_accum.1684261246
Directory /workspace/19.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/19.alert_handler_esc_intr_timeout.2813916228
Short name T584
Test name
Test status
Simulation time 1030625109 ps
CPU time 30.81 seconds
Started Jan 24 01:42:15 PM PST 24
Finished Jan 24 01:43:01 PM PST 24
Peak memory 250340 kb
Host smart-bfc013cf-a282-42ca-8316-1a057c4510ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28139
16228 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_intr_timeout.2813916228
Directory /workspace/19.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_lpg_stub_clk.2835741198
Short name T716
Test name
Test status
Simulation time 44292923178 ps
CPU time 2579.75 seconds
Started Jan 24 01:42:17 PM PST 24
Finished Jan 24 02:25:44 PM PST 24
Peak memory 288360 kb
Host smart-52cbb735-aab5-40c5-b95d-6d73aaee834d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835741198 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg_stub_clk.2835741198
Directory /workspace/19.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/19.alert_handler_ping_timeout.891360640
Short name T317
Test name
Test status
Simulation time 107711439252 ps
CPU time 457.83 seconds
Started Jan 24 01:42:17 PM PST 24
Finished Jan 24 01:50:22 PM PST 24
Peak memory 246696 kb
Host smart-ef789942-c241-4c8c-9b11-6e1a8cf1d4cb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891360640 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_ping_timeout.891360640
Directory /workspace/19.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_random_alerts.1672535580
Short name T266
Test name
Test status
Simulation time 305387167 ps
CPU time 19.86 seconds
Started Jan 24 01:42:03 PM PST 24
Finished Jan 24 01:42:25 PM PST 24
Peak memory 248044 kb
Host smart-251f8d92-ccd5-4929-8b8e-52156455dd42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16725
35580 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_alerts.1672535580
Directory /workspace/19.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/19.alert_handler_random_classes.285262426
Short name T483
Test name
Test status
Simulation time 559435153 ps
CPU time 33.36 seconds
Started Jan 24 01:42:03 PM PST 24
Finished Jan 24 01:42:37 PM PST 24
Peak memory 248060 kb
Host smart-a86b727e-82a9-4576-8143-329d08c2b018
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28526
2426 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_classes.285262426
Directory /workspace/19.alert_handler_random_classes/latest

Test location /workspace/coverage/default/19.alert_handler_sig_int_fail.283154210
Short name T604
Test name
Test status
Simulation time 165301258 ps
CPU time 9.66 seconds
Started Jan 24 01:42:15 PM PST 24
Finished Jan 24 01:42:41 PM PST 24
Peak memory 252180 kb
Host smart-ccd91256-7024-4d32-a149-6f63c3ac98b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28315
4210 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_sig_int_fail.283154210
Directory /workspace/19.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/19.alert_handler_smoke.4110524230
Short name T509
Test name
Test status
Simulation time 1560645622 ps
CPU time 49.15 seconds
Started Jan 24 01:42:05 PM PST 24
Finished Jan 24 01:42:57 PM PST 24
Peak memory 251360 kb
Host smart-7d7f5f51-8bb3-478a-9a34-7c1272a5daf2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41105
24230 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_smoke.4110524230
Directory /workspace/19.alert_handler_smoke/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all.1670140106
Short name T245
Test name
Test status
Simulation time 3564445237 ps
CPU time 45.52 seconds
Started Jan 24 01:42:11 PM PST 24
Finished Jan 24 01:43:02 PM PST 24
Peak memory 248136 kb
Host smart-c4d71671-6da4-4541-b371-da5280623b7e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670140106 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_ha
ndler_stress_all.1670140106
Directory /workspace/19.alert_handler_stress_all/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all_with_rand_reset.88044530
Short name T75
Test name
Test status
Simulation time 28790199439 ps
CPU time 2973.21 seconds
Started Jan 24 01:42:11 PM PST 24
Finished Jan 24 02:31:50 PM PST 24
Peak memory 321772 kb
Host smart-e51a4f90-9ca0-481d-be65-f34444bda0e5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88044530 -assert nopostproc +UVM_TESTNAME=alert_
handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 19.alert_handler_stress_all_with_rand_reset.88044530
Directory /workspace/19.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.alert_handler_alert_accum_saturation.665624202
Short name T231
Test name
Test status
Simulation time 19913446 ps
CPU time 3.01 seconds
Started Jan 24 01:39:19 PM PST 24
Finished Jan 24 01:39:24 PM PST 24
Peak memory 251616 kb
Host smart-8d196edd-582b-47c5-8068-ebecc6634fed
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=665624202 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_alert_accum_saturation.665624202
Directory /workspace/2.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/2.alert_handler_entropy.1224079558
Short name T668
Test name
Test status
Simulation time 40254055491 ps
CPU time 2686.82 seconds
Started Jan 24 01:39:11 PM PST 24
Finished Jan 24 02:24:01 PM PST 24
Peak memory 289084 kb
Host smart-090bc01e-0626-4ee2-9a9b-c96109347d70
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224079558 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy.1224079558
Directory /workspace/2.alert_handler_entropy/latest

Test location /workspace/coverage/default/2.alert_handler_entropy_stress.3825743208
Short name T237
Test name
Test status
Simulation time 281285804 ps
CPU time 9.04 seconds
Started Jan 24 01:39:15 PM PST 24
Finished Jan 24 01:39:25 PM PST 24
Peak memory 239804 kb
Host smart-1a4541bc-a2a3-4acd-82a9-022e4b77397b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3825743208 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy_stress.3825743208
Directory /workspace/2.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/2.alert_handler_esc_alert_accum.2788792939
Short name T578
Test name
Test status
Simulation time 6459560914 ps
CPU time 74.78 seconds
Started Jan 24 01:38:51 PM PST 24
Finished Jan 24 01:40:17 PM PST 24
Peak memory 253644 kb
Host smart-9f43511d-a763-4935-b61c-d65ba14b760b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27887
92939 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_alert_accum.2788792939
Directory /workspace/2.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/2.alert_handler_esc_intr_timeout.2495140437
Short name T573
Test name
Test status
Simulation time 1769979743 ps
CPU time 53.76 seconds
Started Jan 24 01:38:50 PM PST 24
Finished Jan 24 01:39:56 PM PST 24
Peak memory 254576 kb
Host smart-c82e9c0d-7afe-40c7-8985-4c449564e8f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24951
40437 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_intr_timeout.2495140437
Directory /workspace/2.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_lpg.2546965654
Short name T339
Test name
Test status
Simulation time 56807081570 ps
CPU time 3098.5 seconds
Started Jan 24 01:39:19 PM PST 24
Finished Jan 24 02:31:00 PM PST 24
Peak memory 288064 kb
Host smart-8c186570-6ef6-404a-9388-c4ddf6be08c5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546965654 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg.2546965654
Directory /workspace/2.alert_handler_lpg/latest

Test location /workspace/coverage/default/2.alert_handler_lpg_stub_clk.2194892242
Short name T713
Test name
Test status
Simulation time 31738095192 ps
CPU time 1374.16 seconds
Started Jan 24 01:39:15 PM PST 24
Finished Jan 24 02:02:11 PM PST 24
Peak memory 288796 kb
Host smart-db1f33e9-41c8-428c-a68e-f28347ff2938
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2194892242 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg_stub_clk.2194892242
Directory /workspace/2.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/2.alert_handler_ping_timeout.2372379205
Short name T614
Test name
Test status
Simulation time 14197628124 ps
CPU time 144.56 seconds
Started Jan 24 01:39:19 PM PST 24
Finished Jan 24 01:41:46 PM PST 24
Peak memory 246684 kb
Host smart-6a257b22-2580-44f4-bd44-e22b7c3242d2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372379205 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_ping_timeout.2372379205
Directory /workspace/2.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_random_alerts.747070748
Short name T689
Test name
Test status
Simulation time 833132337 ps
CPU time 20.97 seconds
Started Jan 24 01:38:51 PM PST 24
Finished Jan 24 01:39:23 PM PST 24
Peak memory 248044 kb
Host smart-79899af2-9aff-48ca-8324-0e1d341f56a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74707
0748 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_alerts.747070748
Directory /workspace/2.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/2.alert_handler_random_classes.2732172311
Short name T555
Test name
Test status
Simulation time 1057843736 ps
CPU time 27.77 seconds
Started Jan 24 01:38:52 PM PST 24
Finished Jan 24 01:39:30 PM PST 24
Peak memory 247992 kb
Host smart-1e61d5ef-d5e8-4ac6-8d50-7cff32f86fc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27321
72311 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_classes.2732172311
Directory /workspace/2.alert_handler_random_classes/latest

Test location /workspace/coverage/default/2.alert_handler_sec_cm.984831628
Short name T9
Test name
Test status
Simulation time 837511759 ps
CPU time 12.79 seconds
Started Jan 24 01:39:23 PM PST 24
Finished Jan 24 01:39:49 PM PST 24
Peak memory 271764 kb
Host smart-e472591f-ab9f-458c-bad9-2caef74a6ad7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=984831628 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sec_cm.984831628
Directory /workspace/2.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/2.alert_handler_sig_int_fail.3646558944
Short name T380
Test name
Test status
Simulation time 207511343 ps
CPU time 12.39 seconds
Started Jan 24 01:38:51 PM PST 24
Finished Jan 24 01:39:15 PM PST 24
Peak memory 248020 kb
Host smart-b393e8d3-9fc8-4c7f-9926-8b40e3e584fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36465
58944 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sig_int_fail.3646558944
Directory /workspace/2.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/2.alert_handler_smoke.4084383294
Short name T419
Test name
Test status
Simulation time 125337919 ps
CPU time 11.1 seconds
Started Jan 24 01:38:51 PM PST 24
Finished Jan 24 01:39:13 PM PST 24
Peak memory 248000 kb
Host smart-9ecd5455-3069-4547-8588-f814bed3fc9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40843
83294 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_smoke.4084383294
Directory /workspace/2.alert_handler_smoke/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all.1443902967
Short name T271
Test name
Test status
Simulation time 80702476043 ps
CPU time 2844.03 seconds
Started Jan 24 01:39:22 PM PST 24
Finished Jan 24 02:26:52 PM PST 24
Peak memory 287040 kb
Host smart-1e860c75-22d5-4238-a110-ca869c53b041
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443902967 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_han
dler_stress_all.1443902967
Directory /workspace/2.alert_handler_stress_all/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all_with_rand_reset.1774687807
Short name T208
Test name
Test status
Simulation time 251633412273 ps
CPU time 4222.29 seconds
Started Jan 24 01:39:22 PM PST 24
Finished Jan 24 02:49:50 PM PST 24
Peak memory 313440 kb
Host smart-15694e46-908c-4927-b260-14c7d9a9ba64
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774687807 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.alert_handler_stress_all_with_rand_reset.1774687807
Directory /workspace/2.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.alert_handler_entropy.3227414002
Short name T440
Test name
Test status
Simulation time 152935005060 ps
CPU time 1330.89 seconds
Started Jan 24 01:42:14 PM PST 24
Finished Jan 24 02:04:37 PM PST 24
Peak memory 264596 kb
Host smart-eeb2b1cc-de10-42c3-b4af-cbbb578d3c0e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227414002 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_entropy.3227414002
Directory /workspace/20.alert_handler_entropy/latest

Test location /workspace/coverage/default/20.alert_handler_esc_alert_accum.2882517971
Short name T85
Test name
Test status
Simulation time 291684345 ps
CPU time 16.94 seconds
Started Jan 24 01:42:15 PM PST 24
Finished Jan 24 01:42:48 PM PST 24
Peak memory 250300 kb
Host smart-ba3f8571-c711-4b7b-b3b8-a6df7edb61ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28825
17971 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_alert_accum.2882517971
Directory /workspace/20.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/20.alert_handler_esc_intr_timeout.2961443210
Short name T414
Test name
Test status
Simulation time 2268832941 ps
CPU time 40.47 seconds
Started Jan 24 01:42:17 PM PST 24
Finished Jan 24 01:43:25 PM PST 24
Peak memory 248116 kb
Host smart-2452bcb1-957c-4e5c-80d0-0ba002c15308
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29614
43210 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_intr_timeout.2961443210
Directory /workspace/20.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_lpg.1838558969
Short name T311
Test name
Test status
Simulation time 45401034883 ps
CPU time 927.07 seconds
Started Jan 24 01:42:12 PM PST 24
Finished Jan 24 01:57:44 PM PST 24
Peak memory 272112 kb
Host smart-7c6ad6c5-1ac9-41f2-8c9e-d392e891ff10
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838558969 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg.1838558969
Directory /workspace/20.alert_handler_lpg/latest

Test location /workspace/coverage/default/20.alert_handler_ping_timeout.1044790714
Short name T315
Test name
Test status
Simulation time 70631026897 ps
CPU time 229.3 seconds
Started Jan 24 01:42:11 PM PST 24
Finished Jan 24 01:46:06 PM PST 24
Peak memory 250356 kb
Host smart-25d518f6-fd9d-40f3-b26d-4dd4a1fa38c8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044790714 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_ping_timeout.1044790714
Directory /workspace/20.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_random_alerts.2168703207
Short name T644
Test name
Test status
Simulation time 1247069309 ps
CPU time 10.35 seconds
Started Jan 24 01:42:13 PM PST 24
Finished Jan 24 01:42:35 PM PST 24
Peak memory 248068 kb
Host smart-1cc58b7e-f10b-479e-8dbc-de1efc3d298e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21687
03207 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_alerts.2168703207
Directory /workspace/20.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/20.alert_handler_random_classes.1897631334
Short name T645
Test name
Test status
Simulation time 364752864 ps
CPU time 34.65 seconds
Started Jan 24 01:42:12 PM PST 24
Finished Jan 24 01:42:52 PM PST 24
Peak memory 248024 kb
Host smart-ec91e942-89f3-4713-b650-a7c8c69a16db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18976
31334 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_classes.1897631334
Directory /workspace/20.alert_handler_random_classes/latest

Test location /workspace/coverage/default/20.alert_handler_sig_int_fail.2544123082
Short name T629
Test name
Test status
Simulation time 130193703 ps
CPU time 9.6 seconds
Started Jan 24 01:42:12 PM PST 24
Finished Jan 24 01:42:27 PM PST 24
Peak memory 248060 kb
Host smart-f0fd1856-1d7f-49c2-85a4-5c295e252214
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25441
23082 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_sig_int_fail.2544123082
Directory /workspace/20.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/20.alert_handler_smoke.2915284440
Short name T358
Test name
Test status
Simulation time 3799589359 ps
CPU time 57.26 seconds
Started Jan 24 01:42:08 PM PST 24
Finished Jan 24 01:43:11 PM PST 24
Peak memory 248116 kb
Host smart-c7426497-0e1d-461c-8554-9b286d1e2b54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29152
84440 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_smoke.2915284440
Directory /workspace/20.alert_handler_smoke/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all.2955235675
Short name T586
Test name
Test status
Simulation time 33396358717 ps
CPU time 1553.42 seconds
Started Jan 24 01:42:17 PM PST 24
Finished Jan 24 02:08:38 PM PST 24
Peak memory 288004 kb
Host smart-927fc7a7-7341-4614-84a2-9c943268ef17
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955235675 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_ha
ndler_stress_all.2955235675
Directory /workspace/20.alert_handler_stress_all/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all_with_rand_reset.750260272
Short name T413
Test name
Test status
Simulation time 528239496667 ps
CPU time 1822.19 seconds
Started Jan 24 01:42:15 PM PST 24
Finished Jan 24 02:12:54 PM PST 24
Peak memory 281076 kb
Host smart-66f547cd-1e3f-4d4a-b571-6e714c962166
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750260272 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 20.alert_handler_stress_all_with_rand_reset.750260272
Directory /workspace/20.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.alert_handler_entropy.2235951733
Short name T703
Test name
Test status
Simulation time 362885409218 ps
CPU time 3026.89 seconds
Started Jan 24 01:42:19 PM PST 24
Finished Jan 24 02:33:15 PM PST 24
Peak memory 288588 kb
Host smart-ea61d1fd-7404-4e55-b282-4bd15b50e9f1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2235951733 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_entropy.2235951733
Directory /workspace/21.alert_handler_entropy/latest

Test location /workspace/coverage/default/21.alert_handler_esc_alert_accum.1206911300
Short name T661
Test name
Test status
Simulation time 13321394210 ps
CPU time 186.44 seconds
Started Jan 24 01:42:20 PM PST 24
Finished Jan 24 01:45:55 PM PST 24
Peak memory 250364 kb
Host smart-b88c4889-2919-438f-8757-d5d9bb027b5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12069
11300 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_alert_accum.1206911300
Directory /workspace/21.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/21.alert_handler_esc_intr_timeout.681229427
Short name T3
Test name
Test status
Simulation time 1978480909 ps
CPU time 49.3 seconds
Started Jan 24 01:42:17 PM PST 24
Finished Jan 24 01:43:35 PM PST 24
Peak memory 248260 kb
Host smart-2d453a0f-27da-4e9e-9635-733f5e8efc8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68122
9427 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_intr_timeout.681229427
Directory /workspace/21.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_lpg_stub_clk.87666535
Short name T105
Test name
Test status
Simulation time 8655932739 ps
CPU time 988.64 seconds
Started Jan 24 01:42:18 PM PST 24
Finished Jan 24 01:59:17 PM PST 24
Peak memory 272160 kb
Host smart-96130815-f85f-4c40-841d-6063b60c85f9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87666535 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg_stub_clk.87666535
Directory /workspace/21.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/21.alert_handler_ping_timeout.3633589726
Short name T305
Test name
Test status
Simulation time 3687532689 ps
CPU time 77.33 seconds
Started Jan 24 01:42:23 PM PST 24
Finished Jan 24 01:44:08 PM PST 24
Peak memory 249108 kb
Host smart-0eaea178-139c-456d-bb0d-2ca33c35a0da
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633589726 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_ping_timeout.3633589726
Directory /workspace/21.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_random_alerts.3466470658
Short name T544
Test name
Test status
Simulation time 653151484 ps
CPU time 43.17 seconds
Started Jan 24 01:42:20 PM PST 24
Finished Jan 24 01:43:31 PM PST 24
Peak memory 250020 kb
Host smart-1936e17b-1a79-4863-a0b1-7ccd0e9f666f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34664
70658 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_alerts.3466470658
Directory /workspace/21.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/21.alert_handler_random_classes.2348221220
Short name T402
Test name
Test status
Simulation time 152463834 ps
CPU time 13.21 seconds
Started Jan 24 01:42:18 PM PST 24
Finished Jan 24 01:43:01 PM PST 24
Peak memory 248080 kb
Host smart-dfccc4e9-ed69-4c73-91e2-00cdcd0243d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23482
21220 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_classes.2348221220
Directory /workspace/21.alert_handler_random_classes/latest

Test location /workspace/coverage/default/21.alert_handler_sig_int_fail.1033482249
Short name T254
Test name
Test status
Simulation time 342586283 ps
CPU time 22.71 seconds
Started Jan 24 01:42:16 PM PST 24
Finished Jan 24 01:43:02 PM PST 24
Peak memory 251136 kb
Host smart-8accad6d-8361-44c0-98ca-af8e2804595d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10334
82249 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_sig_int_fail.1033482249
Directory /workspace/21.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/21.alert_handler_smoke.2067320326
Short name T630
Test name
Test status
Simulation time 2426394470 ps
CPU time 42.81 seconds
Started Jan 24 01:42:18 PM PST 24
Finished Jan 24 01:43:31 PM PST 24
Peak memory 248196 kb
Host smart-d80a2c44-bde6-4489-85c5-a970e83f7381
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20673
20326 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_smoke.2067320326
Directory /workspace/21.alert_handler_smoke/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all.2164903748
Short name T615
Test name
Test status
Simulation time 4083240157 ps
CPU time 178.91 seconds
Started Jan 24 01:42:17 PM PST 24
Finished Jan 24 01:45:44 PM PST 24
Peak memory 256348 kb
Host smart-7199097f-9c0a-4fd2-83b2-8c219b79ac5d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164903748 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_ha
ndler_stress_all.2164903748
Directory /workspace/21.alert_handler_stress_all/latest

Test location /workspace/coverage/default/22.alert_handler_entropy.2063357809
Short name T239
Test name
Test status
Simulation time 11654297677 ps
CPU time 1283.88 seconds
Started Jan 24 01:42:30 PM PST 24
Finished Jan 24 02:04:22 PM PST 24
Peak memory 288932 kb
Host smart-f3202a96-516f-4623-85c9-5f010b3a1c2e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063357809 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_entropy.2063357809
Directory /workspace/22.alert_handler_entropy/latest

Test location /workspace/coverage/default/22.alert_handler_esc_alert_accum.2857621996
Short name T45
Test name
Test status
Simulation time 2526417533 ps
CPU time 151.85 seconds
Started Jan 24 01:42:27 PM PST 24
Finished Jan 24 01:45:26 PM PST 24
Peak memory 248172 kb
Host smart-0864c495-da62-48b6-92ee-35b33f9f25e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28576
21996 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_alert_accum.2857621996
Directory /workspace/22.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/22.alert_handler_esc_intr_timeout.3930668755
Short name T480
Test name
Test status
Simulation time 83716672 ps
CPU time 2.89 seconds
Started Jan 24 01:42:37 PM PST 24
Finished Jan 24 01:43:14 PM PST 24
Peak memory 237288 kb
Host smart-324136e3-4e83-4780-8c16-5523068d57c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39306
68755 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_intr_timeout.3930668755
Directory /workspace/22.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_lpg.3510191640
Short name T328
Test name
Test status
Simulation time 90036842208 ps
CPU time 2020.33 seconds
Started Jan 24 01:42:29 PM PST 24
Finished Jan 24 02:16:38 PM PST 24
Peak memory 272432 kb
Host smart-8d037a91-1e34-4986-9ae0-8ca9577ff60f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510191640 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg.3510191640
Directory /workspace/22.alert_handler_lpg/latest

Test location /workspace/coverage/default/22.alert_handler_lpg_stub_clk.96758292
Short name T364
Test name
Test status
Simulation time 138393447355 ps
CPU time 2094.18 seconds
Started Jan 24 01:42:29 PM PST 24
Finished Jan 24 02:17:52 PM PST 24
Peak memory 272460 kb
Host smart-f47ee816-1f55-42a1-bb0e-2a49b343740b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96758292 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg_stub_clk.96758292
Directory /workspace/22.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/22.alert_handler_ping_timeout.1120204959
Short name T446
Test name
Test status
Simulation time 41156857839 ps
CPU time 200.81 seconds
Started Jan 24 01:42:32 PM PST 24
Finished Jan 24 01:46:23 PM PST 24
Peak memory 246692 kb
Host smart-2c82800f-f88c-43c1-bd06-2169178e5e15
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120204959 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_ping_timeout.1120204959
Directory /workspace/22.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_random_alerts.3982219147
Short name T570
Test name
Test status
Simulation time 1118672274 ps
CPU time 60.21 seconds
Started Jan 24 01:42:32 PM PST 24
Finished Jan 24 01:44:02 PM PST 24
Peak memory 248064 kb
Host smart-035fa963-f36a-49cc-aac7-edd9ef548ae6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39822
19147 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_alerts.3982219147
Directory /workspace/22.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/22.alert_handler_random_classes.1780359449
Short name T469
Test name
Test status
Simulation time 1602995686 ps
CPU time 14.03 seconds
Started Jan 24 01:42:30 PM PST 24
Finished Jan 24 01:43:13 PM PST 24
Peak memory 248024 kb
Host smart-6de52e85-8d55-4d94-a93a-46c54a7391c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17803
59449 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_classes.1780359449
Directory /workspace/22.alert_handler_random_classes/latest

Test location /workspace/coverage/default/22.alert_handler_sig_int_fail.451848966
Short name T575
Test name
Test status
Simulation time 251727754 ps
CPU time 17.56 seconds
Started Jan 24 01:42:36 PM PST 24
Finished Jan 24 01:43:29 PM PST 24
Peak memory 248068 kb
Host smart-59924aa0-e691-4b7e-a865-8813c6d7db17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45184
8966 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_sig_int_fail.451848966
Directory /workspace/22.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/22.alert_handler_smoke.1704100276
Short name T541
Test name
Test status
Simulation time 452550277 ps
CPU time 27.64 seconds
Started Jan 24 01:42:32 PM PST 24
Finished Jan 24 01:43:30 PM PST 24
Peak memory 248072 kb
Host smart-ab5b0331-cd3a-426f-b6fa-a1074011ce07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17041
00276 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_smoke.1704100276
Directory /workspace/22.alert_handler_smoke/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all.589228740
Short name T415
Test name
Test status
Simulation time 58227819521 ps
CPU time 3229.06 seconds
Started Jan 24 01:42:29 PM PST 24
Finished Jan 24 02:36:47 PM PST 24
Peak memory 288656 kb
Host smart-3757053c-fdca-4266-a0a6-7876c8b7b95f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589228740 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_han
dler_stress_all.589228740
Directory /workspace/22.alert_handler_stress_all/latest

Test location /workspace/coverage/default/23.alert_handler_entropy.1481680263
Short name T69
Test name
Test status
Simulation time 102376103136 ps
CPU time 1536.33 seconds
Started Jan 24 01:42:42 PM PST 24
Finished Jan 24 02:08:52 PM PST 24
Peak memory 272672 kb
Host smart-5ed5f3b1-d1fb-47c3-8bba-8cb78c9fb9b4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1481680263 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_entropy.1481680263
Directory /workspace/23.alert_handler_entropy/latest

Test location /workspace/coverage/default/23.alert_handler_esc_alert_accum.3105130053
Short name T433
Test name
Test status
Simulation time 639594325 ps
CPU time 5.53 seconds
Started Jan 24 01:42:37 PM PST 24
Finished Jan 24 01:43:17 PM PST 24
Peak memory 237624 kb
Host smart-608909d2-47ef-4c1e-a2fe-88fb774d2bd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31051
30053 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_alert_accum.3105130053
Directory /workspace/23.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/23.alert_handler_esc_intr_timeout.2381161686
Short name T429
Test name
Test status
Simulation time 561077265 ps
CPU time 20.71 seconds
Started Jan 24 01:42:30 PM PST 24
Finished Jan 24 01:43:19 PM PST 24
Peak memory 247232 kb
Host smart-b94cb27c-d443-4cf8-ac9b-25044be309da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23811
61686 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_intr_timeout.2381161686
Directory /workspace/23.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_lpg_stub_clk.2212299103
Short name T526
Test name
Test status
Simulation time 96480620577 ps
CPU time 771.75 seconds
Started Jan 24 01:42:46 PM PST 24
Finished Jan 24 01:56:16 PM PST 24
Peak memory 265704 kb
Host smart-39a7ff50-a48a-453a-9345-6bb811c8fd48
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212299103 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg_stub_clk.2212299103
Directory /workspace/23.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/23.alert_handler_ping_timeout.2661402469
Short name T557
Test name
Test status
Simulation time 41289327669 ps
CPU time 200.07 seconds
Started Jan 24 01:42:42 PM PST 24
Finished Jan 24 01:46:36 PM PST 24
Peak memory 245832 kb
Host smart-4d72a89d-26db-4261-b354-5913fa8eba6d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661402469 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_ping_timeout.2661402469
Directory /workspace/23.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_random_alerts.1595714116
Short name T378
Test name
Test status
Simulation time 1221257880 ps
CPU time 20.66 seconds
Started Jan 24 01:42:33 PM PST 24
Finished Jan 24 01:43:25 PM PST 24
Peak memory 248056 kb
Host smart-6eaaf61e-ae72-4339-afbd-d1b3f00806ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15957
14116 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_alerts.1595714116
Directory /workspace/23.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/23.alert_handler_random_classes.1943314633
Short name T33
Test name
Test status
Simulation time 7321975590 ps
CPU time 37.51 seconds
Started Jan 24 01:42:29 PM PST 24
Finished Jan 24 01:43:35 PM PST 24
Peak memory 248100 kb
Host smart-41d84197-83e8-4002-8eaf-ba57701c42e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19433
14633 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_classes.1943314633
Directory /workspace/23.alert_handler_random_classes/latest

Test location /workspace/coverage/default/23.alert_handler_sig_int_fail.3345996349
Short name T572
Test name
Test status
Simulation time 528516907 ps
CPU time 37.95 seconds
Started Jan 24 01:42:40 PM PST 24
Finished Jan 24 01:43:52 PM PST 24
Peak memory 248000 kb
Host smart-b9c82345-1f3a-4537-b1d1-2f7f02ea7496
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33459
96349 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_sig_int_fail.3345996349
Directory /workspace/23.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/23.alert_handler_smoke.3732477559
Short name T367
Test name
Test status
Simulation time 514479054 ps
CPU time 35.78 seconds
Started Jan 24 01:42:32 PM PST 24
Finished Jan 24 01:43:39 PM PST 24
Peak memory 248020 kb
Host smart-782f0207-a3de-4852-a22f-4bea80478a87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37324
77559 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_smoke.3732477559
Directory /workspace/23.alert_handler_smoke/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all.4065037033
Short name T700
Test name
Test status
Simulation time 6607320767 ps
CPU time 132.53 seconds
Started Jan 24 01:42:40 PM PST 24
Finished Jan 24 01:45:25 PM PST 24
Peak memory 256252 kb
Host smart-c0ff89e9-0716-4561-94b5-742588ee4604
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065037033 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_ha
ndler_stress_all.4065037033
Directory /workspace/23.alert_handler_stress_all/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all_with_rand_reset.1601442735
Short name T67
Test name
Test status
Simulation time 170809071156 ps
CPU time 5532.98 seconds
Started Jan 24 01:42:41 PM PST 24
Finished Jan 24 03:15:28 PM PST 24
Peak memory 297260 kb
Host smart-f8d2119a-1f22-4507-8f0c-0bf6ce74170c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601442735 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 23.alert_handler_stress_all_with_rand_reset.1601442735
Directory /workspace/23.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.alert_handler_entropy.469151146
Short name T396
Test name
Test status
Simulation time 49954078886 ps
CPU time 2876.83 seconds
Started Jan 24 01:42:43 PM PST 24
Finished Jan 24 02:31:15 PM PST 24
Peak memory 287932 kb
Host smart-790d1a67-515c-441a-bb72-b5f4ac62f8ea
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469151146 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_entropy.469151146
Directory /workspace/24.alert_handler_entropy/latest

Test location /workspace/coverage/default/24.alert_handler_esc_alert_accum.148974128
Short name T369
Test name
Test status
Simulation time 1521318136 ps
CPU time 113.82 seconds
Started Jan 24 01:42:42 PM PST 24
Finished Jan 24 01:45:10 PM PST 24
Peak memory 249076 kb
Host smart-af5c0eeb-e24f-48a1-8ed5-b85c2958052c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14897
4128 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_alert_accum.148974128
Directory /workspace/24.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/24.alert_handler_esc_intr_timeout.2679571012
Short name T431
Test name
Test status
Simulation time 425982240 ps
CPU time 23.84 seconds
Started Jan 24 01:42:43 PM PST 24
Finished Jan 24 01:43:40 PM PST 24
Peak memory 248068 kb
Host smart-701e1789-5e68-4bbf-b693-7f67f54b7bb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26795
71012 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_intr_timeout.2679571012
Directory /workspace/24.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_lpg_stub_clk.1310048458
Short name T124
Test name
Test status
Simulation time 10547023938 ps
CPU time 1221.62 seconds
Started Jan 24 01:42:55 PM PST 24
Finished Jan 24 02:03:53 PM PST 24
Peak memory 286824 kb
Host smart-ae8c521d-9ec7-44c8-956c-8cf581d84387
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310048458 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg_stub_clk.1310048458
Directory /workspace/24.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/24.alert_handler_ping_timeout.2307632634
Short name T324
Test name
Test status
Simulation time 10304787300 ps
CPU time 410.58 seconds
Started Jan 24 01:42:38 PM PST 24
Finished Jan 24 01:50:02 PM PST 24
Peak memory 247712 kb
Host smart-94d06818-537a-4330-bb74-aac7b4f142d4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307632634 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_ping_timeout.2307632634
Directory /workspace/24.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_random_alerts.3611700553
Short name T561
Test name
Test status
Simulation time 2237813402 ps
CPU time 18.8 seconds
Started Jan 24 01:42:47 PM PST 24
Finished Jan 24 01:43:45 PM PST 24
Peak memory 248080 kb
Host smart-a4a86a20-5d3c-4d3f-a3b1-5013c92a8e8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36117
00553 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_alerts.3611700553
Directory /workspace/24.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/24.alert_handler_random_classes.1465379334
Short name T84
Test name
Test status
Simulation time 201727113 ps
CPU time 17.51 seconds
Started Jan 24 01:42:46 PM PST 24
Finished Jan 24 01:43:42 PM PST 24
Peak memory 248016 kb
Host smart-6ad30577-15ab-490d-a533-c18ac09646b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14653
79334 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_classes.1465379334
Directory /workspace/24.alert_handler_random_classes/latest

Test location /workspace/coverage/default/24.alert_handler_sig_int_fail.1682761056
Short name T244
Test name
Test status
Simulation time 570114435 ps
CPU time 37.06 seconds
Started Jan 24 01:42:39 PM PST 24
Finished Jan 24 01:43:49 PM PST 24
Peak memory 248024 kb
Host smart-cccf8d9b-e87f-4427-9acc-c0897fbf94c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16827
61056 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_sig_int_fail.1682761056
Directory /workspace/24.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/24.alert_handler_smoke.1802215211
Short name T461
Test name
Test status
Simulation time 350325526 ps
CPU time 33.03 seconds
Started Jan 24 01:42:42 PM PST 24
Finished Jan 24 01:43:49 PM PST 24
Peak memory 248092 kb
Host smart-cd610a46-95dc-4d1c-a4ab-26ae1344d5e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18022
15211 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_smoke.1802215211
Directory /workspace/24.alert_handler_smoke/latest

Test location /workspace/coverage/default/25.alert_handler_entropy.3768240353
Short name T265
Test name
Test status
Simulation time 67663444858 ps
CPU time 2251.72 seconds
Started Jan 24 01:42:54 PM PST 24
Finished Jan 24 02:21:03 PM PST 24
Peak memory 285748 kb
Host smart-5c2e8255-e606-4576-9af4-82bb821a3acb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768240353 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_entropy.3768240353
Directory /workspace/25.alert_handler_entropy/latest

Test location /workspace/coverage/default/25.alert_handler_esc_alert_accum.3593553766
Short name T258
Test name
Test status
Simulation time 398610158 ps
CPU time 31.37 seconds
Started Jan 24 01:42:50 PM PST 24
Finished Jan 24 01:44:01 PM PST 24
Peak memory 247988 kb
Host smart-d865a45d-8a86-40c4-b021-db81764e7958
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35935
53766 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_alert_accum.3593553766
Directory /workspace/25.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/25.alert_handler_esc_intr_timeout.2038583031
Short name T351
Test name
Test status
Simulation time 529942653 ps
CPU time 20.67 seconds
Started Jan 24 01:42:50 PM PST 24
Finished Jan 24 01:43:50 PM PST 24
Peak memory 248032 kb
Host smart-a56dc2d0-0143-4932-bda8-b39aca990a90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20385
83031 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_intr_timeout.2038583031
Directory /workspace/25.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_lpg.3903448738
Short name T295
Test name
Test status
Simulation time 12133752052 ps
CPU time 1243.73 seconds
Started Jan 24 02:24:55 PM PST 24
Finished Jan 24 02:45:46 PM PST 24
Peak memory 280660 kb
Host smart-916f6d71-a0ba-4d9e-a22b-130a44c12424
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903448738 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg.3903448738
Directory /workspace/25.alert_handler_lpg/latest

Test location /workspace/coverage/default/25.alert_handler_lpg_stub_clk.3441856116
Short name T554
Test name
Test status
Simulation time 13267147396 ps
CPU time 1204.75 seconds
Started Jan 24 02:01:47 PM PST 24
Finished Jan 24 02:22:03 PM PST 24
Peak memory 288240 kb
Host smart-87a312c3-e1e2-42ac-82e7-5d00656cf3b2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3441856116 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg_stub_clk.3441856116
Directory /workspace/25.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/25.alert_handler_random_alerts.3452939264
Short name T564
Test name
Test status
Simulation time 769692551 ps
CPU time 17.28 seconds
Started Jan 24 01:42:48 PM PST 24
Finished Jan 24 01:43:45 PM PST 24
Peak memory 248024 kb
Host smart-0b06545f-ec22-4d60-99e8-e11d0a881967
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34529
39264 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_alerts.3452939264
Directory /workspace/25.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/25.alert_handler_random_classes.1957101689
Short name T694
Test name
Test status
Simulation time 223432232 ps
CPU time 20.87 seconds
Started Jan 24 01:42:52 PM PST 24
Finished Jan 24 01:43:51 PM PST 24
Peak memory 248052 kb
Host smart-5e8a831e-8e0b-4eab-8872-7a683bd266ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19571
01689 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_classes.1957101689
Directory /workspace/25.alert_handler_random_classes/latest

Test location /workspace/coverage/default/25.alert_handler_sig_int_fail.1426490116
Short name T680
Test name
Test status
Simulation time 164591362 ps
CPU time 7.4 seconds
Started Jan 24 01:42:53 PM PST 24
Finished Jan 24 01:43:38 PM PST 24
Peak memory 239868 kb
Host smart-2957bbfc-b7a2-46cc-852b-5b02b512de7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14264
90116 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_sig_int_fail.1426490116
Directory /workspace/25.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/25.alert_handler_smoke.2049603299
Short name T465
Test name
Test status
Simulation time 247720313 ps
CPU time 4.79 seconds
Started Jan 24 01:42:53 PM PST 24
Finished Jan 24 01:43:35 PM PST 24
Peak memory 239848 kb
Host smart-92046839-71e9-4dc3-83c5-05ed0292e9c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20496
03299 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_smoke.2049603299
Directory /workspace/25.alert_handler_smoke/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all.1635200281
Short name T481
Test name
Test status
Simulation time 50845305292 ps
CPU time 2843.47 seconds
Started Jan 24 01:59:08 PM PST 24
Finished Jan 24 02:46:34 PM PST 24
Peak memory 285508 kb
Host smart-c994401b-78e1-44e1-95b1-cfd66fbde889
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635200281 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_ha
ndler_stress_all.1635200281
Directory /workspace/25.alert_handler_stress_all/latest

Test location /workspace/coverage/default/26.alert_handler_entropy.1311302771
Short name T581
Test name
Test status
Simulation time 6147950173 ps
CPU time 601.8 seconds
Started Jan 24 02:15:47 PM PST 24
Finished Jan 24 02:26:29 PM PST 24
Peak memory 264564 kb
Host smart-b45d08e5-4a8e-4c82-b6e9-544c8ca22a36
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311302771 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_entropy.1311302771
Directory /workspace/26.alert_handler_entropy/latest

Test location /workspace/coverage/default/26.alert_handler_esc_alert_accum.3599135233
Short name T50
Test name
Test status
Simulation time 3152449703 ps
CPU time 69.29 seconds
Started Jan 24 01:43:26 PM PST 24
Finished Jan 24 01:44:53 PM PST 24
Peak memory 250204 kb
Host smart-8faaa71b-b36e-45d0-8343-a6db6b2e9f5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35991
35233 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_alert_accum.3599135233
Directory /workspace/26.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/26.alert_handler_esc_intr_timeout.54951724
Short name T95
Test name
Test status
Simulation time 1477974258 ps
CPU time 42.5 seconds
Started Jan 24 01:43:23 PM PST 24
Finished Jan 24 01:44:24 PM PST 24
Peak memory 248056 kb
Host smart-91bc7df8-da14-4dfc-b8b9-6d44924b190d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54951
724 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_intr_timeout.54951724
Directory /workspace/26.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_ping_timeout.95427183
Short name T585
Test name
Test status
Simulation time 4069741859 ps
CPU time 169.41 seconds
Started Jan 24 01:43:26 PM PST 24
Finished Jan 24 01:46:33 PM PST 24
Peak memory 246632 kb
Host smart-09e52341-2678-4bb3-b1d7-ab2d30224565
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95427183 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_ping_timeout.95427183
Directory /workspace/26.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_random_alerts.901458209
Short name T577
Test name
Test status
Simulation time 2103137679 ps
CPU time 31.92 seconds
Started Jan 24 01:43:17 PM PST 24
Finished Jan 24 01:44:11 PM PST 24
Peak memory 248036 kb
Host smart-0a405970-11ed-4437-8eef-0fe76d931046
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90145
8209 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_alerts.901458209
Directory /workspace/26.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/26.alert_handler_random_classes.979864815
Short name T527
Test name
Test status
Simulation time 212632390 ps
CPU time 13.58 seconds
Started Jan 24 01:43:28 PM PST 24
Finished Jan 24 01:43:58 PM PST 24
Peak memory 252712 kb
Host smart-397bccc4-caea-4afe-9a65-5ccbc42bfa86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97986
4815 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_classes.979864815
Directory /workspace/26.alert_handler_random_classes/latest

Test location /workspace/coverage/default/26.alert_handler_sig_int_fail.173973434
Short name T5
Test name
Test status
Simulation time 319089833 ps
CPU time 6.14 seconds
Started Jan 24 03:42:55 PM PST 24
Finished Jan 24 03:43:03 PM PST 24
Peak memory 237824 kb
Host smart-77667f04-3ac4-40a0-9af5-bcb468bb2c83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17397
3434 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_sig_int_fail.173973434
Directory /workspace/26.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/26.alert_handler_smoke.502209540
Short name T560
Test name
Test status
Simulation time 283079444 ps
CPU time 29.41 seconds
Started Jan 24 01:43:18 PM PST 24
Finished Jan 24 01:44:08 PM PST 24
Peak memory 248048 kb
Host smart-6a0c13ad-8c57-45bd-8dae-3b50592916fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50220
9540 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_smoke.502209540
Directory /workspace/26.alert_handler_smoke/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all.352233458
Short name T102
Test name
Test status
Simulation time 79366934855 ps
CPU time 1906.5 seconds
Started Jan 24 01:55:38 PM PST 24
Finished Jan 24 02:27:26 PM PST 24
Peak memory 288856 kb
Host smart-2ab2caaf-6ec5-4b6a-9495-36219856d6e0
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352233458 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_han
dler_stress_all.352233458
Directory /workspace/26.alert_handler_stress_all/latest

Test location /workspace/coverage/default/27.alert_handler_esc_alert_accum.1906209805
Short name T683
Test name
Test status
Simulation time 1900787061 ps
CPU time 141.82 seconds
Started Jan 24 02:14:10 PM PST 24
Finished Jan 24 02:16:46 PM PST 24
Peak memory 250124 kb
Host smart-867e6c04-27bb-4ea2-836f-85484f0037dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19062
09805 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_alert_accum.1906209805
Directory /workspace/27.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/27.alert_handler_esc_intr_timeout.3628410753
Short name T455
Test name
Test status
Simulation time 3708296328 ps
CPU time 57.04 seconds
Started Jan 24 01:43:41 PM PST 24
Finished Jan 24 01:44:50 PM PST 24
Peak memory 254776 kb
Host smart-76acb17b-69f9-457c-a03c-ad7eda4cbcd2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36284
10753 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_intr_timeout.3628410753
Directory /workspace/27.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_lpg.3419438350
Short name T303
Test name
Test status
Simulation time 47533928123 ps
CPU time 2643.34 seconds
Started Jan 24 01:43:41 PM PST 24
Finished Jan 24 02:27:57 PM PST 24
Peak memory 288676 kb
Host smart-2fc0f901-3561-4901-9617-24f8437f6e5f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419438350 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg.3419438350
Directory /workspace/27.alert_handler_lpg/latest

Test location /workspace/coverage/default/27.alert_handler_lpg_stub_clk.429089580
Short name T119
Test name
Test status
Simulation time 97085733622 ps
CPU time 2650.8 seconds
Started Jan 24 01:43:58 PM PST 24
Finished Jan 24 02:28:22 PM PST 24
Peak memory 286380 kb
Host smart-2d08d85b-f558-442c-ae9a-862f47ca6f4a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429089580 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg_stub_clk.429089580
Directory /workspace/27.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/27.alert_handler_random_alerts.4000090553
Short name T17
Test name
Test status
Simulation time 489847306 ps
CPU time 10.12 seconds
Started Jan 24 02:54:46 PM PST 24
Finished Jan 24 02:55:13 PM PST 24
Peak memory 239924 kb
Host smart-24f9b39c-5931-42ef-aace-bd89372dfc6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40000
90553 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_alerts.4000090553
Directory /workspace/27.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/27.alert_handler_random_classes.1938177547
Short name T462
Test name
Test status
Simulation time 1348680533 ps
CPU time 29.75 seconds
Started Jan 24 02:51:19 PM PST 24
Finished Jan 24 02:51:57 PM PST 24
Peak memory 252452 kb
Host smart-e3255e5e-72ef-4472-bd38-3a426d35a190
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19381
77547 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_classes.1938177547
Directory /workspace/27.alert_handler_random_classes/latest

Test location /workspace/coverage/default/27.alert_handler_sig_int_fail.1466134483
Short name T657
Test name
Test status
Simulation time 667349684 ps
CPU time 28.58 seconds
Started Jan 24 01:43:36 PM PST 24
Finished Jan 24 01:44:20 PM PST 24
Peak memory 248024 kb
Host smart-1d34b86f-d485-40fc-991d-8a98520ae534
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14661
34483 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_sig_int_fail.1466134483
Directory /workspace/27.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/27.alert_handler_smoke.3165915392
Short name T350
Test name
Test status
Simulation time 47038692 ps
CPU time 4.83 seconds
Started Jan 24 01:43:26 PM PST 24
Finished Jan 24 01:43:48 PM PST 24
Peak memory 239804 kb
Host smart-ba46f253-cdc5-40bf-b8e7-219193018414
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31659
15392 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_smoke.3165915392
Directory /workspace/27.alert_handler_smoke/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all_with_rand_reset.139267245
Short name T711
Test name
Test status
Simulation time 55227473385 ps
CPU time 3874.93 seconds
Started Jan 24 01:43:55 PM PST 24
Finished Jan 24 02:48:36 PM PST 24
Peak memory 298048 kb
Host smart-5ed118e6-5050-46d5-a1a1-163e022c798f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139267245 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 27.alert_handler_stress_all_with_rand_reset.139267245
Directory /workspace/27.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.alert_handler_entropy.1572345147
Short name T540
Test name
Test status
Simulation time 12704817138 ps
CPU time 999.22 seconds
Started Jan 24 01:44:11 PM PST 24
Finished Jan 24 02:01:06 PM PST 24
Peak memory 271940 kb
Host smart-9cbb4be7-aeb8-44a6-8e7d-e747ee4a1af2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572345147 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_entropy.1572345147
Directory /workspace/28.alert_handler_entropy/latest

Test location /workspace/coverage/default/28.alert_handler_esc_alert_accum.439708175
Short name T568
Test name
Test status
Simulation time 9065660099 ps
CPU time 135.94 seconds
Started Jan 24 01:44:02 PM PST 24
Finished Jan 24 01:46:35 PM PST 24
Peak memory 250424 kb
Host smart-e1f46fcf-9d40-4bd3-aaaf-56fec6da1748
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43970
8175 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_alert_accum.439708175
Directory /workspace/28.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/28.alert_handler_esc_intr_timeout.3871357155
Short name T94
Test name
Test status
Simulation time 2072731318 ps
CPU time 31.44 seconds
Started Jan 24 01:44:02 PM PST 24
Finished Jan 24 01:44:52 PM PST 24
Peak memory 250288 kb
Host smart-a74170ee-b6e3-4320-abcf-f21f60453ed4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38713
57155 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_intr_timeout.3871357155
Directory /workspace/28.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_lpg.959473442
Short name T336
Test name
Test status
Simulation time 39945089321 ps
CPU time 1515.77 seconds
Started Jan 24 02:44:22 PM PST 24
Finished Jan 24 03:10:00 PM PST 24
Peak memory 288380 kb
Host smart-632c8e34-9d96-4220-8b18-e2b45f6bcc35
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959473442 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg.959473442
Directory /workspace/28.alert_handler_lpg/latest

Test location /workspace/coverage/default/28.alert_handler_lpg_stub_clk.2066408200
Short name T121
Test name
Test status
Simulation time 40066051151 ps
CPU time 853.21 seconds
Started Jan 24 02:05:38 PM PST 24
Finished Jan 24 02:20:43 PM PST 24
Peak memory 271880 kb
Host smart-5036a1ae-1868-4979-8e76-d0e5d25474b2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066408200 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg_stub_clk.2066408200
Directory /workspace/28.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/28.alert_handler_ping_timeout.4078711439
Short name T675
Test name
Test status
Simulation time 23588934419 ps
CPU time 232.62 seconds
Started Jan 24 02:14:10 PM PST 24
Finished Jan 24 02:18:17 PM PST 24
Peak memory 246720 kb
Host smart-c126e905-1e7d-4401-80a0-e39e0b023082
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078711439 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_ping_timeout.4078711439
Directory /workspace/28.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_random_alerts.1928703171
Short name T717
Test name
Test status
Simulation time 3245661773 ps
CPU time 54.09 seconds
Started Jan 24 01:44:04 PM PST 24
Finished Jan 24 01:45:17 PM PST 24
Peak memory 248096 kb
Host smart-b2a5af68-f0e0-46ee-b513-5674e8603b93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19287
03171 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_alerts.1928703171
Directory /workspace/28.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/28.alert_handler_random_classes.2450198662
Short name T377
Test name
Test status
Simulation time 390525247 ps
CPU time 7.03 seconds
Started Jan 24 01:44:01 PM PST 24
Finished Jan 24 01:44:25 PM PST 24
Peak memory 249480 kb
Host smart-5254e474-6135-43b6-89ee-9383fd26e7d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24501
98662 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_classes.2450198662
Directory /workspace/28.alert_handler_random_classes/latest

Test location /workspace/coverage/default/28.alert_handler_sig_int_fail.4131322110
Short name T284
Test name
Test status
Simulation time 768322013 ps
CPU time 52.33 seconds
Started Jan 24 01:50:07 PM PST 24
Finished Jan 24 01:51:02 PM PST 24
Peak memory 248056 kb
Host smart-5c238f33-03bb-4db9-80ef-73e46163844e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41313
22110 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_sig_int_fail.4131322110
Directory /workspace/28.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/28.alert_handler_smoke.4175808409
Short name T718
Test name
Test status
Simulation time 771796649 ps
CPU time 51.01 seconds
Started Jan 24 01:54:03 PM PST 24
Finished Jan 24 01:54:57 PM PST 24
Peak memory 248084 kb
Host smart-53a191c5-ebcb-401e-b65b-78c0a78b5c0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41758
08409 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_smoke.4175808409
Directory /workspace/28.alert_handler_smoke/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all_with_rand_reset.167552186
Short name T35
Test name
Test status
Simulation time 207091341870 ps
CPU time 3709.35 seconds
Started Jan 24 01:44:12 PM PST 24
Finished Jan 24 02:46:18 PM PST 24
Peak memory 304952 kb
Host smart-28b2823c-b39c-4446-a465-2365eb686dfa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167552186 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 28.alert_handler_stress_all_with_rand_reset.167552186
Directory /workspace/28.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.alert_handler_entropy.2310872502
Short name T393
Test name
Test status
Simulation time 199739592553 ps
CPU time 2940.13 seconds
Started Jan 24 01:44:25 PM PST 24
Finished Jan 24 02:33:42 PM PST 24
Peak memory 288404 kb
Host smart-b42816aa-f987-4b40-b520-20d648f1567c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310872502 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_entropy.2310872502
Directory /workspace/29.alert_handler_entropy/latest

Test location /workspace/coverage/default/29.alert_handler_esc_alert_accum.234728278
Short name T672
Test name
Test status
Simulation time 2698456510 ps
CPU time 168.08 seconds
Started Jan 24 02:06:14 PM PST 24
Finished Jan 24 02:09:53 PM PST 24
Peak memory 248192 kb
Host smart-9ec22df6-a756-457b-843d-90c8d0969e56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23472
8278 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_alert_accum.234728278
Directory /workspace/29.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/29.alert_handler_esc_intr_timeout.2200348489
Short name T594
Test name
Test status
Simulation time 727232973 ps
CPU time 44.99 seconds
Started Jan 24 01:44:23 PM PST 24
Finished Jan 24 01:45:26 PM PST 24
Peak memory 250244 kb
Host smart-091ed1e8-a588-487d-9423-f6de4f52d453
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22003
48489 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_intr_timeout.2200348489
Directory /workspace/29.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_lpg.3118691073
Short name T134
Test name
Test status
Simulation time 11529829786 ps
CPU time 1097.3 seconds
Started Jan 24 01:44:24 PM PST 24
Finished Jan 24 02:02:59 PM PST 24
Peak memory 280940 kb
Host smart-2d6e8fe1-ce36-47d4-90f7-9a754486df59
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118691073 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg.3118691073
Directory /workspace/29.alert_handler_lpg/latest

Test location /workspace/coverage/default/29.alert_handler_lpg_stub_clk.3973107127
Short name T611
Test name
Test status
Simulation time 104919772048 ps
CPU time 3172.32 seconds
Started Jan 24 01:44:25 PM PST 24
Finished Jan 24 02:37:34 PM PST 24
Peak memory 288320 kb
Host smart-b096daad-ed63-4077-901a-a01305531ecb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973107127 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg_stub_clk.3973107127
Directory /workspace/29.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/29.alert_handler_ping_timeout.1380391951
Short name T306
Test name
Test status
Simulation time 20601457223 ps
CPU time 229.56 seconds
Started Jan 24 01:44:24 PM PST 24
Finished Jan 24 01:48:31 PM PST 24
Peak memory 251252 kb
Host smart-680dd466-f9ac-4d5d-b811-cbb0ebc2a309
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380391951 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_ping_timeout.1380391951
Directory /workspace/29.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_random_alerts.2090959367
Short name T243
Test name
Test status
Simulation time 3644218959 ps
CPU time 61.01 seconds
Started Jan 24 01:44:11 PM PST 24
Finished Jan 24 01:45:29 PM PST 24
Peak memory 248128 kb
Host smart-1b83b583-b395-426e-8e28-a414865a2e7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20909
59367 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_alerts.2090959367
Directory /workspace/29.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/29.alert_handler_random_classes.2799411010
Short name T587
Test name
Test status
Simulation time 319840736 ps
CPU time 30.65 seconds
Started Jan 24 01:44:13 PM PST 24
Finished Jan 24 01:45:01 PM PST 24
Peak memory 248016 kb
Host smart-bca2b047-54ab-46d3-abc3-8b599c000aee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27994
11010 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_classes.2799411010
Directory /workspace/29.alert_handler_random_classes/latest

Test location /workspace/coverage/default/29.alert_handler_sig_int_fail.1087736857
Short name T280
Test name
Test status
Simulation time 1273497378 ps
CPU time 37.88 seconds
Started Jan 24 01:44:26 PM PST 24
Finished Jan 24 01:45:21 PM PST 24
Peak memory 248032 kb
Host smart-75df98cd-c80b-4cf7-bbb6-011e563ba223
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10877
36857 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_sig_int_fail.1087736857
Directory /workspace/29.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/29.alert_handler_smoke.3156215578
Short name T417
Test name
Test status
Simulation time 364250754 ps
CPU time 33.42 seconds
Started Jan 24 01:50:35 PM PST 24
Finished Jan 24 01:51:15 PM PST 24
Peak memory 248088 kb
Host smart-e896a0a2-5540-43f8-860a-81027d51ee25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31562
15578 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_smoke.3156215578
Directory /workspace/29.alert_handler_smoke/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all.43840406
Short name T47
Test name
Test status
Simulation time 214493186 ps
CPU time 12.83 seconds
Started Jan 24 01:52:03 PM PST 24
Finished Jan 24 01:52:23 PM PST 24
Peak memory 248416 kb
Host smart-5c1ce286-b4af-4db3-b532-3d92c00e612b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43840406 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_hand
ler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_hand
ler_stress_all.43840406
Directory /workspace/29.alert_handler_stress_all/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all_with_rand_reset.140825084
Short name T400
Test name
Test status
Simulation time 144810243909 ps
CPU time 2601.01 seconds
Started Jan 24 01:44:25 PM PST 24
Finished Jan 24 02:28:03 PM PST 24
Peak memory 298236 kb
Host smart-7272e4f4-faf4-46b9-86ab-b1c0070d7e6a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140825084 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 29.alert_handler_stress_all_with_rand_reset.140825084
Directory /workspace/29.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.alert_handler_alert_accum_saturation.1637286433
Short name T227
Test name
Test status
Simulation time 40374225 ps
CPU time 3.57 seconds
Started Jan 24 01:39:22 PM PST 24
Finished Jan 24 01:39:31 PM PST 24
Peak memory 248256 kb
Host smart-d0e45484-b489-463e-9009-98c1088ed4e3
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1637286433 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_alert_accum_saturation.1637286433
Directory /workspace/3.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/3.alert_handler_entropy.460129506
Short name T108
Test name
Test status
Simulation time 27685229540 ps
CPU time 1286.18 seconds
Started Jan 24 01:39:26 PM PST 24
Finished Jan 24 02:01:28 PM PST 24
Peak memory 288244 kb
Host smart-b78e9cf3-5528-41a6-8937-688a69ae0254
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460129506 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy.460129506
Directory /workspace/3.alert_handler_entropy/latest

Test location /workspace/coverage/default/3.alert_handler_entropy_stress.220524032
Short name T374
Test name
Test status
Simulation time 177298500 ps
CPU time 10.61 seconds
Started Jan 24 01:39:22 PM PST 24
Finished Jan 24 01:39:38 PM PST 24
Peak memory 247868 kb
Host smart-54ea3788-9e31-41b6-a09f-dad25bb62874
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=220524032 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy_stress.220524032
Directory /workspace/3.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/3.alert_handler_esc_alert_accum.2111787960
Short name T654
Test name
Test status
Simulation time 3243477179 ps
CPU time 103.82 seconds
Started Jan 24 01:39:27 PM PST 24
Finished Jan 24 01:41:48 PM PST 24
Peak memory 248128 kb
Host smart-b8606603-8c0d-4ff1-8701-2f768473c330
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21117
87960 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_alert_accum.2111787960
Directory /workspace/3.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/3.alert_handler_esc_intr_timeout.1796990371
Short name T637
Test name
Test status
Simulation time 1312015615 ps
CPU time 38.77 seconds
Started Jan 24 01:39:20 PM PST 24
Finished Jan 24 01:40:03 PM PST 24
Peak memory 247300 kb
Host smart-fdbe0942-e409-4cb5-bf75-08695512bd8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17969
90371 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_intr_timeout.1796990371
Directory /workspace/3.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_lpg.2702309232
Short name T688
Test name
Test status
Simulation time 195882064533 ps
CPU time 3051.34 seconds
Started Jan 24 01:39:14 PM PST 24
Finished Jan 24 02:30:07 PM PST 24
Peak memory 280972 kb
Host smart-6e15c081-9ace-4995-95bd-3633eb37390a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702309232 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg.2702309232
Directory /workspace/3.alert_handler_lpg/latest

Test location /workspace/coverage/default/3.alert_handler_lpg_stub_clk.2029853959
Short name T687
Test name
Test status
Simulation time 43922273138 ps
CPU time 865.19 seconds
Started Jan 24 01:39:22 PM PST 24
Finished Jan 24 01:53:52 PM PST 24
Peak memory 271040 kb
Host smart-9e38656e-e9d7-45e8-bdf1-52fa812bbcf3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029853959 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg_stub_clk.2029853959
Directory /workspace/3.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/3.alert_handler_ping_timeout.3338305782
Short name T707
Test name
Test status
Simulation time 5805505459 ps
CPU time 248.69 seconds
Started Jan 24 01:39:20 PM PST 24
Finished Jan 24 01:43:33 PM PST 24
Peak memory 250168 kb
Host smart-38234f5b-4300-481d-8cb0-f7c80d722894
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338305782 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_ping_timeout.3338305782
Directory /workspace/3.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_random_alerts.54688855
Short name T452
Test name
Test status
Simulation time 2328112164 ps
CPU time 33.31 seconds
Started Jan 24 01:39:19 PM PST 24
Finished Jan 24 01:39:55 PM PST 24
Peak memory 252500 kb
Host smart-9f7b38a2-6676-4780-a38e-6e6200677e3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54688
855 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_alerts.54688855
Directory /workspace/3.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/3.alert_handler_random_classes.2075305752
Short name T576
Test name
Test status
Simulation time 949470687 ps
CPU time 56.95 seconds
Started Jan 24 01:39:20 PM PST 24
Finished Jan 24 01:40:20 PM PST 24
Peak memory 254544 kb
Host smart-d1fb7688-162b-4475-8a03-7fc5b883c9c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20753
05752 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_classes.2075305752
Directory /workspace/3.alert_handler_random_classes/latest

Test location /workspace/coverage/default/3.alert_handler_sig_int_fail.3479396786
Short name T580
Test name
Test status
Simulation time 297678862 ps
CPU time 33.55 seconds
Started Jan 24 01:39:20 PM PST 24
Finished Jan 24 01:39:58 PM PST 24
Peak memory 246328 kb
Host smart-e6d9ad9a-3abc-448e-a534-8cd3678f8e0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34793
96786 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sig_int_fail.3479396786
Directory /workspace/3.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/3.alert_handler_smoke.1042078565
Short name T603
Test name
Test status
Simulation time 723617447 ps
CPU time 42.96 seconds
Started Jan 24 01:39:11 PM PST 24
Finished Jan 24 01:39:56 PM PST 24
Peak memory 256244 kb
Host smart-6332eb49-8c20-4232-887f-71ec65261625
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10420
78565 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_smoke.1042078565
Directory /workspace/3.alert_handler_smoke/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all_with_rand_reset.499574111
Short name T691
Test name
Test status
Simulation time 14448557902 ps
CPU time 1496.59 seconds
Started Jan 24 01:39:20 PM PST 24
Finished Jan 24 02:04:19 PM PST 24
Peak memory 281088 kb
Host smart-e7813a8a-fb6f-45fd-80e0-316bf6b522eb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499574111 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 3.alert_handler_stress_all_with_rand_reset.499574111
Directory /workspace/3.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.alert_handler_entropy.1502010896
Short name T109
Test name
Test status
Simulation time 28796436014 ps
CPU time 1648.41 seconds
Started Jan 24 01:44:38 PM PST 24
Finished Jan 24 02:12:17 PM PST 24
Peak memory 272400 kb
Host smart-848db6ee-c4d3-4b6f-84a6-c0eaf184370d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502010896 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_entropy.1502010896
Directory /workspace/30.alert_handler_entropy/latest

Test location /workspace/coverage/default/30.alert_handler_esc_alert_accum.3766486383
Short name T267
Test name
Test status
Simulation time 3075391292 ps
CPU time 157.23 seconds
Started Jan 24 01:44:40 PM PST 24
Finished Jan 24 01:47:26 PM PST 24
Peak memory 247904 kb
Host smart-062b4404-ee50-4c66-a99d-720f01884092
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37664
86383 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_alert_accum.3766486383
Directory /workspace/30.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/30.alert_handler_esc_intr_timeout.2909044261
Short name T408
Test name
Test status
Simulation time 476079219 ps
CPU time 31.73 seconds
Started Jan 24 01:44:42 PM PST 24
Finished Jan 24 01:45:21 PM PST 24
Peak memory 250060 kb
Host smart-c10510a3-8338-4d5f-9381-50f4a984eac1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29090
44261 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_intr_timeout.2909044261
Directory /workspace/30.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_lpg.1409283994
Short name T329
Test name
Test status
Simulation time 71656969059 ps
CPU time 2079.43 seconds
Started Jan 24 01:44:35 PM PST 24
Finished Jan 24 02:19:26 PM PST 24
Peak memory 272772 kb
Host smart-12e758d2-3c82-4b2c-957d-50e3fc8b7b4d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409283994 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg.1409283994
Directory /workspace/30.alert_handler_lpg/latest

Test location /workspace/coverage/default/30.alert_handler_lpg_stub_clk.3764678298
Short name T6
Test name
Test status
Simulation time 80968335102 ps
CPU time 2499.98 seconds
Started Jan 24 01:44:40 PM PST 24
Finished Jan 24 02:26:29 PM PST 24
Peak memory 288148 kb
Host smart-ab859870-8b5a-4d52-aec0-19ab677156bf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764678298 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg_stub_clk.3764678298
Directory /workspace/30.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/30.alert_handler_random_alerts.1326753982
Short name T394
Test name
Test status
Simulation time 203084559 ps
CPU time 14.18 seconds
Started Jan 24 01:44:25 PM PST 24
Finished Jan 24 01:44:56 PM PST 24
Peak memory 256200 kb
Host smart-1bc79c8f-43c3-4716-bf94-904b7002903b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13267
53982 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_alerts.1326753982
Directory /workspace/30.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/30.alert_handler_random_classes.870971182
Short name T410
Test name
Test status
Simulation time 1706010689 ps
CPU time 40.41 seconds
Started Jan 24 02:16:22 PM PST 24
Finished Jan 24 02:17:36 PM PST 24
Peak memory 248028 kb
Host smart-b168984a-b511-4729-9bf1-90127291b7a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87097
1182 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_classes.870971182
Directory /workspace/30.alert_handler_random_classes/latest

Test location /workspace/coverage/default/30.alert_handler_sig_int_fail.3965570078
Short name T574
Test name
Test status
Simulation time 1006741710 ps
CPU time 67.29 seconds
Started Jan 24 01:44:39 PM PST 24
Finished Jan 24 01:45:56 PM PST 24
Peak memory 248344 kb
Host smart-0440e042-ce3c-4f30-bf03-61dd9d394eca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39655
70078 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_sig_int_fail.3965570078
Directory /workspace/30.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/30.alert_handler_smoke.3094529268
Short name T391
Test name
Test status
Simulation time 383486054 ps
CPU time 20.2 seconds
Started Jan 24 01:44:26 PM PST 24
Finished Jan 24 01:45:02 PM PST 24
Peak memory 256228 kb
Host smart-ce14c4ba-8031-4932-984a-242b6b3a93f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30945
29268 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_smoke.3094529268
Directory /workspace/30.alert_handler_smoke/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all.3894225674
Short name T293
Test name
Test status
Simulation time 202595011 ps
CPU time 23.94 seconds
Started Jan 24 01:44:41 PM PST 24
Finished Jan 24 01:45:13 PM PST 24
Peak memory 248084 kb
Host smart-10ed4a65-6cce-4e9e-9794-b01afa0a1318
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894225674 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_ha
ndler_stress_all.3894225674
Directory /workspace/30.alert_handler_stress_all/latest

Test location /workspace/coverage/default/31.alert_handler_entropy.3127861075
Short name T104
Test name
Test status
Simulation time 49299893819 ps
CPU time 1776.34 seconds
Started Jan 24 01:44:49 PM PST 24
Finished Jan 24 02:14:31 PM PST 24
Peak memory 282548 kb
Host smart-583e642b-a74a-4092-919a-542cb3b4fdd1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127861075 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_entropy.3127861075
Directory /workspace/31.alert_handler_entropy/latest

Test location /workspace/coverage/default/31.alert_handler_esc_alert_accum.2004301201
Short name T553
Test name
Test status
Simulation time 2929414972 ps
CPU time 130.41 seconds
Started Jan 24 01:44:50 PM PST 24
Finished Jan 24 01:47:05 PM PST 24
Peak memory 250476 kb
Host smart-7e523b08-22f3-4070-ae2d-6f7716661474
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20043
01201 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_alert_accum.2004301201
Directory /workspace/31.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/31.alert_handler_esc_intr_timeout.1180468685
Short name T677
Test name
Test status
Simulation time 277004122 ps
CPU time 17.8 seconds
Started Jan 24 01:44:41 PM PST 24
Finished Jan 24 01:45:07 PM PST 24
Peak memory 254368 kb
Host smart-15b15cc4-842f-40af-895a-534d37c608cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11804
68685 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_intr_timeout.1180468685
Directory /workspace/31.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_lpg.3559586312
Short name T666
Test name
Test status
Simulation time 15751035847 ps
CPU time 1548.12 seconds
Started Jan 24 01:44:51 PM PST 24
Finished Jan 24 02:10:43 PM PST 24
Peak memory 288380 kb
Host smart-34c7464b-30c8-45dc-adca-ac363e5a3747
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559586312 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg.3559586312
Directory /workspace/31.alert_handler_lpg/latest

Test location /workspace/coverage/default/31.alert_handler_lpg_stub_clk.3825083466
Short name T549
Test name
Test status
Simulation time 9956305990 ps
CPU time 1140.3 seconds
Started Jan 24 01:44:52 PM PST 24
Finished Jan 24 02:03:58 PM PST 24
Peak memory 288504 kb
Host smart-c572c34b-38ed-4532-ad65-d1a2bfa0379e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825083466 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg_stub_clk.3825083466
Directory /workspace/31.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/31.alert_handler_random_alerts.3918327357
Short name T491
Test name
Test status
Simulation time 1737200484 ps
CPU time 31.58 seconds
Started Jan 24 01:44:36 PM PST 24
Finished Jan 24 01:45:18 PM PST 24
Peak memory 248004 kb
Host smart-295a6b07-ecee-43ea-b32b-4baffcf32c7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39183
27357 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_alerts.3918327357
Directory /workspace/31.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/31.alert_handler_random_classes.4213441622
Short name T360
Test name
Test status
Simulation time 349035580 ps
CPU time 11.74 seconds
Started Jan 24 01:44:38 PM PST 24
Finished Jan 24 01:45:00 PM PST 24
Peak memory 251780 kb
Host smart-72834d38-9713-470d-a6d9-a69ec1367b89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42134
41622 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_classes.4213441622
Directory /workspace/31.alert_handler_random_classes/latest

Test location /workspace/coverage/default/31.alert_handler_smoke.643694518
Short name T131
Test name
Test status
Simulation time 459515210 ps
CPU time 14.5 seconds
Started Jan 24 01:44:36 PM PST 24
Finished Jan 24 01:45:01 PM PST 24
Peak memory 247980 kb
Host smart-aeb0a504-390c-4064-87be-38fe2d411fdc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64369
4518 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_smoke.643694518
Directory /workspace/31.alert_handler_smoke/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all.1333863751
Short name T660
Test name
Test status
Simulation time 119830719883 ps
CPU time 1925.59 seconds
Started Jan 24 01:44:56 PM PST 24
Finished Jan 24 02:17:17 PM PST 24
Peak memory 285080 kb
Host smart-5f79e15b-f390-4887-9f31-af779766bcff
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333863751 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_ha
ndler_stress_all.1333863751
Directory /workspace/31.alert_handler_stress_all/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all_with_rand_reset.2354221135
Short name T406
Test name
Test status
Simulation time 92966853690 ps
CPU time 2256.12 seconds
Started Jan 24 01:44:54 PM PST 24
Finished Jan 24 02:22:42 PM PST 24
Peak memory 314124 kb
Host smart-5a28eb73-2026-4ce6-a408-173b55d22397
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354221135 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 31.alert_handler_stress_all_with_rand_reset.2354221135
Directory /workspace/31.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.alert_handler_entropy.2549765782
Short name T624
Test name
Test status
Simulation time 17644820765 ps
CPU time 1457.34 seconds
Started Jan 24 01:45:03 PM PST 24
Finished Jan 24 02:09:34 PM PST 24
Peak memory 288480 kb
Host smart-5dbf6b94-66b5-407b-96ab-729bbfbcb814
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2549765782 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_entropy.2549765782
Directory /workspace/32.alert_handler_entropy/latest

Test location /workspace/coverage/default/32.alert_handler_esc_alert_accum.110369877
Short name T53
Test name
Test status
Simulation time 12561865080 ps
CPU time 178.43 seconds
Started Jan 24 01:44:52 PM PST 24
Finished Jan 24 01:47:55 PM PST 24
Peak memory 248376 kb
Host smart-b79c03b4-7005-4602-9179-1b579c3436d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11036
9877 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_alert_accum.110369877
Directory /workspace/32.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/32.alert_handler_esc_intr_timeout.2202750314
Short name T96
Test name
Test status
Simulation time 535212486 ps
CPU time 7.99 seconds
Started Jan 24 01:44:56 PM PST 24
Finished Jan 24 01:45:19 PM PST 24
Peak memory 250204 kb
Host smart-c2bb2862-60ae-4240-9ed1-e46c3bf4c8f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22027
50314 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_intr_timeout.2202750314
Directory /workspace/32.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_lpg.718842349
Short name T476
Test name
Test status
Simulation time 89394081985 ps
CPU time 2605.25 seconds
Started Jan 24 02:09:08 PM PST 24
Finished Jan 24 02:52:43 PM PST 24
Peak memory 280936 kb
Host smart-0ab51012-e7a8-4f7d-a99c-2b4c71a2acdb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718842349 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg.718842349
Directory /workspace/32.alert_handler_lpg/latest

Test location /workspace/coverage/default/32.alert_handler_lpg_stub_clk.1855488757
Short name T655
Test name
Test status
Simulation time 39032824029 ps
CPU time 982.35 seconds
Started Jan 24 02:31:59 PM PST 24
Finished Jan 24 02:48:56 PM PST 24
Peak memory 286656 kb
Host smart-4e72a8de-545d-44ff-b8e3-96af75d8ec93
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855488757 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg_stub_clk.1855488757
Directory /workspace/32.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/32.alert_handler_random_alerts.1812718854
Short name T463
Test name
Test status
Simulation time 227506001 ps
CPU time 19.65 seconds
Started Jan 24 01:44:52 PM PST 24
Finished Jan 24 01:45:16 PM PST 24
Peak memory 248048 kb
Host smart-d5795817-657a-4644-8589-a5e728ab193a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18127
18854 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_alerts.1812718854
Directory /workspace/32.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/32.alert_handler_random_classes.4278782744
Short name T664
Test name
Test status
Simulation time 618896998 ps
CPU time 41.84 seconds
Started Jan 24 01:44:56 PM PST 24
Finished Jan 24 01:45:53 PM PST 24
Peak memory 248316 kb
Host smart-a6c1c7b7-838a-4263-93db-a35da2e163f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42787
82744 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_classes.4278782744
Directory /workspace/32.alert_handler_random_classes/latest

Test location /workspace/coverage/default/32.alert_handler_sig_int_fail.1381646007
Short name T291
Test name
Test status
Simulation time 1094688221 ps
CPU time 29.74 seconds
Started Jan 24 02:49:39 PM PST 24
Finished Jan 24 02:50:26 PM PST 24
Peak memory 248128 kb
Host smart-8e4c014e-8b4c-42a9-b9f8-4bdd1b26bab5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13816
46007 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_sig_int_fail.1381646007
Directory /workspace/32.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/32.alert_handler_smoke.3756286111
Short name T659
Test name
Test status
Simulation time 132550200 ps
CPU time 15.39 seconds
Started Jan 24 01:44:50 PM PST 24
Finished Jan 24 01:45:10 PM PST 24
Peak memory 248072 kb
Host smart-ac304a8e-6d0f-4bf0-81d9-351b555a8496
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37562
86111 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_smoke.3756286111
Directory /workspace/32.alert_handler_smoke/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all.2182105665
Short name T474
Test name
Test status
Simulation time 147709051 ps
CPU time 16.48 seconds
Started Jan 24 01:45:13 PM PST 24
Finished Jan 24 01:45:39 PM PST 24
Peak memory 248056 kb
Host smart-7b13ee6d-fe44-4ab1-8b19-a653c0bd605f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182105665 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_ha
ndler_stress_all.2182105665
Directory /workspace/32.alert_handler_stress_all/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all_with_rand_reset.1806418265
Short name T65
Test name
Test status
Simulation time 18536643560 ps
CPU time 1325.94 seconds
Started Jan 24 01:45:14 PM PST 24
Finished Jan 24 02:07:29 PM PST 24
Peak memory 269076 kb
Host smart-ad2f970f-946a-4662-a0b7-c306c9c97dd9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806418265 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 32.alert_handler_stress_all_with_rand_reset.1806418265
Directory /workspace/32.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.alert_handler_entropy.2938150726
Short name T589
Test name
Test status
Simulation time 51836585592 ps
CPU time 849.36 seconds
Started Jan 24 01:45:37 PM PST 24
Finished Jan 24 01:59:50 PM PST 24
Peak memory 268096 kb
Host smart-edc64c89-e523-4eaa-90bb-f148dd12b6ed
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938150726 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_entropy.2938150726
Directory /workspace/33.alert_handler_entropy/latest

Test location /workspace/coverage/default/33.alert_handler_esc_alert_accum.1172325489
Short name T663
Test name
Test status
Simulation time 77692369 ps
CPU time 7.76 seconds
Started Jan 24 01:45:16 PM PST 24
Finished Jan 24 01:45:32 PM PST 24
Peak memory 248048 kb
Host smart-fe0769ef-95ec-4be5-8dc5-8177d58525dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11723
25489 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_alert_accum.1172325489
Directory /workspace/33.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/33.alert_handler_esc_intr_timeout.1875173671
Short name T641
Test name
Test status
Simulation time 17618096 ps
CPU time 2.88 seconds
Started Jan 24 01:45:12 PM PST 24
Finished Jan 24 01:45:25 PM PST 24
Peak memory 237752 kb
Host smart-12fd606a-505f-4fbd-9824-77da803b5e15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18751
73671 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_intr_timeout.1875173671
Directory /workspace/33.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_lpg.3415077352
Short name T712
Test name
Test status
Simulation time 102517048884 ps
CPU time 1556.14 seconds
Started Jan 24 01:45:28 PM PST 24
Finished Jan 24 02:11:27 PM PST 24
Peak memory 264388 kb
Host smart-94851b33-ce45-4f80-bb01-893420272977
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415077352 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg.3415077352
Directory /workspace/33.alert_handler_lpg/latest

Test location /workspace/coverage/default/33.alert_handler_lpg_stub_clk.451110282
Short name T366
Test name
Test status
Simulation time 51912260979 ps
CPU time 1449.4 seconds
Started Jan 24 01:45:26 PM PST 24
Finished Jan 24 02:09:39 PM PST 24
Peak memory 264496 kb
Host smart-af047064-d25b-460f-bd93-ecd2cf4dc1c8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451110282 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg_stub_clk.451110282
Directory /workspace/33.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/33.alert_handler_ping_timeout.3472571728
Short name T643
Test name
Test status
Simulation time 1922202318 ps
CPU time 85.24 seconds
Started Jan 24 01:45:37 PM PST 24
Finished Jan 24 01:47:06 PM PST 24
Peak memory 246496 kb
Host smart-18853078-14c4-4b3b-9480-beaaf1678a71
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472571728 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_ping_timeout.3472571728
Directory /workspace/33.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_random_alerts.88646435
Short name T499
Test name
Test status
Simulation time 3607344089 ps
CPU time 56.5 seconds
Started Jan 24 01:45:14 PM PST 24
Finished Jan 24 01:46:20 PM PST 24
Peak memory 248168 kb
Host smart-636da56d-f98f-4c19-b604-6e4415296407
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88646
435 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_alerts.88646435
Directory /workspace/33.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/33.alert_handler_random_classes.3796068320
Short name T92
Test name
Test status
Simulation time 96373622 ps
CPU time 10.72 seconds
Started Jan 24 01:45:13 PM PST 24
Finished Jan 24 01:45:33 PM PST 24
Peak memory 250684 kb
Host smart-3b8a8794-2873-496c-ad8a-378edf3f356d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37960
68320 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_classes.3796068320
Directory /workspace/33.alert_handler_random_classes/latest

Test location /workspace/coverage/default/33.alert_handler_sig_int_fail.846201417
Short name T669
Test name
Test status
Simulation time 721975011 ps
CPU time 45.49 seconds
Started Jan 24 01:45:28 PM PST 24
Finished Jan 24 01:46:17 PM PST 24
Peak memory 254352 kb
Host smart-14222c27-1f1f-47e7-bd5c-cbfcf9dfb0a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84620
1417 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_sig_int_fail.846201417
Directory /workspace/33.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/33.alert_handler_smoke.478619768
Short name T420
Test name
Test status
Simulation time 436374782 ps
CPU time 37.82 seconds
Started Jan 24 01:45:18 PM PST 24
Finished Jan 24 01:46:02 PM PST 24
Peak memory 248016 kb
Host smart-01629c3a-7dba-4ce8-bd58-5f328854c791
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47861
9768 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_smoke.478619768
Directory /workspace/33.alert_handler_smoke/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all.337491929
Short name T242
Test name
Test status
Simulation time 3348456494 ps
CPU time 78.2 seconds
Started Jan 24 01:45:32 PM PST 24
Finished Jan 24 01:46:53 PM PST 24
Peak memory 256372 kb
Host smart-0fad6e95-fadb-43fd-9c09-ae88033b7832
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337491929 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_han
dler_stress_all.337491929
Directory /workspace/33.alert_handler_stress_all/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all_with_rand_reset.1536286504
Short name T207
Test name
Test status
Simulation time 48759904048 ps
CPU time 3007.88 seconds
Started Jan 24 01:45:31 PM PST 24
Finished Jan 24 02:35:42 PM PST 24
Peak memory 289248 kb
Host smart-5ef99d62-9a5d-4c24-8fc0-231a5e9351ad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536286504 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 33.alert_handler_stress_all_with_rand_reset.1536286504
Directory /workspace/33.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.alert_handler_entropy.3262441428
Short name T216
Test name
Test status
Simulation time 80443926080 ps
CPU time 1474.67 seconds
Started Jan 24 02:06:10 PM PST 24
Finished Jan 24 02:31:36 PM PST 24
Peak memory 272196 kb
Host smart-00d9c706-4615-4509-b9e4-e8bf249a3e94
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262441428 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_entropy.3262441428
Directory /workspace/34.alert_handler_entropy/latest

Test location /workspace/coverage/default/34.alert_handler_esc_alert_accum.3634412166
Short name T388
Test name
Test status
Simulation time 1610023738 ps
CPU time 86.74 seconds
Started Jan 24 01:45:44 PM PST 24
Finished Jan 24 01:47:23 PM PST 24
Peak memory 250380 kb
Host smart-093e3a94-2df4-4d1e-9604-1e3214e8c67c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36344
12166 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_alert_accum.3634412166
Directory /workspace/34.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/34.alert_handler_esc_intr_timeout.1551879402
Short name T547
Test name
Test status
Simulation time 3616069520 ps
CPU time 31.89 seconds
Started Jan 24 01:45:46 PM PST 24
Finished Jan 24 01:46:33 PM PST 24
Peak memory 248180 kb
Host smart-39602f98-11c9-4452-b7bc-3d89eec1a8b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15518
79402 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_intr_timeout.1551879402
Directory /workspace/34.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_lpg.1489847944
Short name T631
Test name
Test status
Simulation time 44172264351 ps
CPU time 1046.14 seconds
Started Jan 24 02:48:08 PM PST 24
Finished Jan 24 03:06:03 PM PST 24
Peak memory 282292 kb
Host smart-cfc3d2e5-ddaa-434e-815a-2689441406ea
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489847944 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg.1489847944
Directory /workspace/34.alert_handler_lpg/latest

Test location /workspace/coverage/default/34.alert_handler_lpg_stub_clk.227886451
Short name T436
Test name
Test status
Simulation time 23184807592 ps
CPU time 704.74 seconds
Started Jan 24 01:45:56 PM PST 24
Finished Jan 24 01:58:04 PM PST 24
Peak memory 264572 kb
Host smart-9498b4c7-6d5c-4f98-b4a6-04aa4759564b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227886451 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg_stub_clk.227886451
Directory /workspace/34.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/34.alert_handler_ping_timeout.740979460
Short name T709
Test name
Test status
Simulation time 21941824999 ps
CPU time 211.25 seconds
Started Jan 24 01:45:44 PM PST 24
Finished Jan 24 01:49:28 PM PST 24
Peak memory 248228 kb
Host smart-4c7d052d-e142-4d18-85ce-78b55de6c425
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740979460 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_ping_timeout.740979460
Directory /workspace/34.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_random_alerts.1802342638
Short name T268
Test name
Test status
Simulation time 496653536 ps
CPU time 12.52 seconds
Started Jan 24 01:45:44 PM PST 24
Finished Jan 24 01:46:08 PM PST 24
Peak memory 247972 kb
Host smart-88e88daf-6ecf-4e6b-9ada-1a76d805e4ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18023
42638 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_alerts.1802342638
Directory /workspace/34.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/34.alert_handler_random_classes.2872536810
Short name T423
Test name
Test status
Simulation time 259446821 ps
CPU time 20.29 seconds
Started Jan 24 01:45:44 PM PST 24
Finished Jan 24 01:46:16 PM PST 24
Peak memory 253072 kb
Host smart-5d4ced10-af7c-4d79-8729-dcda695b90b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28725
36810 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_classes.2872536810
Directory /workspace/34.alert_handler_random_classes/latest

Test location /workspace/coverage/default/34.alert_handler_sig_int_fail.120527592
Short name T272
Test name
Test status
Simulation time 224395687 ps
CPU time 27.38 seconds
Started Jan 24 01:45:46 PM PST 24
Finished Jan 24 01:46:29 PM PST 24
Peak memory 248072 kb
Host smart-4631b3b9-fc85-4b37-a29b-5547ff7ea4de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12052
7592 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_sig_int_fail.120527592
Directory /workspace/34.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/34.alert_handler_smoke.794604412
Short name T478
Test name
Test status
Simulation time 1487075343 ps
CPU time 47.67 seconds
Started Jan 24 01:45:33 PM PST 24
Finished Jan 24 01:46:24 PM PST 24
Peak memory 248080 kb
Host smart-792a21c0-28c9-4eaa-bea6-e69d84c0ebf3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79460
4412 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_smoke.794604412
Directory /workspace/34.alert_handler_smoke/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all.3799380788
Short name T235
Test name
Test status
Simulation time 24144488447 ps
CPU time 1152.82 seconds
Started Jan 24 01:45:55 PM PST 24
Finished Jan 24 02:05:31 PM PST 24
Peak memory 288944 kb
Host smart-50738812-3a73-48fa-be67-1050567025dc
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799380788 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_ha
ndler_stress_all.3799380788
Directory /workspace/34.alert_handler_stress_all/latest

Test location /workspace/coverage/default/35.alert_handler_entropy.2635413417
Short name T622
Test name
Test status
Simulation time 306196915284 ps
CPU time 3034.11 seconds
Started Jan 24 01:46:03 PM PST 24
Finished Jan 24 02:37:03 PM PST 24
Peak memory 288080 kb
Host smart-6d5f3b62-ee0f-41bb-80f8-9e8a27107e33
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2635413417 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_entropy.2635413417
Directory /workspace/35.alert_handler_entropy/latest

Test location /workspace/coverage/default/35.alert_handler_esc_alert_accum.725932036
Short name T447
Test name
Test status
Simulation time 680874851 ps
CPU time 46.79 seconds
Started Jan 24 01:46:01 PM PST 24
Finished Jan 24 01:47:13 PM PST 24
Peak memory 247968 kb
Host smart-044e0da9-cb62-4283-ad57-eab9b573f9e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72593
2036 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_alert_accum.725932036
Directory /workspace/35.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/35.alert_handler_esc_intr_timeout.316115649
Short name T494
Test name
Test status
Simulation time 653532141 ps
CPU time 29.7 seconds
Started Jan 24 01:46:04 PM PST 24
Finished Jan 24 01:46:58 PM PST 24
Peak memory 256136 kb
Host smart-26d5dae2-7db3-4b06-acaa-b5cef2e77703
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31611
5649 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_intr_timeout.316115649
Directory /workspace/35.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_lpg.2907117559
Short name T335
Test name
Test status
Simulation time 31798562617 ps
CPU time 2031.8 seconds
Started Jan 24 01:46:01 PM PST 24
Finished Jan 24 02:20:18 PM PST 24
Peak memory 272064 kb
Host smart-cb3daaaa-6415-415a-9223-2b8b5e30fe1b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2907117559 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg.2907117559
Directory /workspace/35.alert_handler_lpg/latest

Test location /workspace/coverage/default/35.alert_handler_lpg_stub_clk.2922126837
Short name T591
Test name
Test status
Simulation time 184021786437 ps
CPU time 1523.65 seconds
Started Jan 24 01:46:14 PM PST 24
Finished Jan 24 02:12:00 PM PST 24
Peak memory 271416 kb
Host smart-086ecd15-c1df-49a9-85e9-937879302867
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922126837 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg_stub_clk.2922126837
Directory /workspace/35.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/35.alert_handler_ping_timeout.134445132
Short name T301
Test name
Test status
Simulation time 12279211019 ps
CPU time 503.97 seconds
Started Jan 24 01:46:01 PM PST 24
Finished Jan 24 01:54:51 PM PST 24
Peak memory 246524 kb
Host smart-901727d3-6fad-41b7-a106-a618b5c08d28
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134445132 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_ping_timeout.134445132
Directory /workspace/35.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_random_alerts.837953270
Short name T256
Test name
Test status
Simulation time 447742331 ps
CPU time 12.55 seconds
Started Jan 24 01:45:53 PM PST 24
Finished Jan 24 01:46:27 PM PST 24
Peak memory 250160 kb
Host smart-4d5052a9-b0ac-4850-9e46-be609a5a8f5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83795
3270 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_alerts.837953270
Directory /workspace/35.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/35.alert_handler_random_classes.2230204413
Short name T456
Test name
Test status
Simulation time 60239309 ps
CPU time 3.84 seconds
Started Jan 24 01:45:54 PM PST 24
Finished Jan 24 01:46:20 PM PST 24
Peak memory 237700 kb
Host smart-d4982d65-f43d-4192-9f5b-53f3fa798793
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22302
04413 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_classes.2230204413
Directory /workspace/35.alert_handler_random_classes/latest

Test location /workspace/coverage/default/35.alert_handler_sig_int_fail.3969908150
Short name T467
Test name
Test status
Simulation time 488652116 ps
CPU time 11.37 seconds
Started Jan 24 02:04:26 PM PST 24
Finished Jan 24 02:05:35 PM PST 24
Peak memory 245940 kb
Host smart-a693f4a5-59c8-40c5-aa20-7fc6ad52150c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39699
08150 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_sig_int_fail.3969908150
Directory /workspace/35.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/35.alert_handler_smoke.4090331855
Short name T627
Test name
Test status
Simulation time 274715289 ps
CPU time 22.41 seconds
Started Jan 24 01:45:52 PM PST 24
Finished Jan 24 01:46:35 PM PST 24
Peak memory 250040 kb
Host smart-8e65f70c-3f0e-46cc-993b-6ae5fab2f9a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40903
31855 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_smoke.4090331855
Directory /workspace/35.alert_handler_smoke/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all.2776112129
Short name T523
Test name
Test status
Simulation time 7085971165 ps
CPU time 34.7 seconds
Started Jan 24 02:31:26 PM PST 24
Finished Jan 24 02:32:08 PM PST 24
Peak memory 248352 kb
Host smart-f0399b3f-b7fd-4d54-854d-cdd4d6ac0385
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776112129 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_ha
ndler_stress_all.2776112129
Directory /workspace/35.alert_handler_stress_all/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all_with_rand_reset.1684681998
Short name T126
Test name
Test status
Simulation time 329502156180 ps
CPU time 4371.54 seconds
Started Jan 24 01:46:16 PM PST 24
Finished Jan 24 02:59:29 PM PST 24
Peak memory 337740 kb
Host smart-80525113-9ac9-4474-8b50-f9152092e3c4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684681998 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 35.alert_handler_stress_all_with_rand_reset.1684681998
Directory /workspace/35.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.alert_handler_entropy.2450931149
Short name T678
Test name
Test status
Simulation time 99867910810 ps
CPU time 1642.86 seconds
Started Jan 24 02:24:16 PM PST 24
Finished Jan 24 02:51:52 PM PST 24
Peak memory 272444 kb
Host smart-08a2cec9-3ad6-489e-b340-77b016d1c618
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450931149 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_entropy.2450931149
Directory /workspace/36.alert_handler_entropy/latest

Test location /workspace/coverage/default/36.alert_handler_esc_alert_accum.2830511664
Short name T543
Test name
Test status
Simulation time 2487508745 ps
CPU time 151.5 seconds
Started Jan 24 01:46:15 PM PST 24
Finished Jan 24 01:49:08 PM PST 24
Peak memory 249188 kb
Host smart-83ba4860-9fbc-4a08-b036-c8b207acb416
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28305
11664 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_alert_accum.2830511664
Directory /workspace/36.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/36.alert_handler_esc_intr_timeout.705938017
Short name T371
Test name
Test status
Simulation time 151836977 ps
CPU time 12.06 seconds
Started Jan 24 01:46:16 PM PST 24
Finished Jan 24 01:46:49 PM PST 24
Peak memory 251436 kb
Host smart-6c8f8ef5-292c-4c63-8ef2-c34f699138a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70593
8017 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_intr_timeout.705938017
Directory /workspace/36.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_lpg.276340485
Short name T312
Test name
Test status
Simulation time 19311004717 ps
CPU time 1386.25 seconds
Started Jan 24 01:52:20 PM PST 24
Finished Jan 24 02:15:28 PM PST 24
Peak memory 272164 kb
Host smart-8a358cfa-a3ab-48ca-a3a3-685c4a63e1d8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276340485 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg.276340485
Directory /workspace/36.alert_handler_lpg/latest

Test location /workspace/coverage/default/36.alert_handler_lpg_stub_clk.3601431962
Short name T693
Test name
Test status
Simulation time 105656065927 ps
CPU time 2239.47 seconds
Started Jan 24 01:46:22 PM PST 24
Finished Jan 24 02:23:59 PM PST 24
Peak memory 286404 kb
Host smart-417b574c-fac4-48e1-92c8-876a11b35b2b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601431962 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg_stub_clk.3601431962
Directory /workspace/36.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/36.alert_handler_ping_timeout.3894893906
Short name T552
Test name
Test status
Simulation time 40820163320 ps
CPU time 490.15 seconds
Started Jan 24 02:19:33 PM PST 24
Finished Jan 24 02:27:49 PM PST 24
Peak memory 250260 kb
Host smart-623268d8-f28d-4471-bcb5-33d6fc1366fb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894893906 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_ping_timeout.3894893906
Directory /workspace/36.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_random_alerts.2577955289
Short name T558
Test name
Test status
Simulation time 18564017 ps
CPU time 3.52 seconds
Started Jan 24 01:46:16 PM PST 24
Finished Jan 24 01:46:41 PM PST 24
Peak memory 237076 kb
Host smart-4bb8ccb8-0e6a-48ce-a270-cf5b1e244e04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25779
55289 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_alerts.2577955289
Directory /workspace/36.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/36.alert_handler_random_classes.3684332870
Short name T376
Test name
Test status
Simulation time 5007790896 ps
CPU time 17.54 seconds
Started Jan 24 01:46:14 PM PST 24
Finished Jan 24 01:46:53 PM PST 24
Peak memory 251216 kb
Host smart-18d39a09-10f6-4162-abc1-619938f98383
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36843
32870 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_classes.3684332870
Directory /workspace/36.alert_handler_random_classes/latest

Test location /workspace/coverage/default/36.alert_handler_sig_int_fail.1633181407
Short name T667
Test name
Test status
Simulation time 5207129942 ps
CPU time 49.85 seconds
Started Jan 24 01:46:14 PM PST 24
Finished Jan 24 01:47:26 PM PST 24
Peak memory 248152 kb
Host smart-58d3a493-d1ec-4fc7-bcce-e563c9d481fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16331
81407 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_sig_int_fail.1633181407
Directory /workspace/36.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/36.alert_handler_smoke.926297944
Short name T512
Test name
Test status
Simulation time 19620883665 ps
CPU time 69.81 seconds
Started Jan 24 01:48:55 PM PST 24
Finished Jan 24 01:50:10 PM PST 24
Peak memory 251516 kb
Host smart-7eca5197-cf44-4ea0-863b-e272f27a0db5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92629
7944 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_smoke.926297944
Directory /workspace/36.alert_handler_smoke/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all.1494984289
Short name T619
Test name
Test status
Simulation time 75192472265 ps
CPU time 4103.07 seconds
Started Jan 24 01:46:21 PM PST 24
Finished Jan 24 02:55:02 PM PST 24
Peak memory 297304 kb
Host smart-f07b11dc-7aed-481e-8957-63e3391b5c6d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494984289 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_ha
ndler_stress_all.1494984289
Directory /workspace/36.alert_handler_stress_all/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all_with_rand_reset.1747574448
Short name T49
Test name
Test status
Simulation time 61933512231 ps
CPU time 4907.64 seconds
Started Jan 24 01:46:24 PM PST 24
Finished Jan 24 03:08:28 PM PST 24
Peak memory 297376 kb
Host smart-149cb81a-b061-455e-8a3c-d3f060636f3f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747574448 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 36.alert_handler_stress_all_with_rand_reset.1747574448
Directory /workspace/36.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.alert_handler_entropy.1002365512
Short name T91
Test name
Test status
Simulation time 77237350191 ps
CPU time 2382.38 seconds
Started Jan 24 01:46:45 PM PST 24
Finished Jan 24 02:26:31 PM PST 24
Peak memory 281608 kb
Host smart-25793c62-0317-4c3a-92b0-a611cf71d13e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002365512 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_entropy.1002365512
Directory /workspace/37.alert_handler_entropy/latest

Test location /workspace/coverage/default/37.alert_handler_esc_alert_accum.898384817
Short name T370
Test name
Test status
Simulation time 14871994985 ps
CPU time 228.89 seconds
Started Jan 24 01:46:36 PM PST 24
Finished Jan 24 01:50:33 PM PST 24
Peak memory 250212 kb
Host smart-f2702b58-3eb9-48aa-88ca-c09c39938ee9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89838
4817 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_alert_accum.898384817
Directory /workspace/37.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/37.alert_handler_esc_intr_timeout.1001595165
Short name T497
Test name
Test status
Simulation time 378549575 ps
CPU time 35.76 seconds
Started Jan 24 01:46:37 PM PST 24
Finished Jan 24 01:47:21 PM PST 24
Peak memory 247960 kb
Host smart-2301726e-6c1e-4fea-a6a8-8cb670383783
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10015
95165 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_intr_timeout.1001595165
Directory /workspace/37.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_lpg.1295730138
Short name T341
Test name
Test status
Simulation time 20613960153 ps
CPU time 1490.83 seconds
Started Jan 24 01:50:27 PM PST 24
Finished Jan 24 02:15:29 PM PST 24
Peak memory 288488 kb
Host smart-04575622-402e-4b07-896b-dc67caa5feb5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295730138 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg.1295730138
Directory /workspace/37.alert_handler_lpg/latest

Test location /workspace/coverage/default/37.alert_handler_lpg_stub_clk.2346701587
Short name T428
Test name
Test status
Simulation time 29254863639 ps
CPU time 1759.4 seconds
Started Jan 24 01:46:43 PM PST 24
Finished Jan 24 02:16:07 PM PST 24
Peak memory 272008 kb
Host smart-9dc21e9f-51a7-4339-aaeb-c6eedd698570
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346701587 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg_stub_clk.2346701587
Directory /workspace/37.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/37.alert_handler_ping_timeout.2431002037
Short name T321
Test name
Test status
Simulation time 8403374518 ps
CPU time 325.2 seconds
Started Jan 24 03:11:50 PM PST 24
Finished Jan 24 03:17:28 PM PST 24
Peak memory 246644 kb
Host smart-0c9bed90-c160-4473-874f-06b40ddab62c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431002037 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_ping_timeout.2431002037
Directory /workspace/37.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_random_alerts.4201077081
Short name T620
Test name
Test status
Simulation time 1406792588 ps
CPU time 30.15 seconds
Started Jan 24 02:14:20 PM PST 24
Finished Jan 24 02:15:06 PM PST 24
Peak memory 253488 kb
Host smart-58e3b927-8d64-4220-9612-3db3bdf69a67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42010
77081 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_alerts.4201077081
Directory /workspace/37.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/37.alert_handler_random_classes.1330204584
Short name T647
Test name
Test status
Simulation time 281338029 ps
CPU time 16.65 seconds
Started Jan 24 02:33:50 PM PST 24
Finished Jan 24 02:34:21 PM PST 24
Peak memory 248028 kb
Host smart-ac7a486b-2f50-44d9-8a35-e53c47d936d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13302
04584 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_classes.1330204584
Directory /workspace/37.alert_handler_random_classes/latest

Test location /workspace/coverage/default/37.alert_handler_sig_int_fail.4108484200
Short name T437
Test name
Test status
Simulation time 661082412 ps
CPU time 47.34 seconds
Started Jan 24 01:46:36 PM PST 24
Finished Jan 24 01:47:31 PM PST 24
Peak memory 251296 kb
Host smart-ebc3a745-74ed-4a8f-a6d4-e5d9852e3a55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41084
84200 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_sig_int_fail.4108484200
Directory /workspace/37.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/37.alert_handler_smoke.3314080708
Short name T418
Test name
Test status
Simulation time 225572951 ps
CPU time 8.92 seconds
Started Jan 24 01:46:25 PM PST 24
Finished Jan 24 01:46:49 PM PST 24
Peak memory 247976 kb
Host smart-fc38ae2e-60be-445f-8938-693bbb020fe2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33140
80708 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_smoke.3314080708
Directory /workspace/37.alert_handler_smoke/latest

Test location /workspace/coverage/default/38.alert_handler_entropy.1809551754
Short name T449
Test name
Test status
Simulation time 26165933477 ps
CPU time 1662.67 seconds
Started Jan 24 02:24:22 PM PST 24
Finished Jan 24 02:52:16 PM PST 24
Peak memory 272048 kb
Host smart-365ebfdd-552e-4aa8-ac0e-3d657a71fe44
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809551754 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_entropy.1809551754
Directory /workspace/38.alert_handler_entropy/latest

Test location /workspace/coverage/default/38.alert_handler_esc_alert_accum.1814878270
Short name T633
Test name
Test status
Simulation time 748755333 ps
CPU time 24.19 seconds
Started Jan 24 02:46:20 PM PST 24
Finished Jan 24 02:46:46 PM PST 24
Peak memory 250260 kb
Host smart-f175f641-8c28-4424-8d32-e883476132ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18148
78270 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_alert_accum.1814878270
Directory /workspace/38.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/38.alert_handler_esc_intr_timeout.2259041633
Short name T502
Test name
Test status
Simulation time 1313722951 ps
CPU time 27.11 seconds
Started Jan 24 02:18:59 PM PST 24
Finished Jan 24 02:19:39 PM PST 24
Peak memory 247348 kb
Host smart-4062ce99-802d-4217-91b1-09852123b92c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22590
41633 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_intr_timeout.2259041633
Directory /workspace/38.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_lpg.3617754874
Short name T617
Test name
Test status
Simulation time 46306307983 ps
CPU time 1350.08 seconds
Started Jan 24 01:47:19 PM PST 24
Finished Jan 24 02:10:03 PM PST 24
Peak memory 286724 kb
Host smart-7358441c-357a-464b-8e83-3b9572c6f68a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617754874 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg.3617754874
Directory /workspace/38.alert_handler_lpg/latest

Test location /workspace/coverage/default/38.alert_handler_lpg_stub_clk.2461589374
Short name T635
Test name
Test status
Simulation time 27250763423 ps
CPU time 1657.06 seconds
Started Jan 24 01:47:21 PM PST 24
Finished Jan 24 02:15:11 PM PST 24
Peak memory 265808 kb
Host smart-31917dd9-45c7-4442-82bb-e17a353a324f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2461589374 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg_stub_clk.2461589374
Directory /workspace/38.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/38.alert_handler_ping_timeout.479308339
Short name T658
Test name
Test status
Simulation time 13393218398 ps
CPU time 584.11 seconds
Started Jan 24 01:47:22 PM PST 24
Finished Jan 24 01:57:20 PM PST 24
Peak memory 250396 kb
Host smart-f1f76f64-6820-4e56-bdc8-d62e61090864
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479308339 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_ping_timeout.479308339
Directory /workspace/38.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_random_alerts.1515408613
Short name T489
Test name
Test status
Simulation time 832425038 ps
CPU time 46.28 seconds
Started Jan 24 01:46:54 PM PST 24
Finished Jan 24 01:47:41 PM PST 24
Peak memory 248060 kb
Host smart-ee0e433b-d0cf-4a29-9c95-d5c3809328b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15154
08613 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_alerts.1515408613
Directory /workspace/38.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/38.alert_handler_random_classes.677908457
Short name T58
Test name
Test status
Simulation time 148363308 ps
CPU time 21.46 seconds
Started Jan 24 02:58:40 PM PST 24
Finished Jan 24 02:59:07 PM PST 24
Peak memory 248224 kb
Host smart-666ccfa1-14e8-4f97-a0c7-7ac59539b19b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67790
8457 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_classes.677908457
Directory /workspace/38.alert_handler_random_classes/latest

Test location /workspace/coverage/default/38.alert_handler_sig_int_fail.1059756471
Short name T698
Test name
Test status
Simulation time 1609627157 ps
CPU time 55.65 seconds
Started Jan 24 01:47:07 PM PST 24
Finished Jan 24 01:48:05 PM PST 24
Peak memory 247984 kb
Host smart-f02d386a-6e24-41f5-9e3a-d3df7e44976e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10597
56471 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_sig_int_fail.1059756471
Directory /workspace/38.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/38.alert_handler_smoke.3699910345
Short name T55
Test name
Test status
Simulation time 118724052 ps
CPU time 7.95 seconds
Started Jan 24 02:27:59 PM PST 24
Finished Jan 24 02:28:26 PM PST 24
Peak memory 239836 kb
Host smart-c0acf01c-dbfe-426c-bd57-58fc438a3535
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36999
10345 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_smoke.3699910345
Directory /workspace/38.alert_handler_smoke/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all.1823018055
Short name T422
Test name
Test status
Simulation time 70179447784 ps
CPU time 2240.52 seconds
Started Jan 24 01:47:19 PM PST 24
Finished Jan 24 02:24:54 PM PST 24
Peak memory 272752 kb
Host smart-f5d43aa2-46ff-4e5a-acd6-d855dcfd4f45
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823018055 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_ha
ndler_stress_all.1823018055
Directory /workspace/38.alert_handler_stress_all/latest

Test location /workspace/coverage/default/39.alert_handler_entropy.1058673084
Short name T545
Test name
Test status
Simulation time 12372224023 ps
CPU time 1375.04 seconds
Started Jan 24 01:47:32 PM PST 24
Finished Jan 24 02:10:51 PM PST 24
Peak memory 289044 kb
Host smart-44b16416-664b-47b0-98f7-fdfdc4e3ec70
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058673084 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_entropy.1058673084
Directory /workspace/39.alert_handler_entropy/latest

Test location /workspace/coverage/default/39.alert_handler_esc_alert_accum.926056945
Short name T662
Test name
Test status
Simulation time 6177895217 ps
CPU time 190.5 seconds
Started Jan 24 01:47:36 PM PST 24
Finished Jan 24 01:51:08 PM PST 24
Peak memory 247408 kb
Host smart-30c27ccf-336d-49ac-a2b8-a3846088efa1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92605
6945 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_alert_accum.926056945
Directory /workspace/39.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/39.alert_handler_esc_intr_timeout.409516691
Short name T283
Test name
Test status
Simulation time 4181042652 ps
CPU time 65.68 seconds
Started Jan 24 01:56:24 PM PST 24
Finished Jan 24 01:57:33 PM PST 24
Peak memory 248196 kb
Host smart-0b72a8ab-bf58-4310-a1a6-e77a0459eaea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40951
6691 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_intr_timeout.409516691
Directory /workspace/39.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_lpg.2718964339
Short name T334
Test name
Test status
Simulation time 225514375901 ps
CPU time 1483.03 seconds
Started Jan 24 01:47:34 PM PST 24
Finished Jan 24 02:12:40 PM PST 24
Peak memory 272760 kb
Host smart-3ac16fe3-1ddb-4f81-ba75-7de1d32201f5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718964339 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg.2718964339
Directory /workspace/39.alert_handler_lpg/latest

Test location /workspace/coverage/default/39.alert_handler_lpg_stub_clk.2693863445
Short name T399
Test name
Test status
Simulation time 47443952254 ps
CPU time 2614.68 seconds
Started Jan 24 01:47:46 PM PST 24
Finished Jan 24 02:31:40 PM PST 24
Peak memory 280888 kb
Host smart-e05bab81-12dd-4d7f-821d-e39e6f01648f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2693863445 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg_stub_clk.2693863445
Directory /workspace/39.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/39.alert_handler_ping_timeout.2039136759
Short name T314
Test name
Test status
Simulation time 12990616680 ps
CPU time 576.9 seconds
Started Jan 24 01:47:33 PM PST 24
Finished Jan 24 01:57:33 PM PST 24
Peak memory 246344 kb
Host smart-700006b8-4b83-4ec7-a8f4-ed1dce739c23
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039136759 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_ping_timeout.2039136759
Directory /workspace/39.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_random_alerts.1543175765
Short name T82
Test name
Test status
Simulation time 1064971207 ps
CPU time 70.29 seconds
Started Jan 24 01:47:18 PM PST 24
Finished Jan 24 01:48:41 PM PST 24
Peak memory 248036 kb
Host smart-a99e550e-781a-4f34-b757-63beab93493a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15431
75765 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_alerts.1543175765
Directory /workspace/39.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/39.alert_handler_random_classes.918834392
Short name T80
Test name
Test status
Simulation time 730610180 ps
CPU time 45.84 seconds
Started Jan 24 01:47:33 PM PST 24
Finished Jan 24 01:48:42 PM PST 24
Peak memory 247040 kb
Host smart-88eac86a-2537-4959-abd5-f86ecfd830c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91883
4392 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_classes.918834392
Directory /workspace/39.alert_handler_random_classes/latest

Test location /workspace/coverage/default/39.alert_handler_sig_int_fail.2343855829
Short name T701
Test name
Test status
Simulation time 446589165 ps
CPU time 31.82 seconds
Started Jan 24 01:47:33 PM PST 24
Finished Jan 24 01:48:28 PM PST 24
Peak memory 248040 kb
Host smart-cd098b99-d348-4ece-9d03-658df9c11f14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23438
55829 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_sig_int_fail.2343855829
Directory /workspace/39.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/39.alert_handler_smoke.3185040145
Short name T470
Test name
Test status
Simulation time 94734229 ps
CPU time 4.89 seconds
Started Jan 24 01:47:20 PM PST 24
Finished Jan 24 01:47:38 PM PST 24
Peak memory 239824 kb
Host smart-d577ecca-5b24-4fdb-b24c-63b0735d154b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31850
40145 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_smoke.3185040145
Directory /workspace/39.alert_handler_smoke/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all.1386297572
Short name T517
Test name
Test status
Simulation time 89981074232 ps
CPU time 2005.93 seconds
Started Jan 24 01:47:46 PM PST 24
Finished Jan 24 02:21:32 PM PST 24
Peak memory 305456 kb
Host smart-d2e01fb6-7596-4624-a304-32e3c092995a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386297572 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_ha
ndler_stress_all.1386297572
Directory /workspace/39.alert_handler_stress_all/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all_with_rand_reset.2767202229
Short name T205
Test name
Test status
Simulation time 19500572752 ps
CPU time 1323.13 seconds
Started Jan 24 01:47:45 PM PST 24
Finished Jan 24 02:10:07 PM PST 24
Peak memory 281612 kb
Host smart-f4ff76e6-3365-4471-8957-54552c3d9846
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767202229 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.alert_handler_stress_all_with_rand_reset.2767202229
Directory /workspace/39.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.alert_handler_alert_accum_saturation.1433064669
Short name T232
Test name
Test status
Simulation time 161181956 ps
CPU time 3.88 seconds
Started Jan 24 01:39:40 PM PST 24
Finished Jan 24 01:40:55 PM PST 24
Peak memory 249308 kb
Host smart-e95268c0-db65-427c-956c-8dcba9150394
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1433064669 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_alert_accum_saturation.1433064669
Directory /workspace/4.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/4.alert_handler_entropy.1033585536
Short name T120
Test name
Test status
Simulation time 93823155428 ps
CPU time 890.4 seconds
Started Jan 24 01:39:24 PM PST 24
Finished Jan 24 01:54:29 PM PST 24
Peak memory 272316 kb
Host smart-04ea9e36-f71b-4f5d-acff-53c1f223ae48
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033585536 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy.1033585536
Directory /workspace/4.alert_handler_entropy/latest

Test location /workspace/coverage/default/4.alert_handler_entropy_stress.3007285900
Short name T638
Test name
Test status
Simulation time 167253356 ps
CPU time 9.7 seconds
Started Jan 24 01:39:37 PM PST 24
Finished Jan 24 01:40:58 PM PST 24
Peak memory 239172 kb
Host smart-a21f8d75-986c-42be-bef4-b7df91941ed4
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3007285900 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy_stress.3007285900
Directory /workspace/4.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/4.alert_handler_esc_alert_accum.1785482802
Short name T466
Test name
Test status
Simulation time 5144127736 ps
CPU time 45.68 seconds
Started Jan 24 01:39:37 PM PST 24
Finished Jan 24 01:41:15 PM PST 24
Peak memory 255860 kb
Host smart-656b740c-2ef3-4fac-9222-cae082b7b2bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17854
82802 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_alert_accum.1785482802
Directory /workspace/4.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/4.alert_handler_esc_intr_timeout.1233021358
Short name T464
Test name
Test status
Simulation time 385199772 ps
CPU time 23.61 seconds
Started Jan 24 01:39:26 PM PST 24
Finished Jan 24 01:40:27 PM PST 24
Peak memory 250088 kb
Host smart-5ec0b8e0-29d1-41b7-a662-0d3cb88bf2bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12330
21358 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_intr_timeout.1233021358
Directory /workspace/4.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_lpg_stub_clk.2975712941
Short name T111
Test name
Test status
Simulation time 35655133257 ps
CPU time 754.62 seconds
Started Jan 24 01:39:25 PM PST 24
Finished Jan 24 01:52:26 PM PST 24
Peak memory 264520 kb
Host smart-2e50fa1c-5523-4283-b20d-1b4eb79346e3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975712941 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg_stub_clk.2975712941
Directory /workspace/4.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/4.alert_handler_ping_timeout.2645572053
Short name T307
Test name
Test status
Simulation time 12050895014 ps
CPU time 494.06 seconds
Started Jan 24 01:39:37 PM PST 24
Finished Jan 24 01:49:01 PM PST 24
Peak memory 248212 kb
Host smart-a81da636-cb73-49fe-8b61-13ba11055376
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645572053 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_ping_timeout.2645572053
Directory /workspace/4.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_random_alerts.2767730531
Short name T32
Test name
Test status
Simulation time 1096658360 ps
CPU time 36.53 seconds
Started Jan 24 01:39:20 PM PST 24
Finished Jan 24 01:40:01 PM PST 24
Peak memory 256220 kb
Host smart-f63fa90d-309a-4046-b05f-789e8ca3510c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27677
30531 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_alerts.2767730531
Directory /workspace/4.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/4.alert_handler_random_classes.539702836
Short name T605
Test name
Test status
Simulation time 341448536 ps
CPU time 22.19 seconds
Started Jan 24 01:39:40 PM PST 24
Finished Jan 24 01:41:13 PM PST 24
Peak memory 253376 kb
Host smart-5a0fc58a-1909-4404-bcf8-eec47af8b579
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53970
2836 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_classes.539702836
Directory /workspace/4.alert_handler_random_classes/latest

Test location /workspace/coverage/default/4.alert_handler_sec_cm.1699022812
Short name T11
Test name
Test status
Simulation time 1287225292 ps
CPU time 20.79 seconds
Started Jan 24 02:46:16 PM PST 24
Finished Jan 24 02:46:40 PM PST 24
Peak memory 271848 kb
Host smart-8f47ccaa-c55b-41f5-a7a5-ea9ba5e7d5c8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1699022812 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sec_cm.1699022812
Directory /workspace/4.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/4.alert_handler_sig_int_fail.3379558063
Short name T372
Test name
Test status
Simulation time 2983884279 ps
CPU time 46.95 seconds
Started Jan 24 01:39:40 PM PST 24
Finished Jan 24 01:41:28 PM PST 24
Peak memory 247772 kb
Host smart-49a70ea2-1688-4ab1-8f34-83f849093153
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33795
58063 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sig_int_fail.3379558063
Directory /workspace/4.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/4.alert_handler_smoke.1556090442
Short name T486
Test name
Test status
Simulation time 614072669 ps
CPU time 36.21 seconds
Started Jan 24 01:39:26 PM PST 24
Finished Jan 24 01:40:38 PM PST 24
Peak memory 250124 kb
Host smart-32201534-3fea-447d-9312-06b837d3c6e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15560
90442 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_smoke.1556090442
Directory /workspace/4.alert_handler_smoke/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all.410988537
Short name T504
Test name
Test status
Simulation time 56140065140 ps
CPU time 3334.05 seconds
Started Jan 24 01:39:37 PM PST 24
Finished Jan 24 02:36:22 PM PST 24
Peak memory 287912 kb
Host smart-e4436f8d-8c56-45fa-8621-f41b136e50fa
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410988537 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_hand
ler_stress_all.410988537
Directory /workspace/4.alert_handler_stress_all/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all_with_rand_reset.872778447
Short name T286
Test name
Test status
Simulation time 92378686104 ps
CPU time 2328.82 seconds
Started Jan 24 01:39:40 PM PST 24
Finished Jan 24 02:19:40 PM PST 24
Peak memory 287220 kb
Host smart-9c094831-3174-411e-b4b3-433999bb7329
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872778447 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 4.alert_handler_stress_all_with_rand_reset.872778447
Directory /workspace/4.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.alert_handler_entropy.2291489705
Short name T57
Test name
Test status
Simulation time 18105573231 ps
CPU time 824.89 seconds
Started Jan 24 03:04:08 PM PST 24
Finished Jan 24 03:18:06 PM PST 24
Peak memory 272024 kb
Host smart-0d66bf81-18ef-4c40-ae68-491404535499
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291489705 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_entropy.2291489705
Directory /workspace/40.alert_handler_entropy/latest

Test location /workspace/coverage/default/40.alert_handler_esc_alert_accum.3657007315
Short name T515
Test name
Test status
Simulation time 5729743829 ps
CPU time 87.35 seconds
Started Jan 24 01:47:42 PM PST 24
Finished Jan 24 01:49:28 PM PST 24
Peak memory 250312 kb
Host smart-2d5b22cb-cb5d-448f-9c7f-3499834ae2c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36570
07315 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_alert_accum.3657007315
Directory /workspace/40.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/40.alert_handler_esc_intr_timeout.1408976403
Short name T373
Test name
Test status
Simulation time 454525171 ps
CPU time 16.81 seconds
Started Jan 24 02:59:16 PM PST 24
Finished Jan 24 02:59:36 PM PST 24
Peak memory 247168 kb
Host smart-50c19d00-1dc4-436f-856b-7719bd09c7ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14089
76403 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_intr_timeout.1408976403
Directory /workspace/40.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_lpg.3511979248
Short name T330
Test name
Test status
Simulation time 11963978678 ps
CPU time 1136.83 seconds
Started Jan 24 01:47:55 PM PST 24
Finished Jan 24 02:07:09 PM PST 24
Peak memory 271960 kb
Host smart-4f9cf5da-d1f1-40d6-b4e6-e25fdc2925a1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511979248 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg.3511979248
Directory /workspace/40.alert_handler_lpg/latest

Test location /workspace/coverage/default/40.alert_handler_lpg_stub_clk.1741652006
Short name T101
Test name
Test status
Simulation time 56491733324 ps
CPU time 1507.2 seconds
Started Jan 24 01:47:54 PM PST 24
Finished Jan 24 02:13:19 PM PST 24
Peak memory 288980 kb
Host smart-5c467d9a-b1e2-4907-b680-680ba1578caa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741652006 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg_stub_clk.1741652006
Directory /workspace/40.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/40.alert_handler_ping_timeout.3375746636
Short name T322
Test name
Test status
Simulation time 14246327399 ps
CPU time 302.82 seconds
Started Jan 24 01:48:00 PM PST 24
Finished Jan 24 01:53:17 PM PST 24
Peak memory 246688 kb
Host smart-f1d5f0fa-cb71-4d93-97c7-0ad2f816c55d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375746636 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_ping_timeout.3375746636
Directory /workspace/40.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_random_alerts.3305650010
Short name T606
Test name
Test status
Simulation time 683630691 ps
CPU time 36.79 seconds
Started Jan 24 01:47:44 PM PST 24
Finished Jan 24 01:48:41 PM PST 24
Peak memory 248040 kb
Host smart-fa649e9e-5e08-4bdb-93cf-53c6100a2318
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33056
50010 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_alerts.3305650010
Directory /workspace/40.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/40.alert_handler_random_classes.1517267345
Short name T613
Test name
Test status
Simulation time 1702109991 ps
CPU time 48.83 seconds
Started Jan 24 01:47:44 PM PST 24
Finished Jan 24 01:48:53 PM PST 24
Peak memory 248024 kb
Host smart-65279c1c-dca2-4b2c-bdff-66374ef6c173
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15172
67345 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_classes.1517267345
Directory /workspace/40.alert_handler_random_classes/latest

Test location /workspace/coverage/default/40.alert_handler_sig_int_fail.823927737
Short name T454
Test name
Test status
Simulation time 185072926 ps
CPU time 22.65 seconds
Started Jan 24 01:47:49 PM PST 24
Finished Jan 24 01:48:32 PM PST 24
Peak memory 248136 kb
Host smart-2c5a88d7-eb90-43bd-b619-f46dd9e8ac3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82392
7737 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_sig_int_fail.823927737
Directory /workspace/40.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/40.alert_handler_smoke.136282056
Short name T353
Test name
Test status
Simulation time 10688753154 ps
CPU time 36.14 seconds
Started Jan 24 01:47:49 PM PST 24
Finished Jan 24 01:48:45 PM PST 24
Peak memory 248112 kb
Host smart-4855640c-d22a-412e-9738-08af2869d9b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13628
2056 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_smoke.136282056
Directory /workspace/40.alert_handler_smoke/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all.1793249641
Short name T83
Test name
Test status
Simulation time 224422517979 ps
CPU time 2255.45 seconds
Started Jan 24 01:48:08 PM PST 24
Finished Jan 24 02:25:51 PM PST 24
Peak memory 285948 kb
Host smart-f812710e-2c05-4976-8bfd-3a7839c370da
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793249641 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_ha
ndler_stress_all.1793249641
Directory /workspace/40.alert_handler_stress_all/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all_with_rand_reset.530263489
Short name T70
Test name
Test status
Simulation time 55547560783 ps
CPU time 3632.28 seconds
Started Jan 24 02:14:14 PM PST 24
Finished Jan 24 03:15:02 PM PST 24
Peak memory 302564 kb
Host smart-76a36d08-7247-47c1-a8c9-6cc85b5286d1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530263489 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 40.alert_handler_stress_all_with_rand_reset.530263489
Directory /workspace/40.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.alert_handler_entropy.3421316069
Short name T623
Test name
Test status
Simulation time 53031976527 ps
CPU time 3027.11 seconds
Started Jan 24 02:52:24 PM PST 24
Finished Jan 24 03:43:02 PM PST 24
Peak memory 286768 kb
Host smart-877704ef-6626-4bd7-b5ad-67aeca63abd2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421316069 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_entropy.3421316069
Directory /workspace/41.alert_handler_entropy/latest

Test location /workspace/coverage/default/41.alert_handler_esc_alert_accum.3504159888
Short name T246
Test name
Test status
Simulation time 9378500284 ps
CPU time 270.61 seconds
Started Jan 24 03:00:23 PM PST 24
Finished Jan 24 03:05:09 PM PST 24
Peak memory 250284 kb
Host smart-af55dc94-78bc-49fc-9ddb-3b772c45bd22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35041
59888 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_alert_accum.3504159888
Directory /workspace/41.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/41.alert_handler_esc_intr_timeout.3087629557
Short name T565
Test name
Test status
Simulation time 192533251 ps
CPU time 5.34 seconds
Started Jan 24 04:28:36 PM PST 24
Finished Jan 24 04:28:43 PM PST 24
Peak memory 248144 kb
Host smart-27c0b17c-a42a-41d0-9c2e-599dedb03b70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30876
29557 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_intr_timeout.3087629557
Directory /workspace/41.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_lpg.795723585
Short name T550
Test name
Test status
Simulation time 64004436460 ps
CPU time 1346.63 seconds
Started Jan 24 01:48:32 PM PST 24
Finished Jan 24 02:11:00 PM PST 24
Peak memory 280908 kb
Host smart-f395f73c-afea-4cf7-ac82-fa5702a2ffbc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795723585 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg.795723585
Directory /workspace/41.alert_handler_lpg/latest

Test location /workspace/coverage/default/41.alert_handler_lpg_stub_clk.2614234299
Short name T706
Test name
Test status
Simulation time 7185152829 ps
CPU time 793.35 seconds
Started Jan 24 01:48:32 PM PST 24
Finished Jan 24 02:01:47 PM PST 24
Peak memory 265748 kb
Host smart-55f16b35-1fdf-4fbb-8593-23f1acf793a7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2614234299 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg_stub_clk.2614234299
Directory /workspace/41.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/41.alert_handler_ping_timeout.3309184080
Short name T318
Test name
Test status
Simulation time 6620309644 ps
CPU time 282.09 seconds
Started Jan 24 01:48:27 PM PST 24
Finished Jan 24 01:53:11 PM PST 24
Peak memory 246612 kb
Host smart-6b747a7a-5c58-4345-8f5e-e3eae8162702
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309184080 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_ping_timeout.3309184080
Directory /workspace/41.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_random_alerts.2862158493
Short name T100
Test name
Test status
Simulation time 932289632 ps
CPU time 57.05 seconds
Started Jan 24 02:19:43 PM PST 24
Finished Jan 24 02:20:44 PM PST 24
Peak memory 248052 kb
Host smart-c74a44f3-c34b-43e1-92d4-55932f17701e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28621
58493 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_alerts.2862158493
Directory /workspace/41.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/41.alert_handler_random_classes.4031857876
Short name T130
Test name
Test status
Simulation time 823074578 ps
CPU time 22.78 seconds
Started Jan 24 01:48:17 PM PST 24
Finished Jan 24 01:48:46 PM PST 24
Peak memory 256168 kb
Host smart-03a38ed6-263e-42f8-b347-94294271b62a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40318
57876 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_classes.4031857876
Directory /workspace/41.alert_handler_random_classes/latest

Test location /workspace/coverage/default/41.alert_handler_sig_int_fail.11279953
Short name T51
Test name
Test status
Simulation time 1478594634 ps
CPU time 47.71 seconds
Started Jan 24 01:48:16 PM PST 24
Finished Jan 24 01:49:10 PM PST 24
Peak memory 254284 kb
Host smart-9fe0be54-36db-47cd-9074-cd66a71623e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11279
953 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_sig_int_fail.11279953
Directory /workspace/41.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/41.alert_handler_smoke.939247253
Short name T500
Test name
Test status
Simulation time 2009780406 ps
CPU time 36.47 seconds
Started Jan 24 01:48:08 PM PST 24
Finished Jan 24 01:48:52 PM PST 24
Peak memory 248008 kb
Host smart-d837dc46-1152-46ce-9402-39728c4c69fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93924
7253 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_smoke.939247253
Directory /workspace/41.alert_handler_smoke/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all.2009234927
Short name T710
Test name
Test status
Simulation time 40011515828 ps
CPU time 1151.88 seconds
Started Jan 24 01:48:54 PM PST 24
Finished Jan 24 02:08:12 PM PST 24
Peak memory 272044 kb
Host smart-d3a0492e-144c-4222-9d34-665592f4e38c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009234927 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_ha
ndler_stress_all.2009234927
Directory /workspace/41.alert_handler_stress_all/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all_with_rand_reset.113584204
Short name T566
Test name
Test status
Simulation time 99396833313 ps
CPU time 2265.98 seconds
Started Jan 24 02:05:31 PM PST 24
Finished Jan 24 02:44:11 PM PST 24
Peak memory 305156 kb
Host smart-911e67f9-5e4f-4363-9e35-ce2df85d3359
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113584204 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 41.alert_handler_stress_all_with_rand_reset.113584204
Directory /workspace/41.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.alert_handler_entropy.1266265051
Short name T519
Test name
Test status
Simulation time 34889031482 ps
CPU time 1092.77 seconds
Started Jan 24 02:52:24 PM PST 24
Finished Jan 24 03:10:48 PM PST 24
Peak memory 272792 kb
Host smart-b5ea4a2b-4c17-4775-bda8-b006469ac67b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266265051 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_entropy.1266265051
Directory /workspace/42.alert_handler_entropy/latest

Test location /workspace/coverage/default/42.alert_handler_esc_alert_accum.3265165967
Short name T695
Test name
Test status
Simulation time 68708242 ps
CPU time 4.97 seconds
Started Jan 24 01:49:00 PM PST 24
Finished Jan 24 01:49:19 PM PST 24
Peak memory 237776 kb
Host smart-7bf0e377-1351-4ef0-8bb9-b49eaba2647d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32651
65967 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_alert_accum.3265165967
Directory /workspace/42.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/42.alert_handler_esc_intr_timeout.4257990205
Short name T89
Test name
Test status
Simulation time 399696524 ps
CPU time 15.78 seconds
Started Jan 24 02:39:58 PM PST 24
Finished Jan 24 02:40:26 PM PST 24
Peak memory 248120 kb
Host smart-a34cd679-3cd8-423b-be53-74b6acdc72ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42579
90205 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_intr_timeout.4257990205
Directory /workspace/42.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_lpg.1214128432
Short name T125
Test name
Test status
Simulation time 10673512837 ps
CPU time 1095.1 seconds
Started Jan 24 01:49:11 PM PST 24
Finished Jan 24 02:07:36 PM PST 24
Peak memory 272748 kb
Host smart-65d05cb6-4b3e-4348-bcab-581ed2948ffc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214128432 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg.1214128432
Directory /workspace/42.alert_handler_lpg/latest

Test location /workspace/coverage/default/42.alert_handler_lpg_stub_clk.1867895360
Short name T217
Test name
Test status
Simulation time 78439339435 ps
CPU time 1634.5 seconds
Started Jan 24 01:49:10 PM PST 24
Finished Jan 24 02:16:35 PM PST 24
Peak memory 271652 kb
Host smart-885c2de2-518e-4dea-8cf2-a7ede5ae5ccf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867895360 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg_stub_clk.1867895360
Directory /workspace/42.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/42.alert_handler_ping_timeout.62918121
Short name T302
Test name
Test status
Simulation time 9846112248 ps
CPU time 194.78 seconds
Started Jan 24 02:58:33 PM PST 24
Finished Jan 24 03:01:52 PM PST 24
Peak memory 249380 kb
Host smart-57095ae6-dfb6-42d5-bedf-4a16539ecc31
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62918121 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_ping_timeout.62918121
Directory /workspace/42.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_random_alerts.3195150220
Short name T44
Test name
Test status
Simulation time 40797065 ps
CPU time 3.82 seconds
Started Jan 24 01:48:35 PM PST 24
Finished Jan 24 01:48:40 PM PST 24
Peak memory 239820 kb
Host smart-9c774b17-6abe-4b40-b9d7-c8d383e99db0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31951
50220 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_alerts.3195150220
Directory /workspace/42.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/42.alert_handler_random_classes.3188127212
Short name T496
Test name
Test status
Simulation time 730394233 ps
CPU time 16.2 seconds
Started Jan 24 02:46:11 PM PST 24
Finished Jan 24 02:46:32 PM PST 24
Peak memory 250372 kb
Host smart-31eceeef-dee1-4738-afea-9c39fecf5de3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31881
27212 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_classes.3188127212
Directory /workspace/42.alert_handler_random_classes/latest

Test location /workspace/coverage/default/42.alert_handler_sig_int_fail.2868170179
Short name T692
Test name
Test status
Simulation time 122957488 ps
CPU time 2.81 seconds
Started Jan 24 02:22:07 PM PST 24
Finished Jan 24 02:22:56 PM PST 24
Peak memory 237756 kb
Host smart-2794fe60-54c3-4b4a-871d-f71021e814bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28681
70179 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_sig_int_fail.2868170179
Directory /workspace/42.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/42.alert_handler_smoke.1410823516
Short name T409
Test name
Test status
Simulation time 686641595 ps
CPU time 12.58 seconds
Started Jan 24 01:48:32 PM PST 24
Finished Jan 24 01:48:47 PM PST 24
Peak memory 247988 kb
Host smart-91a040e0-c54c-40a3-8bba-17255b8e963f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14108
23516 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_smoke.1410823516
Directory /workspace/42.alert_handler_smoke/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all.3286046766
Short name T206
Test name
Test status
Simulation time 15043342805 ps
CPU time 1288.37 seconds
Started Jan 24 01:49:08 PM PST 24
Finished Jan 24 02:10:47 PM PST 24
Peak memory 297272 kb
Host smart-a4bacddf-1cde-4228-b502-9376e023af68
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286046766 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_ha
ndler_stress_all.3286046766
Directory /workspace/42.alert_handler_stress_all/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all_with_rand_reset.1311929443
Short name T59
Test name
Test status
Simulation time 549671335089 ps
CPU time 3194.53 seconds
Started Jan 24 01:49:08 PM PST 24
Finished Jan 24 02:42:34 PM PST 24
Peak memory 289244 kb
Host smart-7f8bd652-4ccd-4b78-8655-2ab88c7e97b3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311929443 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 42.alert_handler_stress_all_with_rand_reset.1311929443
Directory /workspace/42.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.alert_handler_esc_alert_accum.2444773966
Short name T649
Test name
Test status
Simulation time 13041176861 ps
CPU time 370.53 seconds
Started Jan 24 01:49:20 PM PST 24
Finished Jan 24 01:55:37 PM PST 24
Peak memory 249268 kb
Host smart-eb1504c0-eb23-4345-96b0-e81dcafe553f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24447
73966 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_alert_accum.2444773966
Directory /workspace/43.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/43.alert_handler_esc_intr_timeout.2588552360
Short name T21
Test name
Test status
Simulation time 223470250 ps
CPU time 13.45 seconds
Started Jan 24 01:49:20 PM PST 24
Finished Jan 24 01:49:40 PM PST 24
Peak memory 251684 kb
Host smart-9c40f93b-d6c1-4f85-8c71-7800843d7eea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25885
52360 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_intr_timeout.2588552360
Directory /workspace/43.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_lpg_stub_clk.3015398217
Short name T451
Test name
Test status
Simulation time 6807252755 ps
CPU time 652.68 seconds
Started Jan 24 01:49:35 PM PST 24
Finished Jan 24 02:00:29 PM PST 24
Peak memory 264568 kb
Host smart-d1673332-a286-45d0-97d2-bf27325a514a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3015398217 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg_stub_clk.3015398217
Directory /workspace/43.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/43.alert_handler_ping_timeout.3970376959
Short name T320
Test name
Test status
Simulation time 8718599920 ps
CPU time 328.1 seconds
Started Jan 24 01:49:32 PM PST 24
Finished Jan 24 01:55:01 PM PST 24
Peak memory 248144 kb
Host smart-33768736-69aa-4823-8236-af563e283616
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970376959 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_ping_timeout.3970376959
Directory /workspace/43.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_random_alerts.3514784274
Short name T357
Test name
Test status
Simulation time 106678510 ps
CPU time 4.87 seconds
Started Jan 24 01:49:21 PM PST 24
Finished Jan 24 01:49:32 PM PST 24
Peak memory 237172 kb
Host smart-8ad2d8dc-4242-43cb-bbcb-9d22029bedbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35147
84274 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_alerts.3514784274
Directory /workspace/43.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/43.alert_handler_random_classes.1137867992
Short name T650
Test name
Test status
Simulation time 3025090757 ps
CPU time 49.68 seconds
Started Jan 24 01:49:22 PM PST 24
Finished Jan 24 01:50:17 PM PST 24
Peak memory 248116 kb
Host smart-bcdd0e3d-9fe1-46e4-b6b5-28dd4e051e3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11378
67992 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_classes.1137867992
Directory /workspace/43.alert_handler_random_classes/latest

Test location /workspace/coverage/default/43.alert_handler_sig_int_fail.3217471053
Short name T443
Test name
Test status
Simulation time 179979536 ps
CPU time 10.82 seconds
Started Jan 24 01:49:33 PM PST 24
Finished Jan 24 01:49:45 PM PST 24
Peak memory 251276 kb
Host smart-c14e92c2-fa78-4fbc-9627-801411e85dc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32174
71053 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_sig_int_fail.3217471053
Directory /workspace/43.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/43.alert_handler_smoke.1544186485
Short name T77
Test name
Test status
Simulation time 1315568009 ps
CPU time 24.32 seconds
Started Jan 24 01:49:22 PM PST 24
Finished Jan 24 01:49:52 PM PST 24
Peak memory 247988 kb
Host smart-c0946141-2f00-4f2a-b403-160b50f4ed6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15441
86485 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_smoke.1544186485
Directory /workspace/43.alert_handler_smoke/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all.1315998166
Short name T113
Test name
Test status
Simulation time 19426827504 ps
CPU time 1286.31 seconds
Started Jan 24 01:49:33 PM PST 24
Finished Jan 24 02:11:01 PM PST 24
Peak memory 271972 kb
Host smart-852815d0-a825-48f8-ac5f-70ed82b37141
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315998166 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_ha
ndler_stress_all.1315998166
Directory /workspace/43.alert_handler_stress_all/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all_with_rand_reset.2820194330
Short name T54
Test name
Test status
Simulation time 15253566343 ps
CPU time 1659.18 seconds
Started Jan 24 02:02:11 PM PST 24
Finished Jan 24 02:30:11 PM PST 24
Peak memory 305480 kb
Host smart-73e85ffd-7815-40d0-b86e-9f6ef7941381
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820194330 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 43.alert_handler_stress_all_with_rand_reset.2820194330
Directory /workspace/43.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.alert_handler_entropy.1916529059
Short name T656
Test name
Test status
Simulation time 102802941355 ps
CPU time 1304.83 seconds
Started Jan 24 01:49:47 PM PST 24
Finished Jan 24 02:11:35 PM PST 24
Peak memory 271384 kb
Host smart-5e5ffca5-2498-4a66-8d25-eaa8ff5c327e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1916529059 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_entropy.1916529059
Directory /workspace/44.alert_handler_entropy/latest

Test location /workspace/coverage/default/44.alert_handler_esc_alert_accum.3358518757
Short name T389
Test name
Test status
Simulation time 2164297993 ps
CPU time 139.2 seconds
Started Jan 24 01:59:08 PM PST 24
Finished Jan 24 02:01:29 PM PST 24
Peak memory 256272 kb
Host smart-3a09a9ab-24b2-46f1-a988-42fc5b9a5a2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33585
18757 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_alert_accum.3358518757
Directory /workspace/44.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/44.alert_handler_esc_intr_timeout.3575061346
Short name T495
Test name
Test status
Simulation time 305581027 ps
CPU time 12.39 seconds
Started Jan 24 01:49:52 PM PST 24
Finished Jan 24 01:50:06 PM PST 24
Peak memory 250040 kb
Host smart-5fe25cbb-f60e-4c4c-93ba-c602c1fdf095
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35750
61346 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_intr_timeout.3575061346
Directory /workspace/44.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_lpg.1465865627
Short name T715
Test name
Test status
Simulation time 71981835647 ps
CPU time 1869.84 seconds
Started Jan 24 01:49:52 PM PST 24
Finished Jan 24 02:21:05 PM PST 24
Peak memory 272036 kb
Host smart-7509328f-17e4-45d3-9dab-73ce0c9031f0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465865627 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg.1465865627
Directory /workspace/44.alert_handler_lpg/latest

Test location /workspace/coverage/default/44.alert_handler_lpg_stub_clk.594374342
Short name T492
Test name
Test status
Simulation time 107989871020 ps
CPU time 1555.32 seconds
Started Jan 24 01:49:48 PM PST 24
Finished Jan 24 02:15:47 PM PST 24
Peak memory 271092 kb
Host smart-d3939f26-3cfc-4cea-928c-afa2526729af
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594374342 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg_stub_clk.594374342
Directory /workspace/44.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/44.alert_handler_ping_timeout.3548992769
Short name T686
Test name
Test status
Simulation time 30653916514 ps
CPU time 331.55 seconds
Started Jan 24 01:49:48 PM PST 24
Finished Jan 24 01:55:23 PM PST 24
Peak memory 245596 kb
Host smart-abf6eade-96cf-40f8-b3d0-e115983a1d42
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548992769 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_ping_timeout.3548992769
Directory /workspace/44.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_random_alerts.215156643
Short name T640
Test name
Test status
Simulation time 485877955 ps
CPU time 9.38 seconds
Started Jan 24 01:49:32 PM PST 24
Finished Jan 24 01:49:43 PM PST 24
Peak memory 247960 kb
Host smart-f3dd58a2-1fc5-44d2-8c2b-164f2c093a83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21515
6643 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_alerts.215156643
Directory /workspace/44.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/44.alert_handler_random_classes.845100119
Short name T607
Test name
Test status
Simulation time 923696123 ps
CPU time 27.64 seconds
Started Jan 24 01:49:51 PM PST 24
Finished Jan 24 01:50:21 PM PST 24
Peak memory 247988 kb
Host smart-e5fb20db-5cfe-43ff-970e-88d75ec206b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84510
0119 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_classes.845100119
Directory /workspace/44.alert_handler_random_classes/latest

Test location /workspace/coverage/default/44.alert_handler_sig_int_fail.919819639
Short name T636
Test name
Test status
Simulation time 164107700 ps
CPU time 11.49 seconds
Started Jan 24 01:49:52 PM PST 24
Finished Jan 24 01:50:06 PM PST 24
Peak memory 247972 kb
Host smart-f46552b6-3fb9-4c3e-b390-7dbc83fb20bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91981
9639 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_sig_int_fail.919819639
Directory /workspace/44.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/44.alert_handler_smoke.135056027
Short name T473
Test name
Test status
Simulation time 651322773 ps
CPU time 38.17 seconds
Started Jan 24 01:59:20 PM PST 24
Finished Jan 24 02:00:00 PM PST 24
Peak memory 248072 kb
Host smart-9b78e12e-86b3-4092-a207-5ab5dc343eaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13505
6027 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_smoke.135056027
Directory /workspace/44.alert_handler_smoke/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all.2678250873
Short name T642
Test name
Test status
Simulation time 52580370358 ps
CPU time 1418.74 seconds
Started Jan 24 01:49:46 PM PST 24
Finished Jan 24 02:13:27 PM PST 24
Peak memory 289116 kb
Host smart-802226c3-7c72-4c89-9c9f-4d0f4a0aaa31
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678250873 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_ha
ndler_stress_all.2678250873
Directory /workspace/44.alert_handler_stress_all/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all_with_rand_reset.2086530432
Short name T71
Test name
Test status
Simulation time 66962289794 ps
CPU time 2199.1 seconds
Started Jan 24 01:50:05 PM PST 24
Finished Jan 24 02:26:46 PM PST 24
Peak memory 282128 kb
Host smart-8d377823-d2c8-4327-b52e-7ada158ef10c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086530432 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 44.alert_handler_stress_all_with_rand_reset.2086530432
Directory /workspace/44.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.alert_handler_entropy.750106703
Short name T616
Test name
Test status
Simulation time 12144378747 ps
CPU time 1489.68 seconds
Started Jan 24 01:50:15 PM PST 24
Finished Jan 24 02:15:14 PM PST 24
Peak memory 288592 kb
Host smart-7e6df7f6-2e09-4706-8f9b-cfa971dcfd49
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750106703 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_entropy.750106703
Directory /workspace/45.alert_handler_entropy/latest

Test location /workspace/coverage/default/45.alert_handler_esc_alert_accum.838979117
Short name T608
Test name
Test status
Simulation time 4705022548 ps
CPU time 70.5 seconds
Started Jan 24 01:50:16 PM PST 24
Finished Jan 24 01:51:36 PM PST 24
Peak memory 248164 kb
Host smart-0aff372f-3813-4453-960f-0fb5541a700b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83897
9117 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_alert_accum.838979117
Directory /workspace/45.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/45.alert_handler_esc_intr_timeout.28335904
Short name T386
Test name
Test status
Simulation time 280964588 ps
CPU time 20.52 seconds
Started Jan 24 01:50:15 PM PST 24
Finished Jan 24 01:50:45 PM PST 24
Peak memory 247320 kb
Host smart-1c833be5-5c76-4786-aa1c-2ccfa526d2ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28335
904 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_intr_timeout.28335904
Directory /workspace/45.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_lpg.3896138162
Short name T597
Test name
Test status
Simulation time 61038255083 ps
CPU time 1769.22 seconds
Started Jan 24 01:50:16 PM PST 24
Finished Jan 24 02:19:55 PM PST 24
Peak memory 265548 kb
Host smart-06a042a7-5b42-4057-9160-78b2ce07201b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896138162 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg.3896138162
Directory /workspace/45.alert_handler_lpg/latest

Test location /workspace/coverage/default/45.alert_handler_lpg_stub_clk.2938143164
Short name T534
Test name
Test status
Simulation time 183341069114 ps
CPU time 3253.49 seconds
Started Jan 24 01:50:16 PM PST 24
Finished Jan 24 02:44:40 PM PST 24
Peak memory 289096 kb
Host smart-6223cc1d-9d8a-4940-abed-f435d0dbd3ae
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938143164 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg_stub_clk.2938143164
Directory /workspace/45.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/45.alert_handler_ping_timeout.2284639864
Short name T298
Test name
Test status
Simulation time 50421064605 ps
CPU time 567.39 seconds
Started Jan 24 01:50:16 PM PST 24
Finished Jan 24 01:59:53 PM PST 24
Peak memory 246716 kb
Host smart-17340f8e-1665-480d-8af5-f74f23427df6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284639864 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_ping_timeout.2284639864
Directory /workspace/45.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_random_alerts.2980751975
Short name T533
Test name
Test status
Simulation time 27682170 ps
CPU time 4.95 seconds
Started Jan 24 01:50:16 PM PST 24
Finished Jan 24 01:50:30 PM PST 24
Peak memory 239844 kb
Host smart-152115b2-9a1f-4638-8736-9fea03d0ba89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29807
51975 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_alerts.2980751975
Directory /workspace/45.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/45.alert_handler_random_classes.1377730535
Short name T697
Test name
Test status
Simulation time 807468952 ps
CPU time 26.01 seconds
Started Jan 24 01:50:15 PM PST 24
Finished Jan 24 01:50:50 PM PST 24
Peak memory 247160 kb
Host smart-73722962-d42e-4501-a820-b72b35f6c8e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13777
30535 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_classes.1377730535
Directory /workspace/45.alert_handler_random_classes/latest

Test location /workspace/coverage/default/45.alert_handler_sig_int_fail.3123190649
Short name T275
Test name
Test status
Simulation time 764009538 ps
CPU time 54.44 seconds
Started Jan 24 02:31:37 PM PST 24
Finished Jan 24 02:32:55 PM PST 24
Peak memory 254428 kb
Host smart-482dbe26-cb49-48c2-a9ac-66d590101c0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31231
90649 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_sig_int_fail.3123190649
Directory /workspace/45.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/45.alert_handler_smoke.1938258868
Short name T702
Test name
Test status
Simulation time 539976530 ps
CPU time 29.12 seconds
Started Jan 24 01:50:06 PM PST 24
Finished Jan 24 01:50:36 PM PST 24
Peak memory 248012 kb
Host smart-5fe1ad5f-a4fd-49ad-b648-117cf877bbda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19382
58868 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_smoke.1938258868
Directory /workspace/45.alert_handler_smoke/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all.2864974090
Short name T529
Test name
Test status
Simulation time 25150201570 ps
CPU time 936.57 seconds
Started Jan 24 01:50:28 PM PST 24
Finished Jan 24 02:06:16 PM PST 24
Peak memory 271980 kb
Host smart-3fc3c5b1-e25e-47c1-8431-0f5e7b83cde3
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864974090 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_ha
ndler_stress_all.2864974090
Directory /workspace/45.alert_handler_stress_all/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all_with_rand_reset.2233582646
Short name T116
Test name
Test status
Simulation time 364365242027 ps
CPU time 4991.3 seconds
Started Jan 24 01:50:29 PM PST 24
Finished Jan 24 03:13:51 PM PST 24
Peak memory 305420 kb
Host smart-85f469f8-2386-4f69-ac5f-718c263d9413
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233582646 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 45.alert_handler_stress_all_with_rand_reset.2233582646
Directory /workspace/45.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.alert_handler_entropy.1475477758
Short name T296
Test name
Test status
Simulation time 150673581382 ps
CPU time 2452.16 seconds
Started Jan 24 02:19:07 PM PST 24
Finished Jan 24 03:00:10 PM PST 24
Peak memory 287860 kb
Host smart-3d75ae51-58b4-479f-9448-9b098d98eb59
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475477758 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_entropy.1475477758
Directory /workspace/46.alert_handler_entropy/latest

Test location /workspace/coverage/default/46.alert_handler_esc_alert_accum.4047376985
Short name T626
Test name
Test status
Simulation time 2162171174 ps
CPU time 27.43 seconds
Started Jan 24 01:50:33 PM PST 24
Finished Jan 24 01:51:09 PM PST 24
Peak memory 248100 kb
Host smart-536f06d2-70f6-43fc-91f6-2f833afbd704
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40473
76985 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_alert_accum.4047376985
Directory /workspace/46.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/46.alert_handler_esc_intr_timeout.1094386496
Short name T719
Test name
Test status
Simulation time 1096761497 ps
CPU time 38.14 seconds
Started Jan 24 02:06:51 PM PST 24
Finished Jan 24 02:08:07 PM PST 24
Peak memory 247260 kb
Host smart-1e1056c1-a479-4dac-8d53-875ada3e5973
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10943
86496 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_intr_timeout.1094386496
Directory /workspace/46.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_lpg.404254000
Short name T333
Test name
Test status
Simulation time 37971990220 ps
CPU time 2150.92 seconds
Started Jan 24 02:24:26 PM PST 24
Finished Jan 24 03:00:26 PM PST 24
Peak memory 289156 kb
Host smart-fe68f248-d8a7-4c2a-b8bf-4b9599f0a620
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404254000 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg.404254000
Directory /workspace/46.alert_handler_lpg/latest

Test location /workspace/coverage/default/46.alert_handler_lpg_stub_clk.1846962713
Short name T379
Test name
Test status
Simulation time 194659642099 ps
CPU time 2972.2 seconds
Started Jan 24 02:32:16 PM PST 24
Finished Jan 24 03:22:19 PM PST 24
Peak memory 288416 kb
Host smart-751406bc-1903-4cc5-b9ba-b824e9139912
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846962713 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg_stub_clk.1846962713
Directory /workspace/46.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/46.alert_handler_ping_timeout.314332326
Short name T579
Test name
Test status
Simulation time 14007549643 ps
CPU time 148.71 seconds
Started Jan 24 01:50:34 PM PST 24
Finished Jan 24 01:53:10 PM PST 24
Peak memory 250240 kb
Host smart-2a0c8770-64d2-4068-bf9f-b3ab55d9a444
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=314332326 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_ping_timeout.314332326
Directory /workspace/46.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_random_alerts.1130189411
Short name T356
Test name
Test status
Simulation time 68258840 ps
CPU time 5.62 seconds
Started Jan 24 02:15:29 PM PST 24
Finished Jan 24 02:16:19 PM PST 24
Peak memory 239860 kb
Host smart-c0239dd6-972a-4279-a362-4a620015bc2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11301
89411 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_alerts.1130189411
Directory /workspace/46.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/46.alert_handler_random_classes.3312017528
Short name T259
Test name
Test status
Simulation time 561290226 ps
CPU time 35.02 seconds
Started Jan 24 02:29:38 PM PST 24
Finished Jan 24 02:30:27 PM PST 24
Peak memory 248032 kb
Host smart-da742fa5-ed85-431d-a8b4-820b398fb7c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33120
17528 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_classes.3312017528
Directory /workspace/46.alert_handler_random_classes/latest

Test location /workspace/coverage/default/46.alert_handler_sig_int_fail.2833895941
Short name T562
Test name
Test status
Simulation time 163361519 ps
CPU time 19.49 seconds
Started Jan 24 01:50:35 PM PST 24
Finished Jan 24 01:51:01 PM PST 24
Peak memory 250084 kb
Host smart-cdfda338-de73-464a-b50c-7a9cf0093e57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28338
95941 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_sig_int_fail.2833895941
Directory /workspace/46.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/46.alert_handler_smoke.1615895952
Short name T434
Test name
Test status
Simulation time 6464477092 ps
CPU time 67 seconds
Started Jan 24 01:50:26 PM PST 24
Finished Jan 24 01:51:45 PM PST 24
Peak memory 248148 kb
Host smart-4f30b681-6114-4ef4-b20a-016826a431bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16158
95952 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_smoke.1615895952
Directory /workspace/46.alert_handler_smoke/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all.2286386027
Short name T64
Test name
Test status
Simulation time 26495768117 ps
CPU time 2133.2 seconds
Started Jan 24 02:46:11 PM PST 24
Finished Jan 24 03:21:49 PM PST 24
Peak memory 304988 kb
Host smart-d41e5117-95a3-4916-9b25-cc81b3483f1b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286386027 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_ha
ndler_stress_all.2286386027
Directory /workspace/46.alert_handler_stress_all/latest

Test location /workspace/coverage/default/47.alert_handler_entropy.3957945035
Short name T567
Test name
Test status
Simulation time 20542879572 ps
CPU time 1171.34 seconds
Started Jan 24 02:58:46 PM PST 24
Finished Jan 24 03:18:23 PM PST 24
Peak memory 288688 kb
Host smart-748b6ca9-6dcb-4fa1-b28b-bf85a9a40465
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957945035 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_entropy.3957945035
Directory /workspace/47.alert_handler_entropy/latest

Test location /workspace/coverage/default/47.alert_handler_esc_alert_accum.1244666259
Short name T536
Test name
Test status
Simulation time 878454424 ps
CPU time 48.85 seconds
Started Jan 24 01:51:09 PM PST 24
Finished Jan 24 01:52:05 PM PST 24
Peak memory 247180 kb
Host smart-dc66a2d4-4c76-4201-b6c0-91354e4a8914
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12446
66259 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_alert_accum.1244666259
Directory /workspace/47.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/47.alert_handler_esc_intr_timeout.508477416
Short name T407
Test name
Test status
Simulation time 1856702795 ps
CPU time 31.56 seconds
Started Jan 24 01:51:00 PM PST 24
Finished Jan 24 01:51:38 PM PST 24
Peak memory 254440 kb
Host smart-96e75b8a-afe8-40b7-b5a4-cf9e42ecfc20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50847
7416 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_intr_timeout.508477416
Directory /workspace/47.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_lpg.2423032494
Short name T537
Test name
Test status
Simulation time 20735737170 ps
CPU time 879.74 seconds
Started Jan 24 03:34:02 PM PST 24
Finished Jan 24 03:48:47 PM PST 24
Peak memory 271692 kb
Host smart-36bf714b-f52c-4331-bfc5-3a35c9ee24c1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423032494 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg.2423032494
Directory /workspace/47.alert_handler_lpg/latest

Test location /workspace/coverage/default/47.alert_handler_lpg_stub_clk.743481423
Short name T445
Test name
Test status
Simulation time 127860537717 ps
CPU time 1766.1 seconds
Started Jan 24 01:51:09 PM PST 24
Finished Jan 24 02:20:42 PM PST 24
Peak memory 271736 kb
Host smart-dbe6bd93-f924-4a85-bdb2-7d4a8585e7f5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743481423 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg_stub_clk.743481423
Directory /workspace/47.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/47.alert_handler_ping_timeout.986653265
Short name T297
Test name
Test status
Simulation time 3888768873 ps
CPU time 157.58 seconds
Started Jan 24 02:30:48 PM PST 24
Finished Jan 24 02:33:33 PM PST 24
Peak memory 246936 kb
Host smart-41e295d0-f581-4656-a2c4-58d4b3f5179b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986653265 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_ping_timeout.986653265
Directory /workspace/47.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_random_alerts.1619268035
Short name T99
Test name
Test status
Simulation time 296066633 ps
CPU time 27.94 seconds
Started Jan 24 01:51:09 PM PST 24
Finished Jan 24 01:51:43 PM PST 24
Peak memory 247988 kb
Host smart-b0ad3a52-dd7b-445e-8bf1-c78c96542123
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16192
68035 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_alerts.1619268035
Directory /workspace/47.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/47.alert_handler_random_classes.3576906779
Short name T590
Test name
Test status
Simulation time 358064738 ps
CPU time 13.54 seconds
Started Jan 24 01:51:01 PM PST 24
Finished Jan 24 01:51:20 PM PST 24
Peak memory 248052 kb
Host smart-bb28db69-922b-4fcd-b232-307f20138bd2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35769
06779 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_classes.3576906779
Directory /workspace/47.alert_handler_random_classes/latest

Test location /workspace/coverage/default/47.alert_handler_sig_int_fail.3270318144
Short name T86
Test name
Test status
Simulation time 400293512 ps
CPU time 17.03 seconds
Started Jan 24 01:51:09 PM PST 24
Finished Jan 24 01:51:32 PM PST 24
Peak memory 248004 kb
Host smart-d6d59ee9-a836-46c7-891e-07da571ad604
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32703
18144 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_sig_int_fail.3270318144
Directory /workspace/47.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/47.alert_handler_smoke.4047784023
Short name T505
Test name
Test status
Simulation time 2144905494 ps
CPU time 57.54 seconds
Started Jan 24 01:51:09 PM PST 24
Finished Jan 24 01:52:13 PM PST 24
Peak memory 256164 kb
Host smart-165c6a02-1792-4505-8526-c76adc777f47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40477
84023 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_smoke.4047784023
Directory /workspace/47.alert_handler_smoke/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all.1168168399
Short name T682
Test name
Test status
Simulation time 514950511 ps
CPU time 47.39 seconds
Started Jan 24 02:01:27 PM PST 24
Finished Jan 24 02:02:16 PM PST 24
Peak memory 248052 kb
Host smart-3c84a186-2974-410f-a03d-34721b53e6b1
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168168399 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_ha
ndler_stress_all.1168168399
Directory /workspace/47.alert_handler_stress_all/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all_with_rand_reset.1606929720
Short name T361
Test name
Test status
Simulation time 61710780672 ps
CPU time 1713.96 seconds
Started Jan 24 01:51:13 PM PST 24
Finished Jan 24 02:19:51 PM PST 24
Peak memory 305080 kb
Host smart-7b2fc577-67d6-4f96-8717-dad5c9142078
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606929720 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 47.alert_handler_stress_all_with_rand_reset.1606929720
Directory /workspace/47.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.alert_handler_entropy.2045780215
Short name T387
Test name
Test status
Simulation time 150490021534 ps
CPU time 2414.33 seconds
Started Jan 24 01:51:33 PM PST 24
Finished Jan 24 02:31:54 PM PST 24
Peak memory 281424 kb
Host smart-307a8a21-15bc-407a-81a3-07b525b25408
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045780215 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_entropy.2045780215
Directory /workspace/48.alert_handler_entropy/latest

Test location /workspace/coverage/default/48.alert_handler_esc_alert_accum.448013169
Short name T653
Test name
Test status
Simulation time 10792872574 ps
CPU time 159.05 seconds
Started Jan 24 01:51:25 PM PST 24
Finished Jan 24 01:54:05 PM PST 24
Peak memory 250216 kb
Host smart-c0036ab4-24a8-4320-9989-dd4419c84be6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44801
3169 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_alert_accum.448013169
Directory /workspace/48.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/48.alert_handler_esc_intr_timeout.1256671093
Short name T551
Test name
Test status
Simulation time 457107654 ps
CPU time 30.44 seconds
Started Jan 24 01:51:25 PM PST 24
Finished Jan 24 01:51:57 PM PST 24
Peak memory 247000 kb
Host smart-3f796854-9baf-4ff3-9686-ab6e0996771c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12566
71093 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_intr_timeout.1256671093
Directory /workspace/48.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_lpg.658156708
Short name T310
Test name
Test status
Simulation time 180657266673 ps
CPU time 1852.68 seconds
Started Jan 24 01:51:33 PM PST 24
Finished Jan 24 02:22:32 PM PST 24
Peak memory 272780 kb
Host smart-f3ee1d96-cbfb-4a93-b982-6775c1f1ba80
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658156708 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg.658156708
Directory /workspace/48.alert_handler_lpg/latest

Test location /workspace/coverage/default/48.alert_handler_lpg_stub_clk.2945838404
Short name T705
Test name
Test status
Simulation time 37860221761 ps
CPU time 2716.05 seconds
Started Jan 24 01:51:33 PM PST 24
Finished Jan 24 02:36:56 PM PST 24
Peak memory 288996 kb
Host smart-2129488e-290b-4298-9f49-63de8f42d62c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945838404 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg_stub_clk.2945838404
Directory /workspace/48.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/48.alert_handler_ping_timeout.403371760
Short name T7
Test name
Test status
Simulation time 38466636165 ps
CPU time 451.22 seconds
Started Jan 24 01:51:35 PM PST 24
Finished Jan 24 01:59:13 PM PST 24
Peak memory 252804 kb
Host smart-906a0379-2af3-45cb-8120-1f9c93664f37
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403371760 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_ping_timeout.403371760
Directory /workspace/48.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_random_alerts.1271131465
Short name T247
Test name
Test status
Simulation time 2290328508 ps
CPU time 33.52 seconds
Started Jan 24 01:51:32 PM PST 24
Finished Jan 24 01:52:12 PM PST 24
Peak memory 248048 kb
Host smart-cb1bc1f5-674d-44c3-b641-455dfdaa095e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12711
31465 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_alerts.1271131465
Directory /workspace/48.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/48.alert_handler_random_classes.3913042596
Short name T1
Test name
Test status
Simulation time 166880156 ps
CPU time 23.27 seconds
Started Jan 24 01:51:25 PM PST 24
Finished Jan 24 01:51:49 PM PST 24
Peak memory 248012 kb
Host smart-0624fa95-49c9-44b7-bbca-9a1b6b631ae7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39130
42596 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_classes.3913042596
Directory /workspace/48.alert_handler_random_classes/latest

Test location /workspace/coverage/default/48.alert_handler_sig_int_fail.921312512
Short name T281
Test name
Test status
Simulation time 272509075 ps
CPU time 34.47 seconds
Started Jan 24 01:51:35 PM PST 24
Finished Jan 24 01:52:17 PM PST 24
Peak memory 249088 kb
Host smart-e83756a7-f40d-46fb-8903-15c56faaa48d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92131
2512 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_sig_int_fail.921312512
Directory /workspace/48.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/48.alert_handler_smoke.510221580
Short name T588
Test name
Test status
Simulation time 138724182 ps
CPU time 11.04 seconds
Started Jan 24 01:51:15 PM PST 24
Finished Jan 24 01:51:29 PM PST 24
Peak memory 248068 kb
Host smart-c9a70c1f-8b0b-4c06-b7c7-6aa16ff6789e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51022
1580 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_smoke.510221580
Directory /workspace/48.alert_handler_smoke/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all.705646357
Short name T61
Test name
Test status
Simulation time 1903482166 ps
CPU time 58.33 seconds
Started Jan 24 01:51:42 PM PST 24
Finished Jan 24 01:52:45 PM PST 24
Peak memory 248292 kb
Host smart-29d4f8c7-9eee-46a0-82e8-373335545b02
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705646357 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_han
dler_stress_all.705646357
Directory /workspace/48.alert_handler_stress_all/latest

Test location /workspace/coverage/default/49.alert_handler_entropy.3875049346
Short name T508
Test name
Test status
Simulation time 100558030049 ps
CPU time 1649.91 seconds
Started Jan 24 01:52:03 PM PST 24
Finished Jan 24 02:19:41 PM PST 24
Peak memory 272080 kb
Host smart-9b7da9d0-c662-4b89-af30-1b2bc154d2b1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875049346 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_entropy.3875049346
Directory /workspace/49.alert_handler_entropy/latest

Test location /workspace/coverage/default/49.alert_handler_esc_alert_accum.1320465027
Short name T375
Test name
Test status
Simulation time 7098745925 ps
CPU time 142.4 seconds
Started Jan 24 01:51:54 PM PST 24
Finished Jan 24 01:54:24 PM PST 24
Peak memory 248196 kb
Host smart-bfe8a82d-21b6-4e7d-83e6-c4b3ab8854ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13204
65027 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_alert_accum.1320465027
Directory /workspace/49.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/49.alert_handler_esc_intr_timeout.3286388477
Short name T421
Test name
Test status
Simulation time 1856111712 ps
CPU time 57.88 seconds
Started Jan 24 01:51:53 PM PST 24
Finished Jan 24 01:52:57 PM PST 24
Peak memory 247268 kb
Host smart-cf65fcf4-3824-42d1-a599-6cedb6559d80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32863
88477 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_intr_timeout.3286388477
Directory /workspace/49.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_lpg.1224613782
Short name T15
Test name
Test status
Simulation time 59227038665 ps
CPU time 1500.04 seconds
Started Jan 24 01:52:00 PM PST 24
Finished Jan 24 02:17:05 PM PST 24
Peak memory 264164 kb
Host smart-ed89323f-af5d-44e6-bf9a-6b2781ee5b11
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224613782 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg.1224613782
Directory /workspace/49.alert_handler_lpg/latest

Test location /workspace/coverage/default/49.alert_handler_lpg_stub_clk.3442583115
Short name T127
Test name
Test status
Simulation time 42597872164 ps
CPU time 2621.46 seconds
Started Jan 24 01:54:01 PM PST 24
Finished Jan 24 02:37:44 PM PST 24
Peak memory 272080 kb
Host smart-2744aca7-5fa9-4cf8-beb8-1846cb145ba3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442583115 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg_stub_clk.3442583115
Directory /workspace/49.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/49.alert_handler_ping_timeout.388171942
Short name T14
Test name
Test status
Simulation time 9545179061 ps
CPU time 207.49 seconds
Started Jan 24 01:52:00 PM PST 24
Finished Jan 24 01:55:32 PM PST 24
Peak memory 248208 kb
Host smart-054c16eb-ec90-45a4-a50d-7f5bc3e31151
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388171942 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_ping_timeout.388171942
Directory /workspace/49.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_random_alerts.2651381731
Short name T432
Test name
Test status
Simulation time 397077625 ps
CPU time 36.38 seconds
Started Jan 24 01:51:44 PM PST 24
Finished Jan 24 01:52:25 PM PST 24
Peak memory 248052 kb
Host smart-fab23999-f61e-4d1f-b702-182e50278c2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26513
81731 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_alerts.2651381731
Directory /workspace/49.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/49.alert_handler_random_classes.467703545
Short name T634
Test name
Test status
Simulation time 234599037 ps
CPU time 9.64 seconds
Started Jan 24 01:51:53 PM PST 24
Finished Jan 24 01:52:10 PM PST 24
Peak memory 248052 kb
Host smart-b1ca8503-c5dc-41bf-b98c-728c4a97996b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46770
3545 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_classes.467703545
Directory /workspace/49.alert_handler_random_classes/latest

Test location /workspace/coverage/default/49.alert_handler_sig_int_fail.2429096322
Short name T273
Test name
Test status
Simulation time 1888603686 ps
CPU time 66.95 seconds
Started Jan 24 01:51:52 PM PST 24
Finished Jan 24 01:53:04 PM PST 24
Peak memory 248016 kb
Host smart-891a3b35-55c5-4ae7-831e-3e1ec2af77c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24290
96322 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_sig_int_fail.2429096322
Directory /workspace/49.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/49.alert_handler_smoke.149340523
Short name T673
Test name
Test status
Simulation time 556719437 ps
CPU time 18.24 seconds
Started Jan 24 01:51:44 PM PST 24
Finished Jan 24 01:52:07 PM PST 24
Peak memory 248052 kb
Host smart-1320e1d4-fdda-43eb-921c-3f37a7e66784
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14934
0523 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_smoke.149340523
Directory /workspace/49.alert_handler_smoke/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all_with_rand_reset.2995244265
Short name T278
Test name
Test status
Simulation time 980259441082 ps
CPU time 4906.38 seconds
Started Jan 24 01:53:57 PM PST 24
Finished Jan 24 03:15:46 PM PST 24
Peak memory 353888 kb
Host smart-39f21171-b72c-4cab-a01a-eff616c2398d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995244265 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 49.alert_handler_stress_all_with_rand_reset.2995244265
Directory /workspace/49.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.alert_handler_alert_accum_saturation.410848999
Short name T218
Test name
Test status
Simulation time 39875340 ps
CPU time 3.35 seconds
Started Jan 24 01:39:37 PM PST 24
Finished Jan 24 01:40:33 PM PST 24
Peak memory 249432 kb
Host smart-ce415605-971d-45f5-94cf-56633abe15b8
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=410848999 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_alert_accum_saturation.410848999
Directory /workspace/5.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/5.alert_handler_entropy.670858663
Short name T498
Test name
Test status
Simulation time 7232803932 ps
CPU time 866.11 seconds
Started Jan 24 02:05:20 PM PST 24
Finished Jan 24 02:20:35 PM PST 24
Peak memory 272152 kb
Host smart-ede6ba2f-006c-4dc1-ad59-4d4b43b4b4b8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670858663 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy.670858663
Directory /workspace/5.alert_handler_entropy/latest

Test location /workspace/coverage/default/5.alert_handler_entropy_stress.3827424651
Short name T490
Test name
Test status
Simulation time 498492465 ps
CPU time 22.68 seconds
Started Jan 24 01:39:36 PM PST 24
Finished Jan 24 01:40:52 PM PST 24
Peak memory 239772 kb
Host smart-daf01a2e-63d2-4807-bef7-1765fea20424
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3827424651 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy_stress.3827424651
Directory /workspace/5.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/5.alert_handler_esc_alert_accum.3271139723
Short name T583
Test name
Test status
Simulation time 3191675242 ps
CPU time 62.91 seconds
Started Jan 24 01:39:37 PM PST 24
Finished Jan 24 01:41:51 PM PST 24
Peak memory 250192 kb
Host smart-5c3f9100-e156-441d-bd11-861bd423e130
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32711
39723 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_alert_accum.3271139723
Directory /workspace/5.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/5.alert_handler_esc_intr_timeout.1606777657
Short name T639
Test name
Test status
Simulation time 532843627 ps
CPU time 13.37 seconds
Started Jan 24 01:39:37 PM PST 24
Finished Jan 24 01:40:43 PM PST 24
Peak memory 248016 kb
Host smart-39900c15-f8c8-4cb8-90ac-5ba1aa29e0a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16067
77657 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_intr_timeout.1606777657
Directory /workspace/5.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_lpg.1370579308
Short name T309
Test name
Test status
Simulation time 78407492418 ps
CPU time 2427.11 seconds
Started Jan 24 01:39:37 PM PST 24
Finished Jan 24 02:20:57 PM PST 24
Peak memory 288364 kb
Host smart-08f92c8b-f481-42a1-933e-0d6eb9a6325d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370579308 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg.1370579308
Directory /workspace/5.alert_handler_lpg/latest

Test location /workspace/coverage/default/5.alert_handler_lpg_stub_clk.2323317126
Short name T582
Test name
Test status
Simulation time 111176197361 ps
CPU time 1834.27 seconds
Started Jan 24 02:11:48 PM PST 24
Finished Jan 24 02:43:00 PM PST 24
Peak memory 272428 kb
Host smart-aeac75f5-c347-411d-9da6-a524d8d289d0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323317126 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg_stub_clk.2323317126
Directory /workspace/5.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/5.alert_handler_ping_timeout.332510115
Short name T679
Test name
Test status
Simulation time 6167878875 ps
CPU time 273.61 seconds
Started Jan 24 01:39:42 PM PST 24
Finished Jan 24 01:45:14 PM PST 24
Peak memory 246508 kb
Host smart-08ac862d-8db5-4954-af93-1c67ec6a8bb5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332510115 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_ping_timeout.332510115
Directory /workspace/5.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_random_alerts.2503053709
Short name T507
Test name
Test status
Simulation time 1253994487 ps
CPU time 42.55 seconds
Started Jan 24 01:39:37 PM PST 24
Finished Jan 24 01:41:31 PM PST 24
Peak memory 247644 kb
Host smart-0a165dc6-be2a-4846-90e1-63971b032e8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25030
53709 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_alerts.2503053709
Directory /workspace/5.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/5.alert_handler_random_classes.887182890
Short name T516
Test name
Test status
Simulation time 993830917 ps
CPU time 17.29 seconds
Started Jan 24 01:39:37 PM PST 24
Finished Jan 24 01:41:05 PM PST 24
Peak memory 249256 kb
Host smart-b0ed976d-2614-4e9b-82c2-a537b26b6d82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88718
2890 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_classes.887182890
Directory /workspace/5.alert_handler_random_classes/latest

Test location /workspace/coverage/default/5.alert_handler_sig_int_fail.2600278805
Short name T290
Test name
Test status
Simulation time 2021956540 ps
CPU time 21.32 seconds
Started Jan 24 01:39:37 PM PST 24
Finished Jan 24 01:41:09 PM PST 24
Peak memory 250244 kb
Host smart-5b28a9b8-742a-493e-a2ed-10b7030ea74d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26002
78805 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_sig_int_fail.2600278805
Directory /workspace/5.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/5.alert_handler_smoke.838288932
Short name T444
Test name
Test status
Simulation time 2343572469 ps
CPU time 35.25 seconds
Started Jan 24 01:46:00 PM PST 24
Finished Jan 24 01:46:59 PM PST 24
Peak memory 250492 kb
Host smart-71be5e28-d5a5-41fb-b179-4003f1f02d43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83828
8932 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_smoke.838288932
Directory /workspace/5.alert_handler_smoke/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all.3830927416
Short name T60
Test name
Test status
Simulation time 13442165872 ps
CPU time 1263.02 seconds
Started Jan 24 01:39:36 PM PST 24
Finished Jan 24 02:01:28 PM PST 24
Peak memory 281968 kb
Host smart-6a3585df-5c5c-402c-a987-c34b0e4a1e21
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830927416 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_han
dler_stress_all.3830927416
Directory /workspace/5.alert_handler_stress_all/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all_with_rand_reset.978066996
Short name T274
Test name
Test status
Simulation time 34859940627 ps
CPU time 2317.37 seconds
Started Jan 24 01:59:53 PM PST 24
Finished Jan 24 02:38:33 PM PST 24
Peak memory 287708 kb
Host smart-656d9033-f5f6-4e79-93b1-4143f89635cc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978066996 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 5.alert_handler_stress_all_with_rand_reset.978066996
Directory /workspace/5.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.alert_handler_alert_accum_saturation.3265148482
Short name T234
Test name
Test status
Simulation time 45954777 ps
CPU time 2.66 seconds
Started Jan 24 02:58:37 PM PST 24
Finished Jan 24 02:58:46 PM PST 24
Peak memory 249380 kb
Host smart-a033fb00-9b71-430c-a829-a394ddbd1059
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3265148482 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_alert_accum_saturation.3265148482
Directory /workspace/6.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/6.alert_handler_entropy.1233914211
Short name T482
Test name
Test status
Simulation time 13502369692 ps
CPU time 1397.91 seconds
Started Jan 24 01:39:36 PM PST 24
Finished Jan 24 02:03:47 PM PST 24
Peak memory 287792 kb
Host smart-c925e972-fa7d-4411-bbda-047c04a170e3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233914211 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy.1233914211
Directory /workspace/6.alert_handler_entropy/latest

Test location /workspace/coverage/default/6.alert_handler_entropy_stress.336868769
Short name T518
Test name
Test status
Simulation time 3595443301 ps
CPU time 146.74 seconds
Started Jan 24 01:39:40 PM PST 24
Finished Jan 24 01:43:08 PM PST 24
Peak memory 248036 kb
Host smart-8e392e0d-dd47-4eea-a286-b96e1b0f76b8
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=336868769 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy_stress.336868769
Directory /workspace/6.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/6.alert_handler_esc_alert_accum.3039285110
Short name T510
Test name
Test status
Simulation time 1941907741 ps
CPU time 164.48 seconds
Started Jan 24 01:46:21 PM PST 24
Finished Jan 24 01:49:23 PM PST 24
Peak memory 250116 kb
Host smart-dafec80e-6f70-4698-ad46-dffffaba7fbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30392
85110 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_alert_accum.3039285110
Directory /workspace/6.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/6.alert_handler_esc_intr_timeout.2066696384
Short name T596
Test name
Test status
Simulation time 81483353 ps
CPU time 5.44 seconds
Started Jan 24 02:31:25 PM PST 24
Finished Jan 24 02:31:38 PM PST 24
Peak memory 237924 kb
Host smart-30c418fc-3ffd-4b70-b121-1a4c9dee5d23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20666
96384 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_intr_timeout.2066696384
Directory /workspace/6.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_lpg.1515693810
Short name T332
Test name
Test status
Simulation time 23968152296 ps
CPU time 907.93 seconds
Started Jan 24 01:39:40 PM PST 24
Finished Jan 24 01:55:59 PM PST 24
Peak memory 271936 kb
Host smart-af726acb-7ff6-4271-822e-1c9f311b111f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515693810 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg.1515693810
Directory /workspace/6.alert_handler_lpg/latest

Test location /workspace/coverage/default/6.alert_handler_lpg_stub_clk.4095517155
Short name T426
Test name
Test status
Simulation time 160484537921 ps
CPU time 1796.43 seconds
Started Jan 24 01:39:42 PM PST 24
Finished Jan 24 02:10:42 PM PST 24
Peak memory 271700 kb
Host smart-90ca1429-3680-4a7a-a741-18424b013cec
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095517155 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg_stub_clk.4095517155
Directory /workspace/6.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/6.alert_handler_ping_timeout.213913094
Short name T325
Test name
Test status
Simulation time 25821148739 ps
CPU time 277.68 seconds
Started Jan 24 01:56:21 PM PST 24
Finished Jan 24 02:01:02 PM PST 24
Peak memory 250364 kb
Host smart-3de6a4cb-a7ab-4096-a4e5-7cbdefe26359
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=213913094 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_ping_timeout.213913094
Directory /workspace/6.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_random_alerts.3902648866
Short name T424
Test name
Test status
Simulation time 799269293 ps
CPU time 46.15 seconds
Started Jan 24 01:39:40 PM PST 24
Finished Jan 24 01:41:28 PM PST 24
Peak memory 247920 kb
Host smart-385c6fda-0724-47ca-8e7c-3fc67321216f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39026
48866 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_alerts.3902648866
Directory /workspace/6.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/6.alert_handler_random_classes.725464312
Short name T609
Test name
Test status
Simulation time 4710997965 ps
CPU time 30.82 seconds
Started Jan 24 01:55:34 PM PST 24
Finished Jan 24 01:56:07 PM PST 24
Peak memory 248180 kb
Host smart-079dd683-5b69-404a-bf88-c78940518234
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72546
4312 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_classes.725464312
Directory /workspace/6.alert_handler_random_classes/latest

Test location /workspace/coverage/default/6.alert_handler_smoke.1485748173
Short name T599
Test name
Test status
Simulation time 251807198 ps
CPU time 16.99 seconds
Started Jan 24 01:39:40 PM PST 24
Finished Jan 24 01:40:58 PM PST 24
Peak memory 247880 kb
Host smart-73ce5abd-0813-4e7f-9680-ffc01818875b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14857
48173 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_smoke.1485748173
Directory /workspace/6.alert_handler_smoke/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all.2170685196
Short name T559
Test name
Test status
Simulation time 102946094517 ps
CPU time 1310.21 seconds
Started Jan 24 01:39:42 PM PST 24
Finished Jan 24 02:02:35 PM PST 24
Peak memory 288556 kb
Host smart-ff0f02d9-26de-4015-9a19-14b6c0929b9f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170685196 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_han
dler_stress_all.2170685196
Directory /workspace/6.alert_handler_stress_all/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all_with_rand_reset.3626192526
Short name T81
Test name
Test status
Simulation time 50677592304 ps
CPU time 4172.05 seconds
Started Jan 24 02:00:14 PM PST 24
Finished Jan 24 03:09:51 PM PST 24
Peak memory 284720 kb
Host smart-a3120c3f-89ec-4483-be6c-9dc212a3918d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626192526 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 6.alert_handler_stress_all_with_rand_reset.3626192526
Directory /workspace/6.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.alert_handler_alert_accum_saturation.3223761238
Short name T74
Test name
Test status
Simulation time 48827244 ps
CPU time 3.97 seconds
Started Jan 24 02:42:09 PM PST 24
Finished Jan 24 02:42:19 PM PST 24
Peak memory 248344 kb
Host smart-302332dd-fd6e-4722-9afd-28ee7066074b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3223761238 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_alert_accum_saturation.3223761238
Directory /workspace/7.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/7.alert_handler_entropy.1988460646
Short name T548
Test name
Test status
Simulation time 27265135438 ps
CPU time 1972.64 seconds
Started Jan 24 01:39:44 PM PST 24
Finished Jan 24 02:13:46 PM PST 24
Peak memory 283564 kb
Host smart-269cac61-b2f8-4e7c-abe0-bda829292745
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1988460646 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy.1988460646
Directory /workspace/7.alert_handler_entropy/latest

Test location /workspace/coverage/default/7.alert_handler_entropy_stress.4169003673
Short name T684
Test name
Test status
Simulation time 2440303271 ps
CPU time 22.84 seconds
Started Jan 24 01:39:44 PM PST 24
Finished Jan 24 01:41:16 PM PST 24
Peak memory 239960 kb
Host smart-86cdb150-0aa6-4b0e-b656-906056250c4b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4169003673 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy_stress.4169003673
Directory /workspace/7.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/7.alert_handler_esc_alert_accum.3629797679
Short name T52
Test name
Test status
Simulation time 2004254900 ps
CPU time 108.65 seconds
Started Jan 24 01:39:44 PM PST 24
Finished Jan 24 01:42:42 PM PST 24
Peak memory 250408 kb
Host smart-ef21c693-0aba-448f-9bae-548ea8ade89d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36297
97679 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_alert_accum.3629797679
Directory /workspace/7.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/7.alert_handler_esc_intr_timeout.3328556192
Short name T405
Test name
Test status
Simulation time 1022659483 ps
CPU time 25.78 seconds
Started Jan 24 01:39:44 PM PST 24
Finished Jan 24 01:41:19 PM PST 24
Peak memory 247212 kb
Host smart-d46c4ae1-4c99-45de-a3df-c87d7407a936
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33285
56192 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_intr_timeout.3328556192
Directory /workspace/7.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_lpg.1348267714
Short name T632
Test name
Test status
Simulation time 28429323658 ps
CPU time 1495.19 seconds
Started Jan 24 01:39:44 PM PST 24
Finished Jan 24 02:05:48 PM PST 24
Peak memory 272032 kb
Host smart-7bf5323e-c4ff-4d18-b1fb-7f44b5613f46
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348267714 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg.1348267714
Directory /workspace/7.alert_handler_lpg/latest

Test location /workspace/coverage/default/7.alert_handler_lpg_stub_clk.3338905333
Short name T598
Test name
Test status
Simulation time 86321736182 ps
CPU time 1402.47 seconds
Started Jan 24 02:32:18 PM PST 24
Finished Jan 24 02:56:14 PM PST 24
Peak memory 272168 kb
Host smart-d03947eb-e6a0-43c2-a314-673dcffdf732
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338905333 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg_stub_clk.3338905333
Directory /workspace/7.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/7.alert_handler_ping_timeout.145872531
Short name T511
Test name
Test status
Simulation time 16025809301 ps
CPU time 300.75 seconds
Started Jan 24 01:39:36 PM PST 24
Finished Jan 24 01:45:30 PM PST 24
Peak memory 246560 kb
Host smart-1fa5f70e-98d1-4937-acb1-e9f2e501a7f8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145872531 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_ping_timeout.145872531
Directory /workspace/7.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_random_alerts.1666337760
Short name T352
Test name
Test status
Simulation time 454661056 ps
CPU time 17.69 seconds
Started Jan 24 01:39:43 PM PST 24
Finished Jan 24 01:41:08 PM PST 24
Peak memory 248060 kb
Host smart-cbd8470b-4561-4f88-8350-988d84fd7a76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16663
37760 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_alerts.1666337760
Directory /workspace/7.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/7.alert_handler_random_classes.140331714
Short name T538
Test name
Test status
Simulation time 426451823 ps
CPU time 41.32 seconds
Started Jan 24 01:39:44 PM PST 24
Finished Jan 24 01:41:34 PM PST 24
Peak memory 247984 kb
Host smart-2a14682a-f2c5-44a1-be01-48cb42806860
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14033
1714 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_classes.140331714
Directory /workspace/7.alert_handler_random_classes/latest

Test location /workspace/coverage/default/7.alert_handler_sig_int_fail.2615785260
Short name T618
Test name
Test status
Simulation time 334852598 ps
CPU time 6.6 seconds
Started Jan 24 03:46:40 PM PST 24
Finished Jan 24 03:46:49 PM PST 24
Peak memory 249156 kb
Host smart-d9ea5896-53f9-49e0-8e32-b7ba99f5b789
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26157
85260 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_sig_int_fail.2615785260
Directory /workspace/7.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/7.alert_handler_smoke.176155661
Short name T427
Test name
Test status
Simulation time 396167058 ps
CPU time 16.59 seconds
Started Jan 24 02:19:04 PM PST 24
Finished Jan 24 02:19:32 PM PST 24
Peak memory 248068 kb
Host smart-f6ded044-aca3-416d-a4a6-bc803cdab1d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17615
5661 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_smoke.176155661
Directory /workspace/7.alert_handler_smoke/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all_with_rand_reset.3352643341
Short name T404
Test name
Test status
Simulation time 56861976238 ps
CPU time 5483.95 seconds
Started Jan 24 01:39:34 PM PST 24
Finished Jan 24 03:11:43 PM PST 24
Peak memory 330176 kb
Host smart-77677c83-123e-4941-92d4-e8636d8fe1b9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352643341 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.alert_handler_stress_all_with_rand_reset.3352643341
Directory /workspace/7.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.alert_handler_alert_accum_saturation.3578541171
Short name T219
Test name
Test status
Simulation time 22518096 ps
CPU time 2.33 seconds
Started Jan 24 01:39:40 PM PST 24
Finished Jan 24 01:40:43 PM PST 24
Peak memory 248264 kb
Host smart-4721dbca-c4c4-48ca-b757-00f19e8a1ff2
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3578541171 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_alert_accum_saturation.3578541171
Directory /workspace/8.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/8.alert_handler_entropy.28555320
Short name T708
Test name
Test status
Simulation time 72355139266 ps
CPU time 1430.21 seconds
Started Jan 24 02:50:59 PM PST 24
Finished Jan 24 03:15:04 PM PST 24
Peak memory 288720 kb
Host smart-bdb12675-5dd0-4c04-b9c4-5bf5b061348d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28555320 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy.28555320
Directory /workspace/8.alert_handler_entropy/latest

Test location /workspace/coverage/default/8.alert_handler_entropy_stress.1478820777
Short name T368
Test name
Test status
Simulation time 562338028 ps
CPU time 8.64 seconds
Started Jan 24 01:39:46 PM PST 24
Finished Jan 24 01:40:49 PM PST 24
Peak memory 239808 kb
Host smart-486b81ae-155f-4e6f-836a-7bbf27318606
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1478820777 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy_stress.1478820777
Directory /workspace/8.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/8.alert_handler_esc_alert_accum.1610262068
Short name T671
Test name
Test status
Simulation time 8950252925 ps
CPU time 67.65 seconds
Started Jan 24 01:43:37 PM PST 24
Finished Jan 24 01:45:00 PM PST 24
Peak memory 248160 kb
Host smart-36d9399d-3739-4187-86d0-989498739c90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16102
62068 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_alert_accum.1610262068
Directory /workspace/8.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/8.alert_handler_esc_intr_timeout.3042511786
Short name T485
Test name
Test status
Simulation time 589082587 ps
CPU time 10.53 seconds
Started Jan 24 01:39:39 PM PST 24
Finished Jan 24 01:40:56 PM PST 24
Peak memory 248176 kb
Host smart-650b1df4-3877-4895-8567-ed6cbd1b68b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30425
11786 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_intr_timeout.3042511786
Directory /workspace/8.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_lpg.1478666588
Short name T331
Test name
Test status
Simulation time 24727928948 ps
CPU time 1533.7 seconds
Started Jan 24 02:14:16 PM PST 24
Finished Jan 24 02:40:08 PM PST 24
Peak memory 272124 kb
Host smart-758eb2bc-1241-43e4-9a01-5e5e8f8fcf49
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478666588 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg.1478666588
Directory /workspace/8.alert_handler_lpg/latest

Test location /workspace/coverage/default/8.alert_handler_lpg_stub_clk.1081193286
Short name T522
Test name
Test status
Simulation time 93397210995 ps
CPU time 2401.22 seconds
Started Jan 24 01:39:39 PM PST 24
Finished Jan 24 02:20:42 PM PST 24
Peak memory 285212 kb
Host smart-f60e697c-a70b-4867-8ea4-a6ff26fc6ba0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081193286 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg_stub_clk.1081193286
Directory /workspace/8.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/8.alert_handler_random_alerts.485579968
Short name T475
Test name
Test status
Simulation time 604640962 ps
CPU time 34.56 seconds
Started Jan 24 02:15:33 PM PST 24
Finished Jan 24 02:16:51 PM PST 24
Peak memory 248068 kb
Host smart-070403f0-08bd-431b-bab3-acdd227cc1f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48557
9968 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_alerts.485579968
Directory /workspace/8.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/8.alert_handler_random_classes.2987516489
Short name T513
Test name
Test status
Simulation time 321861277 ps
CPU time 4.19 seconds
Started Jan 24 01:39:44 PM PST 24
Finished Jan 24 01:40:57 PM PST 24
Peak memory 237784 kb
Host smart-14af6c5d-8538-459d-aa22-9bd12b87bf05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29875
16489 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_classes.2987516489
Directory /workspace/8.alert_handler_random_classes/latest

Test location /workspace/coverage/default/8.alert_handler_sig_int_fail.2461955625
Short name T448
Test name
Test status
Simulation time 779724176 ps
CPU time 47.18 seconds
Started Jan 24 01:39:46 PM PST 24
Finished Jan 24 01:41:28 PM PST 24
Peak memory 247036 kb
Host smart-15f91735-4a45-4f06-a1ba-a43c287dff47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24619
55625 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_sig_int_fail.2461955625
Directory /workspace/8.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/8.alert_handler_smoke.3277697581
Short name T546
Test name
Test status
Simulation time 690751235 ps
CPU time 20.85 seconds
Started Jan 24 01:39:38 PM PST 24
Finished Jan 24 01:41:08 PM PST 24
Peak memory 251176 kb
Host smart-9f693118-1c7e-4b4c-9ecc-bdb1c5c4c128
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32776
97581 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_smoke.3277697581
Directory /workspace/8.alert_handler_smoke/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all.1889982048
Short name T288
Test name
Test status
Simulation time 58919589980 ps
CPU time 873.69 seconds
Started Jan 24 02:58:08 PM PST 24
Finished Jan 24 03:12:49 PM PST 24
Peak memory 272812 kb
Host smart-0a6900af-470b-46f4-acda-88234c4f689e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889982048 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_han
dler_stress_all.1889982048
Directory /workspace/8.alert_handler_stress_all/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all_with_rand_reset.3570001131
Short name T211
Test name
Test status
Simulation time 155091064191 ps
CPU time 8482.16 seconds
Started Jan 24 01:40:09 PM PST 24
Finished Jan 24 04:02:27 PM PST 24
Peak memory 411528 kb
Host smart-d3d52eca-6330-446b-9ce7-2426394c79be
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570001131 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 8.alert_handler_stress_all_with_rand_reset.3570001131
Directory /workspace/8.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.alert_handler_alert_accum_saturation.2395699390
Short name T117
Test name
Test status
Simulation time 32083842 ps
CPU time 3.09 seconds
Started Jan 24 01:40:16 PM PST 24
Finished Jan 24 01:41:16 PM PST 24
Peak memory 248312 kb
Host smart-e7dd7aea-4863-433a-969c-8c078144be5d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2395699390 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_alert_accum_saturation.2395699390
Directory /workspace/9.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/9.alert_handler_entropy.1737793174
Short name T493
Test name
Test status
Simulation time 57558930749 ps
CPU time 703.1 seconds
Started Jan 24 01:46:09 PM PST 24
Finished Jan 24 01:58:16 PM PST 24
Peak memory 266540 kb
Host smart-1f636252-44bf-4053-bf72-5483400998dc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737793174 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy.1737793174
Directory /workspace/9.alert_handler_entropy/latest

Test location /workspace/coverage/default/9.alert_handler_entropy_stress.3008155916
Short name T472
Test name
Test status
Simulation time 9830983801 ps
CPU time 72.82 seconds
Started Jan 24 01:40:13 PM PST 24
Finished Jan 24 01:42:22 PM PST 24
Peak memory 248100 kb
Host smart-ce254c69-a171-42ef-adcb-c826ba03ee1d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3008155916 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy_stress.3008155916
Directory /workspace/9.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/9.alert_handler_esc_alert_accum.716150882
Short name T610
Test name
Test status
Simulation time 2034253528 ps
CPU time 125.66 seconds
Started Jan 24 01:52:05 PM PST 24
Finished Jan 24 01:54:18 PM PST 24
Peak memory 249088 kb
Host smart-393b00d5-eaad-4de1-8c60-443777516c25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71615
0882 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_alert_accum.716150882
Directory /workspace/9.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/9.alert_handler_esc_intr_timeout.1752252022
Short name T601
Test name
Test status
Simulation time 2793947527 ps
CPU time 38.28 seconds
Started Jan 24 01:40:15 PM PST 24
Finished Jan 24 01:41:50 PM PST 24
Peak memory 248320 kb
Host smart-c98bfde5-2169-4ddb-983a-34eda7f0a710
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17522
52022 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_intr_timeout.1752252022
Directory /workspace/9.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_lpg.3179623596
Short name T262
Test name
Test status
Simulation time 33166721947 ps
CPU time 1889.68 seconds
Started Jan 24 01:40:21 PM PST 24
Finished Jan 24 02:12:48 PM PST 24
Peak memory 272204 kb
Host smart-7af4cbbb-f764-4510-a86d-f1f732468de8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179623596 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg.3179623596
Directory /workspace/9.alert_handler_lpg/latest

Test location /workspace/coverage/default/9.alert_handler_lpg_stub_clk.3819402044
Short name T535
Test name
Test status
Simulation time 57431976664 ps
CPU time 3444.79 seconds
Started Jan 24 01:40:11 PM PST 24
Finished Jan 24 02:38:32 PM PST 24
Peak memory 288524 kb
Host smart-1abd07fd-d586-4909-85f1-d550389f334a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819402044 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg_stub_clk.3819402044
Directory /workspace/9.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/9.alert_handler_ping_timeout.683018426
Short name T308
Test name
Test status
Simulation time 10295411794 ps
CPU time 214.03 seconds
Started Jan 24 01:40:22 PM PST 24
Finished Jan 24 01:44:52 PM PST 24
Peak memory 249236 kb
Host smart-ef718da1-56e8-4e81-a197-3229cb8891e9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683018426 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_ping_timeout.683018426
Directory /workspace/9.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_random_alerts.2510854660
Short name T363
Test name
Test status
Simulation time 691654695 ps
CPU time 33.18 seconds
Started Jan 24 01:40:12 PM PST 24
Finished Jan 24 01:41:42 PM PST 24
Peak memory 247988 kb
Host smart-77d2ee32-c9fe-4908-a707-c78807c998ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25108
54660 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_alerts.2510854660
Directory /workspace/9.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/9.alert_handler_random_classes.3491646898
Short name T563
Test name
Test status
Simulation time 2907504588 ps
CPU time 76.28 seconds
Started Jan 24 01:40:07 PM PST 24
Finished Jan 24 01:42:17 PM PST 24
Peak memory 255256 kb
Host smart-2f7e996f-7b0f-4a63-aa0c-3f55b510e89b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34916
46898 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_classes.3491646898
Directory /workspace/9.alert_handler_random_classes/latest

Test location /workspace/coverage/default/9.alert_handler_sig_int_fail.3319279692
Short name T401
Test name
Test status
Simulation time 850903738 ps
CPU time 9.21 seconds
Started Jan 24 01:40:09 PM PST 24
Finished Jan 24 01:41:13 PM PST 24
Peak memory 245928 kb
Host smart-711f6d33-5d5d-4d41-ab0e-5b660d57a27d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33192
79692 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_sig_int_fail.3319279692
Directory /workspace/9.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/9.alert_handler_smoke.2701154771
Short name T458
Test name
Test status
Simulation time 3395907641 ps
CPU time 37.93 seconds
Started Jan 24 01:40:12 PM PST 24
Finished Jan 24 01:41:46 PM PST 24
Peak memory 249100 kb
Host smart-3cc3eef4-bd81-4d15-9608-c8b44c28aaed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27011
54771 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_smoke.2701154771
Directory /workspace/9.alert_handler_smoke/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all.3751554018
Short name T253
Test name
Test status
Simulation time 173583681922 ps
CPU time 2599.1 seconds
Started Jan 24 01:40:20 PM PST 24
Finished Jan 24 02:24:36 PM PST 24
Peak memory 285028 kb
Host smart-7e8c021e-b430-4a2c-8888-0de1704eeb86
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751554018 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_han
dler_stress_all.3751554018
Directory /workspace/9.alert_handler_stress_all/latest
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