Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
esc_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	8	0	8	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	79186	1			T22	3753		T8	6		T9	1
class_i[0x1]	45496	1			T16	2731		T9	1		T10	81
class_i[0x2]	71210	1			T6	4444		T9	1		T10	22
class_i[0x3]	68455	1			T16	21		T10	173		T33	1

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Summary for Variable esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	64761	1			T22	914		T6	1212		T16	694
alert[0x1]	65041	1			T22	975		T6	1114		T16	723
alert[0x2]	66990	1			T22	925		T6	1087		T16	652
alert[0x3]	67555	1			T22	939		T6	1031		T16	683

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Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

esc_integrity_fail

264071

1

T22

3753

T6

4444

T16

2752

esc_ping_fail

276

1

T8

6

T9

3

T186

2

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Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	esc_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	alert[0x0]	64681	1			T22	914		T6	1212		T16	694
esc_integrity_fail	alert[0x1]	64969	1			T22	975		T6	1114		T16	723
esc_integrity_fail	alert[0x2]	66925	1			T22	925		T6	1087		T16	652
esc_integrity_fail	alert[0x3]	67496	1			T22	939		T6	1031		T16	683
esc_ping_fail	alert[0x0]	80	1			T8	2		T9	1		T208	1
esc_ping_fail	alert[0x1]	72	1			T8	2		T9	1		T208	2
esc_ping_fail	alert[0x2]	65	1			T8	1		T208	1		T210	1
esc_ping_fail	alert[0x3]	59	1			T8	1		T9	1		T186	2

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Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	class_i[0x0]	79130	1			T22	3753		T10	4684		T33	7
esc_integrity_fail	class_i[0x1]	45441	1			T16	2731		T10	81		T41	9
esc_integrity_fail	class_i[0x2]	71118	1			T6	4444		T10	22		T33	827
esc_integrity_fail	class_i[0x3]	68382	1			T16	21		T10	173		T33	1
esc_ping_fail	class_i[0x0]	56	1			T8	6		T9	1		T258	1
esc_ping_fail	class_i[0x1]	55	1			T9	1		T258	7		T262	5
esc_ping_fail	class_i[0x2]	92	1			T9	1		T208	1		T210	3
esc_ping_fail	class_i[0x3]	73	1			T186	2		T208	5		T261	8