Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_edn_req.u_prim_packer_fifo.DataOStableWhenPending_A	0	0	766612282	0	0	643
tb.dut.u_edn_req.u_prim_packer_fifo.ValidOPairedWithReadyI_A	0	0	766612282	0	0	0

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.AckPKnownO_A	0	0	766612282	766423669	0	0
tb.dut.CheckAccuCntDw	0	0	643	643	0	0
tb.dut.CheckEscCntDw	0	0	643	643	0	0
tb.dut.CheckNAlerts	0	0	643	643	0	0
tb.dut.CheckNClasses	0	0	643	643	0	0
tb.dut.CheckNEscSev	0	0	643	643	0	0
tb.dut.CrashdumpKnownO_A	0	0	766612282	766423669	0	0
tb.dut.EdnKnownO_A	0	0	766612282	766423669	0	0
tb.dut.EscPKnownO_A	0	0	766612282	766423669	0	0
tb.dut.FpvSecCmPingTimerCnterCheck_A	0	0	766612282	90	0	0
tb.dut.FpvSecCmPingTimerDoubleLfsrCheck_A	0	0	766612282	90	0	0
tb.dut.FpvSecCmPingTimerEscCnterCheck_A	0	0	766612282	90	0	0
tb.dut.FpvSecCmPingTimerFsmCheck_A	0	0	766612282	90	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	766612282	90	0	0
tb.dut.IrqAKnownO_A	0	0	766612282	766423669	0	0
tb.dut.IrqBKnownO_A	0	0	766612282	766423669	0	0
tb.dut.IrqCKnownO_A	0	0	766612282	766423669	0	0
tb.dut.IrqDKnownO_A	0	0	766612282	766423669	0	0
tb.dut.TlAReadyKnownO_A	0	0	766612282	766423669	0	0
tb.dut.TlDValidKnownO_A	0	0	766612282	766423669	0	0
tb.dut.alert_handler_csr_assert.TlulOOBAddrErr_A	0	0	787095701	4246167	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_0_rd_A	0	0	787095701	9222	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_10_rd_A	0	0	787095701	8813	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_11_rd_A	0	0	787095701	9519	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_12_rd_A	0	0	787095701	10290	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_13_rd_A	0	0	787095701	8799	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_14_rd_A	0	0	787095701	8685	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_15_rd_A	0	0	787095701	9510	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_16_rd_A	0	0	787095701	9604	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_17_rd_A	0	0	787095701	8666	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_18_rd_A	0	0	787095701	9254	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_19_rd_A	0	0	787095701	9472	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_1_rd_A	0	0	787095701	9403	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_20_rd_A	0	0	787095701	9588	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_21_rd_A	0	0	787095701	8734	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_22_rd_A	0	0	787095701	9037	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_23_rd_A	0	0	787095701	8439	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_24_rd_A	0	0	787095701	8975	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_25_rd_A	0	0	787095701	9300	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_26_rd_A	0	0	787095701	9235	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_27_rd_A	0	0	787095701	8720	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_28_rd_A	0	0	787095701	9834	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_29_rd_A	0	0	787095701	9847	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_2_rd_A	0	0	787095701	9737	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_30_rd_A	0	0	787095701	8996	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_31_rd_A	0	0	787095701	9637	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_32_rd_A	0	0	787095701	8757	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_33_rd_A	0	0	787095701	8981	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_34_rd_A	0	0	787095701	9942	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_35_rd_A	0	0	787095701	9827	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_36_rd_A	0	0	787095701	10430	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_37_rd_A	0	0	787095701	9184	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_38_rd_A	0	0	787095701	9783	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_39_rd_A	0	0	787095701	9212	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_3_rd_A	0	0	787095701	8711	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_40_rd_A	0	0	787095701	9179	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_41_rd_A	0	0	787095701	9600	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_42_rd_A	0	0	787095701	9714	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_43_rd_A	0	0	787095701	9577	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_44_rd_A	0	0	787095701	8821	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_45_rd_A	0	0	787095701	9160	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_46_rd_A	0	0	787095701	8925	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_47_rd_A	0	0	787095701	9195	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_48_rd_A	0	0	787095701	9481	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_49_rd_A	0	0	787095701	8628	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_4_rd_A	0	0	787095701	8792	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_50_rd_A	0	0	787095701	8912	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_51_rd_A	0	0	787095701	8579	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_52_rd_A	0	0	787095701	9830	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_53_rd_A	0	0	787095701	8688	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_54_rd_A	0	0	787095701	8824	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_55_rd_A	0	0	787095701	8817	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_56_rd_A	0	0	787095701	8955	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_57_rd_A	0	0	787095701	9432	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_58_rd_A	0	0	787095701	8897	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_59_rd_A	0	0	787095701	9352	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_5_rd_A	0	0	787095701	9027	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_60_rd_A	0	0	787095701	9046	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_61_rd_A	0	0	787095701	8763	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_62_rd_A	0	0	787095701	8745	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_63_rd_A	0	0	787095701	8580	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_64_rd_A	0	0	787095701	9523	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_6_rd_A	0	0	787095701	8843	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_7_rd_A	0	0	787095701	9296	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_8_rd_A	0	0	787095701	9171	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_9_rd_A	0	0	787095701	9546	0	0
tb.dut.alert_handler_csr_assert.classa_regwen_rd_A	0	0	787095701	9381	0	0
tb.dut.alert_handler_csr_assert.classb_regwen_rd_A	0	0	787095701	9083	0	0
tb.dut.alert_handler_csr_assert.classc_regwen_rd_A	0	0	787095701	8971	0	0
tb.dut.alert_handler_csr_assert.classd_regwen_rd_A	0	0	787095701	9993	0	0
tb.dut.alert_handler_csr_assert.intr_enable_rd_A	0	0	787095701	12203	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_0_rd_A	0	0	787095701	8864	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_1_rd_A	0	0	787095701	9128	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_2_rd_A	0	0	787095701	9269	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_3_rd_A	0	0	787095701	8767	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_4_rd_A	0	0	787095701	8798	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_5_rd_A	0	0	787095701	9195	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_6_rd_A	0	0	787095701	10176	0	0
tb.dut.alert_handler_csr_assert.ping_timer_regwen_rd_A	0	0	787095701	9491	0	0
tb.dut.gen_classes[0].FpvSecCmAccuCnterCheck_A	0	0	766612282	90	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerCnterCheck_A	0	0	766612282	90	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerFsmCheck_A	0	0	766612282	90	0	0
tb.dut.gen_classes[0].u_accu.CountSaturateStable_A	0	0	766612282	1968	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigBkwd_A	0	0	766612282	258853	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigFwd_A	0	0	766612282	348560505	0	0
tb.dut.gen_classes[0].u_esc_timer.AccuFailToFsmError_A	0	0	766612282	292	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig0_A	0	0	766612282	1045	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig1_A	0	0	766612282	49	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckClr_A	0	0	766612282	555	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckEn_A	0	0	766355426	267944570	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase0_A	0	0	766612282	1133	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase1_A	0	0	766612282	1108	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase2_A	0	0	766612282	1075	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase3_A	0	0	766612282	1044	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeout0_A	0	0	766612282	2108	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt1_A	0	0	766612282	170074	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt2_A	0	0	766612282	2000	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutStTrig_A	0	0	766612282	59	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStAllEscAsserted_A	0	0	766612282	1654	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStIsTerminal_A	0	0	766612282	1384	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs.AssertConnected_A	0	0	643	643	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs_A	0	0	766612282	766423669	0	0
tb.dut.gen_classes[1].FpvSecCmAccuCnterCheck_A	0	0	766612282	90	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerCnterCheck_A	0	0	766612282	90	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerFsmCheck_A	0	0	766612282	90	0	0
tb.dut.gen_classes[1].u_accu.CountSaturateStable_A	0	0	766612282	3861	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigBkwd_A	0	0	766612282	244451	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigFwd_A	0	0	766612282	410156053	0	0
tb.dut.gen_classes[1].u_esc_timer.AccuFailToFsmError_A	0	0	766612282	332	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig0_A	0	0	766612282	539	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig1_A	0	0	766612282	26	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckClr_A	0	0	766612282	243	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckEn_A	0	0	766355426	334746629	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase0_A	0	0	766612282	628	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase1_A	0	0	766612282	611	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase2_A	0	0	766612282	602	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase3_A	0	0	766612282	591	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeout0_A	0	0	766612282	1031	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt1_A	0	0	766612282	112343	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt2_A	0	0	766612282	933	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutStTrig_A	0	0	766612282	72	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStAllEscAsserted_A	0	0	766612282	1682	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStIsTerminal_A	0	0	766612282	1412	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs.AssertConnected_A	0	0	643	643	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs_A	0	0	766612282	766423669	0	0
tb.dut.gen_classes[2].FpvSecCmAccuCnterCheck_A	0	0	766612282	90	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerCnterCheck_A	0	0	766612282	90	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerFsmCheck_A	0	0	766612282	90	0	0
tb.dut.gen_classes[2].u_accu.CountSaturateStable_A	0	0	766612282	4993	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigBkwd_A	0	0	766612282	234020	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigFwd_A	0	0	766612282	422274443	0	0
tb.dut.gen_classes[2].u_esc_timer.AccuFailToFsmError_A	0	0	766612282	262	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig0_A	0	0	766612282	569	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig1_A	0	0	766612282	30	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckClr_A	0	0	766612282	247	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckEn_A	0	0	766355426	324455361	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase0_A	0	0	766612282	645	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase1_A	0	0	766612282	635	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase2_A	0	0	766612282	625	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase3_A	0	0	766612282	614	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeout0_A	0	0	766612282	882	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt1_A	0	0	766612282	114575	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt2_A	0	0	766612282	796	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutStTrig_A	0	0	766612282	55	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStAllEscAsserted_A	0	0	766612282	1615	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStIsTerminal_A	0	0	766612282	1345	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs.AssertConnected_A	0	0	643	643	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs_A	0	0	766612282	766423669	0	0
tb.dut.gen_classes[3].FpvSecCmAccuCnterCheck_A	0	0	766612282	90	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerCnterCheck_A	0	0	766612282	90	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerFsmCheck_A	0	0	766612282	90	0	0
tb.dut.gen_classes[3].u_accu.CountSaturateStable_A	0	0	766612282	3760	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigBkwd_A	0	0	766612282	194912	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigFwd_A	0	0	766612282	428404645	0	0
tb.dut.gen_classes[3].u_esc_timer.AccuFailToFsmError_A	0	0	766612282	280	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig0_A	0	0	766612282	577	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig1_A	0	0	766612282	32	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckClr_A	0	0	766612282	266	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckEn_A	0	0	766355426	329280855	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase0_A	0	0	766612282	662	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase1_A	0	0	766612282	652	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase2_A	0	0	766612282	642	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase3_A	0	0	766612282	627	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeout0_A	0	0	766612282	578	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt1_A	0	0	766612282	79885	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt2_A	0	0	766612282	481	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutStTrig_A	0	0	766612282	65	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStAllEscAsserted_A	0	0	766612282	1556	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStIsTerminal_A	0	0	766612282	1286	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs.AssertConnected_A	0	0	643	643	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs_A	0	0	766612282	766423669	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	787095701	151912880	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	787095701	786419692	0	0
tb.dut.tlul_assert_device.aReadyKnown_A	0	0	787095701	786419692	0	0
tb.dut.tlul_assert_device.dKnown_A	0	0	787095701	230021689	0	0
tb.dut.tlul_assert_device.dKnown_AKnownEnable	0	0	787095701	786419692	0	0
tb.dut.tlul_assert_device.dReadyKnown_A	0	0	787095701	786419692	0	0
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