Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	44	0	44	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_sig_index_cp	4	0	4	100.00	100	1	1	0
esc_sig_len_cp	11	0	11	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
len_per_esc_sig	44	0	44	100.00	100	1	1	0

Summary for Variable esc_sig_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_sig_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	207	1			T1	1		T2	1		T4	1
index[0x1]	216	1			T2	2		T4	1		T6	1
index[0x2]	194	1			T16	3		T40	1		T8	1
index[0x3]	188	1			T2	1		T22	1		T16	1

---

Summary for Variable esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for esc_sig_len_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
lens_less_than_1000[0]	266	1			T2	3		T4	1		T6	1
lens_less_than_1000[1]	147	1			T10	5		T83	1		T58	6
lens_less_than_1000[2]	113	1			T2	1		T16	1		T8	1
lens_less_than_1000[3]	71	1			T4	1		T41	2		T58	1
lens_less_than_1000[4]	65	1			T22	1		T85	1		T41	1
lens_less_than_1000[5]	53	1			T16	1		T10	2		T41	1
lens_less_than_1000[6]	26	1			T16	1		T8	1		T39	4
lens_less_than_1000[7]	33	1			T1	1		T16	1		T58	1
lens_less_than_1000[8]	17	1			T93	1		T103	1		T278	2
lens_less_than_1000[9]	5	1			T64	1		T98	1		T279	1
len_2	9	1			T88	1		T280	1		T231	2

---

Summary for Cross len_per_esc_sig

Samples crossed: esc_sig_index_cp esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	44	0	44	100.00

Automatically Generated Cross Bins for len_per_esc_sig

Bins

esc_sig_index_cp	esc_sig_len_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	lens_less_than_1000[0]	69	1			T2	1		T4	1		T16	1
index[0x0]	lens_less_than_1000[1]	30	1			T10	2		T37	1		T92	1
index[0x0]	lens_less_than_1000[2]	30	1			T10	3		T38	1		T92	2
index[0x0]	lens_less_than_1000[3]	21	1			T41	2		T281	1		T65	1
index[0x0]	lens_less_than_1000[4]	16	1			T282	1		T103	1		T283	1
index[0x0]	lens_less_than_1000[5]	13	1			T10	1		T90	1		T283	1
index[0x0]	lens_less_than_1000[6]	10	1			T39	2		T52	5		T279	1
index[0x0]	lens_less_than_1000[7]	12	1			T1	1		T16	1		T58	1
index[0x0]	lens_less_than_1000[8]	4	1			T93	1		T103	1		T284	1
index[0x0]	lens_less_than_1000[9]	1	1			T285	1		-	-		-	-
index[0x0]	len_2	1	1			T231	1		-	-		-	-
index[0x1]	lens_less_than_1000[0]	77	1			T2	1		T6	1		T17	1
index[0x1]	lens_less_than_1000[1]	45	1			T10	1		T58	6		T37	2
index[0x1]	lens_less_than_1000[2]	22	1			T2	1		T41	1		T78	1
index[0x1]	lens_less_than_1000[3]	18	1			T4	1		T58	1		T92	1
index[0x1]	lens_less_than_1000[4]	18	1			T281	1		T63	1		T212	1
index[0x1]	lens_less_than_1000[5]	15	1			T84	1		T286	1		T244	1
index[0x1]	lens_less_than_1000[6]	6	1			T8	1		T287	1		T114	1
index[0x1]	lens_less_than_1000[7]	9	1			T60	1		T251	1		T288	1
index[0x1]	lens_less_than_1000[8]	4	1			T289	1		T244	1		T290	1
index[0x1]	lens_less_than_1000[9]	1	1			T64	1		-	-		-	-
index[0x1]	len_2	1	1			T291	1		-	-		-	-
index[0x2]	lens_less_than_1000[0]	65	1			T40	1		T76	4		T60	1
index[0x2]	lens_less_than_1000[1]	39	1			T83	1		T37	1		T91	1
index[0x2]	lens_less_than_1000[2]	31	1			T16	1		T8	1		T10	1
index[0x2]	lens_less_than_1000[3]	16	1			T270	1		T292	1		T293	1
index[0x2]	lens_less_than_1000[4]	11	1			T85	1		T41	1		T86	1
index[0x2]	lens_less_than_1000[5]	12	1			T16	1		T41	1		T231	1
index[0x2]	lens_less_than_1000[6]	6	1			T16	1		T281	1		T64	1
index[0x2]	lens_less_than_1000[7]	6	1			T109	1		T294	1		T295	1
index[0x2]	lens_less_than_1000[8]	4	1			T278	1		T230	1		T296	1
index[0x2]	lens_less_than_1000[9]	2	1			T98	1		T297	1		-	-
index[0x2]	len_2	2	1			T231	1		T298	1		-	-
index[0x3]	lens_less_than_1000[0]	55	1			T2	1		T16	1		T10	1
index[0x3]	lens_less_than_1000[1]	33	1			T10	2		T60	2		T67	2
index[0x3]	lens_less_than_1000[2]	30	1			T10	1		T61	1		T62	1
index[0x3]	lens_less_than_1000[3]	16	1			T37	1		T299	1		T68	1
index[0x3]	lens_less_than_1000[4]	20	1			T22	1		T300	1		T72	1
index[0x3]	lens_less_than_1000[5]	13	1			T10	1		T76	2		T281	1
index[0x3]	lens_less_than_1000[6]	4	1			T39	2		T301	1		T302	1
index[0x3]	lens_less_than_1000[7]	6	1			T288	1		T303	1		T304	1
index[0x3]	lens_less_than_1000[8]	5	1			T278	1		T110	1		T305	2
index[0x3]	lens_less_than_1000[9]	1	1			T279	1		-	-		-	-
index[0x3]	len_2	5	1			T88	1		T280	1		T306	1