Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.89	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	40	6	34	85.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
intr_timeout_cnt_cp	10	0	10	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	40	6	34	85.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	59	1			T10	3		T41	2		T58	3
class_index[0x1]	72	1			T18	1		T10	1		T58	2
class_index[0x2]	55	1			T10	1		T58	1		T77	1
class_index[0x3]	65	1			T10	1		T33	1		T58	4

---

Summary for Variable intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for intr_timeout_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
intr_timeout_cnt[0]	102	1			T18	1		T10	1		T41	2
intr_timeout_cnt[1]	62	1			T10	2		T58	3		T77	1
intr_timeout_cnt[2]	25	1			T37	2		T60	1		T64	1
intr_timeout_cnt[3]	11	1			T58	1		T37	1		T60	1
intr_timeout_cnt[4]	12	1			T58	1		T37	1		T59	3
intr_timeout_cnt[5]	11	1			T33	1		T58	1		T37	1
intr_timeout_cnt[6]	6	1			T10	2		T76	1		T228	1
intr_timeout_cnt[7]	6	1			T65	1		T229	1		T230	1
intr_timeout_cnt[8]	8	1			T89	1		T111	1		T231	1
intr_timeout_cnt[9]	8	1			T10	1		T84	1		T109	1

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	6	34	85.00	6

Automatically Generated Cross Bins for class_cnt_cross

Uncovered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	NUMBER	STATUS
[class_index[0x0]]	[intr_timeout_cnt[3]]	0	1	1
[class_index[0x0]]	[intr_timeout_cnt[7]]	0	1	1
[class_index[0x1]]	[intr_timeout_cnt[7]]	0	1	1
[class_index[0x2]]	[intr_timeout_cnt[4] , intr_timeout_cnt[5]]	--	--	2
[class_index[0x3]]	[intr_timeout_cnt[4]]	0	1	1

Covered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	intr_timeout_cnt[0]	26	1			T10	1		T41	2		T58	1
class_index[0x0]	intr_timeout_cnt[1]	20	1			T10	1		T58	1		T90	1
class_index[0x0]	intr_timeout_cnt[2]	2	1			T229	1		T232	1		-	-
class_index[0x0]	intr_timeout_cnt[4]	5	1			T58	1		T37	1		T233	1
class_index[0x0]	intr_timeout_cnt[5]	1	1			T59	1		-	-		-	-
class_index[0x0]	intr_timeout_cnt[6]	2	1			T76	1		T234	1		-	-
class_index[0x0]	intr_timeout_cnt[8]	1	1			T231	1		-	-		-	-
class_index[0x0]	intr_timeout_cnt[9]	2	1			T10	1		T230	1		-	-
class_index[0x1]	intr_timeout_cnt[0]	34	1			T18	1		T76	2		T93	2
class_index[0x1]	intr_timeout_cnt[1]	15	1			T58	2		T38	1		T60	1
class_index[0x1]	intr_timeout_cnt[2]	4	1			T235	1		T231	1		T236	1
class_index[0x1]	intr_timeout_cnt[3]	3	1			T237	2		T238	1		-	-
class_index[0x1]	intr_timeout_cnt[4]	7	1			T59	3		T69	1		T239	1
class_index[0x1]	intr_timeout_cnt[5]	3	1			T37	1		T92	1		T240	1
class_index[0x1]	intr_timeout_cnt[6]	1	1			T10	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[8]	3	1			T241	1		T242	2		-	-
class_index[0x1]	intr_timeout_cnt[9]	2	1			T109	1		T243	1		-	-
class_index[0x2]	intr_timeout_cnt[0]	15	1			T60	2		T63	1		T223	2
class_index[0x2]	intr_timeout_cnt[1]	14	1			T77	1		T37	1		T78	1
class_index[0x2]	intr_timeout_cnt[2]	10	1			T37	1		T103	2		T48	1
class_index[0x2]	intr_timeout_cnt[3]	6	1			T58	1		T60	1		T229	1
class_index[0x2]	intr_timeout_cnt[6]	1	1			T10	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[7]	3	1			T65	1		T229	1		T241	1
class_index[0x2]	intr_timeout_cnt[8]	3	1			T89	1		T111	1		T244	1
class_index[0x2]	intr_timeout_cnt[9]	3	1			T84	1		T244	1		T245	1
class_index[0x3]	intr_timeout_cnt[0]	27	1			T58	3		T37	1		T38	1
class_index[0x3]	intr_timeout_cnt[1]	13	1			T10	1		T78	1		T87	1
class_index[0x3]	intr_timeout_cnt[2]	9	1			T37	1		T60	1		T64	1
class_index[0x3]	intr_timeout_cnt[3]	2	1			T37	1		T239	1		-	-
class_index[0x3]	intr_timeout_cnt[5]	7	1			T33	1		T58	1		T88	3
class_index[0x3]	intr_timeout_cnt[6]	2	1			T228	1		T246	1		-	-
class_index[0x3]	intr_timeout_cnt[7]	3	1			T230	1		T247	1		T233	1
class_index[0x3]	intr_timeout_cnt[8]	1	1			T248	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[9]	1	1			T223	1		-	-		-	-