Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	361309	1			T24	5		T25	8		T26	1
all_values[1]	361309	1			T24	5		T25	8		T26	1
all_values[2]	361309	1			T24	5		T25	8		T26	1
all_values[3]	361309	1			T24	5		T25	8		T26	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

719051

1

T24

7

T25

21

T26

4

auto[1]

726185

1

T24

13

T25

11

T27

10

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

862000

1

T24

15

T25

14

T26

4

auto[1]

583236

1

T24

5

T25

18

T27

6

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	103762	1			T24	1		T25	2		T26	1
all_values[0]	auto[0]	auto[1]	76065	1			T25	3		T30	3		T185	2
all_values[0]	auto[1]	auto[0]	105341	1			T24	3		T25	1		T27	4
all_values[0]	auto[1]	auto[1]	76141	1			T24	1		T25	2		T30	2
all_values[1]	auto[0]	auto[0]	108704	1			T25	3		T26	1		T27	3
all_values[1]	auto[0]	auto[1]	70900	1			T24	1		T25	4		T27	1
all_values[1]	auto[1]	auto[0]	110210	1			T24	4		T25	1		T30	4
all_values[1]	auto[1]	auto[1]	71495	1			T27	1		T30	2		T185	2
all_values[2]	auto[0]	auto[0]	107548	1			T24	3		T25	2		T26	1
all_values[2]	auto[0]	auto[1]	72099	1			T24	1		T25	4		T27	3
all_values[2]	auto[1]	auto[0]	109000	1			T24	1		T30	2		T185	3
all_values[2]	auto[1]	auto[1]	72662	1			T25	2		T27	1		T30	1
all_values[3]	auto[0]	auto[0]	107990	1			T24	1		T25	3		T26	1
all_values[3]	auto[0]	auto[1]	71983	1			T185	3		T326	2		T327	2
all_values[3]	auto[1]	auto[0]	109445	1			T24	2		T25	2		T27	4
all_values[3]	auto[1]	auto[1]	71891	1			T24	2		T25	3		T185	1