Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	4	0	4	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	361309	1			T24	5		T25	8		T26	1
all_pins[1]	361309	1			T24	5		T25	8		T26	1
all_pins[2]	361309	1			T24	5		T25	8		T26	1
all_pins[3]	361309	1			T24	5		T25	8		T26	1

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1153047	1			T24	17		T25	25		T26	4
values[0x1]	292189	1			T24	3		T25	7		T27	2
transitions[0x0=>0x1]	193156	1			T24	3		T25	5		T27	1
transitions[0x1=>0x0]	193419	1			T24	3		T25	5		T27	1

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	285168	1			T24	4		T25	6		T26	1
all_pins[0]	values[0x1]	76141	1			T24	1		T25	2		T30	2
all_pins[0]	transitions[0x0=>0x1]	75431	1			T24	1		T25	1		T30	2
all_pins[0]	transitions[0x1=>0x0]	71444	1			T24	2		T25	2		T185	1
all_pins[1]	values[0x0]	289814	1			T24	5		T25	8		T26	1
all_pins[1]	values[0x1]	71495	1			T27	1		T30	2		T185	2
all_pins[1]	transitions[0x0=>0x1]	38895	1			T27	1		T30	2		T185	1
all_pins[1]	transitions[0x1=>0x0]	43541	1			T24	1		T25	2		T30	2
all_pins[2]	values[0x0]	288647	1			T24	5		T25	6		T26	1
all_pins[2]	values[0x1]	72662	1			T25	2		T27	1		T30	1
all_pins[2]	transitions[0x0=>0x1]	39629	1			T25	2		T30	1		T185	1
all_pins[2]	transitions[0x1=>0x0]	38462	1			T30	2		T185	2		T327	2
all_pins[3]	values[0x0]	289418	1			T24	3		T25	5		T26	1
all_pins[3]	values[0x1]	71891	1			T24	2		T25	3		T185	1
all_pins[3]	transitions[0x0=>0x1]	39201	1			T24	2		T25	2		T326	1
all_pins[3]	transitions[0x1=>0x0]	39972	1			T25	1		T27	1		T30	1