Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	290	1			T24	4		T25	7		T27	4
all_values[1]	290	1			T24	4		T25	7		T27	4
all_values[2]	290	1			T24	4		T25	7		T27	4
all_values[3]	290	1			T24	4		T25	7		T27	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

649

1

T24

6

T25

20

T27

8

auto[1]

511

1

T24

10

T25

8

T27

8

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

458

1

T24

8

T25

7

T27

9

auto[1]

702

1

T24

8

T25

21

T27

7

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

686

1

T24

10

T25

16

T27

11

auto[1]

474

1

T24

6

T25

12

T27

5

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	24	0	24	100.00
Automatically Generated Cross Bins	24	0	24	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr

cp_intr_test

cp_intr_en

cp_intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_values[0]

auto[0]

auto[0]

auto[0]

56

1

T24

1

T27

1

T326

2

all_values[0]

auto[0]

auto[0]

auto[1]

35

1

T25

1

T30

1

T185

1

all_values[0]

auto[0]

auto[1]

auto[0]

54

1

T24

1

T27

3

T185

2

all_values[0]

auto[0]

auto[1]

auto[1]

30

1

T24

1

T25

2

T30

1

all_values[0]

auto[1]

auto[0]

auto[1]

62

1

T25

4

T30

4

T185

1

all_values[0]

auto[1]

auto[1]

auto[1]

53

1

T24

1

T30

1

T185

3

all_values[1]

auto[0]

auto[0]

auto[0]

66

1

T25

2

T27

1

T327

1

all_values[1]

auto[0]

auto[0]

auto[1]

28

1

T25

3

T30

1

T185

1

all_values[1]

auto[0]

auto[1]

auto[0]

50

1

T24

2

T27

1

T30

1

all_values[1]

auto[0]

auto[1]

auto[1]

23

1

T328

1

T225

1

T329

1

all_values[1]

auto[1]

auto[0]

auto[1]

53

1

T24

2

T25

2

T27

2

all_values[1]

auto[1]

auto[1]

auto[1]

70

1

T30

3

T185

3

T326

1

all_values[2]

auto[0]

auto[0]

auto[0]

73

1

T24

1

T25

1

T30

3

all_values[2]

auto[0]

auto[0]

auto[1]

26

1

T25

1

T27

2

T326

1

all_values[2]

auto[0]

auto[1]

auto[0]

50

1

T24

1

T30

1

T185

2

all_values[2]

auto[0]

auto[1]

auto[1]

29

1

T25

1

T30

1

T185

1

all_values[2]

auto[1]

auto[0]

auto[1]

66

1

T24

1

T25

3

T27

1

all_values[2]

auto[1]

auto[1]

auto[1]

46

1

T24

1

T25

1

T27

1

all_values[3]

auto[0]

auto[0]

auto[0]

68

1

T24

1

T25

2

T27

1

all_values[3]

auto[0]

auto[0]

auto[1]

37

1

T185

1

T326

1

T327

1

all_values[3]

auto[0]

auto[1]

auto[0]

41

1

T24

1

T25

2

T27

2

all_values[3]

auto[0]

auto[1]

auto[1]

20

1

T24

1

T25

1

T185

1

all_values[3]

auto[1]

auto[0]

auto[1]

79

1

T25

1

T185

3

T326

1

all_values[3]

auto[1]

auto[1]

auto[1]

45

1

T24

1

T25

1

T27

1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal