Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
accum_cnt_cp	6	0	6	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	24	0	24	100.00	100	1	1	0

Summary for Variable accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for accum_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
accum_cnt_2000	101258	1			T22	370		T4	556		T6	512
accum_cnt_1000	235933	1			T2	48		T22	396		T4	486
accum_cnt_100	31740	1			T1	1		T2	17		T22	132
accum_cnt_50	73820	1			T1	16		T2	60		T22	177
accum_cnt_10	171816	1			T1	3		T2	66		T3	6
accum_cnt_0	397589	1			T1	64		T2	321		T3	58

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Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	265587	1			T1	21		T2	128		T3	16
class_index[0x1]	265586	1			T1	21		T2	128		T3	16
class_index[0x2]	265586	1			T1	21		T2	128		T3	16
class_index[0x3]	265586	1			T1	21		T2	128		T3	16

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Summary for Cross class_cnt_cross

Samples crossed: class_index_cp accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for class_cnt_cross

Bins

class_index_cp	accum_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	accum_cnt_2000	28558	1			T22	370		T6	512		T10	426
class_index[0x0]	accum_cnt_1000	64070	1			T2	48		T22	344		T6	632
class_index[0x0]	accum_cnt_100	8848	1			T1	1		T2	15		T22	72
class_index[0x0]	accum_cnt_50	22026	1			T1	16		T2	15		T22	70
class_index[0x0]	accum_cnt_10	34053	1			T1	3		T2	39		T3	6
class_index[0x0]	accum_cnt_0	95086	1			T1	1		T2	11		T3	10
class_index[0x1]	accum_cnt_2000	23517	1			T4	556		T16	241		T10	413
class_index[0x1]	accum_cnt_1000	63244	1			T22	7		T4	486		T15	451
class_index[0x1]	accum_cnt_100	7858	1			T22	19		T4	24		T18	10
class_index[0x1]	accum_cnt_50	16380	1			T2	17		T22	21		T4	20
class_index[0x1]	accum_cnt_10	41117	1			T2	10		T22	52		T4	9
class_index[0x1]	accum_cnt_0	99630	1			T1	21		T2	101		T3	16
class_index[0x2]	accum_cnt_2000	25620	1			T16	387		T57	199		T81	272
class_index[0x2]	accum_cnt_1000	55682	1			T5	504		T15	613		T16	532
class_index[0x2]	accum_cnt_100	9188	1			T5	142		T6	1215		T15	63
class_index[0x2]	accum_cnt_50	22506	1			T2	11		T22	32		T5	123
class_index[0x2]	accum_cnt_10	40402	1			T2	11		T22	142		T4	1365
class_index[0x2]	accum_cnt_0	97310	1			T1	21		T2	106		T3	16
class_index[0x3]	accum_cnt_2000	23563	1			T10	141		T80	611		T96	445
class_index[0x3]	accum_cnt_1000	52937	1			T22	45		T5	635		T10	519
class_index[0x3]	accum_cnt_100	5846	1			T2	2		T22	41		T5	70
class_index[0x3]	accum_cnt_50	12908	1			T2	17		T22	54		T18	4
class_index[0x3]	accum_cnt_10	56244	1			T2	6		T22	52		T4	1361
class_index[0x3]	accum_cnt_0	105563	1			T1	21		T2	103		T3	16