Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	71	0	71	100.00
Crosses	138	0	138	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
alert_index_cp	65	0	65	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	130	0	130	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for alert_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	5483	1			T10	27		T86	36		T82	4
alert[0x1]	9021	1			T10	166		T41	1		T61	11
alert[0x2]	3662	1			T8	1		T41	1		T86	525
alert[0x3]	9792	1			T6	895		T8	1		T10	108
alert[0x4]	5960	1			T10	1114		T86	6		T58	18
alert[0x5]	1981	1			T6	24		T16	6		T84	3
alert[0x6]	15795	1			T10	220		T86	13		T58	2
alert[0x7]	7381	1			T10	82		T17	1		T41	3
alert[0x8]	3306	1			T6	55		T10	5		T59	1
alert[0x9]	12082	1			T37	4418		T38	9		T253	1199
alert[0xa]	2159	1			T86	263		T37	8		T60	137
alert[0xb]	9604	1			T6	608		T8	1		T33	22
alert[0xc]	3896	1			T8	1		T10	86		T60	14
alert[0xd]	3737	1			T6	1401		T8	1		T41	3
alert[0xe]	8185	1			T6	70		T37	936		T38	14
alert[0xf]	7820	1			T8	1		T10	3340		T58	4
alert[0x10]	6820	1			T8	2		T9	1		T37	17
alert[0x11]	6033	1			T6	110		T10	19		T86	420
alert[0x12]	8442	1			T6	210		T59	2		T91	1
alert[0x13]	3015	1			T6	50		T10	150		T86	43
alert[0x14]	10835	1			T10	73		T58	162		T91	9
alert[0x15]	7245	1			T6	136		T17	1		T37	186
alert[0x16]	10657	1			T6	119		T33	110		T86	1042
alert[0x17]	4222	1			T6	26		T253	32		T91	48
alert[0x18]	4413	1			T10	1885		T33	1		T41	1
alert[0x19]	11296	1			T6	810		T16	35		T56	2
alert[0x1a]	5252	1			T8	1		T10	127		T76	525
alert[0x1b]	3956	1			T8	1		T10	28		T86	255
alert[0x1c]	5988	1			T6	54		T76	71		T250	1
alert[0x1d]	3046	1			T10	182		T253	24		T60	4
alert[0x1e]	4514	1			T86	170		T58	50		T37	200
alert[0x1f]	7563	1			T86	140		T37	8		T38	205
alert[0x20]	1593	1			T6	34		T41	13		T37	43
alert[0x21]	4875	1			T10	845		T86	5		T76	37
alert[0x22]	2824	1			T9	1		T41	2		T37	36
alert[0x23]	7307	1			T6	75		T10	15		T33	7
alert[0x24]	5302	1			T6	9		T82	2		T58	35
alert[0x25]	7935	1			T6	306		T8	1		T58	4
alert[0x26]	4875	1			T6	22		T8	1		T56	2
alert[0x27]	9186	1			T6	75		T10	2168		T33	1
alert[0x28]	4741	1			T5	1		T6	186		T9	1
alert[0x29]	10335	1			T82	2		T58	132		T76	6
alert[0x2a]	4394	1			T6	11		T10	61		T82	24
alert[0x2b]	9979	1			T6	24		T9	1		T10	29
alert[0x2c]	3965	1			T58	61		T37	261		T253	15
alert[0x2d]	10150	1			T6	1975		T10	40		T86	17
alert[0x2e]	7275	1			T5	2		T6	26		T8	1
alert[0x2f]	14514	1			T9	1		T10	161		T33	26
alert[0x30]	13097	1			T10	6		T37	27		T60	77
alert[0x31]	10179	1			T16	1		T10	27		T86	17
alert[0x32]	6485	1			T8	1		T10	304		T86	285
alert[0x33]	5331	1			T10	197		T37	114		T38	48
alert[0x34]	3883	1			T6	645		T10	107		T86	379
alert[0x35]	14736	1			T6	23		T41	2		T82	33
alert[0x36]	7044	1			T6	65		T58	7		T76	1
alert[0x37]	2223	1			T6	462		T8	1		T10	2
alert[0x38]	3197	1			T10	191		T58	64		T38	10
alert[0x39]	1886	1			T6	68		T10	12		T33	4
alert[0x3a]	7172	1			T6	22		T10	20		T58	117
alert[0x3b]	16423	1			T10	62		T58	2		T37	28
alert[0x3c]	7555	1			T6	177		T86	172		T58	56
alert[0x3d]	6767	1			T6	287		T86	1119		T58	2
alert[0x3e]	3562	1			T76	10		T38	677		T253	1064
alert[0x3f]	5855	1			T10	14		T58	23		T76	60
alert[0x40]	7733	1			T9	1		T41	4		T86	10

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	87686	1			T9	7		T10	5333		T17	2
class_i[0x1]	176125	1			T16	42		T8	13		T10	3
class_i[0x2]	108159	1			T5	3		T6	9060		T8	1
class_i[0x3]	73569	1			T8	1		T10	6532		T33	4

---

Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

alert_integrity_fail

444863

1

T6

9060

T16

42

T10

11873

alert_ping_fail

676

1

T5

3

T8

15

T9

7

---

Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	0	130	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	alert_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	alert[0x0]	5476	1			T10	27		T86	36		T82	4
alert_integrity_fail	alert[0x1]	9010	1			T10	166		T41	1		T61	11
alert_integrity_fail	alert[0x2]	3651	1			T41	1		T86	525		T58	2
alert_integrity_fail	alert[0x3]	9781	1			T6	895		T10	108		T86	144
alert_integrity_fail	alert[0x4]	5946	1			T10	1114		T86	6		T58	18
alert_integrity_fail	alert[0x5]	1967	1			T6	24		T16	6		T84	3
alert_integrity_fail	alert[0x6]	15778	1			T10	220		T86	13		T58	2
alert_integrity_fail	alert[0x7]	7369	1			T10	82		T41	3		T86	2
alert_integrity_fail	alert[0x8]	3297	1			T6	55		T10	5		T59	1
alert_integrity_fail	alert[0x9]	12071	1			T37	4418		T38	9		T253	1199
alert_integrity_fail	alert[0xa]	2148	1			T86	263		T37	8		T60	137
alert_integrity_fail	alert[0xb]	9590	1			T6	608		T33	22		T37	31
alert_integrity_fail	alert[0xc]	3886	1			T10	86		T60	14		T98	85
alert_integrity_fail	alert[0xd]	3727	1			T6	1401		T41	3		T86	717
alert_integrity_fail	alert[0xe]	8180	1			T6	70		T37	936		T38	14
alert_integrity_fail	alert[0xf]	7806	1			T10	3340		T58	4		T38	10
alert_integrity_fail	alert[0x10]	6805	1			T37	17		T60	356		T93	12
alert_integrity_fail	alert[0x11]	6026	1			T6	110		T10	19		T86	420
alert_integrity_fail	alert[0x12]	8431	1			T6	210		T59	2		T91	1
alert_integrity_fail	alert[0x13]	3004	1			T6	50		T10	150		T86	43
alert_integrity_fail	alert[0x14]	10827	1			T10	73		T58	162		T91	9
alert_integrity_fail	alert[0x15]	7231	1			T6	136		T37	186		T60	136
alert_integrity_fail	alert[0x16]	10653	1			T6	119		T33	110		T86	1042
alert_integrity_fail	alert[0x17]	4211	1			T6	26		T253	32		T91	48
alert_integrity_fail	alert[0x18]	4401	1			T10	1885		T33	1		T41	1
alert_integrity_fail	alert[0x19]	11291	1			T6	810		T16	35		T56	2
alert_integrity_fail	alert[0x1a]	5244	1			T10	127		T76	525		T60	8
alert_integrity_fail	alert[0x1b]	3949	1			T10	28		T86	255		T76	7
alert_integrity_fail	alert[0x1c]	5976	1			T6	54		T76	71		T253	480
alert_integrity_fail	alert[0x1d]	3039	1			T10	182		T253	24		T60	4
alert_integrity_fail	alert[0x1e]	4504	1			T86	170		T58	50		T37	200
alert_integrity_fail	alert[0x1f]	7553	1			T86	140		T37	8		T38	205
alert_integrity_fail	alert[0x20]	1586	1			T6	34		T41	13		T37	43
alert_integrity_fail	alert[0x21]	4864	1			T10	845		T86	5		T76	37
alert_integrity_fail	alert[0x22]	2805	1			T41	2		T37	36		T59	5
alert_integrity_fail	alert[0x23]	7300	1			T6	75		T10	15		T33	7
alert_integrity_fail	alert[0x24]	5291	1			T6	9		T82	2		T58	35
alert_integrity_fail	alert[0x25]	7920	1			T6	306		T58	4		T61	24
alert_integrity_fail	alert[0x26]	4865	1			T6	22		T56	2		T33	5
alert_integrity_fail	alert[0x27]	9179	1			T6	75		T10	2168		T33	1
alert_integrity_fail	alert[0x28]	4727	1			T6	186		T76	1		T37	431
alert_integrity_fail	alert[0x29]	10322	1			T82	2		T58	132		T76	6
alert_integrity_fail	alert[0x2a]	4381	1			T6	11		T10	61		T82	24
alert_integrity_fail	alert[0x2b]	9966	1			T6	24		T10	29		T86	80
alert_integrity_fail	alert[0x2c]	3952	1			T58	61		T37	261		T253	15
alert_integrity_fail	alert[0x2d]	10139	1			T6	1975		T10	40		T86	17
alert_integrity_fail	alert[0x2e]	7258	1			T6	26		T58	98		T76	5
alert_integrity_fail	alert[0x2f]	14505	1			T10	161		T33	26		T86	1554
alert_integrity_fail	alert[0x30]	13083	1			T10	6		T37	27		T60	77
alert_integrity_fail	alert[0x31]	10169	1			T16	1		T10	27		T86	17
alert_integrity_fail	alert[0x32]	6478	1			T10	304		T86	285		T88	2
alert_integrity_fail	alert[0x33]	5320	1			T10	197		T37	114		T38	48
alert_integrity_fail	alert[0x34]	3869	1			T6	645		T10	107		T86	379
alert_integrity_fail	alert[0x35]	14726	1			T6	23		T41	2		T82	33
alert_integrity_fail	alert[0x36]	7038	1			T6	65		T58	7		T76	1
alert_integrity_fail	alert[0x37]	2218	1			T6	462		T10	2		T58	21
alert_integrity_fail	alert[0x38]	3188	1			T10	191		T58	64		T38	10
alert_integrity_fail	alert[0x39]	1874	1			T6	68		T10	12		T33	4
alert_integrity_fail	alert[0x3a]	7162	1			T6	22		T10	20		T58	117
alert_integrity_fail	alert[0x3b]	16414	1			T10	62		T58	2		T37	28
alert_integrity_fail	alert[0x3c]	7551	1			T6	177		T86	172		T58	56
alert_integrity_fail	alert[0x3d]	6757	1			T6	287		T86	1119		T58	2
alert_integrity_fail	alert[0x3e]	3555	1			T76	10		T38	677		T253	1064
alert_integrity_fail	alert[0x3f]	5847	1			T10	14		T58	23		T76	60
alert_integrity_fail	alert[0x40]	7726	1			T41	4		T86	10		T76	21
alert_ping_fail	alert[0x0]	7	1			T208	1		T254	1		T255	1
alert_ping_fail	alert[0x1]	11	1			T208	1		T256	2		T257	1
alert_ping_fail	alert[0x2]	11	1			T8	1		T186	1		T258	1
alert_ping_fail	alert[0x3]	11	1			T8	1		T259	1		T257	1
alert_ping_fail	alert[0x4]	14	1			T186	1		T260	1		T261	1
alert_ping_fail	alert[0x5]	14	1			T262	1		T261	1		T256	1
alert_ping_fail	alert[0x6]	17	1			T263	1		T261	1		T259	1
alert_ping_fail	alert[0x7]	12	1			T17	1		T258	1		T249	1
alert_ping_fail	alert[0x8]	9	1			T51	1		T264	1		T254	1
alert_ping_fail	alert[0x9]	11	1			T186	1		T261	1		T256	1
alert_ping_fail	alert[0xa]	11	1			T186	1		T265	1		T266	1
alert_ping_fail	alert[0xb]	14	1			T8	1		T262	1		T261	1
alert_ping_fail	alert[0xc]	10	1			T8	1		T260	1		T265	1
alert_ping_fail	alert[0xd]	10	1			T8	1		T208	1		T261	1
alert_ping_fail	alert[0xe]	5	1			T186	1		T210	1		T51	1
alert_ping_fail	alert[0xf]	14	1			T8	1		T186	1		T258	1
alert_ping_fail	alert[0x10]	15	1			T8	2		T9	1		T186	1
alert_ping_fail	alert[0x11]	7	1			T267	1		T268	1		T269	1
alert_ping_fail	alert[0x12]	11	1			T208	1		T261	1		T257	1
alert_ping_fail	alert[0x13]	11	1			T251	1		T268	1		T269	3
alert_ping_fail	alert[0x14]	8	1			T258	1		T261	1		T270	1
alert_ping_fail	alert[0x15]	14	1			T17	1		T186	1		T262	1
alert_ping_fail	alert[0x16]	4	1			T258	2		T257	1		T271	1
alert_ping_fail	alert[0x17]	11	1			T257	1		T268	1		T269	1
alert_ping_fail	alert[0x18]	12	1			T208	1		T260	1		T262	1
alert_ping_fail	alert[0x19]	5	1			T258	1		T267	1		T272	1
alert_ping_fail	alert[0x1a]	8	1			T8	1		T258	1		T268	1
alert_ping_fail	alert[0x1b]	7	1			T8	1		T258	1		T273	1
alert_ping_fail	alert[0x1c]	12	1			T250	1		T186	1		T258	1
alert_ping_fail	alert[0x1d]	7	1			T208	1		T261	1		T268	1
alert_ping_fail	alert[0x1e]	10	1			T259	1		T269	1		T254	2
alert_ping_fail	alert[0x1f]	10	1			T260	1		T274	1		T266	1
alert_ping_fail	alert[0x20]	7	1			T256	1		T266	1		T271	1
alert_ping_fail	alert[0x21]	11	1			T101	1		T256	1		T268	1
alert_ping_fail	alert[0x22]	19	1			T9	1		T208	2		T262	1
alert_ping_fail	alert[0x23]	7	1			T258	1		T257	1		T254	1
alert_ping_fail	alert[0x24]	11	1			T261	1		T257	1		T269	1
alert_ping_fail	alert[0x25]	15	1			T8	1		T208	1		T210	1
alert_ping_fail	alert[0x26]	10	1			T8	1		T258	2		T264	1
alert_ping_fail	alert[0x27]	7	1			T186	1		T208	1		T210	1
alert_ping_fail	alert[0x28]	14	1			T5	1		T9	1		T258	2
alert_ping_fail	alert[0x29]	13	1			T259	1		T275	1		T265	1
alert_ping_fail	alert[0x2a]	13	1			T262	1		T259	1		T51	1
alert_ping_fail	alert[0x2b]	13	1			T9	1		T263	1		T265	1
alert_ping_fail	alert[0x2c]	13	1			T260	1		T267	1		T268	2
alert_ping_fail	alert[0x2d]	11	1			T208	1		T262	1		T268	1
alert_ping_fail	alert[0x2e]	17	1			T5	2		T8	1		T9	1
alert_ping_fail	alert[0x2f]	9	1			T9	1		T261	1		T267	2
alert_ping_fail	alert[0x30]	14	1			T208	1		T210	2		T262	1
alert_ping_fail	alert[0x31]	10	1			T186	1		T258	1		T260	1
alert_ping_fail	alert[0x32]	7	1			T8	1		T276	2		T272	1
alert_ping_fail	alert[0x33]	11	1			T269	1		T254	2		T271	1
alert_ping_fail	alert[0x34]	14	1			T258	2		T101	1		T276	1
alert_ping_fail	alert[0x35]	10	1			T208	1		T258	1		T101	1
alert_ping_fail	alert[0x36]	6	1			T268	1		T265	1		T271	1
alert_ping_fail	alert[0x37]	5	1			T8	1		T267	1		T268	1
alert_ping_fail	alert[0x38]	9	1			T256	1		T271	2		T273	1
alert_ping_fail	alert[0x39]	12	1			T186	1		T258	1		T261	1
alert_ping_fail	alert[0x3a]	10	1			T265	2		T254	2		T276	1
alert_ping_fail	alert[0x3b]	9	1			T208	1		T256	1		T268	1
alert_ping_fail	alert[0x3c]	4	1			T261	1		T256	1		T267	1
alert_ping_fail	alert[0x3d]	10	1			T262	1		T269	1		T254	3
alert_ping_fail	alert[0x3e]	7	1			T210	1		T258	1		T277	2
alert_ping_fail	alert[0x3f]	8	1			T257	1		T254	1		T271	1
alert_ping_fail	alert[0x40]	7	1			T9	1		T186	1		T261	1

---

Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	class_i[0x0]	87537	1			T10	5333		T33	172		T86	7433
alert_integrity_fail	class_i[0x1]	175962	1			T16	42		T10	3		T33	2
alert_integrity_fail	class_i[0x2]	107988	1			T6	9060		T10	5		T56	4
alert_integrity_fail	class_i[0x3]	73376	1			T10	6532		T33	4		T41	15
alert_ping_fail	class_i[0x0]	149	1			T9	7		T17	2		T251	1
alert_ping_fail	class_i[0x1]	163	1			T8	13		T258	1		T263	3
alert_ping_fail	class_i[0x2]	171	1			T5	3		T8	1		T250	1
alert_ping_fail	class_i[0x3]	193	1			T8	1		T208	5		T210	6