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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.65 99.99 98.67 100.00 100.00 100.00 99.38 99.52


Total test records in report: 848
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T780 /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.1798727548 Feb 04 12:51:26 PM PST 24 Feb 04 12:51:33 PM PST 24 185493106 ps
T781 /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.3673071221 Feb 04 12:51:45 PM PST 24 Feb 04 12:51:53 PM PST 24 61514511 ps
T782 /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.3832566977 Feb 04 12:51:34 PM PST 24 Feb 04 12:51:37 PM PST 24 12688524 ps
T783 /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.3428254559 Feb 04 12:51:45 PM PST 24 Feb 04 12:51:51 PM PST 24 213090479 ps
T145 /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.1621515122 Feb 04 12:51:45 PM PST 24 Feb 04 12:58:49 PM PST 24 30499470364 ps
T127 /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.2661666068 Feb 04 12:51:45 PM PST 24 Feb 04 01:01:30 PM PST 24 4636082988 ps
T141 /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.3889040513 Feb 04 12:52:03 PM PST 24 Feb 04 12:58:22 PM PST 24 8426848356 ps
T129 /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.3457473586 Feb 04 12:51:53 PM PST 24 Feb 04 12:53:08 PM PST 24 705333237 ps
T784 /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.272970699 Feb 04 12:51:37 PM PST 24 Feb 04 12:51:51 PM PST 24 90913754 ps
T785 /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.3984291192 Feb 04 12:51:46 PM PST 24 Feb 04 12:51:54 PM PST 24 83391440 ps
T786 /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.2103082082 Feb 04 12:52:08 PM PST 24 Feb 04 12:52:35 PM PST 24 676201265 ps
T787 /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.2559964830 Feb 04 12:51:45 PM PST 24 Feb 04 12:51:48 PM PST 24 9035380 ps
T788 /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.2266953749 Feb 04 12:51:49 PM PST 24 Feb 04 12:51:57 PM PST 24 17679204 ps
T789 /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.1469134463 Feb 04 12:51:45 PM PST 24 Feb 04 12:51:49 PM PST 24 10061273 ps
T790 /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.2700074451 Feb 04 12:51:48 PM PST 24 Feb 04 12:53:01 PM PST 24 6318130803 ps
T791 /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.445579529 Feb 04 12:51:48 PM PST 24 Feb 04 12:52:33 PM PST 24 517303733 ps
T792 /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.1293325236 Feb 04 12:51:46 PM PST 24 Feb 04 12:51:50 PM PST 24 9534905 ps
T793 /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.3980459456 Feb 04 12:51:48 PM PST 24 Feb 04 12:51:51 PM PST 24 10624948 ps
T794 /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.4060920178 Feb 04 12:51:40 PM PST 24 Feb 04 12:51:46 PM PST 24 135334270 ps
T795 /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.339815334 Feb 04 12:51:49 PM PST 24 Feb 04 12:51:53 PM PST 24 15749244 ps
T796 /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.4273123501 Feb 04 12:51:46 PM PST 24 Feb 04 12:51:53 PM PST 24 116177718 ps
T797 /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.2245240426 Feb 04 12:51:29 PM PST 24 Feb 04 12:51:37 PM PST 24 1283017032 ps
T135 /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.1723640061 Feb 04 12:51:52 PM PST 24 Feb 04 12:55:26 PM PST 24 1978329945 ps
T798 /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.1532287781 Feb 04 12:51:44 PM PST 24 Feb 04 12:51:52 PM PST 24 63606303 ps
T799 /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.2308943732 Feb 04 12:51:38 PM PST 24 Feb 04 12:51:44 PM PST 24 42733460 ps
T800 /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.739907008 Feb 04 12:51:32 PM PST 24 Feb 04 12:51:46 PM PST 24 170843199 ps
T176 /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.379813299 Feb 04 12:51:54 PM PST 24 Feb 04 12:51:59 PM PST 24 115536731 ps
T801 /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.2586358534 Feb 04 12:51:37 PM PST 24 Feb 04 12:51:59 PM PST 24 3613665142 ps
T802 /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.4091337207 Feb 04 12:51:41 PM PST 24 Feb 04 12:51:47 PM PST 24 34271786 ps
T803 /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.2533284010 Feb 04 12:51:55 PM PST 24 Feb 04 12:51:59 PM PST 24 10470999 ps
T804 /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.2628064227 Feb 04 12:51:46 PM PST 24 Feb 04 12:51:56 PM PST 24 70518242 ps
T166 /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.109498784 Feb 04 12:51:47 PM PST 24 Feb 04 12:52:31 PM PST 24 2485225805 ps
T805 /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.2332971606 Feb 04 12:51:48 PM PST 24 Feb 04 12:51:56 PM PST 24 225870432 ps
T806 /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.2945050025 Feb 04 12:51:43 PM PST 24 Feb 04 12:51:47 PM PST 24 38133494 ps
T151 /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.2344301081 Feb 04 12:51:40 PM PST 24 Feb 04 12:58:29 PM PST 24 6018940380 ps
T807 /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.660063191 Feb 04 12:51:47 PM PST 24 Feb 04 12:51:51 PM PST 24 21414446 ps
T808 /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.2664702718 Feb 04 12:51:56 PM PST 24 Feb 04 12:52:01 PM PST 24 24256233 ps
T130 /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.2457897230 Feb 04 12:51:42 PM PST 24 Feb 04 12:54:35 PM PST 24 47406938681 ps
T146 /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.360850963 Feb 04 12:51:34 PM PST 24 Feb 04 12:56:33 PM PST 24 8262446810 ps
T809 /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.1885021078 Feb 04 12:51:48 PM PST 24 Feb 04 12:51:52 PM PST 24 11620514 ps
T810 /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.3199188362 Feb 04 12:51:35 PM PST 24 Feb 04 12:51:51 PM PST 24 652048797 ps
T811 /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.1962675213 Feb 04 12:51:31 PM PST 24 Feb 04 12:51:38 PM PST 24 107575530 ps
T132 /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.4230209674 Feb 04 12:51:49 PM PST 24 Feb 04 12:56:53 PM PST 24 2128569283 ps
T812 /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.2795478757 Feb 04 12:51:51 PM PST 24 Feb 04 12:51:55 PM PST 24 10409501 ps
T813 /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.376135174 Feb 04 12:51:26 PM PST 24 Feb 04 12:51:32 PM PST 24 376331874 ps
T814 /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.1046420515 Feb 04 12:51:48 PM PST 24 Feb 04 12:51:59 PM PST 24 128778972 ps
T149 /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.1827376215 Feb 04 12:51:48 PM PST 24 Feb 04 01:10:10 PM PST 24 63562988705 ps
T175 /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.2608881628 Feb 04 12:51:57 PM PST 24 Feb 04 12:52:41 PM PST 24 1322751719 ps
T154 /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.2359426200 Feb 04 12:52:11 PM PST 24 Feb 04 12:56:20 PM PST 24 11717609569 ps
T815 /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.2385253478 Feb 04 12:51:47 PM PST 24 Feb 04 12:51:51 PM PST 24 11070363 ps
T816 /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.1478421525 Feb 04 12:52:01 PM PST 24 Feb 04 12:52:07 PM PST 24 11967175 ps
T817 /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.2929912239 Feb 04 12:51:48 PM PST 24 Feb 04 12:51:58 PM PST 24 95773051 ps
T158 /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.125519735 Feb 04 12:51:54 PM PST 24 Feb 04 12:54:19 PM PST 24 37160219043 ps
T148 /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.56526643 Feb 04 12:52:10 PM PST 24 Feb 04 12:59:57 PM PST 24 46831732245 ps
T818 /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.1626343818 Feb 04 12:51:47 PM PST 24 Feb 04 12:51:51 PM PST 24 11738239 ps
T819 /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.1365654156 Feb 04 12:51:48 PM PST 24 Feb 04 12:52:30 PM PST 24 1881992663 ps
T169 /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.1471948495 Feb 04 12:51:45 PM PST 24 Feb 04 12:52:24 PM PST 24 5815279740 ps
T820 /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.1026804601 Feb 04 12:51:49 PM PST 24 Feb 04 12:52:09 PM PST 24 275928021 ps
T821 /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.1895190683 Feb 04 12:51:46 PM PST 24 Feb 04 12:51:54 PM PST 24 144658833 ps
T170 /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.69769598 Feb 04 12:51:45 PM PST 24 Feb 04 12:52:06 PM PST 24 587282430 ps
T822 /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.1888614625 Feb 04 12:51:46 PM PST 24 Feb 04 12:52:26 PM PST 24 621690937 ps
T823 /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.2553463898 Feb 04 12:51:56 PM PST 24 Feb 04 12:52:01 PM PST 24 6802489 ps
T824 /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.916059818 Feb 04 12:51:48 PM PST 24 Feb 04 12:51:52 PM PST 24 25606297 ps
T825 /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.2109265920 Feb 04 12:51:29 PM PST 24 Feb 04 12:54:37 PM PST 24 10202580015 ps
T133 /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.3350011956 Feb 04 12:51:34 PM PST 24 Feb 04 12:57:40 PM PST 24 5688902736 ps
T177 /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.1719125536 Feb 04 12:51:45 PM PST 24 Feb 04 12:51:49 PM PST 24 51683243 ps
T171 /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.1747528387 Feb 04 12:51:28 PM PST 24 Feb 04 12:52:40 PM PST 24 1054580401 ps
T826 /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.2858706721 Feb 04 12:51:54 PM PST 24 Feb 04 12:52:19 PM PST 24 608604035 ps
T827 /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.1900809400 Feb 04 12:51:28 PM PST 24 Feb 04 12:51:41 PM PST 24 334016567 ps
T828 /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.3296502718 Feb 04 12:51:43 PM PST 24 Feb 04 12:51:47 PM PST 24 24107619 ps
T829 /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.2553386130 Feb 04 12:51:30 PM PST 24 Feb 04 12:51:34 PM PST 24 10067079 ps
T147 /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.2718618228 Feb 04 12:51:46 PM PST 24 Feb 04 01:00:58 PM PST 24 54366349915 ps
T830 /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.1756012637 Feb 04 12:51:30 PM PST 24 Feb 04 12:51:37 PM PST 24 566803754 ps
T831 /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.4097046585 Feb 04 12:51:53 PM PST 24 Feb 04 12:51:57 PM PST 24 13282707 ps
T832 /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.825781541 Feb 04 12:51:44 PM PST 24 Feb 04 12:51:52 PM PST 24 240523107 ps
T833 /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.463186760 Feb 04 12:51:45 PM PST 24 Feb 04 12:54:56 PM PST 24 3631094603 ps
T834 /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.2328547885 Feb 04 12:51:42 PM PST 24 Feb 04 12:51:49 PM PST 24 37868101 ps
T835 /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.1463173473 Feb 04 12:51:41 PM PST 24 Feb 04 12:52:07 PM PST 24 356438352 ps
T836 /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.1628664682 Feb 04 12:51:33 PM PST 24 Feb 04 12:51:36 PM PST 24 6396613 ps
T837 /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.3860724646 Feb 04 12:51:49 PM PST 24 Feb 04 12:51:53 PM PST 24 11579000 ps
T157 /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.4061962170 Feb 04 12:51:40 PM PST 24 Feb 04 01:00:22 PM PST 24 5598037057 ps
T838 /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.2032234940 Feb 04 12:51:35 PM PST 24 Feb 04 12:52:03 PM PST 24 177120721 ps
T839 /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.3035565211 Feb 04 12:51:30 PM PST 24 Feb 04 12:51:45 PM PST 24 44745641 ps
T840 /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.275903922 Feb 04 12:51:36 PM PST 24 Feb 04 12:51:57 PM PST 24 788599963 ps
T150 /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.1232854834 Feb 04 12:51:44 PM PST 24 Feb 04 12:55:11 PM PST 24 1619382686 ps
T841 /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.3650528494 Feb 04 12:52:12 PM PST 24 Feb 04 12:52:15 PM PST 24 25870620 ps
T842 /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.4118918866 Feb 04 12:51:56 PM PST 24 Feb 04 12:52:00 PM PST 24 43807673 ps
T332 /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.4197402150 Feb 04 12:51:48 PM PST 24 Feb 04 12:59:14 PM PST 24 6391866369 ps
T156 /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.896081541 Feb 04 12:51:31 PM PST 24 Feb 04 12:53:58 PM PST 24 8612280452 ps
T843 /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.2945427660 Feb 04 12:51:48 PM PST 24 Feb 04 12:54:00 PM PST 24 1093590748 ps
T844 /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.542317698 Feb 04 12:51:40 PM PST 24 Feb 04 12:54:40 PM PST 24 1707047100 ps
T165 /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.1265593802 Feb 04 12:52:06 PM PST 24 Feb 04 12:52:48 PM PST 24 351586812 ps
T845 /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.1186009823 Feb 04 12:51:29 PM PST 24 Feb 04 12:51:33 PM PST 24 21309900 ps
T331 /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.3427981194 Feb 04 12:51:54 PM PST 24 Feb 04 01:02:37 PM PST 24 9223469619 ps
T846 /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.4255172136 Feb 04 12:51:28 PM PST 24 Feb 04 12:51:37 PM PST 24 58414866 ps
T847 /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.2110418077 Feb 04 12:51:38 PM PST 24 Feb 04 12:52:01 PM PST 24 767607784 ps
T164 /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.79922078 Feb 04 12:51:30 PM PST 24 Feb 04 12:52:11 PM PST 24 4845735725 ps
T848 /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.3090925014 Feb 04 12:51:40 PM PST 24 Feb 04 12:51:43 PM PST 24 26202129 ps

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.2927077555
Short name T14
Test name
Test status
Simulation time 265220378 ps
CPU time 5.61 seconds
Started Feb 04 12:51:29 PM PST 24
Finished Feb 04 12:51:37 PM PST 24
Peak memory 239804 kb
Host smart-313b5dd4-a10f-4022-a59c-9fdbb599cfe3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2927077555 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_hw_reset.2927077555
Directory /workspace/3.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all.46848065
Short name T22
Test name
Test status
Simulation time 76197589945 ps
CPU time 2927.77 seconds
Started Feb 04 01:22:29 PM PST 24
Finished Feb 04 02:11:18 PM PST 24
Peak memory 289584 kb
Host smart-3b99f5ef-01ca-4ccc-9d91-5a9f6b9062d2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46848065 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_hand
ler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_hand
ler_stress_all.46848065
Directory /workspace/42.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.720459187
Short name T153
Test name
Test status
Simulation time 516576040 ps
CPU time 33.29 seconds
Started Feb 04 12:51:48 PM PST 24
Finished Feb 04 12:52:23 PM PST 24
Peak memory 238660 kb
Host smart-382f0532-2111-4a4f-b625-33ed10ef487d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=720459187 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_intg_err.720459187
Directory /workspace/10.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all_with_rand_reset.3053208978
Short name T10
Test name
Test status
Simulation time 380896563499 ps
CPU time 7536.17 seconds
Started Feb 04 01:19:53 PM PST 24
Finished Feb 04 03:25:31 PM PST 24
Peak memory 363928 kb
Host smart-e1a08078-0d7c-41ae-9e87-47f648c92ce8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053208978 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.alert_handler_stress_all_with_rand_reset.3053208978
Directory /workspace/3.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.alert_handler_sec_cm.4124769681
Short name T11
Test name
Test status
Simulation time 946128060 ps
CPU time 23.93 seconds
Started Feb 04 01:19:37 PM PST 24
Finished Feb 04 01:20:04 PM PST 24
Peak memory 264068 kb
Host smart-94e460a0-7c07-48ae-92c6-06b05c7674e5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4124769681 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sec_cm.4124769681
Directory /workspace/2.alert_handler_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.4292597452
Short name T115
Test name
Test status
Simulation time 340112872 ps
CPU time 24.56 seconds
Started Feb 04 12:51:38 PM PST 24
Finished Feb 04 12:52:04 PM PST 24
Peak memory 253204 kb
Host smart-178f153d-6f36-410f-82b0-698acbc94ebe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4292597452 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_errors.4292597452
Directory /workspace/9.alert_handler_tl_errors/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all_with_rand_reset.1256904259
Short name T16
Test name
Test status
Simulation time 90892770637 ps
CPU time 3985.3 seconds
Started Feb 04 01:20:08 PM PST 24
Finished Feb 04 02:26:39 PM PST 24
Peak memory 321628 kb
Host smart-d073d477-1134-4590-a7b5-0a797385f67d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256904259 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 5.alert_handler_stress_all_with_rand_reset.1256904259
Directory /workspace/5.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.2555680785
Short name T126
Test name
Test status
Simulation time 24905526160 ps
CPU time 651.04 seconds
Started Feb 04 12:51:37 PM PST 24
Finished Feb 04 01:02:34 PM PST 24
Peak memory 272828 kb
Host smart-c7d36576-950f-439d-8fc2-4ed4ec659c30
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555680785 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 10.alert_handler_shadow_reg_errors_with_csr_rw.2555680785
Directory /workspace/10.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/13.alert_handler_lpg.3549359253
Short name T249
Test name
Test status
Simulation time 37832040167 ps
CPU time 2375.37 seconds
Started Feb 04 01:20:27 PM PST 24
Finished Feb 04 02:00:03 PM PST 24
Peak memory 289452 kb
Host smart-2df9487b-4b85-47dc-9ed2-c7535e9a83f5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549359253 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg.3549359253
Directory /workspace/13.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.2661666068
Short name T127
Test name
Test status
Simulation time 4636082988 ps
CPU time 582.82 seconds
Started Feb 04 12:51:45 PM PST 24
Finished Feb 04 01:01:30 PM PST 24
Peak memory 264748 kb
Host smart-7a5d914c-8708-4167-b3af-2bba27672ea4
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661666068 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 12.alert_handler_shadow_reg_errors_with_csr_rw.2661666068
Directory /workspace/12.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all.646466429
Short name T37
Test name
Test status
Simulation time 46329589028 ps
CPU time 1458.65 seconds
Started Feb 04 01:21:09 PM PST 24
Finished Feb 04 01:45:30 PM PST 24
Peak memory 289380 kb
Host smart-56429355-69c5-4791-a4c2-ee21155434eb
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646466429 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_han
dler_stress_all.646466429
Directory /workspace/25.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.3292315150
Short name T118
Test name
Test status
Simulation time 1654949144 ps
CPU time 222.49 seconds
Started Feb 04 12:51:48 PM PST 24
Finished Feb 04 12:55:33 PM PST 24
Peak memory 268724 kb
Host smart-2644384f-4ec2-4055-be7b-d09289518450
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3292315150 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shadow_reg_err
ors.3292315150
Directory /workspace/16.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.3125814807
Short name T30
Test name
Test status
Simulation time 9151263 ps
CPU time 1.51 seconds
Started Feb 04 12:51:43 PM PST 24
Finished Feb 04 12:51:47 PM PST 24
Peak memory 235128 kb
Host smart-52fce662-0f74-4e5b-94be-212cee3e3867
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3125814807 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_intr_test.3125814807
Directory /workspace/9.alert_handler_intr_test/latest

Test location /workspace/coverage/default/17.alert_handler_entropy_stress.3142063989
Short name T7
Test name
Test status
Simulation time 1112164729 ps
CPU time 16.94 seconds
Started Feb 04 01:20:51 PM PST 24
Finished Feb 04 01:21:13 PM PST 24
Peak memory 250972 kb
Host smart-6cbb44db-899a-44cd-936f-1cf9ca9b9e87
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3142063989 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy_stress.3142063989
Directory /workspace/17.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/25.alert_handler_lpg.1489356980
Short name T263
Test name
Test status
Simulation time 139730672002 ps
CPU time 2545.65 seconds
Started Feb 04 01:21:12 PM PST 24
Finished Feb 04 02:03:41 PM PST 24
Peak memory 287028 kb
Host smart-01cc249a-ffbc-4b7e-a3d4-59df0b78acf1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489356980 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg.1489356980
Directory /workspace/25.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.2718618228
Short name T147
Test name
Test status
Simulation time 54366349915 ps
CPU time 548.71 seconds
Started Feb 04 12:51:46 PM PST 24
Finished Feb 04 01:00:58 PM PST 24
Peak memory 271924 kb
Host smart-ca0d3229-9100-42a0-a42b-ef793802a46f
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718618228 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.alert_handler_shadow_reg_errors_with_csr_rw.2718618228
Directory /workspace/6.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/2.alert_handler_ping_timeout.2778385460
Short name T208
Test name
Test status
Simulation time 34712424976 ps
CPU time 381.14 seconds
Started Feb 04 01:19:40 PM PST 24
Finished Feb 04 01:26:11 PM PST 24
Peak memory 247164 kb
Host smart-6e633858-cc8b-448b-a1e7-a3fc6d370791
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2778385460 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_ping_timeout.2778385460
Directory /workspace/2.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.1723640061
Short name T135
Test name
Test status
Simulation time 1978329945 ps
CPU time 212.72 seconds
Started Feb 04 12:51:52 PM PST 24
Finished Feb 04 12:55:26 PM PST 24
Peak memory 264676 kb
Host smart-09888b7f-690e-4719-8f7d-bd4b1cc58f95
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1723640061 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shadow_reg_erro
rs.1723640061
Directory /workspace/7.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.3180293185
Short name T121
Test name
Test status
Simulation time 23931474669 ps
CPU time 330.15 seconds
Started Feb 04 12:51:47 PM PST 24
Finished Feb 04 12:57:20 PM PST 24
Peak memory 269764 kb
Host smart-e536825f-698a-4bfa-a701-5acad222679c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3180293185 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shadow_reg_err
ors.3180293185
Directory /workspace/15.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/9.alert_handler_ping_timeout.609002149
Short name T258
Test name
Test status
Simulation time 15690628804 ps
CPU time 658.18 seconds
Started Feb 04 01:20:08 PM PST 24
Finished Feb 04 01:31:11 PM PST 24
Peak memory 247224 kb
Host smart-331d41c9-c319-4419-a135-7b7e5df3abc2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609002149 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_ping_timeout.609002149
Directory /workspace/9.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_lpg.134713325
Short name T270
Test name
Test status
Simulation time 38814152155 ps
CPU time 2388.56 seconds
Started Feb 04 01:22:20 PM PST 24
Finished Feb 04 02:02:10 PM PST 24
Peak memory 288372 kb
Host smart-5242fe2a-cb7c-4d48-aaaf-ba8b0ad37949
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134713325 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg.134713325
Directory /workspace/41.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.2726682082
Short name T116
Test name
Test status
Simulation time 9998184549 ps
CPU time 285.51 seconds
Started Feb 04 12:51:48 PM PST 24
Finished Feb 04 12:56:36 PM PST 24
Peak memory 268704 kb
Host smart-a064adc0-bbda-4182-8284-a5559b16a58e
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726682082 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.alert_handler_shadow_reg_errors_with_csr_rw.2726682082
Directory /workspace/7.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/47.alert_handler_ping_timeout.3088600675
Short name T271
Test name
Test status
Simulation time 65828035685 ps
CPU time 766.89 seconds
Started Feb 04 01:22:38 PM PST 24
Finished Feb 04 01:35:32 PM PST 24
Peak memory 247200 kb
Host smart-6bdb0a8e-8990-4503-8d64-e0905dbce97a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088600675 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_ping_timeout.3088600675
Directory /workspace/47.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_entropy.1382451581
Short name T6
Test name
Test status
Simulation time 48194076016 ps
CPU time 1271.35 seconds
Started Feb 04 01:19:41 PM PST 24
Finished Feb 04 01:41:01 PM PST 24
Peak memory 286600 kb
Host smart-02d9812f-0e74-47c8-9052-f4fea24c1d06
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382451581 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy.1382451581
Directory /workspace/1.alert_handler_entropy/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.1232854834
Short name T150
Test name
Test status
Simulation time 1619382686 ps
CPU time 203.76 seconds
Started Feb 04 12:51:44 PM PST 24
Finished Feb 04 12:55:11 PM PST 24
Peak memory 264660 kb
Host smart-f1031284-36bd-4455-884f-81e63e168657
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1232854834 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shadow_reg_erro
rs.1232854834
Directory /workspace/8.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.2820725868
Short name T128
Test name
Test status
Simulation time 25701084240 ps
CPU time 852.63 seconds
Started Feb 04 12:51:43 PM PST 24
Finished Feb 04 01:05:58 PM PST 24
Peak memory 272688 kb
Host smart-78ad3786-17e9-4bde-82dd-5b99bfcdd55a
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820725868 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 11.alert_handler_shadow_reg_errors_with_csr_rw.2820725868
Directory /workspace/11.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/36.alert_handler_lpg.3163728572
Short name T17
Test name
Test status
Simulation time 63621369623 ps
CPU time 2125.67 seconds
Started Feb 04 01:22:01 PM PST 24
Finished Feb 04 01:57:28 PM PST 24
Peak memory 283212 kb
Host smart-b81b9cda-a339-4259-b16d-d6e3aaba3b16
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3163728572 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg.3163728572
Directory /workspace/36.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.4146087372
Short name T328
Test name
Test status
Simulation time 55155833 ps
CPU time 1.41 seconds
Started Feb 04 12:51:51 PM PST 24
Finished Feb 04 12:51:55 PM PST 24
Peak memory 235008 kb
Host smart-66c6cc99-b5f8-46b8-9056-5028b13904ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4146087372 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.alert_handler_intr_test.4146087372
Directory /workspace/38.alert_handler_intr_test/latest

Test location /workspace/coverage/default/12.alert_handler_ping_timeout.510657035
Short name T265
Test name
Test status
Simulation time 22391502344 ps
CPU time 462.48 seconds
Started Feb 04 01:20:13 PM PST 24
Finished Feb 04 01:28:03 PM PST 24
Peak memory 246400 kb
Host smart-9d3651a6-b097-4e48-bd06-bd56f21ce8f8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510657035 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_ping_timeout.510657035
Directory /workspace/12.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all.1798351136
Short name T93
Test name
Test status
Simulation time 36200750077 ps
CPU time 2248.74 seconds
Started Feb 04 01:20:11 PM PST 24
Finished Feb 04 01:57:47 PM PST 24
Peak memory 288784 kb
Host smart-9298feb8-d801-444b-b106-eabcd1ebdd4e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798351136 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_han
dler_stress_all.1798351136
Directory /workspace/8.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.3999317363
Short name T152
Test name
Test status
Simulation time 361735479 ps
CPU time 7.3 seconds
Started Feb 04 12:51:31 PM PST 24
Finished Feb 04 12:51:40 PM PST 24
Peak memory 235012 kb
Host smart-9cc54c53-76e7-4ee6-8ce8-50342477aedc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3999317363 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_rw.3999317363
Directory /workspace/0.alert_handler_csr_rw/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all.941566722
Short name T231
Test name
Test status
Simulation time 11277388561 ps
CPU time 376.9 seconds
Started Feb 04 01:22:37 PM PST 24
Finished Feb 04 01:28:56 PM PST 24
Peak memory 256756 kb
Host smart-6e085b15-2a18-4734-ba27-27c7e9047cda
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941566722 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_han
dler_stress_all.941566722
Directory /workspace/45.alert_handler_stress_all/latest

Test location /workspace/coverage/default/6.alert_handler_lpg.750726052
Short name T251
Test name
Test status
Simulation time 8214863084 ps
CPU time 696.98 seconds
Started Feb 04 01:20:06 PM PST 24
Finished Feb 04 01:31:49 PM PST 24
Peak memory 273016 kb
Host smart-b1c1ecf1-d639-4032-84aa-9ccdc01828db
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750726052 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg.750726052
Directory /workspace/6.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.2359426200
Short name T154
Test name
Test status
Simulation time 11717609569 ps
CPU time 246.53 seconds
Started Feb 04 12:52:11 PM PST 24
Finished Feb 04 12:56:20 PM PST 24
Peak memory 264920 kb
Host smart-f8b7681e-b7d1-4f4d-badd-8817c62295f5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2359426200 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shadow_reg_err
ors.2359426200
Directory /workspace/13.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.1447137951
Short name T178
Test name
Test status
Simulation time 342165105 ps
CPU time 42.19 seconds
Started Feb 04 12:51:34 PM PST 24
Finished Feb 04 12:52:17 PM PST 24
Peak memory 236004 kb
Host smart-d8d87e97-4f71-4407-8da4-72e49f2711d1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1447137951 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_intg_err.1447137951
Directory /workspace/9.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/20.alert_handler_sig_int_fail.1134829940
Short name T229
Test name
Test status
Simulation time 712815332 ps
CPU time 25.35 seconds
Started Feb 04 01:20:47 PM PST 24
Finished Feb 04 01:21:19 PM PST 24
Peak memory 254884 kb
Host smart-ba41cdea-03e1-4d87-b867-0c64799d521f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11348
29940 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_sig_int_fail.1134829940
Directory /workspace/20.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/23.alert_handler_ping_timeout.2969722930
Short name T655
Test name
Test status
Simulation time 29964638533 ps
CPU time 638.03 seconds
Started Feb 04 01:21:12 PM PST 24
Finished Feb 04 01:31:53 PM PST 24
Peak memory 247184 kb
Host smart-7e1b488b-36df-4341-845f-81fb2ebf95ea
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969722930 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_ping_timeout.2969722930
Directory /workspace/23.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all_with_rand_reset.1220880277
Short name T244
Test name
Test status
Simulation time 110007832768 ps
CPU time 7158.84 seconds
Started Feb 04 01:21:16 PM PST 24
Finished Feb 04 03:20:38 PM PST 24
Peak memory 314188 kb
Host smart-0cba577b-1642-4dbc-8f3f-44bfd111c285
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220880277 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 25.alert_handler_stress_all_with_rand_reset.1220880277
Directory /workspace/25.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.3427981194
Short name T331
Test name
Test status
Simulation time 9223469619 ps
CPU time 641.01 seconds
Started Feb 04 12:51:54 PM PST 24
Finished Feb 04 01:02:37 PM PST 24
Peak memory 264664 kb
Host smart-cd645ce9-3bf6-4ac3-9488-069339bfc825
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427981194 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.alert_handler_shadow_reg_errors_with_csr_rw.3427981194
Directory /workspace/5.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/11.alert_handler_lpg.2872205121
Short name T737
Test name
Test status
Simulation time 113017060749 ps
CPU time 1698.43 seconds
Started Feb 04 01:20:18 PM PST 24
Finished Feb 04 01:48:41 PM PST 24
Peak memory 266956 kb
Host smart-dadb2f69-76e8-46d8-8325-306f5121df01
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872205121 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg.2872205121
Directory /workspace/11.alert_handler_lpg/latest

Test location /workspace/coverage/default/13.alert_handler_ping_timeout.1043219713
Short name T8
Test name
Test status
Simulation time 27877840221 ps
CPU time 297.73 seconds
Started Feb 04 01:20:27 PM PST 24
Finished Feb 04 01:25:27 PM PST 24
Peak memory 247416 kb
Host smart-49d958ef-3557-447d-a843-7a60fb53634b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043219713 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_ping_timeout.1043219713
Directory /workspace/13.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_entropy.3747763767
Short name T98
Test name
Test status
Simulation time 171892758597 ps
CPU time 2351.84 seconds
Started Feb 04 01:19:52 PM PST 24
Finished Feb 04 01:59:06 PM PST 24
Peak memory 285864 kb
Host smart-7a7fe70d-f18f-4df0-a80d-babca6e942a0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747763767 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy.3747763767
Directory /workspace/3.alert_handler_entropy/latest

Test location /workspace/coverage/default/18.alert_handler_lpg.465606042
Short name T323
Test name
Test status
Simulation time 28397385408 ps
CPU time 1776.48 seconds
Started Feb 04 01:21:10 PM PST 24
Finished Feb 04 01:50:49 PM PST 24
Peak memory 272756 kb
Host smart-4b0095ff-58d0-4e06-963d-fa01b0327c2b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465606042 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg.465606042
Directory /workspace/18.alert_handler_lpg/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all_with_rand_reset.2539417204
Short name T237
Test name
Test status
Simulation time 65800216490 ps
CPU time 4462.21 seconds
Started Feb 04 01:21:11 PM PST 24
Finished Feb 04 02:35:37 PM PST 24
Peak memory 305344 kb
Host smart-377fc73a-5f98-4fff-9c4d-e65655fbd2bf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539417204 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 20.alert_handler_stress_all_with_rand_reset.2539417204
Directory /workspace/20.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all_with_rand_reset.3737082349
Short name T60
Test name
Test status
Simulation time 296869600411 ps
CPU time 6757.04 seconds
Started Feb 04 01:22:01 PM PST 24
Finished Feb 04 03:14:40 PM PST 24
Peak memory 354584 kb
Host smart-54db777e-87c5-4f4d-a463-9ee59a5a3f78
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737082349 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.alert_handler_stress_all_with_rand_reset.3737082349
Directory /workspace/38.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all.1292062928
Short name T248
Test name
Test status
Simulation time 140704385167 ps
CPU time 4102.77 seconds
Started Feb 04 01:19:54 PM PST 24
Finished Feb 04 02:28:19 PM PST 24
Peak memory 301292 kb
Host smart-ee0158d7-0c92-4b55-b205-45265d9fc30b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292062928 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_han
dler_stress_all.1292062928
Directory /workspace/4.alert_handler_stress_all/latest

Test location /workspace/coverage/default/32.alert_handler_random_classes.2957523533
Short name T39
Test name
Test status
Simulation time 1676951614 ps
CPU time 33.3 seconds
Started Feb 04 01:21:27 PM PST 24
Finished Feb 04 01:22:02 PM PST 24
Peak memory 246708 kb
Host smart-28e8b81c-719a-4c23-8728-7408d32c002e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29575
23533 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_classes.2957523533
Directory /workspace/32.alert_handler_random_classes/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.1633430626
Short name T172
Test name
Test status
Simulation time 46396005 ps
CPU time 3.45 seconds
Started Feb 04 12:51:40 PM PST 24
Finished Feb 04 12:51:45 PM PST 24
Peak memory 236364 kb
Host smart-0639dcbf-65f9-4365-b75e-6847f34c1d31
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1633430626 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_intg_err.1633430626
Directory /workspace/19.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.1451283108
Short name T123
Test name
Test status
Simulation time 1749635196 ps
CPU time 184.92 seconds
Started Feb 04 12:51:45 PM PST 24
Finished Feb 04 12:54:53 PM PST 24
Peak memory 264772 kb
Host smart-1dbad99a-6820-44d3-bbb3-95a3c3e2fa6c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1451283108 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shadow_reg_erro
rs.1451283108
Directory /workspace/3.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/0.alert_handler_alert_accum_saturation.3585377011
Short name T198
Test name
Test status
Simulation time 13539593 ps
CPU time 2.31 seconds
Started Feb 04 01:19:30 PM PST 24
Finished Feb 04 01:19:33 PM PST 24
Peak memory 248648 kb
Host smart-b674ad5d-5504-4fee-8c13-0200ee0a1420
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3585377011 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_alert_accum_saturation.3585377011
Directory /workspace/0.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/1.alert_handler_alert_accum_saturation.1625671168
Short name T195
Test name
Test status
Simulation time 42490020 ps
CPU time 3.76 seconds
Started Feb 04 01:19:42 PM PST 24
Finished Feb 04 01:19:54 PM PST 24
Peak memory 248616 kb
Host smart-3b54acac-1895-4ec9-a667-b64695cbfcab
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1625671168 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_alert_accum_saturation.1625671168
Directory /workspace/1.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/10.alert_handler_alert_accum_saturation.1223175528
Short name T193
Test name
Test status
Simulation time 54465267 ps
CPU time 4.1 seconds
Started Feb 04 01:20:13 PM PST 24
Finished Feb 04 01:20:25 PM PST 24
Peak memory 248516 kb
Host smart-5a80c5c6-ed59-41fb-8a2c-95c1d90c8d1c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1223175528 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_alert_accum_saturation.1223175528
Directory /workspace/10.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/12.alert_handler_alert_accum_saturation.3197924873
Short name T189
Test name
Test status
Simulation time 24364461 ps
CPU time 2.59 seconds
Started Feb 04 01:20:20 PM PST 24
Finished Feb 04 01:20:26 PM PST 24
Peak memory 248664 kb
Host smart-73f0919e-bb5f-49ff-ba5e-0375771bd4f3
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3197924873 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_alert_accum_saturation.3197924873
Directory /workspace/12.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all_with_rand_reset.193215737
Short name T109
Test name
Test status
Simulation time 149542444695 ps
CPU time 4498.35 seconds
Started Feb 04 01:19:42 PM PST 24
Finished Feb 04 02:34:50 PM PST 24
Peak memory 304876 kb
Host smart-9e2b0038-1daa-4d50-b3cb-29add2e91e60
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193215737 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 0.alert_handler_stress_all_with_rand_reset.193215737
Directory /workspace/0.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.alert_handler_ping_timeout.533030833
Short name T690
Test name
Test status
Simulation time 27942109930 ps
CPU time 313.45 seconds
Started Feb 04 01:20:15 PM PST 24
Finished Feb 04 01:25:36 PM PST 24
Peak memory 246416 kb
Host smart-431084b8-5ba6-4db3-af44-516c8243767d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533030833 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_ping_timeout.533030833
Directory /workspace/11.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_sig_int_fail.3434849671
Short name T59
Test name
Test status
Simulation time 1839956387 ps
CPU time 31.33 seconds
Started Feb 04 01:20:19 PM PST 24
Finished Feb 04 01:20:54 PM PST 24
Peak memory 254364 kb
Host smart-d2a15289-1a0d-421a-a6ad-b3179d86ec9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34348
49671 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_sig_int_fail.3434849671
Directory /workspace/13.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/19.alert_handler_lpg.3510572989
Short name T252
Test name
Test status
Simulation time 22441454832 ps
CPU time 1875.57 seconds
Started Feb 04 01:20:50 PM PST 24
Finished Feb 04 01:52:12 PM PST 24
Peak memory 288944 kb
Host smart-805cd230-183f-4c09-9c14-9cfe5dbfac3c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510572989 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg.3510572989
Directory /workspace/19.alert_handler_lpg/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all.1485811934
Short name T230
Test name
Test status
Simulation time 465690086017 ps
CPU time 2458.47 seconds
Started Feb 04 01:21:08 PM PST 24
Finished Feb 04 02:02:10 PM PST 24
Peak memory 289388 kb
Host smart-731a3120-9a84-4b58-bd2c-725ce5c8c4c5
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485811934 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_ha
ndler_stress_all.1485811934
Directory /workspace/21.alert_handler_stress_all/latest

Test location /workspace/coverage/default/28.alert_handler_entropy.2244120231
Short name T253
Test name
Test status
Simulation time 76878474068 ps
CPU time 2684.04 seconds
Started Feb 04 01:21:17 PM PST 24
Finished Feb 04 02:06:03 PM PST 24
Peak memory 289336 kb
Host smart-0f6d93d0-be18-4fca-92f4-bd19e52c733d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244120231 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_entropy.2244120231
Directory /workspace/28.alert_handler_entropy/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all_with_rand_reset.1578115764
Short name T246
Test name
Test status
Simulation time 141748436998 ps
CPU time 3947.77 seconds
Started Feb 04 01:20:11 PM PST 24
Finished Feb 04 02:26:06 PM PST 24
Peak memory 288900 kb
Host smart-b3c9b483-f02e-40d4-9fd4-020e47d042c0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578115764 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 9.alert_handler_stress_all_with_rand_reset.1578115764
Directory /workspace/9.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all_with_rand_reset.4059644767
Short name T285
Test name
Test status
Simulation time 116397633939 ps
CPU time 3987.11 seconds
Started Feb 04 01:21:06 PM PST 24
Finished Feb 04 02:27:37 PM PST 24
Peak memory 305572 kb
Host smart-04b87ba9-b4c5-4610-bba3-e81a79a176d6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059644767 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 22.alert_handler_stress_all_with_rand_reset.4059644767
Directory /workspace/22.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all.999729720
Short name T88
Test name
Test status
Simulation time 4803859438 ps
CPU time 94.51 seconds
Started Feb 04 01:20:05 PM PST 24
Finished Feb 04 01:21:45 PM PST 24
Peak memory 256768 kb
Host smart-9cf4e7ff-edc6-497a-9936-59a4042357ad
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999729720 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_hand
ler_stress_all.999729720
Directory /workspace/5.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.33822261
Short name T139
Test name
Test status
Simulation time 10251035525 ps
CPU time 122.71 seconds
Started Feb 04 12:51:48 PM PST 24
Finished Feb 04 12:54:00 PM PST 24
Peak memory 264516 kb
Host smart-965ace90-74ed-4a69-9184-281d549128ca
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=33822261 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shadow_reg_error
s.33822261
Directory /workspace/18.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.4230209674
Short name T132
Test name
Test status
Simulation time 2128569283 ps
CPU time 301.64 seconds
Started Feb 04 12:51:49 PM PST 24
Finished Feb 04 12:56:53 PM PST 24
Peak memory 264672 kb
Host smart-36e974a4-a36f-4b98-b60e-67f1573e5731
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230209674 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.alert_handler_shadow_reg_errors_with_csr_rw.4230209674
Directory /workspace/9.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/12.alert_handler_lpg.3517639572
Short name T312
Test name
Test status
Simulation time 55026818275 ps
CPU time 1513.36 seconds
Started Feb 04 01:20:13 PM PST 24
Finished Feb 04 01:45:34 PM PST 24
Peak memory 272820 kb
Host smart-989bbc7b-8e1d-4900-b619-90d335d10f19
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517639572 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg.3517639572
Directory /workspace/12.alert_handler_lpg/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all_with_rand_reset.1219988932
Short name T291
Test name
Test status
Simulation time 25730011737 ps
CPU time 1351.18 seconds
Started Feb 04 01:20:21 PM PST 24
Finished Feb 04 01:42:55 PM PST 24
Peak memory 289256 kb
Host smart-b63c6863-243d-4fad-af55-bb2ee7066ea3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219988932 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.alert_handler_stress_all_with_rand_reset.1219988932
Directory /workspace/13.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.alert_handler_ping_timeout.3641095767
Short name T638
Test name
Test status
Simulation time 14715430495 ps
CPU time 329.68 seconds
Started Feb 04 01:20:51 PM PST 24
Finished Feb 04 01:26:26 PM PST 24
Peak memory 247144 kb
Host smart-368dda3e-3b3c-45a8-a424-97088c1dfbb8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641095767 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_ping_timeout.3641095767
Directory /workspace/17.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all.150294285
Short name T110
Test name
Test status
Simulation time 47899815088 ps
CPU time 1408.75 seconds
Started Feb 04 01:21:05 PM PST 24
Finished Feb 04 01:44:39 PM PST 24
Peak memory 272348 kb
Host smart-a0a5f468-fac4-4fd8-ac04-c293572a2e98
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150294285 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_han
dler_stress_all.150294285
Directory /workspace/19.alert_handler_stress_all/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all_with_rand_reset.4140663329
Short name T64
Test name
Test status
Simulation time 235563750381 ps
CPU time 4797.84 seconds
Started Feb 04 01:20:44 PM PST 24
Finished Feb 04 02:40:45 PM PST 24
Peak memory 314012 kb
Host smart-d6bc8efc-390e-4fd6-97a8-ab91f240f409
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140663329 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 19.alert_handler_stress_all_with_rand_reset.4140663329
Directory /workspace/19.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.alert_handler_lpg.2212697554
Short name T319
Test name
Test status
Simulation time 47190343978 ps
CPU time 1457.4 seconds
Started Feb 04 01:21:03 PM PST 24
Finished Feb 04 01:45:27 PM PST 24
Peak memory 270452 kb
Host smart-5321e720-4315-40ed-bd13-59cd8c275633
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212697554 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg.2212697554
Directory /workspace/20.alert_handler_lpg/latest

Test location /workspace/coverage/default/27.alert_handler_random_classes.2281255760
Short name T279
Test name
Test status
Simulation time 1214186393 ps
CPU time 24.31 seconds
Started Feb 04 01:21:32 PM PST 24
Finished Feb 04 01:22:00 PM PST 24
Peak memory 246836 kb
Host smart-ec3c60cd-b1e2-4a44-bf17-3af26df82d0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22812
55760 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_classes.2281255760
Directory /workspace/27.alert_handler_random_classes/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all.3176609845
Short name T241
Test name
Test status
Simulation time 11576473564 ps
CPU time 670.38 seconds
Started Feb 04 01:21:59 PM PST 24
Finished Feb 04 01:33:12 PM PST 24
Peak memory 264900 kb
Host smart-c68328de-0656-417e-a4fe-9b8f75dc9cc9
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176609845 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_ha
ndler_stress_all.3176609845
Directory /workspace/38.alert_handler_stress_all/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all.540490211
Short name T76
Test name
Test status
Simulation time 97245374483 ps
CPU time 1201.65 seconds
Started Feb 04 01:22:45 PM PST 24
Finished Feb 04 01:42:49 PM PST 24
Peak memory 281360 kb
Host smart-f08846b1-776b-4695-be60-9ef2e77adf5e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540490211 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_han
dler_stress_all.540490211
Directory /workspace/47.alert_handler_stress_all/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all_with_rand_reset.2992875677
Short name T223
Test name
Test status
Simulation time 30628949680 ps
CPU time 1148.29 seconds
Started Feb 04 01:22:57 PM PST 24
Finished Feb 04 01:42:08 PM PST 24
Peak memory 267768 kb
Host smart-b1e43807-1d31-4b45-b649-34e33ebe34c3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992875677 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 48.alert_handler_stress_all_with_rand_reset.2992875677
Directory /workspace/48.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.2773753822
Short name T125
Test name
Test status
Simulation time 4047437216 ps
CPU time 33.87 seconds
Started Feb 04 12:52:01 PM PST 24
Finished Feb 04 12:52:39 PM PST 24
Peak memory 238792 kb
Host smart-eb72eec0-42ac-46d0-a0ed-d9d9de58b7cb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2773753822 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_intg_err.2773753822
Directory /workspace/11.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/11.alert_handler_lpg_stub_clk.3488085375
Short name T427
Test name
Test status
Simulation time 151048494818 ps
CPU time 2633.57 seconds
Started Feb 04 01:20:16 PM PST 24
Finished Feb 04 02:04:16 PM PST 24
Peak memory 289044 kb
Host smart-b32a7d94-84b9-481d-9a5f-0dea9d997bc1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488085375 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg_stub_clk.3488085375
Directory /workspace/11.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.360850963
Short name T146
Test name
Test status
Simulation time 8262446810 ps
CPU time 295.01 seconds
Started Feb 04 12:51:34 PM PST 24
Finished Feb 04 12:56:33 PM PST 24
Peak memory 264196 kb
Host smart-71bcba4e-13ea-4c0f-92d0-ebf303fa0ca7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=360850963 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shadow_reg_error
s.360850963
Directory /workspace/9.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.1265593802
Short name T165
Test name
Test status
Simulation time 351586812 ps
CPU time 35.48 seconds
Started Feb 04 12:52:06 PM PST 24
Finished Feb 04 12:52:48 PM PST 24
Peak memory 239768 kb
Host smart-789f7bde-a364-4dec-910c-62352e43e4c2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1265593802 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_intg_err.1265593802
Directory /workspace/13.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.1621402071
Short name T174
Test name
Test status
Simulation time 1213158472 ps
CPU time 65.51 seconds
Started Feb 04 12:51:43 PM PST 24
Finished Feb 04 12:52:51 PM PST 24
Peak memory 239772 kb
Host smart-fed31062-f673-4a16-aa68-c56cbe63dc4e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1621402071 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_intg_err.1621402071
Directory /workspace/14.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.109498784
Short name T166
Test name
Test status
Simulation time 2485225805 ps
CPU time 41.3 seconds
Started Feb 04 12:51:47 PM PST 24
Finished Feb 04 12:52:31 PM PST 24
Peak memory 239792 kb
Host smart-cbbb73fa-9d34-4868-bc77-baa10c2afcb0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=109498784 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_intg_err.109498784
Directory /workspace/17.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.1747528387
Short name T171
Test name
Test status
Simulation time 1054580401 ps
CPU time 69.88 seconds
Started Feb 04 12:51:28 PM PST 24
Finished Feb 04 12:52:40 PM PST 24
Peak memory 236196 kb
Host smart-da39128f-4771-47de-9081-79a9afa29dc8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1747528387 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_intg_err.1747528387
Directory /workspace/2.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.79922078
Short name T164
Test name
Test status
Simulation time 4845735725 ps
CPU time 38.97 seconds
Started Feb 04 12:51:30 PM PST 24
Finished Feb 04 12:52:11 PM PST 24
Peak memory 244332 kb
Host smart-3cc623a3-b3dd-4f15-80fb-611f27a79503
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=79922078 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_intg_err.79922078
Directory /workspace/3.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.896081541
Short name T156
Test name
Test status
Simulation time 8612280452 ps
CPU time 143.68 seconds
Started Feb 04 12:51:31 PM PST 24
Finished Feb 04 12:53:58 PM PST 24
Peak memory 266192 kb
Host smart-63ded3e7-50c2-4c71-b8a7-58d795659a38
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=896081541 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shadow_reg_error
s.896081541
Directory /workspace/0.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.3350011956
Short name T133
Test name
Test status
Simulation time 5688902736 ps
CPU time 364.4 seconds
Started Feb 04 12:51:34 PM PST 24
Finished Feb 04 12:57:40 PM PST 24
Peak memory 264232 kb
Host smart-21262608-0a60-45a5-95a3-56165a263e66
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3350011956 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shadow_reg_err
ors.3350011956
Directory /workspace/17.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.2480244344
Short name T173
Test name
Test status
Simulation time 104681385 ps
CPU time 2.6 seconds
Started Feb 04 12:52:14 PM PST 24
Finished Feb 04 12:52:18 PM PST 24
Peak memory 236296 kb
Host smart-607c632c-56a3-4cff-8df0-fb3c85c318a4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2480244344 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_intg_err.2480244344
Directory /workspace/5.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.3012623092
Short name T168
Test name
Test status
Simulation time 37681294 ps
CPU time 3.63 seconds
Started Feb 04 12:51:30 PM PST 24
Finished Feb 04 12:51:35 PM PST 24
Peak memory 236164 kb
Host smart-395c09ad-494c-4307-a057-b0f6b892e5c3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3012623092 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_intg_err.3012623092
Directory /workspace/8.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.4274783506
Short name T28
Test name
Test status
Simulation time 56769315 ps
CPU time 3.52 seconds
Started Feb 04 12:51:39 PM PST 24
Finished Feb 04 12:51:44 PM PST 24
Peak memory 235904 kb
Host smart-9143759f-e384-49f4-be4d-9945a8c6bbcb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4274783506 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_intg_err.4274783506
Directory /workspace/0.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.1471948495
Short name T169
Test name
Test status
Simulation time 5815279740 ps
CPU time 36.49 seconds
Started Feb 04 12:51:45 PM PST 24
Finished Feb 04 12:52:24 PM PST 24
Peak memory 235824 kb
Host smart-bd9a2d1a-d00f-42c2-b4a0-1d2b04e9e7b6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1471948495 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_intg_err.1471948495
Directory /workspace/1.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.1185817327
Short name T167
Test name
Test status
Simulation time 47391071 ps
CPU time 3.26 seconds
Started Feb 04 12:51:48 PM PST 24
Finished Feb 04 12:51:54 PM PST 24
Peak memory 236056 kb
Host smart-0429fe09-2770-43fc-86d7-f6c84406f17c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1185817327 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_intg_err.1185817327
Directory /workspace/15.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.69769598
Short name T170
Test name
Test status
Simulation time 587282430 ps
CPU time 19.53 seconds
Started Feb 04 12:51:45 PM PST 24
Finished Feb 04 12:52:06 PM PST 24
Peak memory 244064 kb
Host smart-8f934c61-42db-4b7c-a9ad-c04413ce6c80
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=69769598 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_intg_err.69769598
Directory /workspace/4.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.379813299
Short name T176
Test name
Test status
Simulation time 115536731 ps
CPU time 2.78 seconds
Started Feb 04 12:51:54 PM PST 24
Finished Feb 04 12:51:59 PM PST 24
Peak memory 236080 kb
Host smart-df6b910b-7dc6-482a-8b8a-57a3fb113546
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=379813299 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_intg_err.379813299
Directory /workspace/6.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.2608881628
Short name T175
Test name
Test status
Simulation time 1322751719 ps
CPU time 39.8 seconds
Started Feb 04 12:51:57 PM PST 24
Finished Feb 04 12:52:41 PM PST 24
Peak memory 248036 kb
Host smart-282f542c-3415-40cd-8457-3b7f639e24f9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2608881628 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_intg_err.2608881628
Directory /workspace/7.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all.2085345816
Short name T35
Test name
Test status
Simulation time 17543459329 ps
CPU time 1799.05 seconds
Started Feb 04 01:20:14 PM PST 24
Finished Feb 04 01:50:21 PM PST 24
Peak memory 288860 kb
Host smart-6e4435d3-da05-4993-b199-ee7c350d0f62
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085345816 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_ha
ndler_stress_all.2085345816
Directory /workspace/11.alert_handler_stress_all/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all.582993997
Short name T32
Test name
Test status
Simulation time 69356926401 ps
CPU time 2377.41 seconds
Started Feb 04 01:21:08 PM PST 24
Finished Feb 04 02:00:48 PM PST 24
Peak memory 282256 kb
Host smart-4a652f0b-5427-42da-9ae5-667361b8127f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582993997 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_han
dler_stress_all.582993997
Directory /workspace/23.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.131283663
Short name T184
Test name
Test status
Simulation time 3735955285 ps
CPU time 235.72 seconds
Started Feb 04 12:51:29 PM PST 24
Finished Feb 04 12:55:26 PM PST 24
Peak memory 239904 kb
Host smart-2763ee30-eb1c-4e0d-871e-c9c4f29a7c4b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=131283663 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_aliasing.131283663
Directory /workspace/0.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.463186760
Short name T833
Test name
Test status
Simulation time 3631094603 ps
CPU time 188.83 seconds
Started Feb 04 12:51:45 PM PST 24
Finished Feb 04 12:54:56 PM PST 24
Peak memory 235828 kb
Host smart-9be17dd8-b07f-48de-9feb-7877d821ba06
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=463186760 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_bit_bash.463186760
Directory /workspace/0.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.1900809400
Short name T827
Test name
Test status
Simulation time 334016567 ps
CPU time 10.65 seconds
Started Feb 04 12:51:28 PM PST 24
Finished Feb 04 12:51:41 PM PST 24
Peak memory 239832 kb
Host smart-b1adacfd-8f64-461c-986b-7a2f6bb6d17d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1900809400 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_hw_reset.1900809400
Directory /workspace/0.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.299312102
Short name T337
Test name
Test status
Simulation time 25455035 ps
CPU time 3.18 seconds
Started Feb 04 12:51:48 PM PST 24
Finished Feb 04 12:51:54 PM PST 24
Peak memory 239848 kb
Host smart-02998ff6-9e70-4fb3-89cf-7dd41edf5c26
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299312102 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 0.alert_handler_csr_mem_rw_with_rand_reset.299312102
Directory /workspace/0.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.1626343818
Short name T818
Test name
Test status
Simulation time 11738239 ps
CPU time 1.58 seconds
Started Feb 04 12:51:47 PM PST 24
Finished Feb 04 12:51:51 PM PST 24
Peak memory 235776 kb
Host smart-a4b21ed4-bdb0-433c-8c98-c3b1d27b6d67
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1626343818 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_intr_test.1626343818
Directory /workspace/0.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.3056167981
Short name T755
Test name
Test status
Simulation time 338123197 ps
CPU time 12.34 seconds
Started Feb 04 12:51:34 PM PST 24
Finished Feb 04 12:51:48 PM PST 24
Peak memory 244116 kb
Host smart-299a8396-ee56-44a2-b07a-61df2b4340ca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3056167981 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_same_csr_out
standing.3056167981
Directory /workspace/0.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.858549399
Short name T144
Test name
Test status
Simulation time 6108263816 ps
CPU time 467.9 seconds
Started Feb 04 12:51:37 PM PST 24
Finished Feb 04 12:59:27 PM PST 24
Peak memory 264860 kb
Host smart-3fe6b444-79d1-47a2-accd-5529d93317cf
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858549399 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.alert_handler_shadow_reg_errors_with_csr_rw.858549399
Directory /workspace/0.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.3782053800
Short name T160
Test name
Test status
Simulation time 579770377 ps
CPU time 18.38 seconds
Started Feb 04 12:51:45 PM PST 24
Finished Feb 04 12:52:05 PM PST 24
Peak memory 247984 kb
Host smart-ed3f57a7-03c4-41a4-a74e-a4f0d678dc36
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3782053800 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_errors.3782053800
Directory /workspace/0.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.2700074451
Short name T790
Test name
Test status
Simulation time 6318130803 ps
CPU time 70.01 seconds
Started Feb 04 12:51:48 PM PST 24
Finished Feb 04 12:53:01 PM PST 24
Peak memory 235900 kb
Host smart-3bcef1b2-e888-4a6d-af11-651556439a74
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2700074451 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_aliasing.2700074451
Directory /workspace/1.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.2109265920
Short name T825
Test name
Test status
Simulation time 10202580015 ps
CPU time 186.7 seconds
Started Feb 04 12:51:29 PM PST 24
Finished Feb 04 12:54:37 PM PST 24
Peak memory 239844 kb
Host smart-c2ba6d2e-00a6-467b-a590-3314553203c7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2109265920 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_bit_bash.2109265920
Directory /workspace/1.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.1938830615
Short name T120
Test name
Test status
Simulation time 220743968 ps
CPU time 8.35 seconds
Started Feb 04 12:51:46 PM PST 24
Finished Feb 04 12:51:57 PM PST 24
Peak memory 239708 kb
Host smart-d44de4d1-4393-4bc5-907e-5a9b3b9e27be
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1938830615 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_hw_reset.1938830615
Directory /workspace/1.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.4255172136
Short name T846
Test name
Test status
Simulation time 58414866 ps
CPU time 6.91 seconds
Started Feb 04 12:51:28 PM PST 24
Finished Feb 04 12:51:37 PM PST 24
Peak memory 250604 kb
Host smart-ec2f26df-adac-42c0-bcce-4bbfb01bee26
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255172136 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 1.alert_handler_csr_mem_rw_with_rand_reset.4255172136
Directory /workspace/1.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.376135174
Short name T813
Test name
Test status
Simulation time 376331874 ps
CPU time 4.21 seconds
Started Feb 04 12:51:26 PM PST 24
Finished Feb 04 12:51:32 PM PST 24
Peak memory 238732 kb
Host smart-35df48ea-3bc6-4f71-aa03-abfe0c0cd7a5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=376135174 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_rw.376135174
Directory /workspace/1.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.2945050025
Short name T806
Test name
Test status
Simulation time 38133494 ps
CPU time 1.42 seconds
Started Feb 04 12:51:43 PM PST 24
Finished Feb 04 12:51:47 PM PST 24
Peak memory 235844 kb
Host smart-851f7a18-56f0-4b5d-a9e6-f2a53352507e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2945050025 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_intr_test.2945050025
Directory /workspace/1.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.2764647444
Short name T748
Test name
Test status
Simulation time 334397770 ps
CPU time 11.19 seconds
Started Feb 04 12:51:20 PM PST 24
Finished Feb 04 12:51:36 PM PST 24
Peak memory 237852 kb
Host smart-58f20ba6-8808-4e1c-afdc-11d9036c9466
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2764647444 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_same_csr_out
standing.2764647444
Directory /workspace/1.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.542317698
Short name T844
Test name
Test status
Simulation time 1707047100 ps
CPU time 177.23 seconds
Started Feb 04 12:51:40 PM PST 24
Finished Feb 04 12:54:40 PM PST 24
Peak memory 264744 kb
Host smart-9e77cb7d-42e1-4ab3-91a4-f498f18d4eab
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=542317698 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shadow_reg_error
s.542317698
Directory /workspace/1.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.2067250388
Short name T23
Test name
Test status
Simulation time 52529270556 ps
CPU time 494.34 seconds
Started Feb 04 12:51:45 PM PST 24
Finished Feb 04 01:00:02 PM PST 24
Peak memory 264868 kb
Host smart-e6d9062c-148c-4348-9262-9b2adb1d1934
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067250388 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.alert_handler_shadow_reg_errors_with_csr_rw.2067250388
Directory /workspace/1.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.3035565211
Short name T839
Test name
Test status
Simulation time 44745641 ps
CPU time 6.37 seconds
Started Feb 04 12:51:30 PM PST 24
Finished Feb 04 12:51:45 PM PST 24
Peak memory 248128 kb
Host smart-db7ed344-618a-47e9-ac0d-db7275a45fac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3035565211 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_errors.3035565211
Directory /workspace/1.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.4091337207
Short name T802
Test name
Test status
Simulation time 34271786 ps
CPU time 4.23 seconds
Started Feb 04 12:51:41 PM PST 24
Finished Feb 04 12:51:47 PM PST 24
Peak memory 238000 kb
Host smart-eb465d7e-5477-4535-b369-44cc7a8cfa39
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091337207 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 10.alert_handler_csr_mem_rw_with_rand_reset.4091337207
Directory /workspace/10.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.2677029014
Short name T768
Test name
Test status
Simulation time 50258619 ps
CPU time 4.56 seconds
Started Feb 04 12:51:41 PM PST 24
Finished Feb 04 12:51:47 PM PST 24
Peak memory 235028 kb
Host smart-8fa7d1d6-fec7-4065-94e4-01768a818f12
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2677029014 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_rw.2677029014
Directory /workspace/10.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.1702611962
Short name T743
Test name
Test status
Simulation time 13720626 ps
CPU time 1.32 seconds
Started Feb 04 12:51:40 PM PST 24
Finished Feb 04 12:51:43 PM PST 24
Peak memory 235656 kb
Host smart-881dabbd-2ae9-4565-9d81-9bc2defcd2e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1702611962 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_intr_test.1702611962
Directory /workspace/10.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.2586358534
Short name T801
Test name
Test status
Simulation time 3613665142 ps
CPU time 19.68 seconds
Started Feb 04 12:51:37 PM PST 24
Finished Feb 04 12:51:59 PM PST 24
Peak memory 244176 kb
Host smart-318676e0-938b-4fe0-ad22-79f0016ae4d5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2586358534 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_same_csr_ou
tstanding.2586358534
Directory /workspace/10.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.3427003442
Short name T142
Test name
Test status
Simulation time 3349098156 ps
CPU time 197.63 seconds
Started Feb 04 12:51:48 PM PST 24
Finished Feb 04 12:55:08 PM PST 24
Peak memory 256316 kb
Host smart-98a55851-8c8b-42f0-9357-eb2212b84e2b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3427003442 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shadow_reg_err
ors.3427003442
Directory /workspace/10.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.260016740
Short name T754
Test name
Test status
Simulation time 172001089 ps
CPU time 12.17 seconds
Started Feb 04 12:51:48 PM PST 24
Finished Feb 04 12:52:03 PM PST 24
Peak memory 248060 kb
Host smart-22561fae-86af-4a4f-bb93-767b39be7c29
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=260016740 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_errors.260016740
Directory /workspace/10.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.3347483079
Short name T762
Test name
Test status
Simulation time 65273784 ps
CPU time 6.97 seconds
Started Feb 04 12:52:07 PM PST 24
Finished Feb 04 12:52:20 PM PST 24
Peak memory 252672 kb
Host smart-0817b680-49e2-4edc-a377-b03bb1497ee5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347483079 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 11.alert_handler_csr_mem_rw_with_rand_reset.3347483079
Directory /workspace/11.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.1981284152
Short name T183
Test name
Test status
Simulation time 66150283 ps
CPU time 5.35 seconds
Started Feb 04 12:51:50 PM PST 24
Finished Feb 04 12:51:58 PM PST 24
Peak memory 235788 kb
Host smart-825bb95e-8e10-4996-8ebc-bac1378b40c9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1981284152 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_rw.1981284152
Directory /workspace/11.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.4125071709
Short name T326
Test name
Test status
Simulation time 9607876 ps
CPU time 1.57 seconds
Started Feb 04 12:52:11 PM PST 24
Finished Feb 04 12:52:15 PM PST 24
Peak memory 235028 kb
Host smart-f7363a3c-90f2-4686-afac-9ae2864bd275
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4125071709 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_intr_test.4125071709
Directory /workspace/11.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.2103082082
Short name T786
Test name
Test status
Simulation time 676201265 ps
CPU time 21.39 seconds
Started Feb 04 12:52:08 PM PST 24
Finished Feb 04 12:52:35 PM PST 24
Peak memory 243988 kb
Host smart-35e9c8ea-3309-4839-933e-da4122680b47
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2103082082 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_same_csr_ou
tstanding.2103082082
Directory /workspace/11.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.162508731
Short name T137
Test name
Test status
Simulation time 14191682021 ps
CPU time 269.24 seconds
Started Feb 04 12:51:44 PM PST 24
Finished Feb 04 12:56:15 PM PST 24
Peak memory 264756 kb
Host smart-fcc3d59e-d54b-4653-ae67-fc364cf2025f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=162508731 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shadow_reg_erro
rs.162508731
Directory /workspace/11.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.3673071221
Short name T781
Test name
Test status
Simulation time 61514511 ps
CPU time 5.75 seconds
Started Feb 04 12:51:45 PM PST 24
Finished Feb 04 12:51:53 PM PST 24
Peak memory 246756 kb
Host smart-8fa58c6b-3e69-4275-8d4f-a6632da9291b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3673071221 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_errors.3673071221
Directory /workspace/11.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.4273123501
Short name T796
Test name
Test status
Simulation time 116177718 ps
CPU time 4.14 seconds
Started Feb 04 12:51:46 PM PST 24
Finished Feb 04 12:51:53 PM PST 24
Peak memory 237416 kb
Host smart-0e7bf84a-b532-495e-95ab-6210f80e6299
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273123501 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 12.alert_handler_csr_mem_rw_with_rand_reset.4273123501
Directory /workspace/12.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.2595923809
Short name T31
Test name
Test status
Simulation time 51778102 ps
CPU time 5.06 seconds
Started Feb 04 12:51:46 PM PST 24
Finished Feb 04 12:51:54 PM PST 24
Peak memory 239728 kb
Host smart-d335a7e7-30b9-43be-a2ab-559790207e45
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2595923809 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_rw.2595923809
Directory /workspace/12.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.1478421525
Short name T816
Test name
Test status
Simulation time 11967175 ps
CPU time 1.67 seconds
Started Feb 04 12:52:01 PM PST 24
Finished Feb 04 12:52:07 PM PST 24
Peak memory 235024 kb
Host smart-211abee2-d3b6-4cc0-9085-e8f53e91db1a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1478421525 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_intr_test.1478421525
Directory /workspace/12.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.228100561
Short name T774
Test name
Test status
Simulation time 382216728 ps
CPU time 19.81 seconds
Started Feb 04 12:52:09 PM PST 24
Finished Feb 04 12:52:33 PM PST 24
Peak memory 243136 kb
Host smart-9b37ef93-b7cb-48f7-a7d5-fc51e3c446ba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=228100561 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_same_csr_out
standing.228100561
Directory /workspace/12.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.125519735
Short name T158
Test name
Test status
Simulation time 37160219043 ps
CPU time 142.42 seconds
Started Feb 04 12:51:54 PM PST 24
Finished Feb 04 12:54:19 PM PST 24
Peak memory 256560 kb
Host smart-305c0f41-a0da-4242-930c-2bd2b762ca9c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=125519735 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shadow_reg_erro
rs.125519735
Directory /workspace/12.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.1286446578
Short name T26
Test name
Test status
Simulation time 185629150 ps
CPU time 13.01 seconds
Started Feb 04 12:51:44 PM PST 24
Finished Feb 04 12:51:59 PM PST 24
Peak memory 247800 kb
Host smart-b6e29c58-3ec7-424f-8fc7-9536d15cc14a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1286446578 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_errors.1286446578
Directory /workspace/12.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.2858706721
Short name T826
Test name
Test status
Simulation time 608604035 ps
CPU time 22.47 seconds
Started Feb 04 12:51:54 PM PST 24
Finished Feb 04 12:52:19 PM PST 24
Peak memory 235988 kb
Host smart-25a079f6-edcd-4f11-82f2-515e2cdc56e0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2858706721 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_intg_err.2858706721
Directory /workspace/12.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.2628064227
Short name T804
Test name
Test status
Simulation time 70518242 ps
CPU time 7.24 seconds
Started Feb 04 12:51:46 PM PST 24
Finished Feb 04 12:51:56 PM PST 24
Peak memory 242640 kb
Host smart-b412159e-de80-406a-b0d5-a37c4264dd21
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628064227 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 13.alert_handler_csr_mem_rw_with_rand_reset.2628064227
Directory /workspace/13.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.2937617820
Short name T760
Test name
Test status
Simulation time 63760425 ps
CPU time 4.76 seconds
Started Feb 04 12:51:50 PM PST 24
Finished Feb 04 12:51:57 PM PST 24
Peak memory 235000 kb
Host smart-c48a7a0d-f6d2-49a7-aa5f-81abd42d5b4d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2937617820 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_rw.2937617820
Directory /workspace/13.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.2999484482
Short name T185
Test name
Test status
Simulation time 8342202 ps
CPU time 1.45 seconds
Started Feb 04 12:51:54 PM PST 24
Finished Feb 04 12:51:57 PM PST 24
Peak memory 235032 kb
Host smart-d767e877-48bd-4f8c-885e-673b7d2a6d43
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2999484482 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_intr_test.2999484482
Directory /workspace/13.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.523749992
Short name T766
Test name
Test status
Simulation time 2114915734 ps
CPU time 35.83 seconds
Started Feb 04 12:51:25 PM PST 24
Finished Feb 04 12:52:03 PM PST 24
Peak memory 243936 kb
Host smart-24938489-4a89-4d50-b8e8-d78876b19c78
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=523749992 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_same_csr_out
standing.523749992
Directory /workspace/13.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.330611641
Short name T134
Test name
Test status
Simulation time 35955951877 ps
CPU time 508.4 seconds
Started Feb 04 12:52:16 PM PST 24
Finished Feb 04 01:00:47 PM PST 24
Peak memory 264716 kb
Host smart-25174f79-e603-4e7a-8b28-a3b4d2d08e35
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330611641 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 13.alert_handler_shadow_reg_errors_with_csr_rw.330611641
Directory /workspace/13.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.2033758539
Short name T161
Test name
Test status
Simulation time 77614323 ps
CPU time 5.99 seconds
Started Feb 04 12:51:43 PM PST 24
Finished Feb 04 12:51:51 PM PST 24
Peak memory 247924 kb
Host smart-0bda622f-8693-4b02-ab99-c88d620f3dc2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2033758539 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_errors.2033758539
Directory /workspace/13.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.2898668427
Short name T338
Test name
Test status
Simulation time 143437307 ps
CPU time 4.61 seconds
Started Feb 04 12:51:44 PM PST 24
Finished Feb 04 12:51:51 PM PST 24
Peak memory 239000 kb
Host smart-8f67438d-b056-4e8f-add4-fbbcdc39eca2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898668427 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 14.alert_handler_csr_mem_rw_with_rand_reset.2898668427
Directory /workspace/14.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.2340214699
Short name T330
Test name
Test status
Simulation time 122785677 ps
CPU time 5.14 seconds
Started Feb 04 12:51:32 PM PST 24
Finished Feb 04 12:51:40 PM PST 24
Peak memory 239784 kb
Host smart-2430a258-763f-4c65-9de3-88d30d5245db
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2340214699 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_rw.2340214699
Directory /workspace/14.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.3832566977
Short name T782
Test name
Test status
Simulation time 12688524 ps
CPU time 1.27 seconds
Started Feb 04 12:51:34 PM PST 24
Finished Feb 04 12:51:37 PM PST 24
Peak memory 234916 kb
Host smart-1a0cd954-b80f-4104-9b49-3b1dbd3fb9ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3832566977 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_intr_test.3832566977
Directory /workspace/14.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.1365654156
Short name T819
Test name
Test status
Simulation time 1881992663 ps
CPU time 39.77 seconds
Started Feb 04 12:51:48 PM PST 24
Finished Feb 04 12:52:30 PM PST 24
Peak memory 243224 kb
Host smart-fd8d198d-de49-41ce-b01d-82b29f0189af
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1365654156 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_same_csr_ou
tstanding.1365654156
Directory /workspace/14.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.2457897230
Short name T130
Test name
Test status
Simulation time 47406938681 ps
CPU time 170.91 seconds
Started Feb 04 12:51:42 PM PST 24
Finished Feb 04 12:54:35 PM PST 24
Peak memory 256540 kb
Host smart-51608013-ff56-4c70-98cf-ed672fdb69ee
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2457897230 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shadow_reg_err
ors.2457897230
Directory /workspace/14.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.1621515122
Short name T145
Test name
Test status
Simulation time 30499470364 ps
CPU time 421.56 seconds
Started Feb 04 12:51:45 PM PST 24
Finished Feb 04 12:58:49 PM PST 24
Peak memory 264676 kb
Host smart-82769055-0dd9-4eea-ab92-315023684b82
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621515122 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 14.alert_handler_shadow_reg_errors_with_csr_rw.1621515122
Directory /workspace/14.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.3228962206
Short name T751
Test name
Test status
Simulation time 40215726 ps
CPU time 6.16 seconds
Started Feb 04 12:51:30 PM PST 24
Finished Feb 04 12:51:39 PM PST 24
Peak memory 247860 kb
Host smart-0e18e52b-9f54-405e-a600-586baf0d4881
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3228962206 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_errors.3228962206
Directory /workspace/14.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.2295667091
Short name T777
Test name
Test status
Simulation time 42707116 ps
CPU time 2.95 seconds
Started Feb 04 12:51:45 PM PST 24
Finished Feb 04 12:51:50 PM PST 24
Peak memory 236968 kb
Host smart-699419ce-8c09-43e2-b68f-79d75494930e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295667091 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 15.alert_handler_csr_mem_rw_with_rand_reset.2295667091
Directory /workspace/15.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.2332971606
Short name T805
Test name
Test status
Simulation time 225870432 ps
CPU time 5.24 seconds
Started Feb 04 12:51:48 PM PST 24
Finished Feb 04 12:51:56 PM PST 24
Peak memory 234776 kb
Host smart-30321c09-8b1e-418c-af4d-417636e47908
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2332971606 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_rw.2332971606
Directory /workspace/15.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.1628664682
Short name T836
Test name
Test status
Simulation time 6396613 ps
CPU time 1.41 seconds
Started Feb 04 12:51:33 PM PST 24
Finished Feb 04 12:51:36 PM PST 24
Peak memory 234008 kb
Host smart-8b8657de-a31b-420a-b66f-f3b3f7284c9b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1628664682 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_intr_test.1628664682
Directory /workspace/15.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.1888614625
Short name T822
Test name
Test status
Simulation time 621690937 ps
CPU time 37.86 seconds
Started Feb 04 12:51:46 PM PST 24
Finished Feb 04 12:52:26 PM PST 24
Peak memory 243232 kb
Host smart-3804d814-d31a-4715-aa74-d0e51abc6265
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1888614625 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_same_csr_ou
tstanding.1888614625
Directory /workspace/15.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.4197402150
Short name T332
Test name
Test status
Simulation time 6391866369 ps
CPU time 444.07 seconds
Started Feb 04 12:51:48 PM PST 24
Finished Feb 04 12:59:14 PM PST 24
Peak memory 268480 kb
Host smart-d8dba986-5f52-4f86-9d53-0e2231292d83
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197402150 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 15.alert_handler_shadow_reg_errors_with_csr_rw.4197402150
Directory /workspace/15.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.4005513986
Short name T772
Test name
Test status
Simulation time 246251312 ps
CPU time 12.8 seconds
Started Feb 04 12:51:34 PM PST 24
Finished Feb 04 12:51:49 PM PST 24
Peak memory 248112 kb
Host smart-fb6eade2-d3b9-4c6f-951a-bf289e32d512
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4005513986 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_errors.4005513986
Directory /workspace/15.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.3115734342
Short name T335
Test name
Test status
Simulation time 150911648 ps
CPU time 4.39 seconds
Started Feb 04 12:51:48 PM PST 24
Finished Feb 04 12:51:54 PM PST 24
Peak memory 239796 kb
Host smart-be1298ad-c4ca-476a-9f0c-d89dad6c2da0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115734342 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 16.alert_handler_csr_mem_rw_with_rand_reset.3115734342
Directory /workspace/16.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.1046420515
Short name T814
Test name
Test status
Simulation time 128778972 ps
CPU time 9.23 seconds
Started Feb 04 12:51:48 PM PST 24
Finished Feb 04 12:51:59 PM PST 24
Peak memory 235776 kb
Host smart-46390939-9e71-4a3f-afb9-42772553dff2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1046420515 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_rw.1046420515
Directory /workspace/16.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.4118918866
Short name T842
Test name
Test status
Simulation time 43807673 ps
CPU time 1.44 seconds
Started Feb 04 12:51:56 PM PST 24
Finished Feb 04 12:52:00 PM PST 24
Peak memory 235832 kb
Host smart-4be95bc6-20cf-431d-b6d0-112bfae745b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4118918866 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_intr_test.4118918866
Directory /workspace/16.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.272970699
Short name T784
Test name
Test status
Simulation time 90913754 ps
CPU time 12.04 seconds
Started Feb 04 12:51:37 PM PST 24
Finished Feb 04 12:51:51 PM PST 24
Peak memory 243092 kb
Host smart-5db9e7c9-f346-46ac-928f-3b3f06baae96
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=272970699 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_same_csr_out
standing.272970699
Directory /workspace/16.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.1827376215
Short name T149
Test name
Test status
Simulation time 63562988705 ps
CPU time 1099.82 seconds
Started Feb 04 12:51:48 PM PST 24
Finished Feb 04 01:10:10 PM PST 24
Peak memory 264588 kb
Host smart-1307536e-9cd2-4ede-a42d-08aad12801bc
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827376215 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 16.alert_handler_shadow_reg_errors_with_csr_rw.1827376215
Directory /workspace/16.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.3199188362
Short name T810
Test name
Test status
Simulation time 652048797 ps
CPU time 12.21 seconds
Started Feb 04 12:51:35 PM PST 24
Finished Feb 04 12:51:51 PM PST 24
Peak memory 248052 kb
Host smart-f31b13e8-e330-4edd-9fa9-ce0ff9a01bf5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3199188362 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_errors.3199188362
Directory /workspace/16.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.1078153860
Short name T770
Test name
Test status
Simulation time 54540140 ps
CPU time 2.07 seconds
Started Feb 04 12:51:36 PM PST 24
Finished Feb 04 12:51:41 PM PST 24
Peak memory 236368 kb
Host smart-6545f406-fcc9-4c16-b9e8-965897310027
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1078153860 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_intg_err.1078153860
Directory /workspace/16.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.1600309176
Short name T744
Test name
Test status
Simulation time 240121652 ps
CPU time 7.13 seconds
Started Feb 04 12:51:58 PM PST 24
Finished Feb 04 12:52:09 PM PST 24
Peak memory 253112 kb
Host smart-9f534847-fa6d-43e4-86bf-d51e233aaa2f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600309176 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 17.alert_handler_csr_mem_rw_with_rand_reset.1600309176
Directory /workspace/17.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.3567637022
Short name T222
Test name
Test status
Simulation time 116580697 ps
CPU time 8.19 seconds
Started Feb 04 12:51:35 PM PST 24
Finished Feb 04 12:51:46 PM PST 24
Peak memory 235064 kb
Host smart-3fc33676-5cd8-4375-bfd3-ef4d5fae313b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3567637022 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_rw.3567637022
Directory /workspace/17.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.1469134463
Short name T789
Test name
Test status
Simulation time 10061273 ps
CPU time 1.51 seconds
Started Feb 04 12:51:45 PM PST 24
Finished Feb 04 12:51:49 PM PST 24
Peak memory 235908 kb
Host smart-1ad136e1-0cbe-4be5-a4f3-bb408416a578
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1469134463 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_intr_test.1469134463
Directory /workspace/17.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.3086417290
Short name T758
Test name
Test status
Simulation time 1147034950 ps
CPU time 18.97 seconds
Started Feb 04 12:51:55 PM PST 24
Finished Feb 04 12:52:16 PM PST 24
Peak memory 243208 kb
Host smart-6d6dcf66-a11b-4574-8dfb-f8a908656d48
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3086417290 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_same_csr_ou
tstanding.3086417290
Directory /workspace/17.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.4061962170
Short name T157
Test name
Test status
Simulation time 5598037057 ps
CPU time 521.09 seconds
Started Feb 04 12:51:40 PM PST 24
Finished Feb 04 01:00:22 PM PST 24
Peak memory 264992 kb
Host smart-b2509500-362d-4fe2-8aff-63bd7d28b3a5
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061962170 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 17.alert_handler_shadow_reg_errors_with_csr_rw.4061962170
Directory /workspace/17.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.275903922
Short name T840
Test name
Test status
Simulation time 788599963 ps
CPU time 18.16 seconds
Started Feb 04 12:51:36 PM PST 24
Finished Feb 04 12:51:57 PM PST 24
Peak memory 248124 kb
Host smart-bf03d114-911f-48f5-ba7f-2bbd0a2a85ce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=275903922 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_errors.275903922
Directory /workspace/17.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.4060920178
Short name T794
Test name
Test status
Simulation time 135334270 ps
CPU time 4.25 seconds
Started Feb 04 12:51:40 PM PST 24
Finished Feb 04 12:51:46 PM PST 24
Peak memory 255480 kb
Host smart-be336ccd-8f71-4b21-b933-e4d419a869fb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060920178 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 18.alert_handler_csr_mem_rw_with_rand_reset.4060920178
Directory /workspace/18.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.2328547885
Short name T834
Test name
Test status
Simulation time 37868101 ps
CPU time 5.7 seconds
Started Feb 04 12:51:42 PM PST 24
Finished Feb 04 12:51:49 PM PST 24
Peak memory 235736 kb
Host smart-6fbbf4d6-c9cb-41da-a42d-919b194da738
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2328547885 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_rw.2328547885
Directory /workspace/18.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.2510397235
Short name T745
Test name
Test status
Simulation time 14690036 ps
CPU time 1.31 seconds
Started Feb 04 12:51:48 PM PST 24
Finished Feb 04 12:51:51 PM PST 24
Peak memory 234056 kb
Host smart-135424c6-6c52-48c2-afc8-c224f075afcc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2510397235 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_intr_test.2510397235
Directory /workspace/18.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.445579529
Short name T791
Test name
Test status
Simulation time 517303733 ps
CPU time 42.83 seconds
Started Feb 04 12:51:48 PM PST 24
Finished Feb 04 12:52:33 PM PST 24
Peak memory 239452 kb
Host smart-bf42abb5-6a1e-436e-a7c7-9a0ef9beeed9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=445579529 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_same_csr_out
standing.445579529
Directory /workspace/18.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.56526643
Short name T148
Test name
Test status
Simulation time 46831732245 ps
CPU time 463.23 seconds
Started Feb 04 12:52:10 PM PST 24
Finished Feb 04 12:59:57 PM PST 24
Peak memory 264828 kb
Host smart-1d315319-0ba4-4f19-924a-b95eea2ba6c6
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56526643 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_
TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -
cm_name 18.alert_handler_shadow_reg_errors_with_csr_rw.56526643
Directory /workspace/18.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.1026804601
Short name T820
Test name
Test status
Simulation time 275928021 ps
CPU time 18.35 seconds
Started Feb 04 12:51:49 PM PST 24
Finished Feb 04 12:52:09 PM PST 24
Peak memory 248080 kb
Host smart-ba3b4e08-fefa-4311-a224-19c8eceda26e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1026804601 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_errors.1026804601
Directory /workspace/18.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.1719125536
Short name T177
Test name
Test status
Simulation time 51683243 ps
CPU time 2.32 seconds
Started Feb 04 12:51:45 PM PST 24
Finished Feb 04 12:51:49 PM PST 24
Peak memory 234904 kb
Host smart-699985fe-6276-4d0e-aaca-a87f77ff0115
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1719125536 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_intg_err.1719125536
Directory /workspace/18.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.3743641603
Short name T742
Test name
Test status
Simulation time 73079933 ps
CPU time 6.57 seconds
Started Feb 04 12:51:54 PM PST 24
Finished Feb 04 12:52:03 PM PST 24
Peak memory 251144 kb
Host smart-7a4ceb2d-19b1-4c0e-aa10-463db692c801
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743641603 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 19.alert_handler_csr_mem_rw_with_rand_reset.3743641603
Directory /workspace/19.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.2929912239
Short name T817
Test name
Test status
Simulation time 95773051 ps
CPU time 7.95 seconds
Started Feb 04 12:51:48 PM PST 24
Finished Feb 04 12:51:58 PM PST 24
Peak memory 239560 kb
Host smart-56ef4505-b837-4f61-bdc2-e6190eabeeda
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2929912239 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_rw.2929912239
Directory /workspace/19.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.1930957960
Short name T225
Test name
Test status
Simulation time 18112961 ps
CPU time 1.33 seconds
Started Feb 04 12:51:57 PM PST 24
Finished Feb 04 12:52:01 PM PST 24
Peak memory 235176 kb
Host smart-d21c11b9-b536-4b96-a1bb-9a8feed31d4f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1930957960 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_intr_test.1930957960
Directory /workspace/19.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.1445842871
Short name T187
Test name
Test status
Simulation time 1109515702 ps
CPU time 11.29 seconds
Started Feb 04 12:51:53 PM PST 24
Finished Feb 04 12:52:09 PM PST 24
Peak memory 243916 kb
Host smart-f24308c4-ae16-4a3c-8fa8-0ad89eb3300d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1445842871 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_same_csr_ou
tstanding.1445842871
Directory /workspace/19.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.1649433389
Short name T140
Test name
Test status
Simulation time 2449042970 ps
CPU time 160.93 seconds
Started Feb 04 12:51:43 PM PST 24
Finished Feb 04 12:54:26 PM PST 24
Peak memory 264160 kb
Host smart-c73029a3-b766-4e0f-80f2-7c9544ff0a74
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1649433389 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shadow_reg_err
ors.1649433389
Directory /workspace/19.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.2036412739
Short name T136
Test name
Test status
Simulation time 20513385444 ps
CPU time 487.56 seconds
Started Feb 04 12:52:14 PM PST 24
Finished Feb 04 01:00:23 PM PST 24
Peak memory 267744 kb
Host smart-af6a7f15-51a7-4180-8f5c-fa712d56224e
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036412739 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 19.alert_handler_shadow_reg_errors_with_csr_rw.2036412739
Directory /workspace/19.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.2306777994
Short name T29
Test name
Test status
Simulation time 154215413 ps
CPU time 5.23 seconds
Started Feb 04 12:52:03 PM PST 24
Finished Feb 04 12:52:11 PM PST 24
Peak memory 252692 kb
Host smart-65fa4295-17c6-4fd3-bd48-1e36173e86b8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2306777994 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_errors.2306777994
Directory /workspace/19.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.641517674
Short name T763
Test name
Test status
Simulation time 8865273783 ps
CPU time 94.8 seconds
Started Feb 04 12:51:29 PM PST 24
Finished Feb 04 12:53:06 PM PST 24
Peak memory 239812 kb
Host smart-a2e8ee55-0eaf-493c-a8d2-1b4c5ae94f51
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=641517674 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_aliasing.641517674
Directory /workspace/2.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.2831748370
Short name T333
Test name
Test status
Simulation time 5824527505 ps
CPU time 355.09 seconds
Started Feb 04 12:51:43 PM PST 24
Finished Feb 04 12:57:40 PM PST 24
Peak memory 239840 kb
Host smart-a7821fe7-3b7b-4c6c-ace5-772fba70581a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2831748370 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_bit_bash.2831748370
Directory /workspace/2.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.1895190683
Short name T821
Test name
Test status
Simulation time 144658833 ps
CPU time 5.4 seconds
Started Feb 04 12:51:46 PM PST 24
Finished Feb 04 12:51:54 PM PST 24
Peak memory 239696 kb
Host smart-725d1d60-9a00-42ce-87c0-f3f8cfaca6ee
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1895190683 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_hw_reset.1895190683
Directory /workspace/2.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.1886610274
Short name T179
Test name
Test status
Simulation time 23529967 ps
CPU time 5.07 seconds
Started Feb 04 12:51:34 PM PST 24
Finished Feb 04 12:51:41 PM PST 24
Peak memory 250968 kb
Host smart-a2d55e16-c9a9-4a85-b97a-9106ea01054d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886610274 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 2.alert_handler_csr_mem_rw_with_rand_reset.1886610274
Directory /workspace/2.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.821722787
Short name T767
Test name
Test status
Simulation time 519093669 ps
CPU time 9.4 seconds
Started Feb 04 12:51:46 PM PST 24
Finished Feb 04 12:51:58 PM PST 24
Peak memory 235756 kb
Host smart-b54762b1-5de8-4992-93d5-7fc6339a31e2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=821722787 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_rw.821722787
Directory /workspace/2.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.3090925014
Short name T848
Test name
Test status
Simulation time 26202129 ps
CPU time 1.27 seconds
Started Feb 04 12:51:40 PM PST 24
Finished Feb 04 12:51:43 PM PST 24
Peak memory 235920 kb
Host smart-94e32c3d-ac46-4490-b46d-cdc17f0d4522
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3090925014 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_intr_test.3090925014
Directory /workspace/2.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.2285718246
Short name T182
Test name
Test status
Simulation time 1958636828 ps
CPU time 37.96 seconds
Started Feb 04 12:51:45 PM PST 24
Finished Feb 04 12:52:26 PM PST 24
Peak memory 244068 kb
Host smart-0b48b147-cdc5-47c8-b7b3-baaa77e98f8e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2285718246 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_same_csr_out
standing.2285718246
Directory /workspace/2.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.3563980472
Short name T138
Test name
Test status
Simulation time 1034679992 ps
CPU time 99.24 seconds
Started Feb 04 12:51:33 PM PST 24
Finished Feb 04 12:53:14 PM PST 24
Peak memory 256476 kb
Host smart-c9adb584-a9d6-41eb-807f-21c6e429d690
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3563980472 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shadow_reg_erro
rs.3563980472
Directory /workspace/2.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.2036681786
Short name T117
Test name
Test status
Simulation time 7452361234 ps
CPU time 312.87 seconds
Started Feb 04 12:51:46 PM PST 24
Finished Feb 04 12:57:02 PM PST 24
Peak memory 268060 kb
Host smart-89e709c4-595b-4f21-8173-75685bcd0af0
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036681786 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.alert_handler_shadow_reg_errors_with_csr_rw.2036681786
Directory /workspace/2.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.4207660692
Short name T757
Test name
Test status
Simulation time 2603943695 ps
CPU time 18.93 seconds
Started Feb 04 12:51:40 PM PST 24
Finished Feb 04 12:52:00 PM PST 24
Peak memory 253148 kb
Host smart-3f71d223-1af4-473b-bf99-f83e2e1ff500
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4207660692 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_errors.4207660692
Directory /workspace/2.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.3296502718
Short name T828
Test name
Test status
Simulation time 24107619 ps
CPU time 1.52 seconds
Started Feb 04 12:51:43 PM PST 24
Finished Feb 04 12:51:47 PM PST 24
Peak memory 235792 kb
Host smart-c5045b9c-82df-43ff-9661-e8a41934e984
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3296502718 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.alert_handler_intr_test.3296502718
Directory /workspace/20.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.660063191
Short name T807
Test name
Test status
Simulation time 21414446 ps
CPU time 1.36 seconds
Started Feb 04 12:51:47 PM PST 24
Finished Feb 04 12:51:51 PM PST 24
Peak memory 235048 kb
Host smart-22ccdf11-7311-4839-bd2f-1c58af361bef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=660063191 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.alert_handler_intr_test.660063191
Directory /workspace/21.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.2385253478
Short name T815
Test name
Test status
Simulation time 11070363 ps
CPU time 1.63 seconds
Started Feb 04 12:51:47 PM PST 24
Finished Feb 04 12:51:51 PM PST 24
Peak memory 235900 kb
Host smart-e271e6fe-3117-4333-a40e-51ce8932d5e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2385253478 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.alert_handler_intr_test.2385253478
Directory /workspace/22.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.3860724646
Short name T837
Test name
Test status
Simulation time 11579000 ps
CPU time 1.28 seconds
Started Feb 04 12:51:49 PM PST 24
Finished Feb 04 12:51:53 PM PST 24
Peak memory 234888 kb
Host smart-675582c0-6aa0-4486-b73f-4e7b9a251d32
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3860724646 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.alert_handler_intr_test.3860724646
Directory /workspace/23.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.2266953749
Short name T788
Test name
Test status
Simulation time 17679204 ps
CPU time 1.23 seconds
Started Feb 04 12:51:49 PM PST 24
Finished Feb 04 12:51:57 PM PST 24
Peak memory 235720 kb
Host smart-b2eef9d5-eb55-49c6-b18b-b13b2bb74373
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2266953749 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.alert_handler_intr_test.2266953749
Directory /workspace/24.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.1293325236
Short name T792
Test name
Test status
Simulation time 9534905 ps
CPU time 1.38 seconds
Started Feb 04 12:51:46 PM PST 24
Finished Feb 04 12:51:50 PM PST 24
Peak memory 234080 kb
Host smart-8ba4f030-6222-4daf-ac09-aaf8560749d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1293325236 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.alert_handler_intr_test.1293325236
Directory /workspace/25.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.916059818
Short name T824
Test name
Test status
Simulation time 25606297 ps
CPU time 1.47 seconds
Started Feb 04 12:51:48 PM PST 24
Finished Feb 04 12:51:52 PM PST 24
Peak memory 235780 kb
Host smart-0aeb6eee-1d23-43b6-9669-63c33acfbd93
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=916059818 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.alert_handler_intr_test.916059818
Directory /workspace/26.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.2559964830
Short name T787
Test name
Test status
Simulation time 9035380 ps
CPU time 1.38 seconds
Started Feb 04 12:51:45 PM PST 24
Finished Feb 04 12:51:48 PM PST 24
Peak memory 235896 kb
Host smart-828f4d40-a75f-466b-b23a-354edfb0ac0b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2559964830 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.alert_handler_intr_test.2559964830
Directory /workspace/27.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.2553463898
Short name T823
Test name
Test status
Simulation time 6802489 ps
CPU time 1.51 seconds
Started Feb 04 12:51:56 PM PST 24
Finished Feb 04 12:52:01 PM PST 24
Peak memory 235928 kb
Host smart-72e80b73-727f-4d5c-a01d-9a726fcb3d6f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2553463898 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.alert_handler_intr_test.2553463898
Directory /workspace/28.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.986703925
Short name T27
Test name
Test status
Simulation time 9874626 ps
CPU time 1.49 seconds
Started Feb 04 12:52:10 PM PST 24
Finished Feb 04 12:52:15 PM PST 24
Peak memory 235948 kb
Host smart-01226d2c-f5ba-4914-b62a-5dae1f5b940a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=986703925 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.alert_handler_intr_test.986703925
Directory /workspace/29.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.2945427660
Short name T843
Test name
Test status
Simulation time 1093590748 ps
CPU time 129.93 seconds
Started Feb 04 12:51:48 PM PST 24
Finished Feb 04 12:54:00 PM PST 24
Peak memory 239792 kb
Host smart-c8192cf6-14ff-4d3a-bf0f-521df22f5e7e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2945427660 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_aliasing.2945427660
Directory /workspace/3.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.683033594
Short name T764
Test name
Test status
Simulation time 6805274385 ps
CPU time 237.89 seconds
Started Feb 04 12:51:48 PM PST 24
Finished Feb 04 12:55:49 PM PST 24
Peak memory 235960 kb
Host smart-010388bc-e4c6-421f-867e-40db782dcf93
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=683033594 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_bit_bash.683033594
Directory /workspace/3.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.3428254559
Short name T783
Test name
Test status
Simulation time 213090479 ps
CPU time 3.86 seconds
Started Feb 04 12:51:45 PM PST 24
Finished Feb 04 12:51:51 PM PST 24
Peak memory 256132 kb
Host smart-39dd15f1-ead3-4519-a6e3-28d973b7b670
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428254559 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 3.alert_handler_csr_mem_rw_with_rand_reset.3428254559
Directory /workspace/3.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.1798727548
Short name T780
Test name
Test status
Simulation time 185493106 ps
CPU time 4.31 seconds
Started Feb 04 12:51:26 PM PST 24
Finished Feb 04 12:51:33 PM PST 24
Peak memory 234860 kb
Host smart-b11fd3bb-5376-434a-be20-281669771345
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1798727548 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_rw.1798727548
Directory /workspace/3.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.2553386130
Short name T829
Test name
Test status
Simulation time 10067079 ps
CPU time 1.61 seconds
Started Feb 04 12:51:30 PM PST 24
Finished Feb 04 12:51:34 PM PST 24
Peak memory 235816 kb
Host smart-1be62d6f-f753-4813-9aed-3a2a56364640
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2553386130 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_intr_test.2553386130
Directory /workspace/3.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.1463173473
Short name T835
Test name
Test status
Simulation time 356438352 ps
CPU time 24.01 seconds
Started Feb 04 12:51:41 PM PST 24
Finished Feb 04 12:52:07 PM PST 24
Peak memory 239844 kb
Host smart-74020d48-cb65-45f2-9a80-57fd2d3bb09e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1463173473 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_same_csr_out
standing.1463173473
Directory /workspace/3.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.581317938
Short name T143
Test name
Test status
Simulation time 27432348837 ps
CPU time 316.87 seconds
Started Feb 04 12:51:45 PM PST 24
Finished Feb 04 12:57:04 PM PST 24
Peak memory 264796 kb
Host smart-333a3c39-c05e-4fe6-b007-a16bb03f0b0e
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581317938 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.alert_handler_shadow_reg_errors_with_csr_rw.581317938
Directory /workspace/3.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.2110418077
Short name T847
Test name
Test status
Simulation time 767607784 ps
CPU time 21.37 seconds
Started Feb 04 12:51:38 PM PST 24
Finished Feb 04 12:52:01 PM PST 24
Peak memory 253888 kb
Host smart-57860c0e-ff70-47fa-864c-c6bbc56695a5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2110418077 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_errors.2110418077
Directory /workspace/3.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.3166928815
Short name T25
Test name
Test status
Simulation time 21739627 ps
CPU time 1.46 seconds
Started Feb 04 12:51:46 PM PST 24
Finished Feb 04 12:51:50 PM PST 24
Peak memory 234920 kb
Host smart-7b5dfc95-6b15-49db-bd48-d456981191f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3166928815 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.alert_handler_intr_test.3166928815
Directory /workspace/30.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.2266851055
Short name T775
Test name
Test status
Simulation time 6761888 ps
CPU time 1.45 seconds
Started Feb 04 12:51:54 PM PST 24
Finished Feb 04 12:51:57 PM PST 24
Peak memory 235856 kb
Host smart-9acfd3d1-0e0a-47f7-984b-cc66633bad74
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2266851055 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.alert_handler_intr_test.2266851055
Directory /workspace/31.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.3592922686
Short name T765
Test name
Test status
Simulation time 47687328 ps
CPU time 2.85 seconds
Started Feb 04 12:52:14 PM PST 24
Finished Feb 04 12:52:19 PM PST 24
Peak memory 235948 kb
Host smart-95279858-6724-4a84-a542-c3a472d0a72c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3592922686 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.alert_handler_intr_test.3592922686
Directory /workspace/32.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.1199047703
Short name T224
Test name
Test status
Simulation time 6395150 ps
CPU time 1.42 seconds
Started Feb 04 12:51:46 PM PST 24
Finished Feb 04 12:51:50 PM PST 24
Peak memory 234124 kb
Host smart-01ed7be4-c216-41fe-8062-b72b813853c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1199047703 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.alert_handler_intr_test.1199047703
Directory /workspace/33.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.2533284010
Short name T803
Test name
Test status
Simulation time 10470999 ps
CPU time 1.54 seconds
Started Feb 04 12:51:55 PM PST 24
Finished Feb 04 12:51:59 PM PST 24
Peak memory 235932 kb
Host smart-bfe9c20e-8403-4335-a28f-961a321b1207
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2533284010 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.alert_handler_intr_test.2533284010
Directory /workspace/34.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.3076354920
Short name T753
Test name
Test status
Simulation time 9653045 ps
CPU time 1.51 seconds
Started Feb 04 12:51:49 PM PST 24
Finished Feb 04 12:51:53 PM PST 24
Peak memory 235868 kb
Host smart-9c6504f5-3681-48de-b126-444ff7488a3b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3076354920 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.alert_handler_intr_test.3076354920
Directory /workspace/35.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.1244927696
Short name T329
Test name
Test status
Simulation time 6477708 ps
CPU time 1.35 seconds
Started Feb 04 12:51:48 PM PST 24
Finished Feb 04 12:51:52 PM PST 24
Peak memory 235916 kb
Host smart-673c2857-b76e-495e-8bc5-27264692c4aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1244927696 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.alert_handler_intr_test.1244927696
Directory /workspace/36.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.3147974758
Short name T750
Test name
Test status
Simulation time 6074443 ps
CPU time 1.41 seconds
Started Feb 04 12:51:56 PM PST 24
Finished Feb 04 12:52:00 PM PST 24
Peak memory 233948 kb
Host smart-25df1266-24ac-443d-b7f6-8f944271ef8c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3147974758 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.alert_handler_intr_test.3147974758
Directory /workspace/37.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.339815334
Short name T795
Test name
Test status
Simulation time 15749244 ps
CPU time 1.29 seconds
Started Feb 04 12:51:49 PM PST 24
Finished Feb 04 12:51:53 PM PST 24
Peak memory 234948 kb
Host smart-ca1f42dd-7b36-47ea-a7d5-f8d27ef92d7a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=339815334 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.alert_handler_intr_test.339815334
Directory /workspace/39.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.814408778
Short name T124
Test name
Test status
Simulation time 3283029104 ps
CPU time 224.92 seconds
Started Feb 04 12:51:44 PM PST 24
Finished Feb 04 12:55:31 PM PST 24
Peak memory 239028 kb
Host smart-b9a00850-f74f-44b7-93d5-0daa71efb8d7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=814408778 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_aliasing.814408778
Directory /workspace/4.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.1907726273
Short name T159
Test name
Test status
Simulation time 2855776170 ps
CPU time 189.37 seconds
Started Feb 04 12:51:46 PM PST 24
Finished Feb 04 12:54:58 PM PST 24
Peak memory 239880 kb
Host smart-b71c0fc9-6d54-4069-87dc-c5b28e9f6473
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1907726273 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_bit_bash.1907726273
Directory /workspace/4.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.2308943732
Short name T799
Test name
Test status
Simulation time 42733460 ps
CPU time 3.85 seconds
Started Feb 04 12:51:38 PM PST 24
Finished Feb 04 12:51:44 PM PST 24
Peak memory 239568 kb
Host smart-1d882153-d9a6-43a3-a483-6a8946a140d6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2308943732 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_hw_reset.2308943732
Directory /workspace/4.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.262881003
Short name T761
Test name
Test status
Simulation time 59305009 ps
CPU time 6.45 seconds
Started Feb 04 12:51:54 PM PST 24
Finished Feb 04 12:52:02 PM PST 24
Peak memory 256228 kb
Host smart-8fcce542-f562-42a8-b582-a5afa2d99e79
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262881003 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 4.alert_handler_csr_mem_rw_with_rand_reset.262881003
Directory /workspace/4.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.1532287781
Short name T798
Test name
Test status
Simulation time 63606303 ps
CPU time 6.06 seconds
Started Feb 04 12:51:44 PM PST 24
Finished Feb 04 12:51:52 PM PST 24
Peak memory 235772 kb
Host smart-01d429b7-86ee-42c0-aa20-e86b00a77434
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1532287781 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_rw.1532287781
Directory /workspace/4.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.3980459456
Short name T793
Test name
Test status
Simulation time 10624948 ps
CPU time 1.39 seconds
Started Feb 04 12:51:48 PM PST 24
Finished Feb 04 12:51:51 PM PST 24
Peak memory 234920 kb
Host smart-c5f2346c-aee1-4933-ab96-95b3cf64ec6f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3980459456 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_intr_test.3980459456
Directory /workspace/4.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.4025771335
Short name T180
Test name
Test status
Simulation time 302133550 ps
CPU time 20.14 seconds
Started Feb 04 12:51:44 PM PST 24
Finished Feb 04 12:52:06 PM PST 24
Peak memory 247920 kb
Host smart-394b5563-a525-4433-8cc7-af49ef868804
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4025771335 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_same_csr_out
standing.4025771335
Directory /workspace/4.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.1597054454
Short name T122
Test name
Test status
Simulation time 10204604507 ps
CPU time 203.65 seconds
Started Feb 04 12:51:48 PM PST 24
Finished Feb 04 12:55:14 PM PST 24
Peak memory 264800 kb
Host smart-21125208-67fa-484a-bcdc-0db714a0b901
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1597054454 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shadow_reg_erro
rs.1597054454
Directory /workspace/4.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.3834455673
Short name T119
Test name
Test status
Simulation time 11717433303 ps
CPU time 350.12 seconds
Started Feb 04 12:51:48 PM PST 24
Finished Feb 04 12:57:40 PM PST 24
Peak memory 264868 kb
Host smart-376e8c15-e8cb-4370-b1e8-f2abd96e99c1
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834455673 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.alert_handler_shadow_reg_errors_with_csr_rw.3834455673
Directory /workspace/4.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.741632884
Short name T163
Test name
Test status
Simulation time 111731070 ps
CPU time 7.98 seconds
Started Feb 04 12:51:48 PM PST 24
Finished Feb 04 12:52:03 PM PST 24
Peak memory 247988 kb
Host smart-420391d6-538a-4e8c-8512-6392b05a7506
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=741632884 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_errors.741632884
Directory /workspace/4.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.2664702718
Short name T808
Test name
Test status
Simulation time 24256233 ps
CPU time 1.36 seconds
Started Feb 04 12:51:56 PM PST 24
Finished Feb 04 12:52:01 PM PST 24
Peak memory 235840 kb
Host smart-499166e5-386d-4246-938c-eebdc4190ce8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2664702718 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.alert_handler_intr_test.2664702718
Directory /workspace/40.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.3350005112
Short name T749
Test name
Test status
Simulation time 24839176 ps
CPU time 1.38 seconds
Started Feb 04 12:51:52 PM PST 24
Finished Feb 04 12:51:55 PM PST 24
Peak memory 235944 kb
Host smart-01b946b2-5d36-412b-82b4-c8a2b0b6d293
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3350005112 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.alert_handler_intr_test.3350005112
Directory /workspace/41.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.4097046585
Short name T831
Test name
Test status
Simulation time 13282707 ps
CPU time 1.69 seconds
Started Feb 04 12:51:53 PM PST 24
Finished Feb 04 12:51:57 PM PST 24
Peak memory 235832 kb
Host smart-3b1b0ce8-be96-4348-a4c8-ae6233140a01
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4097046585 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.alert_handler_intr_test.4097046585
Directory /workspace/42.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.617570581
Short name T756
Test name
Test status
Simulation time 8313023 ps
CPU time 1.39 seconds
Started Feb 04 12:51:53 PM PST 24
Finished Feb 04 12:51:56 PM PST 24
Peak memory 235944 kb
Host smart-16cfcd17-e2b8-4eb0-af03-8d21599a2ad1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=617570581 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.alert_handler_intr_test.617570581
Directory /workspace/43.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.406679109
Short name T776
Test name
Test status
Simulation time 13093251 ps
CPU time 1.52 seconds
Started Feb 04 12:51:56 PM PST 24
Finished Feb 04 12:52:01 PM PST 24
Peak memory 235944 kb
Host smart-ed8013ad-cf18-47e2-be8d-7d335612eb7a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=406679109 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.alert_handler_intr_test.406679109
Directory /workspace/44.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.1885021078
Short name T809
Test name
Test status
Simulation time 11620514 ps
CPU time 1.27 seconds
Started Feb 04 12:51:48 PM PST 24
Finished Feb 04 12:51:52 PM PST 24
Peak memory 235788 kb
Host smart-4946e1fd-7af5-4e14-b3f4-8e41219e7acf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1885021078 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.alert_handler_intr_test.1885021078
Directory /workspace/45.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.1129162795
Short name T759
Test name
Test status
Simulation time 11475782 ps
CPU time 1.38 seconds
Started Feb 04 12:51:51 PM PST 24
Finished Feb 04 12:51:55 PM PST 24
Peak memory 235772 kb
Host smart-d909f805-4658-42e6-887c-5caba940065f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1129162795 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.alert_handler_intr_test.1129162795
Directory /workspace/46.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.335114789
Short name T24
Test name
Test status
Simulation time 15571736 ps
CPU time 1.23 seconds
Started Feb 04 12:51:53 PM PST 24
Finished Feb 04 12:51:56 PM PST 24
Peak memory 234972 kb
Host smart-c841b212-0aff-47ad-b087-8d6ccfcb1182
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=335114789 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.alert_handler_intr_test.335114789
Directory /workspace/47.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.3650528494
Short name T841
Test name
Test status
Simulation time 25870620 ps
CPU time 1.47 seconds
Started Feb 04 12:52:12 PM PST 24
Finished Feb 04 12:52:15 PM PST 24
Peak memory 235852 kb
Host smart-65c11044-a2f5-4366-927e-2fbf2b02e8ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3650528494 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.alert_handler_intr_test.3650528494
Directory /workspace/48.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.2795478757
Short name T812
Test name
Test status
Simulation time 10409501 ps
CPU time 1.27 seconds
Started Feb 04 12:51:51 PM PST 24
Finished Feb 04 12:51:55 PM PST 24
Peak memory 234908 kb
Host smart-b078521f-90fe-4d8f-aa6b-d43aa3efbe75
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2795478757 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.alert_handler_intr_test.2795478757
Directory /workspace/49.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.2403129435
Short name T336
Test name
Test status
Simulation time 64862689 ps
CPU time 6.29 seconds
Started Feb 04 12:51:59 PM PST 24
Finished Feb 04 12:52:10 PM PST 24
Peak memory 250840 kb
Host smart-c54d4b82-395f-4ad3-881a-303b6749a91c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403129435 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 5.alert_handler_csr_mem_rw_with_rand_reset.2403129435
Directory /workspace/5.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.825781541
Short name T832
Test name
Test status
Simulation time 240523107 ps
CPU time 5.89 seconds
Started Feb 04 12:51:44 PM PST 24
Finished Feb 04 12:51:52 PM PST 24
Peak memory 235796 kb
Host smart-5ebedb88-d326-4eed-8589-bdbe5a586bcc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=825781541 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_rw.825781541
Directory /workspace/5.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.1475881567
Short name T327
Test name
Test status
Simulation time 14022142 ps
CPU time 1.27 seconds
Started Feb 04 12:51:43 PM PST 24
Finished Feb 04 12:51:46 PM PST 24
Peak memory 234992 kb
Host smart-2fc47435-c3a8-44ac-8a67-47824e68d784
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1475881567 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_intr_test.1475881567
Directory /workspace/5.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.1459200715
Short name T769
Test name
Test status
Simulation time 371139085 ps
CPU time 10.25 seconds
Started Feb 04 12:51:50 PM PST 24
Finished Feb 04 12:52:03 PM PST 24
Peak memory 239788 kb
Host smart-30f2c4d3-7913-444e-91a7-c1c6a71e92b1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1459200715 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_same_csr_out
standing.1459200715
Directory /workspace/5.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.3457473586
Short name T129
Test name
Test status
Simulation time 705333237 ps
CPU time 73.1 seconds
Started Feb 04 12:51:53 PM PST 24
Finished Feb 04 12:53:08 PM PST 24
Peak memory 254792 kb
Host smart-4cc838af-fcb7-4170-a2a2-a0f763d604ec
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3457473586 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shadow_reg_erro
rs.3457473586
Directory /workspace/5.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.2649678999
Short name T747
Test name
Test status
Simulation time 98183130 ps
CPU time 7.54 seconds
Started Feb 04 12:51:49 PM PST 24
Finished Feb 04 12:51:59 PM PST 24
Peak memory 248068 kb
Host smart-90766a65-429f-491f-b5bb-3ba6d3ee3cd0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2649678999 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_errors.2649678999
Directory /workspace/5.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.3984291192
Short name T785
Test name
Test status
Simulation time 83391440 ps
CPU time 5.6 seconds
Started Feb 04 12:51:46 PM PST 24
Finished Feb 04 12:51:54 PM PST 24
Peak memory 250220 kb
Host smart-58343853-cb65-4941-b4b6-3e556dfdf310
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984291192 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 6.alert_handler_csr_mem_rw_with_rand_reset.3984291192
Directory /workspace/6.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.3608800891
Short name T773
Test name
Test status
Simulation time 19562757 ps
CPU time 3.61 seconds
Started Feb 04 12:51:45 PM PST 24
Finished Feb 04 12:51:51 PM PST 24
Peak memory 234920 kb
Host smart-901d266f-a0fb-41e0-91cc-5e43a1faad98
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3608800891 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_rw.3608800891
Directory /workspace/6.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.2092235235
Short name T339
Test name
Test status
Simulation time 15870445 ps
CPU time 1.33 seconds
Started Feb 04 12:52:17 PM PST 24
Finished Feb 04 12:52:20 PM PST 24
Peak memory 233976 kb
Host smart-adfed4b2-754a-41c2-a769-77f64a9e6236
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2092235235 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_intr_test.2092235235
Directory /workspace/6.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.3125616778
Short name T155
Test name
Test status
Simulation time 501608019 ps
CPU time 18.13 seconds
Started Feb 04 12:51:43 PM PST 24
Finished Feb 04 12:52:04 PM PST 24
Peak memory 239680 kb
Host smart-4f90bee2-839f-46cf-80f5-b7c4a2bcecfe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3125616778 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_same_csr_out
standing.3125616778
Directory /workspace/6.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.3889040513
Short name T141
Test name
Test status
Simulation time 8426848356 ps
CPU time 375.9 seconds
Started Feb 04 12:52:03 PM PST 24
Finished Feb 04 12:58:22 PM PST 24
Peak memory 264756 kb
Host smart-372ab50e-f4fe-4eed-9b04-e43c48d7c27a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3889040513 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shadow_reg_erro
rs.3889040513
Directory /workspace/6.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.1155014595
Short name T162
Test name
Test status
Simulation time 349514118 ps
CPU time 19.39 seconds
Started Feb 04 12:52:04 PM PST 24
Finished Feb 04 12:52:25 PM PST 24
Peak memory 248064 kb
Host smart-e20b807b-2d9d-457e-85cb-d21ec7eef7b8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1155014595 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_errors.1155014595
Directory /workspace/6.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.1381527165
Short name T746
Test name
Test status
Simulation time 64714670 ps
CPU time 5.56 seconds
Started Feb 04 12:51:34 PM PST 24
Finished Feb 04 12:51:41 PM PST 24
Peak memory 247740 kb
Host smart-8348cde3-a616-4db8-92c4-bf8fa00512be
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381527165 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 7.alert_handler_csr_mem_rw_with_rand_reset.1381527165
Directory /workspace/7.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.2521780950
Short name T181
Test name
Test status
Simulation time 89691171 ps
CPU time 4.73 seconds
Started Feb 04 12:51:53 PM PST 24
Finished Feb 04 12:52:02 PM PST 24
Peak memory 239524 kb
Host smart-257ba81a-ca8d-4295-a873-3a3b00ab3f79
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2521780950 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_rw.2521780950
Directory /workspace/7.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.1443641727
Short name T752
Test name
Test status
Simulation time 23479023 ps
CPU time 1.48 seconds
Started Feb 04 12:51:46 PM PST 24
Finished Feb 04 12:51:51 PM PST 24
Peak memory 235816 kb
Host smart-a10ad8ca-d3ff-4b77-b7fe-e40de2364633
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1443641727 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_intr_test.1443641727
Directory /workspace/7.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.937475422
Short name T778
Test name
Test status
Simulation time 281720886 ps
CPU time 21.63 seconds
Started Feb 04 12:51:45 PM PST 24
Finished Feb 04 12:52:09 PM PST 24
Peak memory 244112 kb
Host smart-162eec9f-4244-451e-9eb1-57135297af51
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=937475422 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_same_csr_outs
tanding.937475422
Directory /workspace/7.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.3300560516
Short name T771
Test name
Test status
Simulation time 224957444 ps
CPU time 15.2 seconds
Started Feb 04 12:51:54 PM PST 24
Finished Feb 04 12:52:13 PM PST 24
Peak memory 247980 kb
Host smart-c5bac83a-c3da-4ca8-8d50-9469f746ee62
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3300560516 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_errors.3300560516
Directory /workspace/7.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.1962675213
Short name T811
Test name
Test status
Simulation time 107575530 ps
CPU time 3.7 seconds
Started Feb 04 12:51:31 PM PST 24
Finished Feb 04 12:51:38 PM PST 24
Peak memory 237792 kb
Host smart-a80925f9-cced-45c6-9307-5bed43cbbe66
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962675213 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 8.alert_handler_csr_mem_rw_with_rand_reset.1962675213
Directory /workspace/8.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.1756012637
Short name T830
Test name
Test status
Simulation time 566803754 ps
CPU time 5.77 seconds
Started Feb 04 12:51:30 PM PST 24
Finished Feb 04 12:51:37 PM PST 24
Peak memory 235656 kb
Host smart-fbca5003-efa0-42d7-9e0b-8dbda37e1def
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1756012637 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_rw.1756012637
Directory /workspace/8.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.1186009823
Short name T845
Test name
Test status
Simulation time 21309900 ps
CPU time 1.92 seconds
Started Feb 04 12:51:29 PM PST 24
Finished Feb 04 12:51:33 PM PST 24
Peak memory 235824 kb
Host smart-66e33d67-d27b-4088-ba88-96d9c40c0efb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1186009823 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_intr_test.1186009823
Directory /workspace/8.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.322826400
Short name T779
Test name
Test status
Simulation time 1585851304 ps
CPU time 25.56 seconds
Started Feb 04 12:51:37 PM PST 24
Finished Feb 04 12:52:05 PM PST 24
Peak memory 244100 kb
Host smart-e426cec4-264d-4738-8e9b-6937accf7b4b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=322826400 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_same_csr_outs
tanding.322826400
Directory /workspace/8.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.2344301081
Short name T151
Test name
Test status
Simulation time 6018940380 ps
CPU time 407.15 seconds
Started Feb 04 12:51:40 PM PST 24
Finished Feb 04 12:58:29 PM PST 24
Peak memory 264808 kb
Host smart-b5860c37-c905-4801-97b8-5f52d758669e
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344301081 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.alert_handler_shadow_reg_errors_with_csr_rw.2344301081
Directory /workspace/8.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.739907008
Short name T800
Test name
Test status
Simulation time 170843199 ps
CPU time 11.44 seconds
Started Feb 04 12:51:32 PM PST 24
Finished Feb 04 12:51:46 PM PST 24
Peak memory 252280 kb
Host smart-fbfeda1e-08e7-45c9-821e-ad3c51e34c66
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=739907008 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_errors.739907008
Directory /workspace/8.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.3275680334
Short name T131
Test name
Test status
Simulation time 31468501 ps
CPU time 6.23 seconds
Started Feb 04 12:51:45 PM PST 24
Finished Feb 04 12:51:53 PM PST 24
Peak memory 254552 kb
Host smart-59f0418b-d3e1-439b-9c63-eadcf5cc590c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275680334 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 9.alert_handler_csr_mem_rw_with_rand_reset.3275680334
Directory /workspace/9.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.2245240426
Short name T797
Test name
Test status
Simulation time 1283017032 ps
CPU time 5.71 seconds
Started Feb 04 12:51:29 PM PST 24
Finished Feb 04 12:51:37 PM PST 24
Peak memory 239660 kb
Host smart-5022c829-df34-41c3-a0a1-dc0bf78e74cb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2245240426 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_rw.2245240426
Directory /workspace/9.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.2032234940
Short name T838
Test name
Test status
Simulation time 177120721 ps
CPU time 24.21 seconds
Started Feb 04 12:51:35 PM PST 24
Finished Feb 04 12:52:03 PM PST 24
Peak memory 247908 kb
Host smart-04414c12-257b-4a04-ad94-9a3fae7b7667
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2032234940 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_same_csr_out
standing.2032234940
Directory /workspace/9.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/default/0.alert_handler_entropy.3239758613
Short name T72
Test name
Test status
Simulation time 43235900303 ps
CPU time 2457.08 seconds
Started Feb 04 01:19:43 PM PST 24
Finished Feb 04 02:00:48 PM PST 24
Peak memory 281252 kb
Host smart-5d693200-1a23-45d8-b81b-f04af9a8578a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239758613 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy.3239758613
Directory /workspace/0.alert_handler_entropy/latest

Test location /workspace/coverage/default/0.alert_handler_entropy_stress.2014581092
Short name T355
Test name
Test status
Simulation time 595079387 ps
CPU time 9.9 seconds
Started Feb 04 01:19:43 PM PST 24
Finished Feb 04 01:20:01 PM PST 24
Peak memory 240064 kb
Host smart-1bd9cf2b-39f4-405c-868f-9a995465ba77
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2014581092 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy_stress.2014581092
Directory /workspace/0.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/0.alert_handler_esc_alert_accum.1229943342
Short name T414
Test name
Test status
Simulation time 679502790 ps
CPU time 53.79 seconds
Started Feb 04 01:19:33 PM PST 24
Finished Feb 04 01:20:28 PM PST 24
Peak memory 255004 kb
Host smart-9b829ba1-2470-4aee-a6a1-cb3b010b131b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12299
43342 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_alert_accum.1229943342
Directory /workspace/0.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/0.alert_handler_esc_intr_timeout.4226758319
Short name T364
Test name
Test status
Simulation time 165177956 ps
CPU time 13 seconds
Started Feb 04 01:19:43 PM PST 24
Finished Feb 04 01:20:04 PM PST 24
Peak memory 250948 kb
Host smart-22dd9800-d56c-4f20-bb6d-fe7e77ab2079
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42267
58319 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_intr_timeout.4226758319
Directory /workspace/0.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_lpg.562632471
Short name T334
Test name
Test status
Simulation time 23937232446 ps
CPU time 588.67 seconds
Started Feb 04 01:19:33 PM PST 24
Finished Feb 04 01:29:24 PM PST 24
Peak memory 270588 kb
Host smart-51458d86-5c87-4c37-94de-af2e732bbc8f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562632471 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg.562632471
Directory /workspace/0.alert_handler_lpg/latest

Test location /workspace/coverage/default/0.alert_handler_lpg_stub_clk.1564443390
Short name T212
Test name
Test status
Simulation time 14385732385 ps
CPU time 1263.13 seconds
Started Feb 04 01:19:36 PM PST 24
Finished Feb 04 01:40:43 PM PST 24
Peak memory 284204 kb
Host smart-2f803300-b136-4c66-9593-ade3e1b33520
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1564443390 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg_stub_clk.1564443390
Directory /workspace/0.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/0.alert_handler_ping_timeout.3259153103
Short name T273
Test name
Test status
Simulation time 12328469870 ps
CPU time 98.18 seconds
Started Feb 04 01:19:42 PM PST 24
Finished Feb 04 01:21:29 PM PST 24
Peak memory 246732 kb
Host smart-07456ee2-162e-4b2f-8252-e5b1d343786c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3259153103 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_ping_timeout.3259153103
Directory /workspace/0.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_random_alerts.2119990179
Short name T342
Test name
Test status
Simulation time 352366789 ps
CPU time 38.69 seconds
Started Feb 04 01:19:41 PM PST 24
Finished Feb 04 01:20:29 PM PST 24
Peak memory 248432 kb
Host smart-9663ee28-a31e-4614-972c-265cffd927c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21199
90179 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_alerts.2119990179
Directory /workspace/0.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/0.alert_handler_random_classes.404039022
Short name T496
Test name
Test status
Simulation time 138262481 ps
CPU time 15.22 seconds
Started Feb 04 01:19:42 PM PST 24
Finished Feb 04 01:20:06 PM PST 24
Peak memory 252444 kb
Host smart-1588368d-5030-4a94-86cb-ee708a5ea5df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40403
9022 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_classes.404039022
Directory /workspace/0.alert_handler_random_classes/latest

Test location /workspace/coverage/default/0.alert_handler_sec_cm.1173875159
Short name T43
Test name
Test status
Simulation time 1122823129 ps
CPU time 49.49 seconds
Started Feb 04 01:19:37 PM PST 24
Finished Feb 04 01:20:30 PM PST 24
Peak memory 272120 kb
Host smart-f03fd921-e06b-41d5-9035-def90d9dcb17
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1173875159 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sec_cm.1173875159
Directory /workspace/0.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/0.alert_handler_smoke.162954011
Short name T354
Test name
Test status
Simulation time 333311529 ps
CPU time 11.23 seconds
Started Feb 04 01:19:31 PM PST 24
Finished Feb 04 01:19:43 PM PST 24
Peak memory 248496 kb
Host smart-c5a4c2ac-254a-4164-bc89-b34cb1264aef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16295
4011 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_smoke.162954011
Directory /workspace/0.alert_handler_smoke/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all.2285878588
Short name T68
Test name
Test status
Simulation time 61856419810 ps
CPU time 3267.05 seconds
Started Feb 04 01:19:37 PM PST 24
Finished Feb 04 02:14:07 PM PST 24
Peak memory 289444 kb
Host smart-37a407bb-e814-4176-a4c9-ce7879583849
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285878588 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_han
dler_stress_all.2285878588
Directory /workspace/0.alert_handler_stress_all/latest

Test location /workspace/coverage/default/1.alert_handler_entropy_stress.3637486440
Short name T571
Test name
Test status
Simulation time 870264568 ps
CPU time 12.99 seconds
Started Feb 04 01:19:43 PM PST 24
Finished Feb 04 01:20:04 PM PST 24
Peak memory 252096 kb
Host smart-bcc55095-483a-4cdc-9bfd-781b53f2ce33
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3637486440 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy_stress.3637486440
Directory /workspace/1.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/1.alert_handler_esc_alert_accum.190230394
Short name T440
Test name
Test status
Simulation time 1753732654 ps
CPU time 141.8 seconds
Started Feb 04 01:19:34 PM PST 24
Finished Feb 04 01:21:58 PM PST 24
Peak memory 255680 kb
Host smart-2b115e20-2a9d-4188-a0a8-6102870d7032
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19023
0394 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_alert_accum.190230394
Directory /workspace/1.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/1.alert_handler_esc_intr_timeout.1806877101
Short name T48
Test name
Test status
Simulation time 2499361432 ps
CPU time 45.39 seconds
Started Feb 04 01:19:33 PM PST 24
Finished Feb 04 01:20:20 PM PST 24
Peak memory 255396 kb
Host smart-005a605f-ea99-46d4-918d-442b8de1a80d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18068
77101 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_intr_timeout.1806877101
Directory /workspace/1.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_lpg.3319169372
Short name T325
Test name
Test status
Simulation time 13606654578 ps
CPU time 1544.84 seconds
Started Feb 04 01:19:28 PM PST 24
Finished Feb 04 01:45:15 PM PST 24
Peak memory 289432 kb
Host smart-b76fbb12-494a-437c-ba53-1d6cdce33280
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319169372 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg.3319169372
Directory /workspace/1.alert_handler_lpg/latest

Test location /workspace/coverage/default/1.alert_handler_lpg_stub_clk.2481040117
Short name T670
Test name
Test status
Simulation time 30319743702 ps
CPU time 1699.27 seconds
Started Feb 04 01:19:42 PM PST 24
Finished Feb 04 01:48:10 PM PST 24
Peak memory 267000 kb
Host smart-1348e3a6-fcf2-44da-9502-5ba422de3961
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481040117 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg_stub_clk.2481040117
Directory /workspace/1.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/1.alert_handler_ping_timeout.2554486498
Short name T261
Test name
Test status
Simulation time 94698415731 ps
CPU time 394.15 seconds
Started Feb 04 01:19:41 PM PST 24
Finished Feb 04 01:26:24 PM PST 24
Peak memory 246324 kb
Host smart-f1d1a747-4cb8-434c-99c1-e4f1401b55ac
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2554486498 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_ping_timeout.2554486498
Directory /workspace/1.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_random_alerts.135758851
Short name T346
Test name
Test status
Simulation time 3989299848 ps
CPU time 53 seconds
Started Feb 04 01:19:43 PM PST 24
Finished Feb 04 01:20:44 PM PST 24
Peak memory 248472 kb
Host smart-cce94d20-3294-4918-953f-21d39cb266f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13575
8851 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_alerts.135758851
Directory /workspace/1.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/1.alert_handler_random_classes.425403933
Short name T481
Test name
Test status
Simulation time 365310821 ps
CPU time 22.02 seconds
Started Feb 04 01:19:35 PM PST 24
Finished Feb 04 01:20:01 PM PST 24
Peak memory 254224 kb
Host smart-6cb17c16-5e4b-44fc-a704-89fecdad7329
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42540
3933 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_classes.425403933
Directory /workspace/1.alert_handler_random_classes/latest

Test location /workspace/coverage/default/1.alert_handler_sec_cm.2932294243
Short name T12
Test name
Test status
Simulation time 214226401 ps
CPU time 12.73 seconds
Started Feb 04 01:19:38 PM PST 24
Finished Feb 04 01:19:54 PM PST 24
Peak memory 276108 kb
Host smart-1c48a1af-5d93-48d9-9134-7ea6e2048e1f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2932294243 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sec_cm.2932294243
Directory /workspace/1.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/1.alert_handler_sig_int_fail.3162464460
Short name T487
Test name
Test status
Simulation time 358906607 ps
CPU time 16.6 seconds
Started Feb 04 01:19:41 PM PST 24
Finished Feb 04 01:20:07 PM PST 24
Peak memory 248384 kb
Host smart-758c0e3a-e153-4208-8e13-f1a74ce70f08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31624
64460 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sig_int_fail.3162464460
Directory /workspace/1.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/1.alert_handler_smoke.2857062255
Short name T468
Test name
Test status
Simulation time 411404742 ps
CPU time 27.13 seconds
Started Feb 04 01:19:42 PM PST 24
Finished Feb 04 01:20:18 PM PST 24
Peak memory 248432 kb
Host smart-d2cd810a-5133-4dfd-97f5-3a3d0cd5e7e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28570
62255 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_smoke.2857062255
Directory /workspace/1.alert_handler_smoke/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all.2505165786
Short name T112
Test name
Test status
Simulation time 52286992185 ps
CPU time 2897.65 seconds
Started Feb 04 01:19:39 PM PST 24
Finished Feb 04 02:08:00 PM PST 24
Peak memory 288716 kb
Host smart-8d398dca-01ff-4da1-9b91-60ba02ee1c5c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505165786 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_han
dler_stress_all.2505165786
Directory /workspace/1.alert_handler_stress_all/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all_with_rand_reset.3239951463
Short name T520
Test name
Test status
Simulation time 435600220546 ps
CPU time 2294.51 seconds
Started Feb 04 01:19:46 PM PST 24
Finished Feb 04 01:58:06 PM PST 24
Peak memory 289556 kb
Host smart-4139df5e-07cb-4443-8a11-6ed7430e83d7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239951463 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.alert_handler_stress_all_with_rand_reset.3239951463
Directory /workspace/1.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.alert_handler_entropy.3877092386
Short name T488
Test name
Test status
Simulation time 10354932325 ps
CPU time 802.52 seconds
Started Feb 04 01:20:18 PM PST 24
Finished Feb 04 01:33:45 PM PST 24
Peak memory 269000 kb
Host smart-d3c764da-09a3-4ed1-8405-162a3da125b8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877092386 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy.3877092386
Directory /workspace/10.alert_handler_entropy/latest

Test location /workspace/coverage/default/10.alert_handler_entropy_stress.2895944130
Short name T206
Test name
Test status
Simulation time 3724102256 ps
CPU time 18.86 seconds
Started Feb 04 01:20:21 PM PST 24
Finished Feb 04 01:20:43 PM PST 24
Peak memory 248500 kb
Host smart-6163c45c-b526-4e86-a8a8-4920c8761b17
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2895944130 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy_stress.2895944130
Directory /workspace/10.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/10.alert_handler_esc_alert_accum.3754981983
Short name T651
Test name
Test status
Simulation time 2875596673 ps
CPU time 35.02 seconds
Started Feb 04 01:20:14 PM PST 24
Finished Feb 04 01:20:57 PM PST 24
Peak memory 247872 kb
Host smart-d2880a6a-843f-47d5-95df-16600b6998b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37549
81983 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_alert_accum.3754981983
Directory /workspace/10.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/10.alert_handler_esc_intr_timeout.1318116219
Short name T524
Test name
Test status
Simulation time 360330439 ps
CPU time 10.36 seconds
Started Feb 04 01:20:14 PM PST 24
Finished Feb 04 01:20:33 PM PST 24
Peak memory 246728 kb
Host smart-84e1bdbd-bea5-486b-9522-7c9565f52a80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13181
16219 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_intr_timeout.1318116219
Directory /workspace/10.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_lpg.938695508
Short name T693
Test name
Test status
Simulation time 84044091871 ps
CPU time 1402.55 seconds
Started Feb 04 01:20:27 PM PST 24
Finished Feb 04 01:43:51 PM PST 24
Peak memory 287604 kb
Host smart-bb9daa2e-5cab-4160-a278-bc9e7124146a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938695508 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg.938695508
Directory /workspace/10.alert_handler_lpg/latest

Test location /workspace/coverage/default/10.alert_handler_lpg_stub_clk.1744799562
Short name T503
Test name
Test status
Simulation time 108012237590 ps
CPU time 1267.56 seconds
Started Feb 04 01:20:18 PM PST 24
Finished Feb 04 01:41:30 PM PST 24
Peak memory 272072 kb
Host smart-78e2cd52-36c4-4472-98d7-c2806cc72079
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744799562 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg_stub_clk.1744799562
Directory /workspace/10.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/10.alert_handler_ping_timeout.2766029268
Short name T499
Test name
Test status
Simulation time 4973138470 ps
CPU time 213.17 seconds
Started Feb 04 01:20:13 PM PST 24
Finished Feb 04 01:23:54 PM PST 24
Peak memory 247184 kb
Host smart-84615e26-7af8-4d7a-89e7-c54afef0181c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766029268 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_ping_timeout.2766029268
Directory /workspace/10.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_random_alerts.2166319066
Short name T691
Test name
Test status
Simulation time 720027724 ps
CPU time 22.59 seconds
Started Feb 04 01:20:11 PM PST 24
Finished Feb 04 01:20:40 PM PST 24
Peak memory 248372 kb
Host smart-9a0fa514-a00c-4d88-ae72-ed7af740afbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21663
19066 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_alerts.2166319066
Directory /workspace/10.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/10.alert_handler_random_classes.3124586066
Short name T713
Test name
Test status
Simulation time 2096810194 ps
CPU time 38.81 seconds
Started Feb 04 01:20:21 PM PST 24
Finished Feb 04 01:21:03 PM PST 24
Peak memory 254664 kb
Host smart-161b5c8f-aaf1-43fc-81ea-f621d20a49d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31245
86066 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_classes.3124586066
Directory /workspace/10.alert_handler_random_classes/latest

Test location /workspace/coverage/default/10.alert_handler_sig_int_fail.2586700653
Short name T573
Test name
Test status
Simulation time 73293382 ps
CPU time 8.78 seconds
Started Feb 04 01:20:14 PM PST 24
Finished Feb 04 01:20:30 PM PST 24
Peak memory 246700 kb
Host smart-d4612a38-be65-46ac-8209-156eb53e6798
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25867
00653 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_sig_int_fail.2586700653
Directory /workspace/10.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/10.alert_handler_smoke.1056023830
Short name T21
Test name
Test status
Simulation time 139220856 ps
CPU time 12.06 seconds
Started Feb 04 01:20:12 PM PST 24
Finished Feb 04 01:20:31 PM PST 24
Peak memory 248368 kb
Host smart-9b621129-4560-4c55-b263-a46a62f72db6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10560
23830 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_smoke.1056023830
Directory /workspace/10.alert_handler_smoke/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all.1923685578
Short name T52
Test name
Test status
Simulation time 53650168002 ps
CPU time 1180.66 seconds
Started Feb 04 01:20:16 PM PST 24
Finished Feb 04 01:40:03 PM PST 24
Peak memory 283932 kb
Host smart-52982e68-58c3-4526-b679-5581d8cd6da7
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923685578 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_ha
ndler_stress_all.1923685578
Directory /workspace/10.alert_handler_stress_all/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all_with_rand_reset.1597119700
Short name T665
Test name
Test status
Simulation time 28836139608 ps
CPU time 2715.46 seconds
Started Feb 04 01:20:12 PM PST 24
Finished Feb 04 02:05:36 PM PST 24
Peak memory 289556 kb
Host smart-81c95ffa-44af-4eb3-9a72-8e5f217100bd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597119700 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 10.alert_handler_stress_all_with_rand_reset.1597119700
Directory /workspace/10.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.alert_handler_alert_accum_saturation.2504621977
Short name T196
Test name
Test status
Simulation time 87658192 ps
CPU time 3.71 seconds
Started Feb 04 01:20:27 PM PST 24
Finished Feb 04 01:20:32 PM PST 24
Peak memory 248664 kb
Host smart-ac741fbb-9a7c-4456-8f78-d16c6ffe43c6
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2504621977 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_alert_accum_saturation.2504621977
Directory /workspace/11.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/11.alert_handler_entropy.3944425962
Short name T683
Test name
Test status
Simulation time 17142425853 ps
CPU time 926.43 seconds
Started Feb 04 01:20:16 PM PST 24
Finished Feb 04 01:35:49 PM PST 24
Peak memory 281340 kb
Host smart-e78a719d-cf60-4c07-ae03-536c7ed789af
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944425962 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy.3944425962
Directory /workspace/11.alert_handler_entropy/latest

Test location /workspace/coverage/default/11.alert_handler_entropy_stress.2930934929
Short name T386
Test name
Test status
Simulation time 156072274 ps
CPU time 9.37 seconds
Started Feb 04 01:20:15 PM PST 24
Finished Feb 04 01:20:32 PM PST 24
Peak memory 240248 kb
Host smart-ff59fa2d-b7a9-4db2-b4c8-d493dc7be004
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2930934929 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy_stress.2930934929
Directory /workspace/11.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/11.alert_handler_esc_alert_accum.1251229752
Short name T661
Test name
Test status
Simulation time 5842236400 ps
CPU time 93.96 seconds
Started Feb 04 01:20:16 PM PST 24
Finished Feb 04 01:21:56 PM PST 24
Peak memory 256752 kb
Host smart-39cf43f4-fb2b-46cd-a6ab-914d38b7e09c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12512
29752 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_alert_accum.1251229752
Directory /workspace/11.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/11.alert_handler_esc_intr_timeout.137296629
Short name T410
Test name
Test status
Simulation time 1088799837 ps
CPU time 69.84 seconds
Started Feb 04 01:20:14 PM PST 24
Finished Feb 04 01:21:31 PM PST 24
Peak memory 254116 kb
Host smart-6dc4b9b2-a608-487d-8cc5-91b86b75c248
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13729
6629 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_intr_timeout.137296629
Directory /workspace/11.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_random_alerts.386610348
Short name T447
Test name
Test status
Simulation time 194310492 ps
CPU time 17.21 seconds
Started Feb 04 01:20:21 PM PST 24
Finished Feb 04 01:20:42 PM PST 24
Peak memory 248376 kb
Host smart-f33b8777-96ea-4eca-8398-dffb330614b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38661
0348 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_alerts.386610348
Directory /workspace/11.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/11.alert_handler_random_classes.2619193802
Short name T593
Test name
Test status
Simulation time 2560832363 ps
CPU time 38.43 seconds
Started Feb 04 01:20:14 PM PST 24
Finished Feb 04 01:21:00 PM PST 24
Peak memory 255488 kb
Host smart-8c20a111-9b5b-44f9-b445-1f20fec98d19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26191
93802 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_classes.2619193802
Directory /workspace/11.alert_handler_random_classes/latest

Test location /workspace/coverage/default/11.alert_handler_sig_int_fail.1563136019
Short name T84
Test name
Test status
Simulation time 197276724 ps
CPU time 12.84 seconds
Started Feb 04 01:20:16 PM PST 24
Finished Feb 04 01:20:35 PM PST 24
Peak memory 251128 kb
Host smart-1cdaf1fb-9cdf-4c63-9dff-7cea9dd7977d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15631
36019 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_sig_int_fail.1563136019
Directory /workspace/11.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/11.alert_handler_smoke.3381697304
Short name T632
Test name
Test status
Simulation time 558057460 ps
CPU time 30.32 seconds
Started Feb 04 01:20:27 PM PST 24
Finished Feb 04 01:20:59 PM PST 24
Peak memory 248440 kb
Host smart-e34da2a8-4715-465c-bbb5-9d436b08fd6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33816
97304 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_smoke.3381697304
Directory /workspace/11.alert_handler_smoke/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all_with_rand_reset.2497070745
Short name T467
Test name
Test status
Simulation time 13338391692 ps
CPU time 928.38 seconds
Started Feb 04 01:20:13 PM PST 24
Finished Feb 04 01:35:49 PM PST 24
Peak memory 273276 kb
Host smart-fa2bbc1b-7279-4b69-9f5a-3d3612ce925b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497070745 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 11.alert_handler_stress_all_with_rand_reset.2497070745
Directory /workspace/11.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.alert_handler_entropy.271265295
Short name T61
Test name
Test status
Simulation time 31526959359 ps
CPU time 2016.57 seconds
Started Feb 04 01:20:20 PM PST 24
Finished Feb 04 01:54:01 PM PST 24
Peak memory 289048 kb
Host smart-898498aa-8140-464a-b807-e27efb3a0689
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271265295 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy.271265295
Directory /workspace/12.alert_handler_entropy/latest

Test location /workspace/coverage/default/12.alert_handler_entropy_stress.4011148992
Short name T426
Test name
Test status
Simulation time 1294253731 ps
CPU time 14.57 seconds
Started Feb 04 01:20:12 PM PST 24
Finished Feb 04 01:20:35 PM PST 24
Peak memory 240176 kb
Host smart-1aa5b7bf-b68e-42c3-9194-3f5b40657bc2
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4011148992 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy_stress.4011148992
Directory /workspace/12.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/12.alert_handler_esc_alert_accum.949209863
Short name T663
Test name
Test status
Simulation time 26805064816 ps
CPU time 263.21 seconds
Started Feb 04 01:20:11 PM PST 24
Finished Feb 04 01:24:41 PM PST 24
Peak memory 256712 kb
Host smart-0a5b097f-769e-4d52-8ffb-3a8829e82b0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94920
9863 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_alert_accum.949209863
Directory /workspace/12.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/12.alert_handler_esc_intr_timeout.4013426385
Short name T409
Test name
Test status
Simulation time 45477257 ps
CPU time 4.1 seconds
Started Feb 04 01:20:19 PM PST 24
Finished Feb 04 01:20:27 PM PST 24
Peak memory 238296 kb
Host smart-20189f1f-9029-4b57-8f2b-7818e62e7368
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40134
26385 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_intr_timeout.4013426385
Directory /workspace/12.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_lpg_stub_clk.2965113900
Short name T284
Test name
Test status
Simulation time 69821816303 ps
CPU time 1435.78 seconds
Started Feb 04 01:20:15 PM PST 24
Finished Feb 04 01:44:18 PM PST 24
Peak memory 287516 kb
Host smart-a386d515-0e0e-43de-a10d-25c04e122b0b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965113900 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg_stub_clk.2965113900
Directory /workspace/12.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/12.alert_handler_random_alerts.1322856247
Short name T630
Test name
Test status
Simulation time 52341065 ps
CPU time 7.79 seconds
Started Feb 04 01:20:15 PM PST 24
Finished Feb 04 01:20:30 PM PST 24
Peak memory 252664 kb
Host smart-f719eece-9b53-42c4-a5ec-7d510cb5f71d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13228
56247 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_alerts.1322856247
Directory /workspace/12.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/12.alert_handler_random_classes.4143254482
Short name T618
Test name
Test status
Simulation time 135462354 ps
CPU time 13.23 seconds
Started Feb 04 01:20:20 PM PST 24
Finished Feb 04 01:20:37 PM PST 24
Peak memory 254352 kb
Host smart-9e0d30ef-4c37-400a-8f9f-87c4f01e3af0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41432
54482 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_classes.4143254482
Directory /workspace/12.alert_handler_random_classes/latest

Test location /workspace/coverage/default/12.alert_handler_sig_int_fail.2294526562
Short name T238
Test name
Test status
Simulation time 1484067301 ps
CPU time 34.31 seconds
Started Feb 04 01:20:15 PM PST 24
Finished Feb 04 01:20:57 PM PST 24
Peak memory 254484 kb
Host smart-beadbc84-7f95-43d8-a4bc-faa346b2963b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22945
26562 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_sig_int_fail.2294526562
Directory /workspace/12.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/12.alert_handler_smoke.1748902639
Short name T387
Test name
Test status
Simulation time 11814452322 ps
CPU time 39.85 seconds
Started Feb 04 01:20:21 PM PST 24
Finished Feb 04 01:21:04 PM PST 24
Peak memory 248520 kb
Host smart-d3b76fe1-f6db-4188-b030-0105de82cca4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17489
02639 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_smoke.1748902639
Directory /workspace/12.alert_handler_smoke/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all.2185490126
Short name T66
Test name
Test status
Simulation time 68035592840 ps
CPU time 798.66 seconds
Started Feb 04 01:20:15 PM PST 24
Finished Feb 04 01:33:41 PM PST 24
Peak memory 264932 kb
Host smart-e1352e75-628d-4bd7-aaee-c15b232b321d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185490126 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_ha
ndler_stress_all.2185490126
Directory /workspace/12.alert_handler_stress_all/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all_with_rand_reset.2958832455
Short name T660
Test name
Test status
Simulation time 19276287835 ps
CPU time 1831.32 seconds
Started Feb 04 01:20:18 PM PST 24
Finished Feb 04 01:50:54 PM PST 24
Peak memory 289488 kb
Host smart-f1a87220-7446-4732-9c1e-2ee0a202bf23
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958832455 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.alert_handler_stress_all_with_rand_reset.2958832455
Directory /workspace/12.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.alert_handler_alert_accum_saturation.330349041
Short name T194
Test name
Test status
Simulation time 13504058 ps
CPU time 2.3 seconds
Started Feb 04 01:20:29 PM PST 24
Finished Feb 04 01:20:32 PM PST 24
Peak memory 248676 kb
Host smart-23cb2a56-7177-4f4a-a73a-7e0d6173c02b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=330349041 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_alert_accum_saturation.330349041
Directory /workspace/13.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/13.alert_handler_entropy.4119438898
Short name T681
Test name
Test status
Simulation time 35945905767 ps
CPU time 886.86 seconds
Started Feb 04 01:20:19 PM PST 24
Finished Feb 04 01:35:10 PM PST 24
Peak memory 272644 kb
Host smart-27953e78-061c-4ec1-859f-e50880bf33c9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119438898 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy.4119438898
Directory /workspace/13.alert_handler_entropy/latest

Test location /workspace/coverage/default/13.alert_handler_entropy_stress.1649683726
Short name T352
Test name
Test status
Simulation time 102415844 ps
CPU time 7.15 seconds
Started Feb 04 01:20:27 PM PST 24
Finished Feb 04 01:20:36 PM PST 24
Peak memory 240244 kb
Host smart-ce12f7eb-64e8-4bd0-ad2b-dd5127fd5f22
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1649683726 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy_stress.1649683726
Directory /workspace/13.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/13.alert_handler_esc_alert_accum.400743629
Short name T384
Test name
Test status
Simulation time 3076210196 ps
CPU time 37.51 seconds
Started Feb 04 01:20:27 PM PST 24
Finished Feb 04 01:21:05 PM PST 24
Peak memory 255252 kb
Host smart-e67fbb46-d27c-45dc-8bc5-ac834604a4d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40074
3629 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_alert_accum.400743629
Directory /workspace/13.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/13.alert_handler_esc_intr_timeout.1748488179
Short name T78
Test name
Test status
Simulation time 331919120 ps
CPU time 16.99 seconds
Started Feb 04 01:20:12 PM PST 24
Finished Feb 04 01:20:37 PM PST 24
Peak memory 254812 kb
Host smart-3b76ddf6-f8e9-40eb-ada0-739308839309
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17484
88179 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_intr_timeout.1748488179
Directory /workspace/13.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_lpg_stub_clk.3460596684
Short name T725
Test name
Test status
Simulation time 35365251695 ps
CPU time 2100.18 seconds
Started Feb 04 01:20:29 PM PST 24
Finished Feb 04 01:55:30 PM PST 24
Peak memory 272264 kb
Host smart-660a891c-466f-43ff-9f6f-01f4ab5c7a0d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460596684 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg_stub_clk.3460596684
Directory /workspace/13.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/13.alert_handler_random_alerts.728330255
Short name T505
Test name
Test status
Simulation time 627837453 ps
CPU time 36.99 seconds
Started Feb 04 01:20:20 PM PST 24
Finished Feb 04 01:21:01 PM PST 24
Peak memory 254888 kb
Host smart-5a6b43f7-5a5c-4d8b-b34a-e7b256bf216f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72833
0255 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_alerts.728330255
Directory /workspace/13.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/13.alert_handler_random_classes.2708198424
Short name T592
Test name
Test status
Simulation time 953398285 ps
CPU time 43.22 seconds
Started Feb 04 01:20:14 PM PST 24
Finished Feb 04 01:21:05 PM PST 24
Peak memory 246716 kb
Host smart-ff643a97-b5b0-4220-8707-cb4d7bf979d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27081
98424 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_classes.2708198424
Directory /workspace/13.alert_handler_random_classes/latest

Test location /workspace/coverage/default/13.alert_handler_smoke.920526620
Short name T350
Test name
Test status
Simulation time 579271736 ps
CPU time 32.75 seconds
Started Feb 04 01:20:15 PM PST 24
Finished Feb 04 01:20:55 PM PST 24
Peak memory 248468 kb
Host smart-d86b0a47-7fe3-468c-a951-9a2fcba27762
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92052
6620 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_smoke.920526620
Directory /workspace/13.alert_handler_smoke/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all.3963731389
Short name T100
Test name
Test status
Simulation time 101906186017 ps
CPU time 1244.94 seconds
Started Feb 04 01:20:24 PM PST 24
Finished Feb 04 01:41:11 PM PST 24
Peak memory 273128 kb
Host smart-466d0ccc-de98-4f25-a5d8-54f440c071bd
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963731389 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_ha
ndler_stress_all.3963731389
Directory /workspace/13.alert_handler_stress_all/latest

Test location /workspace/coverage/default/14.alert_handler_alert_accum_saturation.1520660561
Short name T200
Test name
Test status
Simulation time 329102086 ps
CPU time 4.17 seconds
Started Feb 04 01:20:22 PM PST 24
Finished Feb 04 01:20:29 PM PST 24
Peak memory 248588 kb
Host smart-938f53e7-10a8-450d-ae7c-df1323039f6f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1520660561 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_alert_accum_saturation.1520660561
Directory /workspace/14.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/14.alert_handler_entropy.1380221915
Short name T544
Test name
Test status
Simulation time 26726194155 ps
CPU time 1630.18 seconds
Started Feb 04 01:20:23 PM PST 24
Finished Feb 04 01:47:36 PM PST 24
Peak memory 273232 kb
Host smart-fdca836f-baab-4821-939a-5de825f20131
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380221915 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy.1380221915
Directory /workspace/14.alert_handler_entropy/latest

Test location /workspace/coverage/default/14.alert_handler_entropy_stress.1294561483
Short name T545
Test name
Test status
Simulation time 11264496194 ps
CPU time 55.62 seconds
Started Feb 04 01:20:30 PM PST 24
Finished Feb 04 01:21:27 PM PST 24
Peak memory 240336 kb
Host smart-134424c8-211c-41dd-a227-b13e14babfc1
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1294561483 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy_stress.1294561483
Directory /workspace/14.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/14.alert_handler_esc_alert_accum.3262699046
Short name T492
Test name
Test status
Simulation time 2673228062 ps
CPU time 56.84 seconds
Started Feb 04 01:20:24 PM PST 24
Finished Feb 04 01:21:23 PM PST 24
Peak memory 256032 kb
Host smart-da433a2e-3216-4e8b-a8d4-7052252ac156
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32626
99046 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_alert_accum.3262699046
Directory /workspace/14.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/14.alert_handler_esc_intr_timeout.1074320086
Short name T609
Test name
Test status
Simulation time 1089899013 ps
CPU time 56.05 seconds
Started Feb 04 01:20:30 PM PST 24
Finished Feb 04 01:21:27 PM PST 24
Peak memory 255176 kb
Host smart-ec90a0b4-b182-4867-9024-42917fd11214
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10743
20086 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_intr_timeout.1074320086
Directory /workspace/14.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_lpg.790409461
Short name T274
Test name
Test status
Simulation time 47827198896 ps
CPU time 2622.89 seconds
Started Feb 04 01:20:20 PM PST 24
Finished Feb 04 02:04:07 PM PST 24
Peak memory 285092 kb
Host smart-f89db655-4b08-4bd8-aa6c-760ab50429ff
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790409461 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg.790409461
Directory /workspace/14.alert_handler_lpg/latest

Test location /workspace/coverage/default/14.alert_handler_lpg_stub_clk.752771343
Short name T565
Test name
Test status
Simulation time 38286901006 ps
CPU time 855.11 seconds
Started Feb 04 01:20:20 PM PST 24
Finished Feb 04 01:34:39 PM PST 24
Peak memory 272636 kb
Host smart-06c0d6c4-de99-4f92-8291-48586d3c380f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=752771343 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg_stub_clk.752771343
Directory /workspace/14.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/14.alert_handler_ping_timeout.621748788
Short name T558
Test name
Test status
Simulation time 13913297597 ps
CPU time 557.73 seconds
Started Feb 04 01:20:27 PM PST 24
Finished Feb 04 01:29:46 PM PST 24
Peak memory 247420 kb
Host smart-4e0d6b4b-2e1a-4c27-b83a-0d0795330c16
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621748788 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_ping_timeout.621748788
Directory /workspace/14.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_random_alerts.3104020309
Short name T626
Test name
Test status
Simulation time 727726906 ps
CPU time 21.39 seconds
Started Feb 04 01:20:25 PM PST 24
Finished Feb 04 01:20:48 PM PST 24
Peak memory 254140 kb
Host smart-95092933-b285-43a0-a785-b1604967f7c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31040
20309 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_alerts.3104020309
Directory /workspace/14.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/14.alert_handler_random_classes.1093975431
Short name T292
Test name
Test status
Simulation time 273647093 ps
CPU time 11.8 seconds
Started Feb 04 01:20:21 PM PST 24
Finished Feb 04 01:20:36 PM PST 24
Peak memory 254328 kb
Host smart-429271f8-7143-46af-a04b-789c255f4a08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10939
75431 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_classes.1093975431
Directory /workspace/14.alert_handler_random_classes/latest

Test location /workspace/coverage/default/14.alert_handler_sig_int_fail.4212247816
Short name T697
Test name
Test status
Simulation time 8470626937 ps
CPU time 71.62 seconds
Started Feb 04 01:20:24 PM PST 24
Finished Feb 04 01:21:37 PM PST 24
Peak memory 256088 kb
Host smart-2133e283-6481-4d45-b8a2-2c298e8463a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42122
47816 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_sig_int_fail.4212247816
Directory /workspace/14.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/14.alert_handler_smoke.722340999
Short name T516
Test name
Test status
Simulation time 2391398067 ps
CPU time 67.61 seconds
Started Feb 04 01:20:23 PM PST 24
Finished Feb 04 01:21:33 PM PST 24
Peak memory 248556 kb
Host smart-6fc48311-9156-4856-b26e-843414c1f84b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72234
0999 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_smoke.722340999
Directory /workspace/14.alert_handler_smoke/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all.3204185743
Short name T38
Test name
Test status
Simulation time 43468433303 ps
CPU time 1599.27 seconds
Started Feb 04 01:20:19 PM PST 24
Finished Feb 04 01:47:03 PM PST 24
Peak memory 272868 kb
Host smart-700eda9d-2413-42e7-b814-e679aee577a2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204185743 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_ha
ndler_stress_all.3204185743
Directory /workspace/14.alert_handler_stress_all/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all_with_rand_reset.1248440216
Short name T36
Test name
Test status
Simulation time 113525506602 ps
CPU time 3949.75 seconds
Started Feb 04 01:20:21 PM PST 24
Finished Feb 04 02:26:14 PM PST 24
Peak memory 305340 kb
Host smart-32537d5a-4102-4a2a-9a7f-2bb8a4ecf28c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248440216 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 14.alert_handler_stress_all_with_rand_reset.1248440216
Directory /workspace/14.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.alert_handler_alert_accum_saturation.1404416323
Short name T94
Test name
Test status
Simulation time 115818117 ps
CPU time 3.2 seconds
Started Feb 04 01:20:24 PM PST 24
Finished Feb 04 01:20:29 PM PST 24
Peak memory 248672 kb
Host smart-91509b48-1cb5-428d-885f-3e1aa96e334e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1404416323 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_alert_accum_saturation.1404416323
Directory /workspace/15.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/15.alert_handler_entropy.3898451330
Short name T97
Test name
Test status
Simulation time 39429651547 ps
CPU time 2204.19 seconds
Started Feb 04 01:20:24 PM PST 24
Finished Feb 04 01:57:11 PM PST 24
Peak memory 273128 kb
Host smart-460cac41-b6c0-4f94-aa88-a874bb6d7ec9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898451330 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy.3898451330
Directory /workspace/15.alert_handler_entropy/latest

Test location /workspace/coverage/default/15.alert_handler_entropy_stress.2038686057
Short name T221
Test name
Test status
Simulation time 582442824 ps
CPU time 6.38 seconds
Started Feb 04 01:20:26 PM PST 24
Finished Feb 04 01:20:34 PM PST 24
Peak memory 240104 kb
Host smart-00c056ef-423a-4228-b35b-879924859236
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2038686057 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy_stress.2038686057
Directory /workspace/15.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/15.alert_handler_esc_alert_accum.2342447410
Short name T297
Test name
Test status
Simulation time 1593764980 ps
CPU time 127.73 seconds
Started Feb 04 01:20:22 PM PST 24
Finished Feb 04 01:22:33 PM PST 24
Peak memory 255844 kb
Host smart-8e275d90-c544-4622-bcc2-de584bb496f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23424
47410 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_alert_accum.2342447410
Directory /workspace/15.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/15.alert_handler_esc_intr_timeout.1612749617
Short name T429
Test name
Test status
Simulation time 1812754221 ps
CPU time 38.51 seconds
Started Feb 04 01:20:27 PM PST 24
Finished Feb 04 01:21:07 PM PST 24
Peak memory 254048 kb
Host smart-87b61f4f-a67c-4615-a30b-ef4956427f30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16127
49617 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_intr_timeout.1612749617
Directory /workspace/15.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_lpg.529303911
Short name T733
Test name
Test status
Simulation time 83113563271 ps
CPU time 1507.18 seconds
Started Feb 04 01:20:20 PM PST 24
Finished Feb 04 01:45:31 PM PST 24
Peak memory 269072 kb
Host smart-fcedd8cb-32db-4ce2-a7c0-0842ec4218d3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=529303911 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg.529303911
Directory /workspace/15.alert_handler_lpg/latest

Test location /workspace/coverage/default/15.alert_handler_lpg_stub_clk.290983536
Short name T610
Test name
Test status
Simulation time 32614408922 ps
CPU time 1589.44 seconds
Started Feb 04 01:20:21 PM PST 24
Finished Feb 04 01:46:54 PM PST 24
Peak memory 288712 kb
Host smart-d00e3fd1-09a3-4ed1-b3cf-288e771bde4b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290983536 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg_stub_clk.290983536
Directory /workspace/15.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/15.alert_handler_ping_timeout.2960757380
Short name T607
Test name
Test status
Simulation time 3884468017 ps
CPU time 150.68 seconds
Started Feb 04 01:20:22 PM PST 24
Finished Feb 04 01:22:56 PM PST 24
Peak memory 247364 kb
Host smart-3963d0c5-93f5-42f6-8edc-500bcb0f98f4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960757380 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_ping_timeout.2960757380
Directory /workspace/15.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_random_alerts.369287458
Short name T554
Test name
Test status
Simulation time 294863710 ps
CPU time 17.05 seconds
Started Feb 04 01:20:24 PM PST 24
Finished Feb 04 01:20:43 PM PST 24
Peak memory 248444 kb
Host smart-127a85cd-a94a-47e0-a334-aff65aef70ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36928
7458 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_alerts.369287458
Directory /workspace/15.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/15.alert_handler_random_classes.3643052319
Short name T588
Test name
Test status
Simulation time 3448729126 ps
CPU time 22.76 seconds
Started Feb 04 01:20:27 PM PST 24
Finished Feb 04 01:20:52 PM PST 24
Peak memory 254144 kb
Host smart-d2b2242d-fa1c-4041-9d09-da8147aca47a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36430
52319 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_classes.3643052319
Directory /workspace/15.alert_handler_random_classes/latest

Test location /workspace/coverage/default/15.alert_handler_sig_int_fail.1146951527
Short name T65
Test name
Test status
Simulation time 465197218 ps
CPU time 29.81 seconds
Started Feb 04 01:20:24 PM PST 24
Finished Feb 04 01:20:56 PM PST 24
Peak memory 255148 kb
Host smart-5c7fefa1-4aa0-4679-90d0-59e3da7a02d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11469
51527 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_sig_int_fail.1146951527
Directory /workspace/15.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/15.alert_handler_smoke.2243842370
Short name T433
Test name
Test status
Simulation time 1244398825 ps
CPU time 20.86 seconds
Started Feb 04 01:20:21 PM PST 24
Finished Feb 04 01:20:46 PM PST 24
Peak memory 248440 kb
Host smart-fabd8a33-0831-4223-940d-d7b45fd23a7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22438
42370 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_smoke.2243842370
Directory /workspace/15.alert_handler_smoke/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all.3392563301
Short name T594
Test name
Test status
Simulation time 21235488209 ps
CPU time 647.14 seconds
Started Feb 04 01:20:24 PM PST 24
Finished Feb 04 01:31:14 PM PST 24
Peak memory 256656 kb
Host smart-3f057988-aef1-4f43-94c1-076d5407bb99
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392563301 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_ha
ndler_stress_all.3392563301
Directory /workspace/15.alert_handler_stress_all/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all_with_rand_reset.2926344724
Short name T41
Test name
Test status
Simulation time 39697300254 ps
CPU time 193 seconds
Started Feb 04 01:20:31 PM PST 24
Finished Feb 04 01:23:46 PM PST 24
Peak memory 265068 kb
Host smart-f6ad07fc-d8a1-4b16-a397-dbf9d228b274
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926344724 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.alert_handler_stress_all_with_rand_reset.2926344724
Directory /workspace/15.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.alert_handler_alert_accum_saturation.3856234851
Short name T203
Test name
Test status
Simulation time 44012509 ps
CPU time 2.12 seconds
Started Feb 04 01:20:30 PM PST 24
Finished Feb 04 01:20:33 PM PST 24
Peak memory 248680 kb
Host smart-3a17b2fb-dae6-473a-b49f-969ba8997b0b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3856234851 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_alert_accum_saturation.3856234851
Directory /workspace/16.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/16.alert_handler_entropy.1881896698
Short name T289
Test name
Test status
Simulation time 27638996611 ps
CPU time 1762.15 seconds
Started Feb 04 01:20:31 PM PST 24
Finished Feb 04 01:49:56 PM PST 24
Peak memory 273028 kb
Host smart-a8695b1a-ceb7-44b2-a3b9-6fdbf70df57e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1881896698 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy.1881896698
Directory /workspace/16.alert_handler_entropy/latest

Test location /workspace/coverage/default/16.alert_handler_entropy_stress.2268021627
Short name T400
Test name
Test status
Simulation time 447478710 ps
CPU time 7.73 seconds
Started Feb 04 01:20:33 PM PST 24
Finished Feb 04 01:20:43 PM PST 24
Peak memory 240216 kb
Host smart-9c426474-6b3b-47ce-99bd-93053fb29697
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2268021627 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy_stress.2268021627
Directory /workspace/16.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/16.alert_handler_esc_alert_accum.281380432
Short name T549
Test name
Test status
Simulation time 3355279425 ps
CPU time 94.99 seconds
Started Feb 04 01:20:31 PM PST 24
Finished Feb 04 01:22:08 PM PST 24
Peak memory 248184 kb
Host smart-05456381-31f1-4734-8338-4e13e0501515
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28138
0432 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_alert_accum.281380432
Directory /workspace/16.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/16.alert_handler_esc_intr_timeout.2481736731
Short name T424
Test name
Test status
Simulation time 650312994 ps
CPU time 43.32 seconds
Started Feb 04 01:20:40 PM PST 24
Finished Feb 04 01:21:24 PM PST 24
Peak memory 254484 kb
Host smart-d127e7f0-be98-4876-8c22-a4903a831f41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24817
36731 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_intr_timeout.2481736731
Directory /workspace/16.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_lpg.3343894595
Short name T307
Test name
Test status
Simulation time 602666431043 ps
CPU time 2617.11 seconds
Started Feb 04 01:20:33 PM PST 24
Finished Feb 04 02:04:12 PM PST 24
Peak memory 272592 kb
Host smart-7f162e56-9b59-481c-a154-6949d4cea576
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3343894595 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg.3343894595
Directory /workspace/16.alert_handler_lpg/latest

Test location /workspace/coverage/default/16.alert_handler_lpg_stub_clk.464309348
Short name T211
Test name
Test status
Simulation time 12286779925 ps
CPU time 1231.25 seconds
Started Feb 04 01:20:33 PM PST 24
Finished Feb 04 01:41:06 PM PST 24
Peak memory 288640 kb
Host smart-88bfd2d1-4830-41ff-bf20-dd43f72f3581
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464309348 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg_stub_clk.464309348
Directory /workspace/16.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/16.alert_handler_ping_timeout.1459399259
Short name T272
Test name
Test status
Simulation time 47138318411 ps
CPU time 455.26 seconds
Started Feb 04 01:20:32 PM PST 24
Finished Feb 04 01:28:09 PM PST 24
Peak memory 246432 kb
Host smart-98efdfdc-71cf-4fb4-8b89-93dc80963c08
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459399259 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_ping_timeout.1459399259
Directory /workspace/16.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_random_alerts.319043276
Short name T34
Test name
Test status
Simulation time 296252913 ps
CPU time 27.64 seconds
Started Feb 04 01:20:34 PM PST 24
Finished Feb 04 01:21:03 PM PST 24
Peak memory 255188 kb
Host smart-e5389730-de75-4a6f-97ee-83b50259d938
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31904
3276 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_alerts.319043276
Directory /workspace/16.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/16.alert_handler_random_classes.3377841032
Short name T591
Test name
Test status
Simulation time 1201218353 ps
CPU time 49.98 seconds
Started Feb 04 01:20:32 PM PST 24
Finished Feb 04 01:21:23 PM PST 24
Peak memory 255212 kb
Host smart-8c17657b-17fd-442b-8cb9-8488fc803aae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33778
41032 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_classes.3377841032
Directory /workspace/16.alert_handler_random_classes/latest

Test location /workspace/coverage/default/16.alert_handler_sig_int_fail.165863687
Short name T656
Test name
Test status
Simulation time 635687248 ps
CPU time 39.38 seconds
Started Feb 04 01:20:32 PM PST 24
Finished Feb 04 01:21:13 PM PST 24
Peak memory 246868 kb
Host smart-0fb89bf4-7e71-4e5d-8af6-09a1b6a05faa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16586
3687 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_sig_int_fail.165863687
Directory /workspace/16.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/16.alert_handler_smoke.2479513616
Short name T74
Test name
Test status
Simulation time 8429274423 ps
CPU time 47.41 seconds
Started Feb 04 01:20:29 PM PST 24
Finished Feb 04 01:21:17 PM PST 24
Peak memory 248580 kb
Host smart-158709f1-cdbc-4444-98b0-7702ec49c6a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24795
13616 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_smoke.2479513616
Directory /workspace/16.alert_handler_smoke/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all.229078236
Short name T643
Test name
Test status
Simulation time 29995084885 ps
CPU time 836.02 seconds
Started Feb 04 01:20:40 PM PST 24
Finished Feb 04 01:34:37 PM PST 24
Peak memory 272968 kb
Host smart-25c48f43-86e3-4ab5-bc9f-c3a1a122689f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229078236 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_han
dler_stress_all.229078236
Directory /workspace/16.alert_handler_stress_all/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all_with_rand_reset.3152345619
Short name T611
Test name
Test status
Simulation time 91086615719 ps
CPU time 7878.25 seconds
Started Feb 04 01:20:30 PM PST 24
Finished Feb 04 03:31:50 PM PST 24
Peak memory 355180 kb
Host smart-c2687a34-d71f-4800-948f-126ae71fd326
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152345619 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 16.alert_handler_stress_all_with_rand_reset.3152345619
Directory /workspace/16.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.alert_handler_alert_accum_saturation.1225339135
Short name T191
Test name
Test status
Simulation time 55189711 ps
CPU time 2.75 seconds
Started Feb 04 01:20:50 PM PST 24
Finished Feb 04 01:20:59 PM PST 24
Peak memory 256784 kb
Host smart-1b1b8a0c-eeb6-41e7-9af8-2e02a2bafac7
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1225339135 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_alert_accum_saturation.1225339135
Directory /workspace/17.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/17.alert_handler_entropy.2740135202
Short name T299
Test name
Test status
Simulation time 67570232249 ps
CPU time 2375.79 seconds
Started Feb 04 01:20:49 PM PST 24
Finished Feb 04 02:00:32 PM PST 24
Peak memory 289528 kb
Host smart-415579e9-94f6-4e15-ba80-990685588b57
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740135202 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy.2740135202
Directory /workspace/17.alert_handler_entropy/latest

Test location /workspace/coverage/default/17.alert_handler_esc_alert_accum.1191369210
Short name T378
Test name
Test status
Simulation time 439441674 ps
CPU time 33.5 seconds
Started Feb 04 01:20:32 PM PST 24
Finished Feb 04 01:21:08 PM PST 24
Peak memory 255404 kb
Host smart-1f80a306-94df-4336-aa4e-4a8c0593bea3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11913
69210 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_alert_accum.1191369210
Directory /workspace/17.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/17.alert_handler_esc_intr_timeout.592648671
Short name T504
Test name
Test status
Simulation time 5356711654 ps
CPU time 81.21 seconds
Started Feb 04 01:20:40 PM PST 24
Finished Feb 04 01:22:02 PM PST 24
Peak memory 254376 kb
Host smart-5e6ddca1-9321-4935-9a9d-6139e4bcafe1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59264
8671 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_intr_timeout.592648671
Directory /workspace/17.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_lpg.2247360029
Short name T214
Test name
Test status
Simulation time 56184969936 ps
CPU time 687.17 seconds
Started Feb 04 01:20:47 PM PST 24
Finished Feb 04 01:32:21 PM PST 24
Peak memory 264960 kb
Host smart-db102a80-8172-46d0-bf09-b8cabec8c0c3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247360029 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg.2247360029
Directory /workspace/17.alert_handler_lpg/latest

Test location /workspace/coverage/default/17.alert_handler_lpg_stub_clk.4059364081
Short name T627
Test name
Test status
Simulation time 28619382406 ps
CPU time 713.01 seconds
Started Feb 04 01:21:08 PM PST 24
Finished Feb 04 01:33:03 PM PST 24
Peak memory 272088 kb
Host smart-6e89f285-1ebc-48e4-b1e9-dd9d1d4dff21
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059364081 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg_stub_clk.4059364081
Directory /workspace/17.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/17.alert_handler_random_alerts.623187683
Short name T399
Test name
Test status
Simulation time 1953037007 ps
CPU time 29.31 seconds
Started Feb 04 01:20:34 PM PST 24
Finished Feb 04 01:21:05 PM PST 24
Peak memory 248432 kb
Host smart-7490c71c-c240-4951-9cdb-e5ae17c388e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62318
7683 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_alerts.623187683
Directory /workspace/17.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/17.alert_handler_random_classes.3063924295
Short name T40
Test name
Test status
Simulation time 118338656 ps
CPU time 8.55 seconds
Started Feb 04 01:20:31 PM PST 24
Finished Feb 04 01:20:42 PM PST 24
Peak memory 253520 kb
Host smart-1b30e9cd-a65e-4c31-8371-ccef27a3ac35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30639
24295 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_classes.3063924295
Directory /workspace/17.alert_handler_random_classes/latest

Test location /workspace/coverage/default/17.alert_handler_sig_int_fail.1874032644
Short name T406
Test name
Test status
Simulation time 1071774215 ps
CPU time 35.62 seconds
Started Feb 04 01:20:54 PM PST 24
Finished Feb 04 01:21:33 PM PST 24
Peak memory 255032 kb
Host smart-48d07acf-3f96-4eb3-8534-436b7ae75cc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18740
32644 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_sig_int_fail.1874032644
Directory /workspace/17.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/17.alert_handler_smoke.4105228391
Short name T457
Test name
Test status
Simulation time 76441728 ps
CPU time 5.05 seconds
Started Feb 04 01:20:35 PM PST 24
Finished Feb 04 01:20:41 PM PST 24
Peak memory 240320 kb
Host smart-d1880355-8429-4f27-a239-508f00d54745
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41052
28391 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_smoke.4105228391
Directory /workspace/17.alert_handler_smoke/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all.1658037572
Short name T508
Test name
Test status
Simulation time 33427276164 ps
CPU time 2159.64 seconds
Started Feb 04 01:20:55 PM PST 24
Finished Feb 04 01:56:59 PM PST 24
Peak memory 287412 kb
Host smart-bb987805-a783-4811-b70f-145f761ef313
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658037572 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_ha
ndler_stress_all.1658037572
Directory /workspace/17.alert_handler_stress_all/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all_with_rand_reset.4079620181
Short name T227
Test name
Test status
Simulation time 32152410162 ps
CPU time 1950.98 seconds
Started Feb 04 01:20:51 PM PST 24
Finished Feb 04 01:53:27 PM PST 24
Peak memory 288788 kb
Host smart-561f7933-abd2-4993-9b15-ee797c2f901b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079620181 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 17.alert_handler_stress_all_with_rand_reset.4079620181
Directory /workspace/17.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.alert_handler_alert_accum_saturation.1334823324
Short name T55
Test name
Test status
Simulation time 16358404 ps
CPU time 2.67 seconds
Started Feb 04 01:20:46 PM PST 24
Finished Feb 04 01:20:51 PM PST 24
Peak memory 248676 kb
Host smart-46324f84-c96c-47ec-bffa-c24c73bb5859
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1334823324 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_alert_accum_saturation.1334823324
Directory /workspace/18.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/18.alert_handler_entropy.644660723
Short name T634
Test name
Test status
Simulation time 52840019046 ps
CPU time 3053.52 seconds
Started Feb 04 01:20:51 PM PST 24
Finished Feb 04 02:11:50 PM PST 24
Peak memory 288700 kb
Host smart-ce18841d-b44c-40ff-965e-98e0d0786634
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644660723 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy.644660723
Directory /workspace/18.alert_handler_entropy/latest

Test location /workspace/coverage/default/18.alert_handler_entropy_stress.827169273
Short name T434
Test name
Test status
Simulation time 1030188774 ps
CPU time 44.03 seconds
Started Feb 04 01:20:50 PM PST 24
Finished Feb 04 01:21:40 PM PST 24
Peak memory 248228 kb
Host smart-449d5bfd-14bd-42b4-b9bb-d65a57aa359b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=827169273 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy_stress.827169273
Directory /workspace/18.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/18.alert_handler_esc_alert_accum.96919199
Short name T658
Test name
Test status
Simulation time 641168857 ps
CPU time 39.92 seconds
Started Feb 04 01:21:10 PM PST 24
Finished Feb 04 01:21:52 PM PST 24
Peak memory 247452 kb
Host smart-4016f082-e646-40c9-98fa-90614c30f562
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96919
199 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_alert_accum.96919199
Directory /workspace/18.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/18.alert_handler_esc_intr_timeout.2999482992
Short name T73
Test name
Test status
Simulation time 1886367262 ps
CPU time 13.1 seconds
Started Feb 04 01:20:49 PM PST 24
Finished Feb 04 01:21:09 PM PST 24
Peak memory 252456 kb
Host smart-4c6e45cb-cc9a-4915-9f0d-3eaa2a2ac0f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29994
82992 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_intr_timeout.2999482992
Directory /workspace/18.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_lpg_stub_clk.2413128876
Short name T583
Test name
Test status
Simulation time 188893877928 ps
CPU time 3057.31 seconds
Started Feb 04 01:20:46 PM PST 24
Finished Feb 04 02:11:46 PM PST 24
Peak memory 288596 kb
Host smart-ff141f91-98bb-4254-93cc-85169762fd17
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413128876 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg_stub_clk.2413128876
Directory /workspace/18.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/18.alert_handler_ping_timeout.1379835370
Short name T186
Test name
Test status
Simulation time 28866835939 ps
CPU time 274.75 seconds
Started Feb 04 01:20:48 PM PST 24
Finished Feb 04 01:25:29 PM PST 24
Peak memory 247184 kb
Host smart-dcd3fa2d-8b85-4fa9-882a-c929814e00b4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1379835370 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_ping_timeout.1379835370
Directory /workspace/18.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_random_alerts.4257168446
Short name T699
Test name
Test status
Simulation time 88253789 ps
CPU time 10.88 seconds
Started Feb 04 01:21:12 PM PST 24
Finished Feb 04 01:21:26 PM PST 24
Peak memory 248360 kb
Host smart-32fe3db0-b576-443c-8e9d-b9911fd1577c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42571
68446 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_alerts.4257168446
Directory /workspace/18.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/18.alert_handler_random_classes.923189760
Short name T462
Test name
Test status
Simulation time 189267421 ps
CPU time 18.96 seconds
Started Feb 04 01:20:48 PM PST 24
Finished Feb 04 01:21:14 PM PST 24
Peak memory 246776 kb
Host smart-a93be342-295d-4fa9-bcde-ef4f64b2ea57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92318
9760 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_classes.923189760
Directory /workspace/18.alert_handler_random_classes/latest

Test location /workspace/coverage/default/18.alert_handler_sig_int_fail.3273352487
Short name T235
Test name
Test status
Simulation time 1124019784 ps
CPU time 19.85 seconds
Started Feb 04 01:20:44 PM PST 24
Finished Feb 04 01:21:06 PM PST 24
Peak memory 253296 kb
Host smart-5c603095-fd74-4983-97e7-07bcb2978843
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32733
52487 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_sig_int_fail.3273352487
Directory /workspace/18.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/18.alert_handler_smoke.3840705774
Short name T486
Test name
Test status
Simulation time 2864243514 ps
CPU time 71.32 seconds
Started Feb 04 01:20:48 PM PST 24
Finished Feb 04 01:22:05 PM PST 24
Peak memory 256684 kb
Host smart-b6cefc85-3992-4eb8-ad46-69d0de8bdbe1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38407
05774 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_smoke.3840705774
Directory /workspace/18.alert_handler_smoke/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all.125929494
Short name T726
Test name
Test status
Simulation time 112556212298 ps
CPU time 1730.96 seconds
Started Feb 04 01:20:48 PM PST 24
Finished Feb 04 01:49:45 PM PST 24
Peak memory 272532 kb
Host smart-cf4be810-5dce-4d1f-b3d1-1a41daf67b29
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125929494 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_han
dler_stress_all.125929494
Directory /workspace/18.alert_handler_stress_all/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all_with_rand_reset.1496714720
Short name T226
Test name
Test status
Simulation time 249894582816 ps
CPU time 4280.1 seconds
Started Feb 04 01:21:11 PM PST 24
Finished Feb 04 02:32:35 PM PST 24
Peak memory 305296 kb
Host smart-b9c732e4-2d43-41f5-86d2-c14b00cef3a6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496714720 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.alert_handler_stress_all_with_rand_reset.1496714720
Directory /workspace/18.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.alert_handler_alert_accum_saturation.1229545747
Short name T197
Test name
Test status
Simulation time 36537245 ps
CPU time 3.35 seconds
Started Feb 04 01:20:46 PM PST 24
Finished Feb 04 01:20:52 PM PST 24
Peak memory 248688 kb
Host smart-0c3f8d75-aa31-4cc5-98e8-47c89f7eb760
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1229545747 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_alert_accum_saturation.1229545747
Directory /workspace/19.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/19.alert_handler_entropy.514587312
Short name T500
Test name
Test status
Simulation time 92770716866 ps
CPU time 1030.53 seconds
Started Feb 04 01:20:46 PM PST 24
Finished Feb 04 01:37:59 PM PST 24
Peak memory 272516 kb
Host smart-94a34ee9-17fd-476a-900d-e04510ca33ba
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514587312 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy.514587312
Directory /workspace/19.alert_handler_entropy/latest

Test location /workspace/coverage/default/19.alert_handler_entropy_stress.1024349747
Short name T220
Test name
Test status
Simulation time 2174563361 ps
CPU time 13.47 seconds
Started Feb 04 01:21:11 PM PST 24
Finished Feb 04 01:21:26 PM PST 24
Peak memory 240356 kb
Host smart-b9006953-7071-41e2-81f6-bda62e000494
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1024349747 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy_stress.1024349747
Directory /workspace/19.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/19.alert_handler_esc_alert_accum.813191219
Short name T662
Test name
Test status
Simulation time 5754832726 ps
CPU time 106.97 seconds
Started Feb 04 01:21:12 PM PST 24
Finished Feb 04 01:23:02 PM PST 24
Peak memory 256320 kb
Host smart-de2656b8-c9a5-4061-b920-193f9c375a8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81319
1219 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_alert_accum.813191219
Directory /workspace/19.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/19.alert_handler_esc_intr_timeout.55805155
Short name T727
Test name
Test status
Simulation time 642419722 ps
CPU time 28.84 seconds
Started Feb 04 01:20:50 PM PST 24
Finished Feb 04 01:21:25 PM PST 24
Peak memory 253860 kb
Host smart-eec24bd9-9585-4507-95ff-51bfc4b85bdf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55805
155 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_intr_timeout.55805155
Directory /workspace/19.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_lpg_stub_clk.4081995193
Short name T57
Test name
Test status
Simulation time 31180647930 ps
CPU time 1961.54 seconds
Started Feb 04 01:21:07 PM PST 24
Finished Feb 04 01:53:51 PM PST 24
Peak memory 272716 kb
Host smart-38a060d3-e130-48d2-a5fa-8b5f2a7281fa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081995193 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg_stub_clk.4081995193
Directory /workspace/19.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/19.alert_handler_ping_timeout.4079584940
Short name T51
Test name
Test status
Simulation time 14931511507 ps
CPU time 142.98 seconds
Started Feb 04 01:21:08 PM PST 24
Finished Feb 04 01:23:34 PM PST 24
Peak memory 247228 kb
Host smart-cfbddfce-27cc-4448-a3d8-76b108d12f91
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079584940 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_ping_timeout.4079584940
Directory /workspace/19.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_random_alerts.3695463026
Short name T441
Test name
Test status
Simulation time 172415787 ps
CPU time 15.48 seconds
Started Feb 04 01:20:55 PM PST 24
Finished Feb 04 01:21:14 PM PST 24
Peak memory 248424 kb
Host smart-3aede7c5-ed11-4b62-8b80-a11fa322c2eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36954
63026 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_alerts.3695463026
Directory /workspace/19.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/19.alert_handler_random_classes.4253127070
Short name T45
Test name
Test status
Simulation time 298856714 ps
CPU time 28.57 seconds
Started Feb 04 01:20:51 PM PST 24
Finished Feb 04 01:21:25 PM PST 24
Peak memory 254048 kb
Host smart-e48a910c-eed7-4f70-81b2-cb3f4e53d936
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42531
27070 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_classes.4253127070
Directory /workspace/19.alert_handler_random_classes/latest

Test location /workspace/coverage/default/19.alert_handler_sig_int_fail.2474478162
Short name T233
Test name
Test status
Simulation time 762263427 ps
CPU time 32.19 seconds
Started Feb 04 01:20:51 PM PST 24
Finished Feb 04 01:21:28 PM PST 24
Peak memory 253700 kb
Host smart-5c66f68e-0da3-47c6-87f7-95c7b762bcaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24744
78162 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_sig_int_fail.2474478162
Directory /workspace/19.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/19.alert_handler_smoke.2272158412
Short name T213
Test name
Test status
Simulation time 223539674 ps
CPU time 15.66 seconds
Started Feb 04 01:21:10 PM PST 24
Finished Feb 04 01:21:28 PM PST 24
Peak memory 248420 kb
Host smart-89562887-6122-4cc5-93ca-7e86f58537d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22721
58412 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_smoke.2272158412
Directory /workspace/19.alert_handler_smoke/latest

Test location /workspace/coverage/default/2.alert_handler_alert_accum_saturation.1547279775
Short name T199
Test name
Test status
Simulation time 118153675 ps
CPU time 2.34 seconds
Started Feb 04 01:19:39 PM PST 24
Finished Feb 04 01:19:44 PM PST 24
Peak memory 248664 kb
Host smart-0c5a1a04-947b-434c-9b76-bcb1212466d6
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1547279775 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_alert_accum_saturation.1547279775
Directory /workspace/2.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/2.alert_handler_entropy.3617155043
Short name T642
Test name
Test status
Simulation time 183375644734 ps
CPU time 3222.84 seconds
Started Feb 04 01:19:39 PM PST 24
Finished Feb 04 02:13:25 PM PST 24
Peak memory 289332 kb
Host smart-9d46195e-80d5-46fc-a4fc-6a35aeb9809a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617155043 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy.3617155043
Directory /workspace/2.alert_handler_entropy/latest

Test location /workspace/coverage/default/2.alert_handler_entropy_stress.502802333
Short name T547
Test name
Test status
Simulation time 813050915 ps
CPU time 18.28 seconds
Started Feb 04 01:19:42 PM PST 24
Finished Feb 04 01:20:09 PM PST 24
Peak memory 240268 kb
Host smart-bac34a53-7486-4a6f-b7c3-3cd48dbdec94
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=502802333 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy_stress.502802333
Directory /workspace/2.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/2.alert_handler_esc_alert_accum.1170533241
Short name T366
Test name
Test status
Simulation time 3435224686 ps
CPU time 96.97 seconds
Started Feb 04 01:19:50 PM PST 24
Finished Feb 04 01:21:29 PM PST 24
Peak memory 256020 kb
Host smart-54dcaff1-6a6d-41e5-8e29-21b04f698c08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11705
33241 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_alert_accum.1170533241
Directory /workspace/2.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/2.alert_handler_esc_intr_timeout.2240723706
Short name T397
Test name
Test status
Simulation time 2363803812 ps
CPU time 38.31 seconds
Started Feb 04 01:19:39 PM PST 24
Finished Feb 04 01:20:20 PM PST 24
Peak memory 254340 kb
Host smart-042a5cf0-7ae0-4b20-b726-91395291ccb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22407
23706 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_intr_timeout.2240723706
Directory /workspace/2.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_lpg.2595204146
Short name T314
Test name
Test status
Simulation time 32016502204 ps
CPU time 839.27 seconds
Started Feb 04 01:19:39 PM PST 24
Finished Feb 04 01:33:41 PM PST 24
Peak memory 264964 kb
Host smart-530117e7-53eb-4ecc-be8e-bc9f3c4cd228
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595204146 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg.2595204146
Directory /workspace/2.alert_handler_lpg/latest

Test location /workspace/coverage/default/2.alert_handler_lpg_stub_clk.3461089872
Short name T527
Test name
Test status
Simulation time 13796849121 ps
CPU time 1431.08 seconds
Started Feb 04 01:19:39 PM PST 24
Finished Feb 04 01:43:33 PM PST 24
Peak memory 288764 kb
Host smart-ebd85eca-6328-4b76-98f6-999c90981baa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461089872 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg_stub_clk.3461089872
Directory /workspace/2.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/2.alert_handler_random_alerts.1285960220
Short name T513
Test name
Test status
Simulation time 1256315856 ps
CPU time 40.76 seconds
Started Feb 04 01:19:40 PM PST 24
Finished Feb 04 01:20:29 PM PST 24
Peak memory 248432 kb
Host smart-85f7256c-affe-40e2-95e8-2e5921b2ddc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12859
60220 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_alerts.1285960220
Directory /workspace/2.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/2.alert_handler_random_classes.1988586185
Short name T728
Test name
Test status
Simulation time 6586680276 ps
CPU time 46.91 seconds
Started Feb 04 01:19:42 PM PST 24
Finished Feb 04 01:20:38 PM PST 24
Peak memory 255836 kb
Host smart-8cdc9c15-f7e2-475f-bc83-6d216e6ac652
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19885
86185 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_classes.1988586185
Directory /workspace/2.alert_handler_random_classes/latest

Test location /workspace/coverage/default/2.alert_handler_sig_int_fail.1666345945
Short name T453
Test name
Test status
Simulation time 1658549645 ps
CPU time 34.7 seconds
Started Feb 04 01:19:41 PM PST 24
Finished Feb 04 01:20:25 PM PST 24
Peak memory 246676 kb
Host smart-a42bd3c3-81c8-49e2-a58e-8d44b8df957e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16663
45945 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sig_int_fail.1666345945
Directory /workspace/2.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/2.alert_handler_smoke.3457034764
Short name T515
Test name
Test status
Simulation time 801299633 ps
CPU time 23.42 seconds
Started Feb 04 01:19:40 PM PST 24
Finished Feb 04 01:20:10 PM PST 24
Peak memory 248432 kb
Host smart-c0d7045c-2550-4d3b-b3df-ac01a928d41d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34570
34764 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_smoke.3457034764
Directory /workspace/2.alert_handler_smoke/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all.2192100074
Short name T645
Test name
Test status
Simulation time 128338247564 ps
CPU time 2034.19 seconds
Started Feb 04 01:19:38 PM PST 24
Finished Feb 04 01:53:36 PM PST 24
Peak memory 273072 kb
Host smart-bc83e5e9-f638-413b-9372-7d650788ae85
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192100074 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_han
dler_stress_all.2192100074
Directory /workspace/2.alert_handler_stress_all/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all_with_rand_reset.2609304104
Short name T243
Test name
Test status
Simulation time 188737085420 ps
CPU time 6065.42 seconds
Started Feb 04 01:19:42 PM PST 24
Finished Feb 04 03:00:57 PM PST 24
Peak memory 305988 kb
Host smart-9599346b-45dd-4c4e-a00b-276a269b46da
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609304104 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.alert_handler_stress_all_with_rand_reset.2609304104
Directory /workspace/2.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.alert_handler_entropy.1718088833
Short name T561
Test name
Test status
Simulation time 125528974468 ps
CPU time 2242.82 seconds
Started Feb 04 01:21:09 PM PST 24
Finished Feb 04 01:58:35 PM PST 24
Peak memory 289388 kb
Host smart-a3ac508a-eebe-442b-903a-950eac2fc4f5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1718088833 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_entropy.1718088833
Directory /workspace/20.alert_handler_entropy/latest

Test location /workspace/coverage/default/20.alert_handler_esc_alert_accum.2848646031
Short name T717
Test name
Test status
Simulation time 7643836187 ps
CPU time 155.38 seconds
Started Feb 04 01:20:48 PM PST 24
Finished Feb 04 01:23:29 PM PST 24
Peak memory 256328 kb
Host smart-bbecb12d-4eeb-48c8-8d49-cd04df45cbd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28486
46031 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_alert_accum.2848646031
Directory /workspace/20.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/20.alert_handler_esc_intr_timeout.1284966475
Short name T729
Test name
Test status
Simulation time 44206845 ps
CPU time 4.14 seconds
Started Feb 04 01:21:12 PM PST 24
Finished Feb 04 01:21:19 PM PST 24
Peak memory 238280 kb
Host smart-9263e6d5-7b5e-49b0-afe1-7d58075666e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12849
66475 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_intr_timeout.1284966475
Directory /workspace/20.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_lpg_stub_clk.1146920346
Short name T696
Test name
Test status
Simulation time 11827307958 ps
CPU time 1189.87 seconds
Started Feb 04 01:21:07 PM PST 24
Finished Feb 04 01:41:00 PM PST 24
Peak memory 271104 kb
Host smart-bc4bf963-e0d0-4185-83c2-8ef298e8b4b5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1146920346 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg_stub_clk.1146920346
Directory /workspace/20.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/20.alert_handler_ping_timeout.2591541219
Short name T266
Test name
Test status
Simulation time 10334763769 ps
CPU time 214.61 seconds
Started Feb 04 01:21:15 PM PST 24
Finished Feb 04 01:24:53 PM PST 24
Peak memory 247052 kb
Host smart-73ec7117-e756-45d0-aa89-e88a093cd9cd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591541219 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_ping_timeout.2591541219
Directory /workspace/20.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_random_alerts.3447677971
Short name T359
Test name
Test status
Simulation time 86108543 ps
CPU time 10.76 seconds
Started Feb 04 01:20:47 PM PST 24
Finished Feb 04 01:21:04 PM PST 24
Peak memory 256624 kb
Host smart-68558d80-a331-41b9-9743-be49a78ed566
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34476
77971 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_alerts.3447677971
Directory /workspace/20.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/20.alert_handler_random_classes.2618771857
Short name T411
Test name
Test status
Simulation time 116580962 ps
CPU time 5.56 seconds
Started Feb 04 01:21:12 PM PST 24
Finished Feb 04 01:21:21 PM PST 24
Peak memory 238516 kb
Host smart-5f71dc4d-d4c0-44c6-bf44-690e5fabd730
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26187
71857 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_classes.2618771857
Directory /workspace/20.alert_handler_random_classes/latest

Test location /workspace/coverage/default/20.alert_handler_smoke.4103699236
Short name T461
Test name
Test status
Simulation time 1490990794 ps
CPU time 25.07 seconds
Started Feb 04 01:20:46 PM PST 24
Finished Feb 04 01:21:14 PM PST 24
Peak memory 248420 kb
Host smart-7e5e344c-e26e-4d5a-8979-0eb2e46022dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41036
99236 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_smoke.4103699236
Directory /workspace/20.alert_handler_smoke/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all.47226906
Short name T576
Test name
Test status
Simulation time 7089185023 ps
CPU time 69.79 seconds
Started Feb 04 01:21:07 PM PST 24
Finished Feb 04 01:22:20 PM PST 24
Peak memory 256764 kb
Host smart-529776ec-3522-46d9-8862-370f15147a1f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47226906 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_hand
ler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_hand
ler_stress_all.47226906
Directory /workspace/20.alert_handler_stress_all/latest

Test location /workspace/coverage/default/21.alert_handler_entropy.2666911152
Short name T622
Test name
Test status
Simulation time 14459093256 ps
CPU time 1085.23 seconds
Started Feb 04 01:21:07 PM PST 24
Finished Feb 04 01:39:15 PM PST 24
Peak memory 285036 kb
Host smart-4e0c99d3-f254-4cdc-81b0-7d86a5cae077
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666911152 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_entropy.2666911152
Directory /workspace/21.alert_handler_entropy/latest

Test location /workspace/coverage/default/21.alert_handler_esc_alert_accum.1165491818
Short name T412
Test name
Test status
Simulation time 4448991255 ps
CPU time 90.43 seconds
Started Feb 04 01:21:11 PM PST 24
Finished Feb 04 01:22:44 PM PST 24
Peak memory 255864 kb
Host smart-734ba2d1-6085-44ca-ade6-83fe58366d1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11654
91818 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_alert_accum.1165491818
Directory /workspace/21.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/21.alert_handler_esc_intr_timeout.700553102
Short name T372
Test name
Test status
Simulation time 4220610948 ps
CPU time 50.83 seconds
Started Feb 04 01:21:12 PM PST 24
Finished Feb 04 01:22:05 PM PST 24
Peak memory 248028 kb
Host smart-c0471150-e4e5-4777-92af-41221edaa604
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70055
3102 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_intr_timeout.700553102
Directory /workspace/21.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_lpg.3980215566
Short name T219
Test name
Test status
Simulation time 38422966356 ps
CPU time 2120.47 seconds
Started Feb 04 01:21:09 PM PST 24
Finished Feb 04 01:56:32 PM PST 24
Peak memory 273000 kb
Host smart-dbd3a790-c6fa-4129-9c04-1d3e846aaccf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980215566 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg.3980215566
Directory /workspace/21.alert_handler_lpg/latest

Test location /workspace/coverage/default/21.alert_handler_lpg_stub_clk.40185797
Short name T301
Test name
Test status
Simulation time 38415729975 ps
CPU time 2458.81 seconds
Started Feb 04 01:21:12 PM PST 24
Finished Feb 04 02:02:14 PM PST 24
Peak memory 288732 kb
Host smart-eb65c851-52bf-4f1a-904f-0f1b594b3b4d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40185797 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg_stub_clk.40185797
Directory /workspace/21.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/21.alert_handler_ping_timeout.74256279
Short name T710
Test name
Test status
Simulation time 34654032473 ps
CPU time 546.08 seconds
Started Feb 04 01:21:12 PM PST 24
Finished Feb 04 01:30:21 PM PST 24
Peak memory 247004 kb
Host smart-e2fe1b3d-d919-4c24-9678-6ef181c80a30
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74256279 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_ping_timeout.74256279
Directory /workspace/21.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_random_alerts.843452736
Short name T649
Test name
Test status
Simulation time 682594390 ps
CPU time 25.61 seconds
Started Feb 04 01:21:08 PM PST 24
Finished Feb 04 01:21:36 PM PST 24
Peak memory 255200 kb
Host smart-e9154e46-d895-498a-9d0b-eb7322e5a864
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84345
2736 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_alerts.843452736
Directory /workspace/21.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/21.alert_handler_random_classes.3940465996
Short name T420
Test name
Test status
Simulation time 715155223 ps
CPU time 36.99 seconds
Started Feb 04 01:21:14 PM PST 24
Finished Feb 04 01:21:53 PM PST 24
Peak memory 255216 kb
Host smart-7b424616-2176-486f-8c63-601306a92ecc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39404
65996 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_classes.3940465996
Directory /workspace/21.alert_handler_random_classes/latest

Test location /workspace/coverage/default/21.alert_handler_sig_int_fail.3160845061
Short name T33
Test name
Test status
Simulation time 9101629330 ps
CPU time 43.65 seconds
Started Feb 04 01:21:10 PM PST 24
Finished Feb 04 01:21:56 PM PST 24
Peak memory 253816 kb
Host smart-2aa8a8e7-9e0b-4ccc-80f8-73025ae845c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31608
45061 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_sig_int_fail.3160845061
Directory /workspace/21.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/21.alert_handler_smoke.3807762
Short name T704
Test name
Test status
Simulation time 576766286 ps
CPU time 40.01 seconds
Started Feb 04 01:21:12 PM PST 24
Finished Feb 04 01:21:55 PM PST 24
Peak memory 248464 kb
Host smart-babba41a-5690-4e41-ac64-d2c75e2b6fb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38077
62 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_smoke.3807762
Directory /workspace/21.alert_handler_smoke/latest

Test location /workspace/coverage/default/22.alert_handler_entropy.26505969
Short name T616
Test name
Test status
Simulation time 114969548157 ps
CPU time 1597.12 seconds
Started Feb 04 01:21:06 PM PST 24
Finished Feb 04 01:47:47 PM PST 24
Peak memory 272656 kb
Host smart-dd81127b-42ec-4eeb-947e-cd3f32e8bd9f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26505969 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_entropy.26505969
Directory /workspace/22.alert_handler_entropy/latest

Test location /workspace/coverage/default/22.alert_handler_esc_alert_accum.2787632226
Short name T282
Test name
Test status
Simulation time 9288502341 ps
CPU time 279.04 seconds
Started Feb 04 01:21:20 PM PST 24
Finished Feb 04 01:26:00 PM PST 24
Peak memory 256680 kb
Host smart-78477bb2-5733-497b-ba1a-ae1445733810
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27876
32226 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_alert_accum.2787632226
Directory /workspace/22.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/22.alert_handler_esc_intr_timeout.166655689
Short name T540
Test name
Test status
Simulation time 836405199 ps
CPU time 45.69 seconds
Started Feb 04 01:21:11 PM PST 24
Finished Feb 04 01:21:58 PM PST 24
Peak memory 254520 kb
Host smart-9da55810-5416-4f66-a65a-45b4d84edc82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16665
5689 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_intr_timeout.166655689
Directory /workspace/22.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_lpg.1526066487
Short name T313
Test name
Test status
Simulation time 144248125117 ps
CPU time 1485.42 seconds
Started Feb 04 01:21:03 PM PST 24
Finished Feb 04 01:45:55 PM PST 24
Peak memory 272652 kb
Host smart-45eaadcc-954c-4b03-9d5b-d6c96b89f5f7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526066487 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg.1526066487
Directory /workspace/22.alert_handler_lpg/latest

Test location /workspace/coverage/default/22.alert_handler_lpg_stub_clk.3178701906
Short name T437
Test name
Test status
Simulation time 67420542383 ps
CPU time 2268.67 seconds
Started Feb 04 01:21:06 PM PST 24
Finished Feb 04 01:58:59 PM PST 24
Peak memory 281344 kb
Host smart-748ea601-8ad9-4d13-a21c-1e06cd37fc51
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178701906 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg_stub_clk.3178701906
Directory /workspace/22.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/22.alert_handler_ping_timeout.3181199145
Short name T259
Test name
Test status
Simulation time 5194273696 ps
CPU time 218.81 seconds
Started Feb 04 01:21:16 PM PST 24
Finished Feb 04 01:24:57 PM PST 24
Peak memory 247208 kb
Host smart-cb94c25e-6d3e-4823-aa50-93975710286e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181199145 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_ping_timeout.3181199145
Directory /workspace/22.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_random_alerts.2533655000
Short name T523
Test name
Test status
Simulation time 278202949 ps
CPU time 23.3 seconds
Started Feb 04 01:21:07 PM PST 24
Finished Feb 04 01:21:33 PM PST 24
Peak memory 255372 kb
Host smart-7febe43b-63e7-4e96-887b-b042b63ef04b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25336
55000 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_alerts.2533655000
Directory /workspace/22.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/22.alert_handler_random_classes.2196140687
Short name T396
Test name
Test status
Simulation time 51906827 ps
CPU time 4.27 seconds
Started Feb 04 01:21:03 PM PST 24
Finished Feb 04 01:21:14 PM PST 24
Peak memory 238524 kb
Host smart-369981bf-f30f-485c-a15b-d66f774218ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21961
40687 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_classes.2196140687
Directory /workspace/22.alert_handler_random_classes/latest

Test location /workspace/coverage/default/22.alert_handler_sig_int_fail.4144447407
Short name T532
Test name
Test status
Simulation time 1633608168 ps
CPU time 29.8 seconds
Started Feb 04 01:21:32 PM PST 24
Finished Feb 04 01:22:05 PM PST 24
Peak memory 253736 kb
Host smart-dc4eaa34-90c2-415f-9439-264c7b7e01ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41444
47407 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_sig_int_fail.4144447407
Directory /workspace/22.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/22.alert_handler_smoke.3740914374
Short name T528
Test name
Test status
Simulation time 421486494 ps
CPU time 2.97 seconds
Started Feb 04 01:21:04 PM PST 24
Finished Feb 04 01:21:13 PM PST 24
Peak memory 240216 kb
Host smart-fc5ce1f9-e01e-4ade-8473-743f91f57d65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37409
14374 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_smoke.3740914374
Directory /workspace/22.alert_handler_smoke/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all.2341746920
Short name T502
Test name
Test status
Simulation time 227110995308 ps
CPU time 3190.14 seconds
Started Feb 04 01:21:11 PM PST 24
Finished Feb 04 02:14:24 PM PST 24
Peak memory 288820 kb
Host smart-88a621e8-31c3-4505-a741-40b655775ebe
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341746920 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_ha
ndler_stress_all.2341746920
Directory /workspace/22.alert_handler_stress_all/latest

Test location /workspace/coverage/default/23.alert_handler_entropy.1400616558
Short name T86
Test name
Test status
Simulation time 30343461632 ps
CPU time 2183.49 seconds
Started Feb 04 01:21:11 PM PST 24
Finished Feb 04 01:57:37 PM PST 24
Peak memory 283240 kb
Host smart-4be4b653-2544-47bd-aa73-5a5e32bc8899
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1400616558 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_entropy.1400616558
Directory /workspace/23.alert_handler_entropy/latest

Test location /workspace/coverage/default/23.alert_handler_esc_alert_accum.2976118973
Short name T376
Test name
Test status
Simulation time 10959018708 ps
CPU time 265.37 seconds
Started Feb 04 01:21:12 PM PST 24
Finished Feb 04 01:25:41 PM PST 24
Peak memory 256696 kb
Host smart-27915481-3075-4164-9493-c8dc2f2e2bc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29761
18973 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_alert_accum.2976118973
Directory /workspace/23.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/23.alert_handler_esc_intr_timeout.325159723
Short name T517
Test name
Test status
Simulation time 968526794 ps
CPU time 33.37 seconds
Started Feb 04 01:21:06 PM PST 24
Finished Feb 04 01:21:43 PM PST 24
Peak memory 254704 kb
Host smart-bb33145b-27e4-48c0-9567-05bf1ef9d293
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32515
9723 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_intr_timeout.325159723
Directory /workspace/23.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_lpg.2327513079
Short name T15
Test name
Test status
Simulation time 40243169134 ps
CPU time 679.75 seconds
Started Feb 04 01:21:10 PM PST 24
Finished Feb 04 01:32:32 PM PST 24
Peak memory 273144 kb
Host smart-3d2e6ea4-4bfd-4ef7-b591-83ce19c10198
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327513079 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg.2327513079
Directory /workspace/23.alert_handler_lpg/latest

Test location /workspace/coverage/default/23.alert_handler_lpg_stub_clk.3305727154
Short name T215
Test name
Test status
Simulation time 157471955536 ps
CPU time 2405.95 seconds
Started Feb 04 01:21:12 PM PST 24
Finished Feb 04 02:01:21 PM PST 24
Peak memory 286360 kb
Host smart-66004437-a7e2-40e7-8d12-ad8eb5dd29c5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305727154 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg_stub_clk.3305727154
Directory /workspace/23.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/23.alert_handler_random_alerts.652366519
Short name T587
Test name
Test status
Simulation time 5469329822 ps
CPU time 32.69 seconds
Started Feb 04 01:21:08 PM PST 24
Finished Feb 04 01:21:43 PM PST 24
Peak memory 248688 kb
Host smart-c8c152c7-373b-4df6-a621-da30889a8f7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65236
6519 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_alerts.652366519
Directory /workspace/23.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/23.alert_handler_random_classes.1669131264
Short name T562
Test name
Test status
Simulation time 2537490210 ps
CPU time 12.54 seconds
Started Feb 04 01:21:12 PM PST 24
Finished Feb 04 01:21:27 PM PST 24
Peak memory 252236 kb
Host smart-053c0913-8d7a-4e49-af3e-b58556da3f8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16691
31264 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_classes.1669131264
Directory /workspace/23.alert_handler_random_classes/latest

Test location /workspace/coverage/default/23.alert_handler_sig_int_fail.850119968
Short name T619
Test name
Test status
Simulation time 179428349 ps
CPU time 20.68 seconds
Started Feb 04 01:21:20 PM PST 24
Finished Feb 04 01:21:42 PM PST 24
Peak memory 255016 kb
Host smart-1620756b-a20c-4271-8cb6-b29be6805fe0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85011
9968 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_sig_int_fail.850119968
Directory /workspace/23.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/23.alert_handler_smoke.1072236382
Short name T647
Test name
Test status
Simulation time 546893550 ps
CPU time 22.21 seconds
Started Feb 04 01:21:11 PM PST 24
Finished Feb 04 01:21:35 PM PST 24
Peak memory 248496 kb
Host smart-d1030f04-664b-4809-b29b-ebe51191c218
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10722
36382 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_smoke.1072236382
Directory /workspace/23.alert_handler_smoke/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all_with_rand_reset.3241147318
Short name T50
Test name
Test status
Simulation time 42315049278 ps
CPU time 4308.26 seconds
Started Feb 04 01:21:14 PM PST 24
Finished Feb 04 02:33:05 PM PST 24
Peak memory 346484 kb
Host smart-9d614f74-2d15-4900-8091-a785639589bb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241147318 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 23.alert_handler_stress_all_with_rand_reset.3241147318
Directory /workspace/23.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.alert_handler_entropy.4039265173
Short name T104
Test name
Test status
Simulation time 10456969808 ps
CPU time 1051.75 seconds
Started Feb 04 01:21:19 PM PST 24
Finished Feb 04 01:38:53 PM PST 24
Peak memory 289284 kb
Host smart-add0f486-475f-4a74-b9d1-8a4bb619c098
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039265173 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_entropy.4039265173
Directory /workspace/24.alert_handler_entropy/latest

Test location /workspace/coverage/default/24.alert_handler_esc_alert_accum.2721280179
Short name T482
Test name
Test status
Simulation time 737048214 ps
CPU time 74.61 seconds
Started Feb 04 01:21:14 PM PST 24
Finished Feb 04 01:22:31 PM PST 24
Peak memory 255924 kb
Host smart-1c45c663-2673-4ae4-9f6b-17c45cc69741
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27212
80179 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_alert_accum.2721280179
Directory /workspace/24.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/24.alert_handler_esc_intr_timeout.2077477018
Short name T559
Test name
Test status
Simulation time 2152990708 ps
CPU time 37.8 seconds
Started Feb 04 01:21:16 PM PST 24
Finished Feb 04 01:21:56 PM PST 24
Peak memory 253976 kb
Host smart-4b3edce5-81f9-4bc8-b85b-5e06fb701477
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20774
77018 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_intr_timeout.2077477018
Directory /workspace/24.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_lpg.104631399
Short name T605
Test name
Test status
Simulation time 84492991580 ps
CPU time 1081.32 seconds
Started Feb 04 01:21:12 PM PST 24
Finished Feb 04 01:39:17 PM PST 24
Peak memory 272636 kb
Host smart-a8eda983-00d8-4292-8a3c-7d03ce49cd1f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104631399 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg.104631399
Directory /workspace/24.alert_handler_lpg/latest

Test location /workspace/coverage/default/24.alert_handler_lpg_stub_clk.707559447
Short name T80
Test name
Test status
Simulation time 34891882051 ps
CPU time 2156.83 seconds
Started Feb 04 01:21:06 PM PST 24
Finished Feb 04 01:57:07 PM PST 24
Peak memory 281340 kb
Host smart-6250cf50-2b73-484c-a146-24a678d8104f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707559447 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg_stub_clk.707559447
Directory /workspace/24.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/24.alert_handler_ping_timeout.3689455427
Short name T590
Test name
Test status
Simulation time 8586871796 ps
CPU time 342.48 seconds
Started Feb 04 01:21:14 PM PST 24
Finished Feb 04 01:26:59 PM PST 24
Peak memory 247216 kb
Host smart-555bcab0-3fe3-470b-b86a-082f0f361677
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689455427 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_ping_timeout.3689455427
Directory /workspace/24.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_random_alerts.1954885299
Short name T421
Test name
Test status
Simulation time 567824292 ps
CPU time 19.68 seconds
Started Feb 04 01:21:12 PM PST 24
Finished Feb 04 01:21:35 PM PST 24
Peak memory 255080 kb
Host smart-f06fcfc2-9086-45a6-bdc9-ccb26f84b5c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19548
85299 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_alerts.1954885299
Directory /workspace/24.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/24.alert_handler_random_classes.3337121380
Short name T348
Test name
Test status
Simulation time 100427477 ps
CPU time 4.84 seconds
Started Feb 04 01:21:21 PM PST 24
Finished Feb 04 01:21:27 PM PST 24
Peak memory 238516 kb
Host smart-671a583d-5cc0-4921-8e91-452a9ebf68ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33371
21380 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_classes.3337121380
Directory /workspace/24.alert_handler_random_classes/latest

Test location /workspace/coverage/default/24.alert_handler_sig_int_fail.1892028204
Short name T382
Test name
Test status
Simulation time 12170766188 ps
CPU time 43.57 seconds
Started Feb 04 01:21:19 PM PST 24
Finished Feb 04 01:22:03 PM PST 24
Peak memory 255720 kb
Host smart-017f04f0-fcb0-464d-8617-bfac742e5e38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18920
28204 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_sig_int_fail.1892028204
Directory /workspace/24.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/24.alert_handler_smoke.98291124
Short name T718
Test name
Test status
Simulation time 2631820993 ps
CPU time 46.07 seconds
Started Feb 04 01:21:32 PM PST 24
Finished Feb 04 01:22:22 PM PST 24
Peak memory 256660 kb
Host smart-2ec7bd69-97db-4815-b4ca-00217d375bcc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98291
124 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_smoke.98291124
Directory /workspace/24.alert_handler_smoke/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all.3639519897
Short name T574
Test name
Test status
Simulation time 534799427555 ps
CPU time 2271.6 seconds
Started Feb 04 01:21:14 PM PST 24
Finished Feb 04 01:59:08 PM PST 24
Peak memory 288780 kb
Host smart-6ee276c4-5198-4918-8e49-8e2dc25c114d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639519897 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_ha
ndler_stress_all.3639519897
Directory /workspace/24.alert_handler_stress_all/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all_with_rand_reset.4266336160
Short name T402
Test name
Test status
Simulation time 22700061299 ps
CPU time 1666.37 seconds
Started Feb 04 01:21:18 PM PST 24
Finished Feb 04 01:49:05 PM PST 24
Peak memory 286980 kb
Host smart-b7f6a2b1-bfd3-493b-a182-c96429a7f18e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266336160 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 24.alert_handler_stress_all_with_rand_reset.4266336160
Directory /workspace/24.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.alert_handler_entropy.3149233090
Short name T425
Test name
Test status
Simulation time 14318204265 ps
CPU time 1429.32 seconds
Started Feb 04 01:21:10 PM PST 24
Finished Feb 04 01:45:02 PM PST 24
Peak memory 288912 kb
Host smart-0f74a718-0b7e-4d1d-ac72-6298117c9698
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149233090 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_entropy.3149233090
Directory /workspace/25.alert_handler_entropy/latest

Test location /workspace/coverage/default/25.alert_handler_esc_alert_accum.1190792977
Short name T491
Test name
Test status
Simulation time 6174025432 ps
CPU time 194.52 seconds
Started Feb 04 01:21:13 PM PST 24
Finished Feb 04 01:24:30 PM PST 24
Peak memory 256696 kb
Host smart-6d27e41e-7f69-4968-a73e-1d7d49c1d5b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11907
92977 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_alert_accum.1190792977
Directory /workspace/25.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/25.alert_handler_esc_intr_timeout.2189879076
Short name T477
Test name
Test status
Simulation time 975526937 ps
CPU time 28.21 seconds
Started Feb 04 01:21:12 PM PST 24
Finished Feb 04 01:21:43 PM PST 24
Peak memory 253004 kb
Host smart-3c1babbd-9b35-4e27-8e5f-ee8d2980f74f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21898
79076 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_intr_timeout.2189879076
Directory /workspace/25.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_lpg_stub_clk.2030083944
Short name T536
Test name
Test status
Simulation time 28683632906 ps
CPU time 990.45 seconds
Started Feb 04 01:21:11 PM PST 24
Finished Feb 04 01:37:44 PM PST 24
Peak memory 270336 kb
Host smart-21aed7a5-2b92-486a-94df-8b87584d93fe
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030083944 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg_stub_clk.2030083944
Directory /workspace/25.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/25.alert_handler_ping_timeout.936630842
Short name T736
Test name
Test status
Simulation time 8541381064 ps
CPU time 336.37 seconds
Started Feb 04 01:21:07 PM PST 24
Finished Feb 04 01:26:46 PM PST 24
Peak memory 246392 kb
Host smart-dff09ccd-45a6-48cd-848c-6953455d8174
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=936630842 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_ping_timeout.936630842
Directory /workspace/25.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_random_alerts.3422476049
Short name T721
Test name
Test status
Simulation time 131671457 ps
CPU time 5.89 seconds
Started Feb 04 01:21:11 PM PST 24
Finished Feb 04 01:21:20 PM PST 24
Peak memory 256620 kb
Host smart-072ee073-db64-4403-be1a-8ecab9c61b2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34224
76049 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_alerts.3422476049
Directory /workspace/25.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/25.alert_handler_random_classes.167468170
Short name T550
Test name
Test status
Simulation time 1238157057 ps
CPU time 40.76 seconds
Started Feb 04 01:21:14 PM PST 24
Finished Feb 04 01:21:57 PM PST 24
Peak memory 253312 kb
Host smart-95c1b313-3a0d-4522-b939-3ccd9b6ed73e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16746
8170 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_classes.167468170
Directory /workspace/25.alert_handler_random_classes/latest

Test location /workspace/coverage/default/25.alert_handler_sig_int_fail.4194694
Short name T510
Test name
Test status
Simulation time 948883350 ps
CPU time 17 seconds
Started Feb 04 01:21:11 PM PST 24
Finished Feb 04 01:21:31 PM PST 24
Peak memory 248344 kb
Host smart-830bbfd8-652d-4290-82c6-684eb88c433a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41946
94 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_sig_int_fail.4194694
Directory /workspace/25.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/25.alert_handler_smoke.3877978901
Short name T85
Test name
Test status
Simulation time 373224870 ps
CPU time 33.17 seconds
Started Feb 04 01:21:12 PM PST 24
Finished Feb 04 01:21:48 PM PST 24
Peak memory 248420 kb
Host smart-8a690777-b6a9-4425-985d-6736429b7a8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38779
78901 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_smoke.3877978901
Directory /workspace/25.alert_handler_smoke/latest

Test location /workspace/coverage/default/26.alert_handler_entropy.1499044982
Short name T529
Test name
Test status
Simulation time 41741148228 ps
CPU time 2523.61 seconds
Started Feb 04 01:21:12 PM PST 24
Finished Feb 04 02:03:19 PM PST 24
Peak memory 288716 kb
Host smart-7cd3f76a-75a7-4360-b532-691344508318
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1499044982 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_entropy.1499044982
Directory /workspace/26.alert_handler_entropy/latest

Test location /workspace/coverage/default/26.alert_handler_esc_alert_accum.3220822828
Short name T445
Test name
Test status
Simulation time 1742016397 ps
CPU time 114.55 seconds
Started Feb 04 01:21:20 PM PST 24
Finished Feb 04 01:23:16 PM PST 24
Peak memory 256076 kb
Host smart-c56054cf-2911-406f-b151-c911b0d60209
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32208
22828 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_alert_accum.3220822828
Directory /workspace/26.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/26.alert_handler_esc_intr_timeout.834598303
Short name T370
Test name
Test status
Simulation time 3885391499 ps
CPU time 60.13 seconds
Started Feb 04 01:21:14 PM PST 24
Finished Feb 04 01:22:18 PM PST 24
Peak memory 255044 kb
Host smart-defb4ba0-8b7e-47fc-abc6-638918957768
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83459
8303 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_intr_timeout.834598303
Directory /workspace/26.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_lpg.2759323689
Short name T667
Test name
Test status
Simulation time 42514315325 ps
CPU time 2033.26 seconds
Started Feb 04 01:21:14 PM PST 24
Finished Feb 04 01:55:10 PM PST 24
Peak memory 272700 kb
Host smart-e23832aa-ee16-4711-ae7d-1a4c1427e273
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759323689 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg.2759323689
Directory /workspace/26.alert_handler_lpg/latest

Test location /workspace/coverage/default/26.alert_handler_lpg_stub_clk.3464783599
Short name T724
Test name
Test status
Simulation time 122588154460 ps
CPU time 1837.82 seconds
Started Feb 04 01:21:08 PM PST 24
Finished Feb 04 01:51:49 PM PST 24
Peak memory 272156 kb
Host smart-8231cc43-9775-4b6b-a3d0-1bb527866938
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464783599 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg_stub_clk.3464783599
Directory /workspace/26.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/26.alert_handler_ping_timeout.1062497090
Short name T277
Test name
Test status
Simulation time 9358470315 ps
CPU time 405.96 seconds
Started Feb 04 01:21:10 PM PST 24
Finished Feb 04 01:27:59 PM PST 24
Peak memory 247112 kb
Host smart-8b796d8d-0de6-4314-8814-5a56d574373b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062497090 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_ping_timeout.1062497090
Directory /workspace/26.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_random_alerts.1613125536
Short name T603
Test name
Test status
Simulation time 1769993135 ps
CPU time 57.95 seconds
Started Feb 04 01:21:20 PM PST 24
Finished Feb 04 01:22:19 PM PST 24
Peak memory 248424 kb
Host smart-95b40dda-5d96-4191-bf8d-1c15b83246c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16131
25536 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_alerts.1613125536
Directory /workspace/26.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/26.alert_handler_random_classes.2685424562
Short name T585
Test name
Test status
Simulation time 421642790 ps
CPU time 28.33 seconds
Started Feb 04 01:21:15 PM PST 24
Finished Feb 04 01:21:46 PM PST 24
Peak memory 254768 kb
Host smart-8aa5d596-f69a-481a-8bfd-34159f443f98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26854
24562 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_classes.2685424562
Directory /workspace/26.alert_handler_random_classes/latest

Test location /workspace/coverage/default/26.alert_handler_sig_int_fail.1760149860
Short name T358
Test name
Test status
Simulation time 233108978 ps
CPU time 32.08 seconds
Started Feb 04 01:21:18 PM PST 24
Finished Feb 04 01:21:52 PM PST 24
Peak memory 248432 kb
Host smart-12070360-6bc3-492c-9d55-50f0f9d621f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17601
49860 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_sig_int_fail.1760149860
Directory /workspace/26.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/26.alert_handler_smoke.3825556225
Short name T703
Test name
Test status
Simulation time 1203813373 ps
CPU time 70.91 seconds
Started Feb 04 01:21:19 PM PST 24
Finished Feb 04 01:22:31 PM PST 24
Peak memory 255128 kb
Host smart-67a39b1c-b2d0-4440-bdde-cab3c2e20e32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38255
56225 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_smoke.3825556225
Directory /workspace/26.alert_handler_smoke/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all.3749321429
Short name T720
Test name
Test status
Simulation time 105701451967 ps
CPU time 1150.25 seconds
Started Feb 04 01:21:17 PM PST 24
Finished Feb 04 01:40:29 PM PST 24
Peak memory 284328 kb
Host smart-d8430009-daff-47a3-8ec0-5b24e3c8e9f1
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749321429 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_ha
ndler_stress_all.3749321429
Directory /workspace/26.alert_handler_stress_all/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all_with_rand_reset.698908048
Short name T218
Test name
Test status
Simulation time 169560254886 ps
CPU time 2902.25 seconds
Started Feb 04 01:21:11 PM PST 24
Finished Feb 04 02:09:37 PM PST 24
Peak memory 305012 kb
Host smart-704b87db-5aad-4efd-b5f1-691cf722f9e4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698908048 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 26.alert_handler_stress_all_with_rand_reset.698908048
Directory /workspace/26.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.alert_handler_entropy.3799050476
Short name T706
Test name
Test status
Simulation time 226211293059 ps
CPU time 3332.16 seconds
Started Feb 04 01:21:33 PM PST 24
Finished Feb 04 02:17:09 PM PST 24
Peak memory 289436 kb
Host smart-73a79c1c-c1db-43f0-ad33-9ab55f361f1f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799050476 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_entropy.3799050476
Directory /workspace/27.alert_handler_entropy/latest

Test location /workspace/coverage/default/27.alert_handler_esc_alert_accum.2252673960
Short name T205
Test name
Test status
Simulation time 2489573338 ps
CPU time 136.72 seconds
Started Feb 04 01:21:11 PM PST 24
Finished Feb 04 01:23:31 PM PST 24
Peak memory 256096 kb
Host smart-dd1aaf69-c547-4c4c-a599-5af3c1079457
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22526
73960 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_alert_accum.2252673960
Directory /workspace/27.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/27.alert_handler_esc_intr_timeout.3340066351
Short name T679
Test name
Test status
Simulation time 118370878 ps
CPU time 15.66 seconds
Started Feb 04 01:21:10 PM PST 24
Finished Feb 04 01:21:28 PM PST 24
Peak memory 254440 kb
Host smart-850554e8-58ab-4de5-ad9e-a61300d2bea2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33400
66351 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_intr_timeout.3340066351
Directory /workspace/27.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_lpg.2638990303
Short name T308
Test name
Test status
Simulation time 14737893079 ps
CPU time 1293.36 seconds
Started Feb 04 01:21:32 PM PST 24
Finished Feb 04 01:43:09 PM PST 24
Peak memory 288872 kb
Host smart-e3d5c5c4-2403-4fbb-a023-7a2a403844ca
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638990303 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg.2638990303
Directory /workspace/27.alert_handler_lpg/latest

Test location /workspace/coverage/default/27.alert_handler_lpg_stub_clk.2016578520
Short name T81
Test name
Test status
Simulation time 116510168076 ps
CPU time 1973.87 seconds
Started Feb 04 01:21:16 PM PST 24
Finished Feb 04 01:54:13 PM PST 24
Peak memory 273096 kb
Host smart-5ac96276-4bad-4efb-abe9-d4ca3f539d08
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2016578520 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg_stub_clk.2016578520
Directory /workspace/27.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/27.alert_handler_ping_timeout.437819347
Short name T653
Test name
Test status
Simulation time 37892113257 ps
CPU time 299.19 seconds
Started Feb 04 01:21:12 PM PST 24
Finished Feb 04 01:26:14 PM PST 24
Peak memory 247208 kb
Host smart-70b1f659-4e6c-4db5-a306-c6f76dca2f30
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437819347 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_ping_timeout.437819347
Directory /workspace/27.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_random_alerts.1941795416
Short name T552
Test name
Test status
Simulation time 2935164291 ps
CPU time 24.51 seconds
Started Feb 04 01:21:13 PM PST 24
Finished Feb 04 01:21:40 PM PST 24
Peak memory 248568 kb
Host smart-2448dcb8-eb14-40e6-a5bd-15d958de954f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19417
95416 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_alerts.1941795416
Directory /workspace/27.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/27.alert_handler_sig_int_fail.3398752878
Short name T512
Test name
Test status
Simulation time 884270390 ps
CPU time 21.99 seconds
Started Feb 04 01:21:19 PM PST 24
Finished Feb 04 01:21:43 PM PST 24
Peak memory 248432 kb
Host smart-f47d5b38-2981-495b-ac89-3fd6c2aead2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33987
52878 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_sig_int_fail.3398752878
Directory /workspace/27.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/27.alert_handler_smoke.2826141923
Short name T46
Test name
Test status
Simulation time 116582387 ps
CPU time 10.32 seconds
Started Feb 04 01:21:12 PM PST 24
Finished Feb 04 01:21:25 PM PST 24
Peak memory 248424 kb
Host smart-4f6edd9e-7543-49bc-b197-4526c9883424
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28261
41923 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_smoke.2826141923
Directory /workspace/27.alert_handler_smoke/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all.4255837940
Short name T71
Test name
Test status
Simulation time 5552876869 ps
CPU time 337.79 seconds
Started Feb 04 01:21:12 PM PST 24
Finished Feb 04 01:26:53 PM PST 24
Peak memory 256796 kb
Host smart-4e8cb9c4-5592-417e-8039-25beb2c8eb18
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255837940 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_ha
ndler_stress_all.4255837940
Directory /workspace/27.alert_handler_stress_all/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all_with_rand_reset.3080520489
Short name T641
Test name
Test status
Simulation time 98627392896 ps
CPU time 1027.13 seconds
Started Feb 04 01:21:32 PM PST 24
Finished Feb 04 01:38:43 PM PST 24
Peak memory 285432 kb
Host smart-7bbc585f-4d75-4ab4-9a2c-635081230b64
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080520489 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.alert_handler_stress_all_with_rand_reset.3080520489
Directory /workspace/27.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.alert_handler_esc_alert_accum.509242366
Short name T730
Test name
Test status
Simulation time 4881927894 ps
CPU time 67.88 seconds
Started Feb 04 01:21:16 PM PST 24
Finished Feb 04 01:22:26 PM PST 24
Peak memory 256156 kb
Host smart-2ab446b9-8882-4c4e-9dee-d5d3e717aa33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50924
2366 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_alert_accum.509242366
Directory /workspace/28.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/28.alert_handler_esc_intr_timeout.1286989879
Short name T620
Test name
Test status
Simulation time 865646251 ps
CPU time 45.28 seconds
Started Feb 04 01:21:14 PM PST 24
Finished Feb 04 01:22:01 PM PST 24
Peak memory 247968 kb
Host smart-9703230d-7a5c-491b-8b0b-29e0d5f385c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12869
89879 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_intr_timeout.1286989879
Directory /workspace/28.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_lpg.323766318
Short name T497
Test name
Test status
Simulation time 8556243532 ps
CPU time 813.75 seconds
Started Feb 04 01:21:32 PM PST 24
Finished Feb 04 01:35:10 PM PST 24
Peak memory 272392 kb
Host smart-506f1fe9-e6fa-4c08-8784-6bd3c3573284
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323766318 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg.323766318
Directory /workspace/28.alert_handler_lpg/latest

Test location /workspace/coverage/default/28.alert_handler_lpg_stub_clk.3303512869
Short name T407
Test name
Test status
Simulation time 109730043965 ps
CPU time 2704.54 seconds
Started Feb 04 01:21:27 PM PST 24
Finished Feb 04 02:06:33 PM PST 24
Peak memory 288980 kb
Host smart-4a16f2cc-c31d-49fb-871b-05db9ff43e32
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3303512869 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg_stub_clk.3303512869
Directory /workspace/28.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/28.alert_handler_ping_timeout.1252959682
Short name T602
Test name
Test status
Simulation time 11576899520 ps
CPU time 457.29 seconds
Started Feb 04 01:21:32 PM PST 24
Finished Feb 04 01:29:13 PM PST 24
Peak memory 254544 kb
Host smart-93a53f33-c552-419d-87c2-7ec260540f96
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252959682 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_ping_timeout.1252959682
Directory /workspace/28.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_random_alerts.2881613766
Short name T375
Test name
Test status
Simulation time 467640589 ps
CPU time 36.24 seconds
Started Feb 04 01:21:11 PM PST 24
Finished Feb 04 01:21:50 PM PST 24
Peak memory 248420 kb
Host smart-15cfa822-709a-4b77-89a2-384ce01fcce8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28816
13766 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_alerts.2881613766
Directory /workspace/28.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/28.alert_handler_random_classes.1287084079
Short name T548
Test name
Test status
Simulation time 497314530 ps
CPU time 23.62 seconds
Started Feb 04 01:21:13 PM PST 24
Finished Feb 04 01:21:39 PM PST 24
Peak memory 248448 kb
Host smart-1625d971-92fc-4557-aa94-1fe8dd3b67db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12870
84079 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_classes.1287084079
Directory /workspace/28.alert_handler_random_classes/latest

Test location /workspace/coverage/default/28.alert_handler_sig_int_fail.2039537802
Short name T606
Test name
Test status
Simulation time 8575253946 ps
CPU time 48.98 seconds
Started Feb 04 01:21:32 PM PST 24
Finished Feb 04 01:22:25 PM PST 24
Peak memory 247216 kb
Host smart-93f30ae2-1a4d-4ee6-b9ec-dfaae4957f45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20395
37802 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_sig_int_fail.2039537802
Directory /workspace/28.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/28.alert_handler_smoke.3653051427
Short name T349
Test name
Test status
Simulation time 10694601863 ps
CPU time 48.86 seconds
Started Feb 04 01:21:19 PM PST 24
Finished Feb 04 01:22:09 PM PST 24
Peak memory 248608 kb
Host smart-0fdc2f3b-3922-4fed-bd26-446641f0ee9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36530
51427 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_smoke.3653051427
Directory /workspace/28.alert_handler_smoke/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all.2049508539
Short name T678
Test name
Test status
Simulation time 10602238070 ps
CPU time 326.92 seconds
Started Feb 04 01:21:28 PM PST 24
Finished Feb 04 01:26:57 PM PST 24
Peak memory 252760 kb
Host smart-b0263acb-ba5a-4a71-bcff-a9d23662039b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049508539 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_ha
ndler_stress_all.2049508539
Directory /workspace/28.alert_handler_stress_all/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all_with_rand_reset.1614407721
Short name T304
Test name
Test status
Simulation time 23148330792 ps
CPU time 1458.6 seconds
Started Feb 04 01:21:29 PM PST 24
Finished Feb 04 01:45:50 PM PST 24
Peak memory 271264 kb
Host smart-7c59cfc4-4ef8-42a0-936a-50da49bc69a5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614407721 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.alert_handler_stress_all_with_rand_reset.1614407721
Directory /workspace/28.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.alert_handler_entropy.4269001650
Short name T530
Test name
Test status
Simulation time 111489618670 ps
CPU time 1990.5 seconds
Started Feb 04 01:21:25 PM PST 24
Finished Feb 04 01:54:37 PM PST 24
Peak memory 273108 kb
Host smart-59747b05-4b60-4fe5-922c-723be11dd1a1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4269001650 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_entropy.4269001650
Directory /workspace/29.alert_handler_entropy/latest

Test location /workspace/coverage/default/29.alert_handler_esc_alert_accum.3826772938
Short name T443
Test name
Test status
Simulation time 8827728109 ps
CPU time 97.12 seconds
Started Feb 04 01:21:22 PM PST 24
Finished Feb 04 01:23:00 PM PST 24
Peak memory 248512 kb
Host smart-d61ebcb0-ba0d-493c-ae3a-0b2eeb188cbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38267
72938 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_alert_accum.3826772938
Directory /workspace/29.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/29.alert_handler_esc_intr_timeout.903578309
Short name T474
Test name
Test status
Simulation time 1637980799 ps
CPU time 42.47 seconds
Started Feb 04 01:21:28 PM PST 24
Finished Feb 04 01:22:14 PM PST 24
Peak memory 254656 kb
Host smart-c4cc30c4-fd42-4d79-939f-d960577a1eac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90357
8309 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_intr_timeout.903578309
Directory /workspace/29.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_lpg.2491817789
Short name T687
Test name
Test status
Simulation time 9621906248 ps
CPU time 892.94 seconds
Started Feb 04 01:21:24 PM PST 24
Finished Feb 04 01:36:18 PM PST 24
Peak memory 271932 kb
Host smart-8860eef3-3f9e-4700-b7cc-00a37d9392f6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491817789 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg.2491817789
Directory /workspace/29.alert_handler_lpg/latest

Test location /workspace/coverage/default/29.alert_handler_lpg_stub_clk.4211183635
Short name T360
Test name
Test status
Simulation time 63298014886 ps
CPU time 1122.08 seconds
Started Feb 04 01:21:26 PM PST 24
Finished Feb 04 01:40:10 PM PST 24
Peak memory 264956 kb
Host smart-a634b74a-90c1-41d5-8b93-6c251687f594
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211183635 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg_stub_clk.4211183635
Directory /workspace/29.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/29.alert_handler_ping_timeout.4135787077
Short name T268
Test name
Test status
Simulation time 22681440520 ps
CPU time 431.22 seconds
Started Feb 04 01:21:28 PM PST 24
Finished Feb 04 01:28:41 PM PST 24
Peak memory 247432 kb
Host smart-ce469b1c-f4e3-4f96-8ceb-610b055e14a1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135787077 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_ping_timeout.4135787077
Directory /workspace/29.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_random_alerts.123492448
Short name T452
Test name
Test status
Simulation time 794250746 ps
CPU time 18.97 seconds
Started Feb 04 01:21:26 PM PST 24
Finished Feb 04 01:21:47 PM PST 24
Peak memory 248432 kb
Host smart-7d697428-74f3-4a39-a141-cac17f4091cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12349
2448 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_alerts.123492448
Directory /workspace/29.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/29.alert_handler_random_classes.4073950708
Short name T70
Test name
Test status
Simulation time 469510086 ps
CPU time 8.46 seconds
Started Feb 04 01:21:25 PM PST 24
Finished Feb 04 01:21:34 PM PST 24
Peak memory 250208 kb
Host smart-9e9073e2-5642-41fb-993c-c20b8c66df31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40739
50708 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_classes.4073950708
Directory /workspace/29.alert_handler_random_classes/latest

Test location /workspace/coverage/default/29.alert_handler_sig_int_fail.1692411355
Short name T722
Test name
Test status
Simulation time 1503746865 ps
CPU time 21.52 seconds
Started Feb 04 01:21:21 PM PST 24
Finished Feb 04 01:21:44 PM PST 24
Peak memory 246736 kb
Host smart-caeccad6-1871-43e3-9d8a-023e2dae7328
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16924
11355 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_sig_int_fail.1692411355
Directory /workspace/29.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/29.alert_handler_smoke.710692167
Short name T483
Test name
Test status
Simulation time 361879597 ps
CPU time 32.54 seconds
Started Feb 04 01:21:20 PM PST 24
Finished Feb 04 01:21:54 PM PST 24
Peak memory 248440 kb
Host smart-69788b2f-7b3d-4ee1-824e-3e8261341493
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71069
2167 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_smoke.710692167
Directory /workspace/29.alert_handler_smoke/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all.2539558991
Short name T296
Test name
Test status
Simulation time 58656069178 ps
CPU time 1371.49 seconds
Started Feb 04 01:21:27 PM PST 24
Finished Feb 04 01:44:20 PM PST 24
Peak memory 289180 kb
Host smart-e2157ebc-a037-4844-a7f5-5ea1a040525d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539558991 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_ha
ndler_stress_all.2539558991
Directory /workspace/29.alert_handler_stress_all/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all_with_rand_reset.2532808812
Short name T99
Test name
Test status
Simulation time 168268892000 ps
CPU time 2708.26 seconds
Started Feb 04 01:21:22 PM PST 24
Finished Feb 04 02:06:32 PM PST 24
Peak memory 289164 kb
Host smart-fd1463b2-2e3b-47fd-9d6a-08ce1dfc3c97
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532808812 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.alert_handler_stress_all_with_rand_reset.2532808812
Directory /workspace/29.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.alert_handler_alert_accum_saturation.4184801331
Short name T190
Test name
Test status
Simulation time 35864944 ps
CPU time 3.3 seconds
Started Feb 04 01:19:52 PM PST 24
Finished Feb 04 01:19:57 PM PST 24
Peak memory 248548 kb
Host smart-9bec07d9-d167-4856-89b5-b402c082b2bf
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4184801331 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_alert_accum_saturation.4184801331
Directory /workspace/3.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/3.alert_handler_entropy_stress.2486903785
Short name T566
Test name
Test status
Simulation time 106476850 ps
CPU time 6.94 seconds
Started Feb 04 01:19:52 PM PST 24
Finished Feb 04 01:20:00 PM PST 24
Peak memory 240160 kb
Host smart-bb8b830a-aec0-42e2-8ba8-2d2e4a8e2437
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2486903785 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy_stress.2486903785
Directory /workspace/3.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/3.alert_handler_esc_alert_accum.1658648866
Short name T533
Test name
Test status
Simulation time 1180982425 ps
CPU time 61.7 seconds
Started Feb 04 01:19:43 PM PST 24
Finished Feb 04 01:20:53 PM PST 24
Peak memory 255816 kb
Host smart-1aeb5c0b-4782-4d76-bcb9-4fbad0aeaea9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16586
48866 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_alert_accum.1658648866
Directory /workspace/3.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/3.alert_handler_esc_intr_timeout.178977196
Short name T19
Test name
Test status
Simulation time 2249743069 ps
CPU time 33.78 seconds
Started Feb 04 01:19:39 PM PST 24
Finished Feb 04 01:20:20 PM PST 24
Peak memory 248028 kb
Host smart-d42f9892-b472-4895-815b-49f624fbe4f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17897
7196 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_intr_timeout.178977196
Directory /workspace/3.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_lpg.3821604484
Short name T668
Test name
Test status
Simulation time 16874698266 ps
CPU time 1367.22 seconds
Started Feb 04 01:19:57 PM PST 24
Finished Feb 04 01:42:45 PM PST 24
Peak memory 281368 kb
Host smart-0dc39635-751a-443e-9f31-e467eaea3c59
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821604484 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg.3821604484
Directory /workspace/3.alert_handler_lpg/latest

Test location /workspace/coverage/default/3.alert_handler_lpg_stub_clk.1130864063
Short name T465
Test name
Test status
Simulation time 23301619125 ps
CPU time 631.2 seconds
Started Feb 04 01:19:57 PM PST 24
Finished Feb 04 01:30:29 PM PST 24
Peak memory 264984 kb
Host smart-52950d49-0e2b-41b7-9791-10c84b28206b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130864063 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg_stub_clk.1130864063
Directory /workspace/3.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/3.alert_handler_ping_timeout.1878251944
Short name T255
Test name
Test status
Simulation time 5893324885 ps
CPU time 258.44 seconds
Started Feb 04 01:19:51 PM PST 24
Finished Feb 04 01:24:11 PM PST 24
Peak memory 246472 kb
Host smart-c5559493-8efe-4352-a90d-356f714cd86e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878251944 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_ping_timeout.1878251944
Directory /workspace/3.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_random_alerts.573417129
Short name T20
Test name
Test status
Simulation time 531647015 ps
CPU time 19.04 seconds
Started Feb 04 01:19:39 PM PST 24
Finished Feb 04 01:20:01 PM PST 24
Peak memory 254200 kb
Host smart-eddeb0cb-e8bd-45a2-ace6-e274b7573a6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57341
7129 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_alerts.573417129
Directory /workspace/3.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/3.alert_handler_random_classes.3516291080
Short name T435
Test name
Test status
Simulation time 2512651264 ps
CPU time 33.68 seconds
Started Feb 04 01:19:41 PM PST 24
Finished Feb 04 01:20:24 PM PST 24
Peak memory 254980 kb
Host smart-35bb0894-2732-46af-8d34-da8e63ef0861
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35162
91080 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_classes.3516291080
Directory /workspace/3.alert_handler_random_classes/latest

Test location /workspace/coverage/default/3.alert_handler_sec_cm.2799265104
Short name T42
Test name
Test status
Simulation time 1803375248 ps
CPU time 24.23 seconds
Started Feb 04 01:19:56 PM PST 24
Finished Feb 04 01:20:21 PM PST 24
Peak memory 274040 kb
Host smart-104d2e98-5daf-41b3-a8b7-705a5d5831b4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2799265104 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sec_cm.2799265104
Directory /workspace/3.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/3.alert_handler_sig_int_fail.1397643891
Short name T280
Test name
Test status
Simulation time 53450548 ps
CPU time 6.39 seconds
Started Feb 04 01:19:38 PM PST 24
Finished Feb 04 01:19:48 PM PST 24
Peak memory 246708 kb
Host smart-28c53a52-fa2c-49c8-8628-4a666e91006b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13976
43891 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sig_int_fail.1397643891
Directory /workspace/3.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/3.alert_handler_smoke.3976709737
Short name T95
Test name
Test status
Simulation time 991548620 ps
CPU time 55.87 seconds
Started Feb 04 01:19:43 PM PST 24
Finished Feb 04 01:20:47 PM PST 24
Peak memory 255264 kb
Host smart-6b5c942d-5053-4458-91bd-670ddc6b5ddb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39767
09737 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_smoke.3976709737
Directory /workspace/3.alert_handler_smoke/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all.3526573873
Short name T388
Test name
Test status
Simulation time 14610819757 ps
CPU time 1895.01 seconds
Started Feb 04 01:19:52 PM PST 24
Finished Feb 04 01:51:29 PM PST 24
Peak memory 289452 kb
Host smart-65868aa4-e4fd-4368-966f-c3539a540f93
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526573873 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_han
dler_stress_all.3526573873
Directory /workspace/3.alert_handler_stress_all/latest

Test location /workspace/coverage/default/30.alert_handler_entropy.3174765983
Short name T106
Test name
Test status
Simulation time 63781022532 ps
CPU time 1449.01 seconds
Started Feb 04 01:21:28 PM PST 24
Finished Feb 04 01:45:39 PM PST 24
Peak memory 288456 kb
Host smart-45d008e6-5292-4e55-804a-acf8ad9a5a81
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174765983 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_entropy.3174765983
Directory /workspace/30.alert_handler_entropy/latest

Test location /workspace/coverage/default/30.alert_handler_esc_alert_accum.1842663643
Short name T564
Test name
Test status
Simulation time 33714039830 ps
CPU time 247.34 seconds
Started Feb 04 01:21:28 PM PST 24
Finished Feb 04 01:25:36 PM PST 24
Peak memory 256016 kb
Host smart-68ba070d-3de4-46e4-9a87-f72d5ddbc966
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18426
63643 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_alert_accum.1842663643
Directory /workspace/30.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/30.alert_handler_esc_intr_timeout.2467182883
Short name T377
Test name
Test status
Simulation time 831934299 ps
CPU time 18.31 seconds
Started Feb 04 01:21:21 PM PST 24
Finished Feb 04 01:21:41 PM PST 24
Peak memory 253268 kb
Host smart-2e7784d2-e79c-4a47-9b54-2e7da8263f92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24671
82883 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_intr_timeout.2467182883
Directory /workspace/30.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_lpg.2247815269
Short name T320
Test name
Test status
Simulation time 34511046377 ps
CPU time 1083.26 seconds
Started Feb 04 01:21:29 PM PST 24
Finished Feb 04 01:39:36 PM PST 24
Peak memory 264836 kb
Host smart-989320fe-36e5-4de2-a7c8-c20fa4bf7ea1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247815269 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg.2247815269
Directory /workspace/30.alert_handler_lpg/latest

Test location /workspace/coverage/default/30.alert_handler_lpg_stub_clk.2752739213
Short name T281
Test name
Test status
Simulation time 61952877767 ps
CPU time 1769.05 seconds
Started Feb 04 01:21:24 PM PST 24
Finished Feb 04 01:50:55 PM PST 24
Peak memory 271280 kb
Host smart-ea364036-eb72-4341-91ba-b564a0787da4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752739213 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg_stub_clk.2752739213
Directory /workspace/30.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/30.alert_handler_ping_timeout.2543385189
Short name T692
Test name
Test status
Simulation time 11043852481 ps
CPU time 232.05 seconds
Started Feb 04 01:21:29 PM PST 24
Finished Feb 04 01:25:24 PM PST 24
Peak memory 247424 kb
Host smart-4aff0059-e9d4-4714-b5b2-80863ae956f4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2543385189 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_ping_timeout.2543385189
Directory /workspace/30.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_random_alerts.756698306
Short name T3
Test name
Test status
Simulation time 3157456579 ps
CPU time 48.64 seconds
Started Feb 04 01:21:25 PM PST 24
Finished Feb 04 01:22:14 PM PST 24
Peak memory 248580 kb
Host smart-7ea94e61-7a45-49c4-94c5-cc2e026e8bd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75669
8306 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_alerts.756698306
Directory /workspace/30.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/30.alert_handler_random_classes.735960426
Short name T107
Test name
Test status
Simulation time 1159951296 ps
CPU time 26.53 seconds
Started Feb 04 01:21:28 PM PST 24
Finished Feb 04 01:21:58 PM PST 24
Peak memory 254844 kb
Host smart-ca669ab0-bd93-4caf-8e5d-c2b2542aa8f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73596
0426 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_classes.735960426
Directory /workspace/30.alert_handler_random_classes/latest

Test location /workspace/coverage/default/30.alert_handler_sig_int_fail.3059866193
Short name T439
Test name
Test status
Simulation time 281274093 ps
CPU time 21.46 seconds
Started Feb 04 01:21:27 PM PST 24
Finished Feb 04 01:21:50 PM PST 24
Peak memory 255120 kb
Host smart-9e6b73cf-bbcc-4529-b4a4-b1730f71dbd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30598
66193 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_sig_int_fail.3059866193
Directory /workspace/30.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/30.alert_handler_smoke.2859303842
Short name T542
Test name
Test status
Simulation time 695936251 ps
CPU time 12.97 seconds
Started Feb 04 01:21:25 PM PST 24
Finished Feb 04 01:21:39 PM PST 24
Peak memory 248432 kb
Host smart-d05bfc79-9265-470d-8fab-e2a522e92e6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28593
03842 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_smoke.2859303842
Directory /workspace/30.alert_handler_smoke/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all.3080603909
Short name T701
Test name
Test status
Simulation time 15189598760 ps
CPU time 402.85 seconds
Started Feb 04 01:21:24 PM PST 24
Finished Feb 04 01:28:08 PM PST 24
Peak memory 256596 kb
Host smart-291269da-3733-4ef4-a923-fd23af22406e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080603909 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_ha
ndler_stress_all.3080603909
Directory /workspace/30.alert_handler_stress_all/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all_with_rand_reset.2361589572
Short name T551
Test name
Test status
Simulation time 46360478590 ps
CPU time 1561.68 seconds
Started Feb 04 01:21:26 PM PST 24
Finished Feb 04 01:47:30 PM PST 24
Peak memory 269956 kb
Host smart-71b71155-b502-42bf-a38a-a6184e1419c3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361589572 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.alert_handler_stress_all_with_rand_reset.2361589572
Directory /workspace/30.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.alert_handler_entropy.2787165299
Short name T569
Test name
Test status
Simulation time 312977538757 ps
CPU time 2850.92 seconds
Started Feb 04 01:21:26 PM PST 24
Finished Feb 04 02:08:58 PM PST 24
Peak memory 289108 kb
Host smart-835a8fa5-77d2-45e0-ad05-088b312d9f69
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787165299 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_entropy.2787165299
Directory /workspace/31.alert_handler_entropy/latest

Test location /workspace/coverage/default/31.alert_handler_esc_alert_accum.2240581765
Short name T428
Test name
Test status
Simulation time 474687929 ps
CPU time 13.16 seconds
Started Feb 04 01:21:21 PM PST 24
Finished Feb 04 01:21:35 PM PST 24
Peak memory 254240 kb
Host smart-d6f7c43d-5017-4948-b34a-a832670adafb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22405
81765 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_alert_accum.2240581765
Directory /workspace/31.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/31.alert_handler_esc_intr_timeout.3589830976
Short name T405
Test name
Test status
Simulation time 141279080 ps
CPU time 16.34 seconds
Started Feb 04 01:21:22 PM PST 24
Finished Feb 04 01:21:40 PM PST 24
Peak memory 254604 kb
Host smart-e91bfa77-c1b7-4f46-a474-016f34ed4fb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35898
30976 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_intr_timeout.3589830976
Directory /workspace/31.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_lpg.3979731556
Short name T570
Test name
Test status
Simulation time 29974636572 ps
CPU time 1649.02 seconds
Started Feb 04 01:21:29 PM PST 24
Finished Feb 04 01:49:01 PM PST 24
Peak memory 273020 kb
Host smart-91722517-0b87-4f89-a3bc-379c74b211c8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979731556 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg.3979731556
Directory /workspace/31.alert_handler_lpg/latest

Test location /workspace/coverage/default/31.alert_handler_lpg_stub_clk.4137041069
Short name T303
Test name
Test status
Simulation time 50994890911 ps
CPU time 2911.69 seconds
Started Feb 04 01:21:30 PM PST 24
Finished Feb 04 02:10:04 PM PST 24
Peak memory 286008 kb
Host smart-2a3c3285-22bf-4da8-8de1-1a615c068d57
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137041069 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg_stub_clk.4137041069
Directory /workspace/31.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/31.alert_handler_ping_timeout.2505928547
Short name T217
Test name
Test status
Simulation time 36149518801 ps
CPU time 407.67 seconds
Started Feb 04 01:21:22 PM PST 24
Finished Feb 04 01:28:10 PM PST 24
Peak memory 247208 kb
Host smart-b8031a81-7f18-47da-bd1c-ff84369bf757
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505928547 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_ping_timeout.2505928547
Directory /workspace/31.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_random_alerts.2548863286
Short name T731
Test name
Test status
Simulation time 1654004308 ps
CPU time 35.78 seconds
Started Feb 04 01:21:28 PM PST 24
Finished Feb 04 01:22:05 PM PST 24
Peak memory 255416 kb
Host smart-18f84496-cf02-49ea-9f2e-8423af819933
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25488
63286 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_alerts.2548863286
Directory /workspace/31.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/31.alert_handler_random_classes.4146201208
Short name T444
Test name
Test status
Simulation time 1246467284 ps
CPU time 44.25 seconds
Started Feb 04 01:21:28 PM PST 24
Finished Feb 04 01:22:16 PM PST 24
Peak memory 254852 kb
Host smart-b02dd219-aa93-47de-8d8b-5b2030e4e3fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41462
01208 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_classes.4146201208
Directory /workspace/31.alert_handler_random_classes/latest

Test location /workspace/coverage/default/31.alert_handler_sig_int_fail.2935372900
Short name T302
Test name
Test status
Simulation time 1888591641 ps
CPU time 58.92 seconds
Started Feb 04 01:21:21 PM PST 24
Finished Feb 04 01:22:21 PM PST 24
Peak memory 254748 kb
Host smart-d9de3edf-d19c-4a4d-953c-a55b74dc611c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29353
72900 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_sig_int_fail.2935372900
Directory /workspace/31.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/31.alert_handler_smoke.2108222598
Short name T340
Test name
Test status
Simulation time 5298174210 ps
CPU time 16.96 seconds
Started Feb 04 01:21:22 PM PST 24
Finished Feb 04 01:21:40 PM PST 24
Peak memory 248552 kb
Host smart-607b12a6-a237-4bf1-b43b-e0596d2d1796
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21082
22598 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_smoke.2108222598
Directory /workspace/31.alert_handler_smoke/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all.3157289780
Short name T56
Test name
Test status
Simulation time 4739806482 ps
CPU time 288.63 seconds
Started Feb 04 01:21:26 PM PST 24
Finished Feb 04 01:26:16 PM PST 24
Peak memory 256784 kb
Host smart-bf331787-d90f-4b5b-8bc9-8b2d48e588af
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157289780 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_ha
ndler_stress_all.3157289780
Directory /workspace/31.alert_handler_stress_all/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all_with_rand_reset.2360813413
Short name T69
Test name
Test status
Simulation time 33881165326 ps
CPU time 1995.63 seconds
Started Feb 04 01:21:23 PM PST 24
Finished Feb 04 01:54:39 PM PST 24
Peak memory 281464 kb
Host smart-f92de5ba-00be-4c80-ad5d-3e8170301706
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360813413 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 31.alert_handler_stress_all_with_rand_reset.2360813413
Directory /workspace/31.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.alert_handler_entropy.3654783732
Short name T449
Test name
Test status
Simulation time 197829773763 ps
CPU time 2893.23 seconds
Started Feb 04 01:21:30 PM PST 24
Finished Feb 04 02:09:46 PM PST 24
Peak memory 287812 kb
Host smart-75fdcdc0-2f32-4912-ae62-d566ec415ef2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654783732 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_entropy.3654783732
Directory /workspace/32.alert_handler_entropy/latest

Test location /workspace/coverage/default/32.alert_handler_esc_alert_accum.1213143450
Short name T389
Test name
Test status
Simulation time 1097570041 ps
CPU time 111.57 seconds
Started Feb 04 01:21:31 PM PST 24
Finished Feb 04 01:23:26 PM PST 24
Peak memory 255884 kb
Host smart-611f6f99-137f-4c12-bbda-440dcbf37c73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12131
43450 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_alert_accum.1213143450
Directory /workspace/32.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/32.alert_handler_esc_intr_timeout.846150353
Short name T347
Test name
Test status
Simulation time 125183464 ps
CPU time 3.18 seconds
Started Feb 04 01:21:32 PM PST 24
Finished Feb 04 01:21:40 PM PST 24
Peak memory 238440 kb
Host smart-09b1095d-f4b9-47fd-aef9-1468ada3d7e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84615
0353 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_intr_timeout.846150353
Directory /workspace/32.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_lpg.3737155634
Short name T311
Test name
Test status
Simulation time 17421781778 ps
CPU time 1385.49 seconds
Started Feb 04 01:21:39 PM PST 24
Finished Feb 04 01:44:49 PM PST 24
Peak memory 283232 kb
Host smart-8e4ec19c-3b7b-43e5-ada6-bd227a432026
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737155634 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg.3737155634
Directory /workspace/32.alert_handler_lpg/latest

Test location /workspace/coverage/default/32.alert_handler_lpg_stub_clk.2045180465
Short name T589
Test name
Test status
Simulation time 35709843540 ps
CPU time 1661.94 seconds
Started Feb 04 01:21:30 PM PST 24
Finished Feb 04 01:49:16 PM PST 24
Peak memory 272480 kb
Host smart-a27a8aca-7161-49c9-9a56-5bf4c31d001d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045180465 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg_stub_clk.2045180465
Directory /workspace/32.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/32.alert_handler_ping_timeout.1884091926
Short name T210
Test name
Test status
Simulation time 20646971830 ps
CPU time 149.14 seconds
Started Feb 04 01:21:37 PM PST 24
Finished Feb 04 01:24:12 PM PST 24
Peak memory 248536 kb
Host smart-ab0c3bd2-e11f-41fa-9496-e487216c92aa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884091926 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_ping_timeout.1884091926
Directory /workspace/32.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_random_alerts.3204505657
Short name T432
Test name
Test status
Simulation time 524712981 ps
CPU time 14.96 seconds
Started Feb 04 01:21:24 PM PST 24
Finished Feb 04 01:21:40 PM PST 24
Peak memory 248448 kb
Host smart-2326c95f-8390-443d-aeb4-51b5b92d2cf4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32045
05657 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_alerts.3204505657
Directory /workspace/32.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/32.alert_handler_sig_int_fail.3100322193
Short name T494
Test name
Test status
Simulation time 253742783 ps
CPU time 9.59 seconds
Started Feb 04 01:21:39 PM PST 24
Finished Feb 04 01:21:53 PM PST 24
Peak memory 246168 kb
Host smart-91f74b3a-0db6-4ecf-9d4a-9a5293d83f01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31003
22193 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_sig_int_fail.3100322193
Directory /workspace/32.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/32.alert_handler_smoke.2951306626
Short name T708
Test name
Test status
Simulation time 8080167854 ps
CPU time 24.46 seconds
Started Feb 04 01:21:23 PM PST 24
Finished Feb 04 01:21:49 PM PST 24
Peak memory 248552 kb
Host smart-656aa095-08f2-4982-8786-2e383f79cd80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29513
06626 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_smoke.2951306626
Directory /workspace/32.alert_handler_smoke/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all.3506704925
Short name T90
Test name
Test status
Simulation time 5899782020 ps
CPU time 138.05 seconds
Started Feb 04 01:21:28 PM PST 24
Finished Feb 04 01:23:48 PM PST 24
Peak memory 256744 kb
Host smart-12df0883-e026-4414-8f34-3fb50a707c82
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506704925 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_ha
ndler_stress_all.3506704925
Directory /workspace/32.alert_handler_stress_all/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all_with_rand_reset.821463584
Short name T67
Test name
Test status
Simulation time 67000615263 ps
CPU time 1256.71 seconds
Started Feb 04 01:21:30 PM PST 24
Finished Feb 04 01:42:29 PM PST 24
Peak memory 285084 kb
Host smart-43aeedd4-e0bb-43b2-89b9-b783bd1b7dba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821463584 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 32.alert_handler_stress_all_with_rand_reset.821463584
Directory /workspace/32.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.alert_handler_entropy.3951443352
Short name T102
Test name
Test status
Simulation time 49897148568 ps
CPU time 1330.95 seconds
Started Feb 04 01:21:28 PM PST 24
Finished Feb 04 01:43:41 PM PST 24
Peak memory 286056 kb
Host smart-a91087f7-694f-4c4d-b0e6-efe2894e35bd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951443352 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_entropy.3951443352
Directory /workspace/33.alert_handler_entropy/latest

Test location /workspace/coverage/default/33.alert_handler_esc_alert_accum.3829892872
Short name T469
Test name
Test status
Simulation time 2331748035 ps
CPU time 141.6 seconds
Started Feb 04 01:21:30 PM PST 24
Finished Feb 04 01:23:54 PM PST 24
Peak memory 249560 kb
Host smart-bf21ce21-a352-405d-b1bc-c9afc9f4ac58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38298
92872 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_alert_accum.3829892872
Directory /workspace/33.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/33.alert_handler_esc_intr_timeout.2481092749
Short name T522
Test name
Test status
Simulation time 280585414 ps
CPU time 28.98 seconds
Started Feb 04 01:21:31 PM PST 24
Finished Feb 04 01:22:03 PM PST 24
Peak memory 254868 kb
Host smart-aac0816f-8607-438f-a7b3-947c5de03e54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24810
92749 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_intr_timeout.2481092749
Directory /workspace/33.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_lpg.724512424
Short name T209
Test name
Test status
Simulation time 25384949814 ps
CPU time 945.51 seconds
Started Feb 04 01:21:28 PM PST 24
Finished Feb 04 01:37:17 PM PST 24
Peak memory 289104 kb
Host smart-be12f4ce-95d2-44a2-9d2c-6c463c18d618
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724512424 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg.724512424
Directory /workspace/33.alert_handler_lpg/latest

Test location /workspace/coverage/default/33.alert_handler_lpg_stub_clk.1694662883
Short name T430
Test name
Test status
Simulation time 71770865266 ps
CPU time 2220.83 seconds
Started Feb 04 01:21:28 PM PST 24
Finished Feb 04 01:58:31 PM PST 24
Peak memory 288820 kb
Host smart-1b8e9fb0-37db-4152-b43d-8fc943923888
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694662883 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg_stub_clk.1694662883
Directory /workspace/33.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/33.alert_handler_ping_timeout.1637768716
Short name T612
Test name
Test status
Simulation time 33661894202 ps
CPU time 579.65 seconds
Started Feb 04 01:21:39 PM PST 24
Finished Feb 04 01:31:23 PM PST 24
Peak memory 247432 kb
Host smart-62b2c45e-d4f3-4ac6-8787-461b61d6222e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637768716 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_ping_timeout.1637768716
Directory /workspace/33.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_random_alerts.3926728537
Short name T473
Test name
Test status
Simulation time 563898936 ps
CPU time 26.79 seconds
Started Feb 04 01:21:30 PM PST 24
Finished Feb 04 01:22:00 PM PST 24
Peak memory 254884 kb
Host smart-bd16927e-acde-4eb0-abf5-2be28d00ae3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39267
28537 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_alerts.3926728537
Directory /workspace/33.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/33.alert_handler_random_classes.2266463749
Short name T677
Test name
Test status
Simulation time 2091861326 ps
CPU time 37.11 seconds
Started Feb 04 01:21:30 PM PST 24
Finished Feb 04 01:22:10 PM PST 24
Peak memory 255144 kb
Host smart-332c4949-3548-454d-b000-e5fbb05ec4f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22664
63749 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_classes.2266463749
Directory /workspace/33.alert_handler_random_classes/latest

Test location /workspace/coverage/default/33.alert_handler_sig_int_fail.944214452
Short name T228
Test name
Test status
Simulation time 1279076814 ps
CPU time 22.26 seconds
Started Feb 04 01:21:39 PM PST 24
Finished Feb 04 01:22:06 PM PST 24
Peak memory 253976 kb
Host smart-14b2625f-b2f9-4dad-8ee1-80558f4b61d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94421
4452 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_sig_int_fail.944214452
Directory /workspace/33.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/33.alert_handler_smoke.1212355345
Short name T541
Test name
Test status
Simulation time 362735112 ps
CPU time 24.08 seconds
Started Feb 04 01:21:31 PM PST 24
Finished Feb 04 01:21:59 PM PST 24
Peak memory 248452 kb
Host smart-2d1ad899-1743-4e1b-8d3c-29ad22234f5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12123
55345 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_smoke.1212355345
Directory /workspace/33.alert_handler_smoke/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all.1163689830
Short name T521
Test name
Test status
Simulation time 281978643076 ps
CPU time 2820.12 seconds
Started Feb 04 01:21:39 PM PST 24
Finished Feb 04 02:08:43 PM PST 24
Peak memory 288700 kb
Host smart-789c8a7b-f439-4c76-a361-d42cf32777be
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163689830 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_ha
ndler_stress_all.1163689830
Directory /workspace/33.alert_handler_stress_all/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all_with_rand_reset.2668925057
Short name T300
Test name
Test status
Simulation time 122768538231 ps
CPU time 5117.5 seconds
Started Feb 04 01:21:29 PM PST 24
Finished Feb 04 02:46:50 PM PST 24
Peak memory 338800 kb
Host smart-ad0a1e2f-6109-4218-be7a-9af4faa100cf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668925057 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 33.alert_handler_stress_all_with_rand_reset.2668925057
Directory /workspace/33.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.alert_handler_entropy.1139566352
Short name T582
Test name
Test status
Simulation time 49345304731 ps
CPU time 673.06 seconds
Started Feb 04 01:21:50 PM PST 24
Finished Feb 04 01:33:08 PM PST 24
Peak memory 271948 kb
Host smart-6655e303-06d0-4d9a-8dc8-a75a4d466fd9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139566352 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_entropy.1139566352
Directory /workspace/34.alert_handler_entropy/latest

Test location /workspace/coverage/default/34.alert_handler_esc_alert_accum.2153349636
Short name T599
Test name
Test status
Simulation time 10699408099 ps
CPU time 154.99 seconds
Started Feb 04 01:21:46 PM PST 24
Finished Feb 04 01:24:22 PM PST 24
Peak memory 256284 kb
Host smart-c5c378ea-99af-4dbd-babc-26973cf8319e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21533
49636 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_alert_accum.2153349636
Directory /workspace/34.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/34.alert_handler_esc_intr_timeout.1968887532
Short name T75
Test name
Test status
Simulation time 75367614 ps
CPU time 7.89 seconds
Started Feb 04 01:21:45 PM PST 24
Finished Feb 04 01:21:54 PM PST 24
Peak memory 252332 kb
Host smart-57810bcb-d4dc-4812-b340-8822c868e5dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19688
87532 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_intr_timeout.1968887532
Directory /workspace/34.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_lpg.3313293728
Short name T5
Test name
Test status
Simulation time 31508372986 ps
CPU time 1529.11 seconds
Started Feb 04 01:21:50 PM PST 24
Finished Feb 04 01:47:23 PM PST 24
Peak memory 266952 kb
Host smart-483f042e-3eb6-4f06-a64b-729a6a65e533
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313293728 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg.3313293728
Directory /workspace/34.alert_handler_lpg/latest

Test location /workspace/coverage/default/34.alert_handler_lpg_stub_clk.1127782006
Short name T395
Test name
Test status
Simulation time 9101833433 ps
CPU time 1064.52 seconds
Started Feb 04 01:21:48 PM PST 24
Finished Feb 04 01:39:33 PM PST 24
Peak memory 271180 kb
Host smart-9e2f9956-5718-414c-ac87-3ddce1705a7b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127782006 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg_stub_clk.1127782006
Directory /workspace/34.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/34.alert_handler_ping_timeout.2182029215
Short name T269
Test name
Test status
Simulation time 7751411110 ps
CPU time 305.55 seconds
Started Feb 04 01:21:45 PM PST 24
Finished Feb 04 01:26:51 PM PST 24
Peak memory 246308 kb
Host smart-ea9b96f9-1fac-4054-9f4e-816d6efc9e15
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2182029215 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_ping_timeout.2182029215
Directory /workspace/34.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_random_alerts.444121685
Short name T463
Test name
Test status
Simulation time 378837641 ps
CPU time 14.79 seconds
Started Feb 04 01:21:49 PM PST 24
Finished Feb 04 01:22:07 PM PST 24
Peak memory 248460 kb
Host smart-9105b331-f3d6-458c-9616-7b3b44878138
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44412
1685 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_alerts.444121685
Directory /workspace/34.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/34.alert_handler_random_classes.449630926
Short name T379
Test name
Test status
Simulation time 504826303 ps
CPU time 27.18 seconds
Started Feb 04 01:21:47 PM PST 24
Finished Feb 04 01:22:15 PM PST 24
Peak memory 255160 kb
Host smart-5029f4eb-a56c-4b82-81c0-4b225ed0b118
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44963
0926 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_classes.449630926
Directory /workspace/34.alert_handler_random_classes/latest

Test location /workspace/coverage/default/34.alert_handler_sig_int_fail.3867443844
Short name T232
Test name
Test status
Simulation time 1632710392 ps
CPU time 28.06 seconds
Started Feb 04 01:21:47 PM PST 24
Finished Feb 04 01:22:16 PM PST 24
Peak memory 247052 kb
Host smart-f3d2f874-ab46-4580-993c-71b3c836bf33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38674
43844 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_sig_int_fail.3867443844
Directory /workspace/34.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/34.alert_handler_smoke.1614196725
Short name T431
Test name
Test status
Simulation time 15760042760 ps
CPU time 61.74 seconds
Started Feb 04 01:21:30 PM PST 24
Finished Feb 04 01:22:34 PM PST 24
Peak memory 256532 kb
Host smart-30adaabe-6e2a-4efe-bfd0-ea2f3700d867
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16141
96725 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_smoke.1614196725
Directory /workspace/34.alert_handler_smoke/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all.71503265
Short name T438
Test name
Test status
Simulation time 30932334258 ps
CPU time 1706.16 seconds
Started Feb 04 01:21:45 PM PST 24
Finished Feb 04 01:50:12 PM PST 24
Peak memory 298212 kb
Host smart-956d8d76-4fa4-4c7c-b99b-d19a51485251
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71503265 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_hand
ler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_hand
ler_stress_all.71503265
Directory /workspace/34.alert_handler_stress_all/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all_with_rand_reset.258125357
Short name T471
Test name
Test status
Simulation time 29425730141 ps
CPU time 936.28 seconds
Started Feb 04 01:21:47 PM PST 24
Finished Feb 04 01:37:25 PM PST 24
Peak memory 272972 kb
Host smart-fa59ddef-7c25-4a70-aa6c-fa2a89807813
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258125357 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 34.alert_handler_stress_all_with_rand_reset.258125357
Directory /workspace/34.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.alert_handler_entropy.2133344410
Short name T278
Test name
Test status
Simulation time 18664591665 ps
CPU time 746.17 seconds
Started Feb 04 01:21:47 PM PST 24
Finished Feb 04 01:34:14 PM PST 24
Peak memory 273020 kb
Host smart-0a6e6b65-39f2-4a35-a016-e7eeb07de58b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2133344410 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_entropy.2133344410
Directory /workspace/35.alert_handler_entropy/latest

Test location /workspace/coverage/default/35.alert_handler_esc_alert_accum.1413142733
Short name T702
Test name
Test status
Simulation time 4098980449 ps
CPU time 262.66 seconds
Started Feb 04 01:21:46 PM PST 24
Finished Feb 04 01:26:10 PM PST 24
Peak memory 256068 kb
Host smart-1397ec69-4ef8-4f4f-8734-712e569763c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14131
42733 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_alert_accum.1413142733
Directory /workspace/35.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/35.alert_handler_esc_intr_timeout.2442172395
Short name T709
Test name
Test status
Simulation time 104333847 ps
CPU time 6.99 seconds
Started Feb 04 01:21:47 PM PST 24
Finished Feb 04 01:21:55 PM PST 24
Peak memory 252364 kb
Host smart-c1576f22-3b6c-4e34-bbad-6d2efc5c8de6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24421
72395 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_intr_timeout.2442172395
Directory /workspace/35.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_lpg.4050728801
Short name T216
Test name
Test status
Simulation time 115880493552 ps
CPU time 3327.07 seconds
Started Feb 04 01:21:51 PM PST 24
Finished Feb 04 02:17:23 PM PST 24
Peak memory 289076 kb
Host smart-c69f2065-56ae-41a6-85fe-39a4f23b4594
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050728801 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg.4050728801
Directory /workspace/35.alert_handler_lpg/latest

Test location /workspace/coverage/default/35.alert_handler_lpg_stub_clk.2652730208
Short name T484
Test name
Test status
Simulation time 56370512797 ps
CPU time 1936.77 seconds
Started Feb 04 01:21:49 PM PST 24
Finished Feb 04 01:54:09 PM PST 24
Peak memory 284028 kb
Host smart-48d51cd2-e7be-460d-9c30-32659acb5a0a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652730208 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg_stub_clk.2652730208
Directory /workspace/35.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/35.alert_handler_ping_timeout.2927251034
Short name T257
Test name
Test status
Simulation time 14398694705 ps
CPU time 323.32 seconds
Started Feb 04 01:21:50 PM PST 24
Finished Feb 04 01:27:17 PM PST 24
Peak memory 247472 kb
Host smart-12d3103b-c0c0-4274-9e3e-ea3386676b55
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927251034 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_ping_timeout.2927251034
Directory /workspace/35.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_random_alerts.1010688555
Short name T459
Test name
Test status
Simulation time 2369675685 ps
CPU time 31.47 seconds
Started Feb 04 01:21:47 PM PST 24
Finished Feb 04 01:22:20 PM PST 24
Peak memory 248564 kb
Host smart-d544021e-ff82-423e-8fa3-78639dd50fc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10106
88555 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_alerts.1010688555
Directory /workspace/35.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/35.alert_handler_random_classes.862835825
Short name T628
Test name
Test status
Simulation time 393202423 ps
CPU time 12.48 seconds
Started Feb 04 01:21:51 PM PST 24
Finished Feb 04 01:22:08 PM PST 24
Peak memory 247940 kb
Host smart-c13c2ede-37e6-4f1f-ae2e-1a070c98ac88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86283
5825 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_classes.862835825
Directory /workspace/35.alert_handler_random_classes/latest

Test location /workspace/coverage/default/35.alert_handler_sig_int_fail.585501627
Short name T572
Test name
Test status
Simulation time 121981039 ps
CPU time 3.04 seconds
Started Feb 04 01:21:45 PM PST 24
Finished Feb 04 01:21:49 PM PST 24
Peak memory 238316 kb
Host smart-66fa4f90-739f-4385-884b-5311133bb1ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58550
1627 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_sig_int_fail.585501627
Directory /workspace/35.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/35.alert_handler_smoke.1134051785
Short name T390
Test name
Test status
Simulation time 155430315 ps
CPU time 9.5 seconds
Started Feb 04 01:21:47 PM PST 24
Finished Feb 04 01:21:58 PM PST 24
Peak memory 248420 kb
Host smart-07f96c50-2945-441a-b091-d5225698c824
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11340
51785 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_smoke.1134051785
Directory /workspace/35.alert_handler_smoke/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all.1366116354
Short name T719
Test name
Test status
Simulation time 43568559608 ps
CPU time 2448.51 seconds
Started Feb 04 01:21:47 PM PST 24
Finished Feb 04 02:02:37 PM PST 24
Peak memory 285284 kb
Host smart-bd45a6dc-c912-428b-b013-579fd4ab65db
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366116354 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_ha
ndler_stress_all.1366116354
Directory /workspace/35.alert_handler_stress_all/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all_with_rand_reset.3412128026
Short name T114
Test name
Test status
Simulation time 62579294041 ps
CPU time 1624.37 seconds
Started Feb 04 01:21:45 PM PST 24
Finished Feb 04 01:48:50 PM PST 24
Peak memory 289684 kb
Host smart-77b6a11a-ba27-438c-998d-d349cde3051e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412128026 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 35.alert_handler_stress_all_with_rand_reset.3412128026
Directory /workspace/35.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.alert_handler_entropy.1502494696
Short name T423
Test name
Test status
Simulation time 21436899688 ps
CPU time 1195.34 seconds
Started Feb 04 01:22:02 PM PST 24
Finished Feb 04 01:41:58 PM PST 24
Peak memory 281256 kb
Host smart-44e740db-9546-4e97-87df-0992cab78704
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502494696 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_entropy.1502494696
Directory /workspace/36.alert_handler_entropy/latest

Test location /workspace/coverage/default/36.alert_handler_esc_alert_accum.1939473788
Short name T415
Test name
Test status
Simulation time 1048613290 ps
CPU time 52.56 seconds
Started Feb 04 01:21:45 PM PST 24
Finished Feb 04 01:22:39 PM PST 24
Peak memory 255792 kb
Host smart-59d59189-4b09-4b72-a8d8-d2e34f07593c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19394
73788 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_alert_accum.1939473788
Directory /workspace/36.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/36.alert_handler_esc_intr_timeout.1246847103
Short name T568
Test name
Test status
Simulation time 2877632968 ps
CPU time 27.47 seconds
Started Feb 04 01:21:45 PM PST 24
Finished Feb 04 01:22:14 PM PST 24
Peak memory 254800 kb
Host smart-685a3bc3-8c55-4d78-8162-fce429467097
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12468
47103 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_intr_timeout.1246847103
Directory /workspace/36.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_lpg_stub_clk.504723340
Short name T96
Test name
Test status
Simulation time 33733833518 ps
CPU time 1854.77 seconds
Started Feb 04 01:22:00 PM PST 24
Finished Feb 04 01:52:57 PM PST 24
Peak memory 284104 kb
Host smart-0ee8781c-b795-4b9a-a143-5ebf080c6fe1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504723340 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg_stub_clk.504723340
Directory /workspace/36.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/36.alert_handler_ping_timeout.1846050181
Short name T256
Test name
Test status
Simulation time 15646323661 ps
CPU time 331.79 seconds
Started Feb 04 01:22:00 PM PST 24
Finished Feb 04 01:27:34 PM PST 24
Peak memory 246520 kb
Host smart-145fe575-7040-4fb7-8c4f-ffd3db9b5e4e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846050181 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_ping_timeout.1846050181
Directory /workspace/36.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_random_alerts.870661596
Short name T485
Test name
Test status
Simulation time 3514643515 ps
CPU time 34.03 seconds
Started Feb 04 01:21:48 PM PST 24
Finished Feb 04 01:22:23 PM PST 24
Peak memory 248532 kb
Host smart-6d3dd6aa-0fb5-4210-9e97-89b4c288d3a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87066
1596 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_alerts.870661596
Directory /workspace/36.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/36.alert_handler_random_classes.2702596382
Short name T356
Test name
Test status
Simulation time 852237708 ps
CPU time 33.48 seconds
Started Feb 04 01:21:54 PM PST 24
Finished Feb 04 01:22:29 PM PST 24
Peak memory 255128 kb
Host smart-1f86b233-5f7b-4fc9-ba05-0e6a7709e860
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27025
96382 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_classes.2702596382
Directory /workspace/36.alert_handler_random_classes/latest

Test location /workspace/coverage/default/36.alert_handler_sig_int_fail.4074774175
Short name T629
Test name
Test status
Simulation time 3000470791 ps
CPU time 43.62 seconds
Started Feb 04 01:21:50 PM PST 24
Finished Feb 04 01:22:38 PM PST 24
Peak memory 248592 kb
Host smart-57cd6710-9fca-4d7c-a29a-6aa64a943360
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40747
74175 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_sig_int_fail.4074774175
Directory /workspace/36.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/36.alert_handler_smoke.809887135
Short name T633
Test name
Test status
Simulation time 425857403 ps
CPU time 45.21 seconds
Started Feb 04 01:21:47 PM PST 24
Finished Feb 04 01:22:34 PM PST 24
Peak memory 248424 kb
Host smart-74ff0098-c6c4-46d3-ade6-6bc0817d4164
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80988
7135 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_smoke.809887135
Directory /workspace/36.alert_handler_smoke/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all.634241741
Short name T392
Test name
Test status
Simulation time 203889517259 ps
CPU time 2039.53 seconds
Started Feb 04 01:22:01 PM PST 24
Finished Feb 04 01:56:02 PM PST 24
Peak memory 281304 kb
Host smart-acc30df8-8c5a-4a94-871d-2e3ffd6f3fce
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634241741 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_han
dler_stress_all.634241741
Directory /workspace/36.alert_handler_stress_all/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all_with_rand_reset.412395840
Short name T623
Test name
Test status
Simulation time 43830195876 ps
CPU time 4374.09 seconds
Started Feb 04 01:21:59 PM PST 24
Finished Feb 04 02:34:56 PM PST 24
Peak memory 337428 kb
Host smart-feb383a5-c19e-4e3c-a6d5-4d7ba47ab0ec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412395840 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 36.alert_handler_stress_all_with_rand_reset.412395840
Directory /workspace/36.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.alert_handler_entropy.993264884
Short name T646
Test name
Test status
Simulation time 93309663524 ps
CPU time 2915.56 seconds
Started Feb 04 01:22:02 PM PST 24
Finished Feb 04 02:10:39 PM PST 24
Peak memory 289024 kb
Host smart-de2f57c5-3a43-4811-b828-95a554db9c6e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993264884 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_entropy.993264884
Directory /workspace/37.alert_handler_entropy/latest

Test location /workspace/coverage/default/37.alert_handler_esc_alert_accum.3258258983
Short name T83
Test name
Test status
Simulation time 5962318577 ps
CPU time 103.25 seconds
Started Feb 04 01:22:03 PM PST 24
Finished Feb 04 01:23:48 PM PST 24
Peak memory 254784 kb
Host smart-7342ec9b-474c-4dd2-8f87-26ee39e62703
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32582
58983 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_alert_accum.3258258983
Directory /workspace/37.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/37.alert_handler_esc_intr_timeout.1040025699
Short name T357
Test name
Test status
Simulation time 330659435 ps
CPU time 30.14 seconds
Started Feb 04 01:22:02 PM PST 24
Finished Feb 04 01:22:33 PM PST 24
Peak memory 254880 kb
Host smart-1dc396f9-3465-4d1d-b3f2-24ef12a3fce2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10400
25699 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_intr_timeout.1040025699
Directory /workspace/37.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_lpg.24061270
Short name T310
Test name
Test status
Simulation time 553881420135 ps
CPU time 2518.27 seconds
Started Feb 04 01:22:06 PM PST 24
Finished Feb 04 02:04:06 PM PST 24
Peak memory 288804 kb
Host smart-29110ac5-c053-4def-b88a-5ede4c6d3539
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24061270 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg.24061270
Directory /workspace/37.alert_handler_lpg/latest

Test location /workspace/coverage/default/37.alert_handler_lpg_stub_clk.4051922003
Short name T595
Test name
Test status
Simulation time 81511753954 ps
CPU time 1113.18 seconds
Started Feb 04 01:22:03 PM PST 24
Finished Feb 04 01:40:37 PM PST 24
Peak memory 281348 kb
Host smart-78600b24-255e-4bac-9f7f-cb4352202a4c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051922003 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg_stub_clk.4051922003
Directory /workspace/37.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/37.alert_handler_ping_timeout.3194617893
Short name T636
Test name
Test status
Simulation time 10824387224 ps
CPU time 464.04 seconds
Started Feb 04 01:22:07 PM PST 24
Finished Feb 04 01:29:52 PM PST 24
Peak memory 247220 kb
Host smart-a65032cb-6bd1-4b09-890d-ee140d95e7b8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3194617893 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_ping_timeout.3194617893
Directory /workspace/37.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_random_alerts.2878946009
Short name T422
Test name
Test status
Simulation time 710618580 ps
CPU time 30.56 seconds
Started Feb 04 01:22:03 PM PST 24
Finished Feb 04 01:22:35 PM PST 24
Peak memory 248456 kb
Host smart-c64028fb-e249-45d7-b000-b2e101e1b549
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28789
46009 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_alerts.2878946009
Directory /workspace/37.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/37.alert_handler_random_classes.302809765
Short name T77
Test name
Test status
Simulation time 442402014 ps
CPU time 9.03 seconds
Started Feb 04 01:22:01 PM PST 24
Finished Feb 04 01:22:11 PM PST 24
Peak memory 247952 kb
Host smart-026e7347-4f55-4c0b-b0c8-aefa81fc9641
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30280
9765 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_classes.302809765
Directory /workspace/37.alert_handler_random_classes/latest

Test location /workspace/coverage/default/37.alert_handler_sig_int_fail.4276552703
Short name T380
Test name
Test status
Simulation time 527305277 ps
CPU time 18.06 seconds
Started Feb 04 01:22:04 PM PST 24
Finished Feb 04 01:22:23 PM PST 24
Peak memory 246616 kb
Host smart-7edb1482-144c-4c77-b683-96f66bbfe32c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42765
52703 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_sig_int_fail.4276552703
Directory /workspace/37.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/37.alert_handler_smoke.722890862
Short name T351
Test name
Test status
Simulation time 87078001 ps
CPU time 4.18 seconds
Started Feb 04 01:21:59 PM PST 24
Finished Feb 04 01:22:06 PM PST 24
Peak memory 240384 kb
Host smart-882f88a6-3873-4d31-b15f-076889a98b3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72289
0862 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_smoke.722890862
Directory /workspace/37.alert_handler_smoke/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all.3734196608
Short name T470
Test name
Test status
Simulation time 1143796461 ps
CPU time 92.73 seconds
Started Feb 04 01:22:05 PM PST 24
Finished Feb 04 01:23:39 PM PST 24
Peak memory 256588 kb
Host smart-5c295453-ca57-4bc8-af91-38cf15945ec3
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734196608 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_ha
ndler_stress_all.3734196608
Directory /workspace/37.alert_handler_stress_all/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all_with_rand_reset.3283767588
Short name T58
Test name
Test status
Simulation time 61035939331 ps
CPU time 4600.95 seconds
Started Feb 04 01:22:02 PM PST 24
Finished Feb 04 02:38:45 PM PST 24
Peak memory 305476 kb
Host smart-df23e382-bccb-4bb0-a4e9-e06240199442
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283767588 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 37.alert_handler_stress_all_with_rand_reset.3283767588
Directory /workspace/37.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.alert_handler_entropy.3744565734
Short name T475
Test name
Test status
Simulation time 26410762953 ps
CPU time 1394.15 seconds
Started Feb 04 01:22:03 PM PST 24
Finished Feb 04 01:45:18 PM PST 24
Peak memory 288916 kb
Host smart-c339560d-6158-4e40-b7c2-e5e71e865850
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744565734 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_entropy.3744565734
Directory /workspace/38.alert_handler_entropy/latest

Test location /workspace/coverage/default/38.alert_handler_esc_alert_accum.2686824560
Short name T598
Test name
Test status
Simulation time 1959816222 ps
CPU time 85.27 seconds
Started Feb 04 01:22:06 PM PST 24
Finished Feb 04 01:23:32 PM PST 24
Peak memory 255752 kb
Host smart-432dbc4f-64a0-44c3-9420-312620df85e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26868
24560 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_alert_accum.2686824560
Directory /workspace/38.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/38.alert_handler_esc_intr_timeout.1797047258
Short name T613
Test name
Test status
Simulation time 2246283378 ps
CPU time 46.47 seconds
Started Feb 04 01:22:02 PM PST 24
Finished Feb 04 01:22:49 PM PST 24
Peak memory 254952 kb
Host smart-e6564954-a301-40c2-9f36-092682f030df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17970
47258 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_intr_timeout.1797047258
Directory /workspace/38.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_lpg.1517330662
Short name T290
Test name
Test status
Simulation time 41295565713 ps
CPU time 2166.01 seconds
Started Feb 04 01:22:04 PM PST 24
Finished Feb 04 01:58:11 PM PST 24
Peak memory 288476 kb
Host smart-aafda315-ec77-4054-9fdd-3524ff26b121
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517330662 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg.1517330662
Directory /workspace/38.alert_handler_lpg/latest

Test location /workspace/coverage/default/38.alert_handler_lpg_stub_clk.2835313282
Short name T4
Test name
Test status
Simulation time 937871201351 ps
CPU time 2946.91 seconds
Started Feb 04 01:22:03 PM PST 24
Finished Feb 04 02:11:12 PM PST 24
Peak memory 288244 kb
Host smart-11c58025-457c-48d1-a644-1dfcc4cde4ba
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835313282 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg_stub_clk.2835313282
Directory /workspace/38.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/38.alert_handler_ping_timeout.280696060
Short name T267
Test name
Test status
Simulation time 110507155562 ps
CPU time 323.64 seconds
Started Feb 04 01:22:02 PM PST 24
Finished Feb 04 01:27:27 PM PST 24
Peak memory 247340 kb
Host smart-bb502184-12fe-45b9-a6b3-1e4b53cdfa11
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280696060 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_ping_timeout.280696060
Directory /workspace/38.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_random_alerts.1213686231
Short name T694
Test name
Test status
Simulation time 178899580 ps
CPU time 19.65 seconds
Started Feb 04 01:22:05 PM PST 24
Finished Feb 04 01:22:26 PM PST 24
Peak memory 255104 kb
Host smart-47414733-5874-48c5-885c-6b33201ede13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12136
86231 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_alerts.1213686231
Directory /workspace/38.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/38.alert_handler_random_classes.3167537768
Short name T305
Test name
Test status
Simulation time 1045914329 ps
CPU time 56.52 seconds
Started Feb 04 01:22:04 PM PST 24
Finished Feb 04 01:23:02 PM PST 24
Peak memory 248412 kb
Host smart-c0d12796-3f23-4cbb-9e8e-fb5cb24adf80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31675
37768 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_classes.3167537768
Directory /workspace/38.alert_handler_random_classes/latest

Test location /workspace/coverage/default/38.alert_handler_sig_int_fail.1511284634
Short name T674
Test name
Test status
Simulation time 5081074830 ps
CPU time 74.95 seconds
Started Feb 04 01:22:00 PM PST 24
Finished Feb 04 01:23:17 PM PST 24
Peak memory 255348 kb
Host smart-2d8bb18a-1896-4ad9-8dc9-12a0f1672fd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15112
84634 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_sig_int_fail.1511284634
Directory /workspace/38.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/38.alert_handler_smoke.654565106
Short name T341
Test name
Test status
Simulation time 198827831 ps
CPU time 14.33 seconds
Started Feb 04 01:22:00 PM PST 24
Finished Feb 04 01:22:16 PM PST 24
Peak memory 248452 kb
Host smart-1ab5d43f-818e-4065-8541-970d06241e25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65456
5106 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_smoke.654565106
Directory /workspace/38.alert_handler_smoke/latest

Test location /workspace/coverage/default/39.alert_handler_entropy.3986107427
Short name T654
Test name
Test status
Simulation time 72495007634 ps
CPU time 1315.93 seconds
Started Feb 04 01:22:15 PM PST 24
Finished Feb 04 01:44:16 PM PST 24
Peak memory 272644 kb
Host smart-6fe15e08-b6d2-4aec-abdf-66fb9e457e9b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986107427 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_entropy.3986107427
Directory /workspace/39.alert_handler_entropy/latest

Test location /workspace/coverage/default/39.alert_handler_esc_alert_accum.1855511775
Short name T680
Test name
Test status
Simulation time 6378914360 ps
CPU time 187.25 seconds
Started Feb 04 01:22:18 PM PST 24
Finished Feb 04 01:25:27 PM PST 24
Peak memory 255980 kb
Host smart-ed138b72-c4e7-4e52-86d2-f14aba5b8894
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18555
11775 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_alert_accum.1855511775
Directory /workspace/39.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/39.alert_handler_esc_intr_timeout.1536612290
Short name T639
Test name
Test status
Simulation time 4518707608 ps
CPU time 27.62 seconds
Started Feb 04 01:22:26 PM PST 24
Finished Feb 04 01:22:55 PM PST 24
Peak memory 254452 kb
Host smart-75897c7c-91ce-47c7-8406-c4c2cde1c413
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15366
12290 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_intr_timeout.1536612290
Directory /workspace/39.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_lpg.2856040946
Short name T316
Test name
Test status
Simulation time 34390372342 ps
CPU time 1409.27 seconds
Started Feb 04 01:22:17 PM PST 24
Finished Feb 04 01:45:49 PM PST 24
Peak memory 283052 kb
Host smart-ac7bfd0c-0e32-447f-a826-c22007b4e5d4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856040946 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg.2856040946
Directory /workspace/39.alert_handler_lpg/latest

Test location /workspace/coverage/default/39.alert_handler_lpg_stub_clk.2297595153
Short name T689
Test name
Test status
Simulation time 30247811334 ps
CPU time 1085.79 seconds
Started Feb 04 01:22:19 PM PST 24
Finished Feb 04 01:40:27 PM PST 24
Peak memory 264556 kb
Host smart-999b24c8-59b8-4b29-a4d5-8b9cacf6df4e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2297595153 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg_stub_clk.2297595153
Directory /workspace/39.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/39.alert_handler_ping_timeout.640633976
Short name T546
Test name
Test status
Simulation time 16247318572 ps
CPU time 191.46 seconds
Started Feb 04 01:22:20 PM PST 24
Finished Feb 04 01:25:33 PM PST 24
Peak memory 246480 kb
Host smart-89be9a76-f9e9-463d-8df1-e2fe9730cab6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640633976 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_ping_timeout.640633976
Directory /workspace/39.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_random_alerts.4107169813
Short name T383
Test name
Test status
Simulation time 800161284 ps
CPU time 22.99 seconds
Started Feb 04 01:22:17 PM PST 24
Finished Feb 04 01:22:43 PM PST 24
Peak memory 248456 kb
Host smart-fc924c8a-d3c9-435a-9836-50893bf5e451
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41071
69813 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_alerts.4107169813
Directory /workspace/39.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/39.alert_handler_random_classes.411423499
Short name T458
Test name
Test status
Simulation time 604878752 ps
CPU time 13.86 seconds
Started Feb 04 01:22:20 PM PST 24
Finished Feb 04 01:22:35 PM PST 24
Peak memory 246492 kb
Host smart-7b462bb5-4d3f-4d55-b93f-7f1fa815559c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41142
3499 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_classes.411423499
Directory /workspace/39.alert_handler_random_classes/latest

Test location /workspace/coverage/default/39.alert_handler_sig_int_fail.4118788394
Short name T239
Test name
Test status
Simulation time 258529385 ps
CPU time 27.69 seconds
Started Feb 04 01:22:19 PM PST 24
Finished Feb 04 01:22:48 PM PST 24
Peak memory 246804 kb
Host smart-35a61298-38df-4644-a54d-db1cb8591e59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41187
88394 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_sig_int_fail.4118788394
Directory /workspace/39.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/39.alert_handler_smoke.588042288
Short name T537
Test name
Test status
Simulation time 1575636900 ps
CPU time 40.94 seconds
Started Feb 04 01:22:01 PM PST 24
Finished Feb 04 01:22:43 PM PST 24
Peak memory 248444 kb
Host smart-2f3e74c1-fbfc-4b30-b6c1-a1d49003a48c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58804
2288 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_smoke.588042288
Directory /workspace/39.alert_handler_smoke/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all.3082315933
Short name T63
Test name
Test status
Simulation time 74041951754 ps
CPU time 748.1 seconds
Started Feb 04 01:22:19 PM PST 24
Finished Feb 04 01:34:49 PM PST 24
Peak memory 265000 kb
Host smart-690c7af3-fd4c-462e-8b90-03bbfce1695c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082315933 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_ha
ndler_stress_all.3082315933
Directory /workspace/39.alert_handler_stress_all/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all_with_rand_reset.1092366771
Short name T242
Test name
Test status
Simulation time 37964975242 ps
CPU time 2817.82 seconds
Started Feb 04 01:22:17 PM PST 24
Finished Feb 04 02:09:18 PM PST 24
Peak memory 297844 kb
Host smart-d83cb7aa-720b-4cb8-b3b8-ea356b3751b0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092366771 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.alert_handler_stress_all_with_rand_reset.1092366771
Directory /workspace/39.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.alert_handler_alert_accum_saturation.2045663907
Short name T204
Test name
Test status
Simulation time 18924517 ps
CPU time 2.77 seconds
Started Feb 04 01:19:52 PM PST 24
Finished Feb 04 01:19:56 PM PST 24
Peak memory 248684 kb
Host smart-fd9e96ce-5755-4f5d-8765-dceae74030a0
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2045663907 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_alert_accum_saturation.2045663907
Directory /workspace/4.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/4.alert_handler_entropy.2129236926
Short name T373
Test name
Test status
Simulation time 10709406589 ps
CPU time 1259.37 seconds
Started Feb 04 01:19:52 PM PST 24
Finished Feb 04 01:40:53 PM PST 24
Peak memory 289416 kb
Host smart-699aa6c6-c2e7-41e1-8e1c-3f0972541239
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129236926 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy.2129236926
Directory /workspace/4.alert_handler_entropy/latest

Test location /workspace/coverage/default/4.alert_handler_entropy_stress.1693502885
Short name T417
Test name
Test status
Simulation time 1787090886 ps
CPU time 17.24 seconds
Started Feb 04 01:19:53 PM PST 24
Finished Feb 04 01:20:12 PM PST 24
Peak memory 240232 kb
Host smart-bea43168-e0c2-4a0e-9f2b-9810be9f6708
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1693502885 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy_stress.1693502885
Directory /workspace/4.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/4.alert_handler_esc_alert_accum.3013125416
Short name T735
Test name
Test status
Simulation time 88325362 ps
CPU time 7.48 seconds
Started Feb 04 01:19:56 PM PST 24
Finished Feb 04 01:20:04 PM PST 24
Peak memory 240236 kb
Host smart-ec079bce-079a-4753-817e-87289da26423
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30131
25416 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_alert_accum.3013125416
Directory /workspace/4.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/4.alert_handler_esc_intr_timeout.1659782748
Short name T87
Test name
Test status
Simulation time 911848453 ps
CPU time 50.55 seconds
Started Feb 04 01:19:53 PM PST 24
Finished Feb 04 01:20:45 PM PST 24
Peak memory 254788 kb
Host smart-8e6c5806-aeb1-4ffb-8e8d-d8dd7a5449a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16597
82748 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_intr_timeout.1659782748
Directory /workspace/4.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_lpg.1422288824
Short name T539
Test name
Test status
Simulation time 43905203385 ps
CPU time 1738.61 seconds
Started Feb 04 01:19:57 PM PST 24
Finished Feb 04 01:48:57 PM PST 24
Peak memory 272680 kb
Host smart-6bb1ee70-f97c-4416-a459-91a73b34c3b9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422288824 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg.1422288824
Directory /workspace/4.alert_handler_lpg/latest

Test location /workspace/coverage/default/4.alert_handler_lpg_stub_clk.1010896408
Short name T480
Test name
Test status
Simulation time 12059703838 ps
CPU time 1618.9 seconds
Started Feb 04 01:20:04 PM PST 24
Finished Feb 04 01:47:08 PM PST 24
Peak memory 289256 kb
Host smart-d2648904-9964-40a8-85fa-9de968f3dc6a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010896408 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg_stub_clk.1010896408
Directory /workspace/4.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/4.alert_handler_ping_timeout.2639684448
Short name T586
Test name
Test status
Simulation time 9975786561 ps
CPU time 442.34 seconds
Started Feb 04 01:19:52 PM PST 24
Finished Feb 04 01:27:16 PM PST 24
Peak memory 247296 kb
Host smart-7469f44a-828f-4ee5-a78b-b6d0366bd674
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2639684448 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_ping_timeout.2639684448
Directory /workspace/4.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_random_alerts.2531820914
Short name T498
Test name
Test status
Simulation time 714381957 ps
CPU time 4.52 seconds
Started Feb 04 01:19:56 PM PST 24
Finished Feb 04 01:20:01 PM PST 24
Peak memory 240240 kb
Host smart-01739735-9d57-4d85-a0d2-67ad1f301cbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25318
20914 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_alerts.2531820914
Directory /workspace/4.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/4.alert_handler_random_classes.734600143
Short name T596
Test name
Test status
Simulation time 239667618 ps
CPU time 8.55 seconds
Started Feb 04 01:19:51 PM PST 24
Finished Feb 04 01:20:02 PM PST 24
Peak memory 253392 kb
Host smart-65f4ff2d-07e8-463c-9bb2-908072c58ad5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73460
0143 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_classes.734600143
Directory /workspace/4.alert_handler_random_classes/latest

Test location /workspace/coverage/default/4.alert_handler_sec_cm.390639730
Short name T13
Test name
Test status
Simulation time 415718771 ps
CPU time 24.58 seconds
Started Feb 04 01:19:58 PM PST 24
Finished Feb 04 01:20:23 PM PST 24
Peak memory 277276 kb
Host smart-838866a1-f617-49a0-ab0c-3c11c6ba4c02
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=390639730 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sec_cm.390639730
Directory /workspace/4.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/4.alert_handler_sig_int_fail.1307611293
Short name T240
Test name
Test status
Simulation time 213738170 ps
CPU time 14.18 seconds
Started Feb 04 01:19:54 PM PST 24
Finished Feb 04 01:20:10 PM PST 24
Peak memory 246668 kb
Host smart-a1787108-5458-414f-bbd3-b4fbb58c559d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13076
11293 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sig_int_fail.1307611293
Directory /workspace/4.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/4.alert_handler_smoke.4089584516
Short name T688
Test name
Test status
Simulation time 499090226 ps
CPU time 8.54 seconds
Started Feb 04 01:20:04 PM PST 24
Finished Feb 04 01:20:18 PM PST 24
Peak memory 248432 kb
Host smart-4d549695-ad84-4fd7-992e-c39164b1f8a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40895
84516 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_smoke.4089584516
Directory /workspace/4.alert_handler_smoke/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all_with_rand_reset.3778293599
Short name T578
Test name
Test status
Simulation time 156151545418 ps
CPU time 10338.2 seconds
Started Feb 04 01:19:53 PM PST 24
Finished Feb 04 04:12:14 PM PST 24
Peak memory 338184 kb
Host smart-ab4cede7-1b46-4aaa-b6dd-b7913a53278b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778293599 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.alert_handler_stress_all_with_rand_reset.3778293599
Directory /workspace/4.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.alert_handler_entropy.3380325675
Short name T580
Test name
Test status
Simulation time 100652258413 ps
CPU time 1318.29 seconds
Started Feb 04 01:22:19 PM PST 24
Finished Feb 04 01:44:19 PM PST 24
Peak memory 272368 kb
Host smart-376ca57e-f9bb-4443-babb-6a72c1d75efb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380325675 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_entropy.3380325675
Directory /workspace/40.alert_handler_entropy/latest

Test location /workspace/coverage/default/40.alert_handler_esc_alert_accum.1893492219
Short name T509
Test name
Test status
Simulation time 2317419227 ps
CPU time 124.57 seconds
Started Feb 04 01:22:14 PM PST 24
Finished Feb 04 01:24:24 PM PST 24
Peak memory 248120 kb
Host smart-0b6942c5-690e-4e87-866f-ca8525b518d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18934
92219 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_alert_accum.1893492219
Directory /workspace/40.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/40.alert_handler_esc_intr_timeout.1917555723
Short name T740
Test name
Test status
Simulation time 624533973 ps
CPU time 14.03 seconds
Started Feb 04 01:22:25 PM PST 24
Finished Feb 04 01:22:41 PM PST 24
Peak memory 253480 kb
Host smart-0b68453a-44f5-4cd7-9c39-bf3fe181dc07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19175
55723 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_intr_timeout.1917555723
Directory /workspace/40.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_lpg.3529282244
Short name T659
Test name
Test status
Simulation time 7919857859 ps
CPU time 677.71 seconds
Started Feb 04 01:22:17 PM PST 24
Finished Feb 04 01:33:38 PM PST 24
Peak memory 264952 kb
Host smart-056ceea1-f0f9-40b7-b729-c8cdd685e128
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529282244 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg.3529282244
Directory /workspace/40.alert_handler_lpg/latest

Test location /workspace/coverage/default/40.alert_handler_lpg_stub_clk.874614532
Short name T381
Test name
Test status
Simulation time 13980349853 ps
CPU time 1377.94 seconds
Started Feb 04 01:22:17 PM PST 24
Finished Feb 04 01:45:18 PM PST 24
Peak memory 289476 kb
Host smart-0bcbb5f5-38b9-41bf-a6c2-b7dcaa2b73c0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874614532 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg_stub_clk.874614532
Directory /workspace/40.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/40.alert_handler_ping_timeout.3334021384
Short name T472
Test name
Test status
Simulation time 8157805530 ps
CPU time 54.12 seconds
Started Feb 04 01:22:18 PM PST 24
Finished Feb 04 01:23:14 PM PST 24
Peak memory 247308 kb
Host smart-7be1d2ff-45f5-4132-8410-08d619f9203f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334021384 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_ping_timeout.3334021384
Directory /workspace/40.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_random_alerts.876921800
Short name T1
Test name
Test status
Simulation time 972588214 ps
CPU time 51.86 seconds
Started Feb 04 01:22:15 PM PST 24
Finished Feb 04 01:23:12 PM PST 24
Peak memory 255132 kb
Host smart-b9944f77-b552-49ef-b69a-cfdf79a563f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87692
1800 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_alerts.876921800
Directory /workspace/40.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/40.alert_handler_random_classes.3857502726
Short name T362
Test name
Test status
Simulation time 284072222 ps
CPU time 20.04 seconds
Started Feb 04 01:22:19 PM PST 24
Finished Feb 04 01:22:41 PM PST 24
Peak memory 246628 kb
Host smart-839a16ed-a0d9-4237-be50-2525a547227e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38575
02726 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_classes.3857502726
Directory /workspace/40.alert_handler_random_classes/latest

Test location /workspace/coverage/default/40.alert_handler_sig_int_fail.481036394
Short name T413
Test name
Test status
Simulation time 612110503 ps
CPU time 17.01 seconds
Started Feb 04 01:22:17 PM PST 24
Finished Feb 04 01:22:37 PM PST 24
Peak memory 255344 kb
Host smart-6fd03f58-6530-463e-b0e0-3dabbef6ba78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48103
6394 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_sig_int_fail.481036394
Directory /workspace/40.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/40.alert_handler_smoke.1582641654
Short name T446
Test name
Test status
Simulation time 499109606 ps
CPU time 14.88 seconds
Started Feb 04 01:22:25 PM PST 24
Finished Feb 04 01:22:41 PM PST 24
Peak memory 248180 kb
Host smart-b9323ab6-12b7-45a2-b913-fc29c6aee1ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15826
41654 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_smoke.1582641654
Directory /workspace/40.alert_handler_smoke/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all.4018733310
Short name T408
Test name
Test status
Simulation time 769827603 ps
CPU time 44.9 seconds
Started Feb 04 01:22:16 PM PST 24
Finished Feb 04 01:23:05 PM PST 24
Peak memory 248432 kb
Host smart-15c454c8-e5f5-4f98-b1b7-5dde80410a0a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018733310 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_ha
ndler_stress_all.4018733310
Directory /workspace/40.alert_handler_stress_all/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all_with_rand_reset.4076396325
Short name T103
Test name
Test status
Simulation time 43876953436 ps
CPU time 2109.64 seconds
Started Feb 04 01:22:26 PM PST 24
Finished Feb 04 01:57:37 PM PST 24
Peak memory 289104 kb
Host smart-6784026b-ec22-46d3-8697-7722d7e7e6e5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076396325 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 40.alert_handler_stress_all_with_rand_reset.4076396325
Directory /workspace/40.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.alert_handler_entropy.2223202745
Short name T394
Test name
Test status
Simulation time 54934704871 ps
CPU time 1643.02 seconds
Started Feb 04 01:22:18 PM PST 24
Finished Feb 04 01:49:43 PM PST 24
Peak memory 272128 kb
Host smart-dc968ea2-0c91-448a-ad2e-021aa9d4e8db
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223202745 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_entropy.2223202745
Directory /workspace/41.alert_handler_entropy/latest

Test location /workspace/coverage/default/41.alert_handler_esc_alert_accum.3616530810
Short name T614
Test name
Test status
Simulation time 3463953593 ps
CPU time 53.9 seconds
Started Feb 04 01:22:18 PM PST 24
Finished Feb 04 01:23:14 PM PST 24
Peak memory 255524 kb
Host smart-e25c03bf-7fd7-4d61-b987-deac0d5c5574
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36165
30810 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_alert_accum.3616530810
Directory /workspace/41.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/41.alert_handler_esc_intr_timeout.1342529083
Short name T344
Test name
Test status
Simulation time 281372360 ps
CPU time 5.35 seconds
Started Feb 04 01:22:16 PM PST 24
Finished Feb 04 01:22:25 PM PST 24
Peak memory 238372 kb
Host smart-39631f2f-d8df-4368-9063-9c2c7104fed3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13425
29083 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_intr_timeout.1342529083
Directory /workspace/41.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_lpg_stub_clk.150650075
Short name T652
Test name
Test status
Simulation time 54181506094 ps
CPU time 1329.71 seconds
Started Feb 04 01:22:19 PM PST 24
Finished Feb 04 01:44:30 PM PST 24
Peak memory 284792 kb
Host smart-71a9bdfa-886d-4c12-8b11-e323fd9e0950
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150650075 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg_stub_clk.150650075
Directory /workspace/41.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/41.alert_handler_ping_timeout.2916579194
Short name T276
Test name
Test status
Simulation time 10814732635 ps
CPU time 412.52 seconds
Started Feb 04 01:22:18 PM PST 24
Finished Feb 04 01:29:13 PM PST 24
Peak memory 247340 kb
Host smart-9215f98d-5289-4368-9e61-b96ff5d537d5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916579194 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_ping_timeout.2916579194
Directory /workspace/41.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_random_alerts.613075363
Short name T684
Test name
Test status
Simulation time 2700569423 ps
CPU time 39.57 seconds
Started Feb 04 01:22:19 PM PST 24
Finished Feb 04 01:23:00 PM PST 24
Peak memory 248588 kb
Host smart-8dc607ac-bdd8-4068-aea2-e2465c01534d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61307
5363 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_alerts.613075363
Directory /workspace/41.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/41.alert_handler_random_classes.560623573
Short name T621
Test name
Test status
Simulation time 768513168 ps
CPU time 25.2 seconds
Started Feb 04 01:22:16 PM PST 24
Finished Feb 04 01:22:45 PM PST 24
Peak memory 254384 kb
Host smart-9d4d014c-0d69-475b-b27c-93d77fb9a455
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56062
3573 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_classes.560623573
Directory /workspace/41.alert_handler_random_classes/latest

Test location /workspace/coverage/default/41.alert_handler_sig_int_fail.1358362816
Short name T707
Test name
Test status
Simulation time 471395979 ps
CPU time 15.08 seconds
Started Feb 04 01:22:25 PM PST 24
Finished Feb 04 01:22:42 PM PST 24
Peak memory 254144 kb
Host smart-58837f3f-874a-48d7-9a9a-e4f0699a1107
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13583
62816 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_sig_int_fail.1358362816
Directory /workspace/41.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/41.alert_handler_smoke.512294717
Short name T563
Test name
Test status
Simulation time 358239036 ps
CPU time 21.13 seconds
Started Feb 04 01:22:16 PM PST 24
Finished Feb 04 01:22:41 PM PST 24
Peak memory 248452 kb
Host smart-7fc57eeb-7e78-416d-99b2-5bbf1b1c1d19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51229
4717 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_smoke.512294717
Directory /workspace/41.alert_handler_smoke/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all.3728469672
Short name T669
Test name
Test status
Simulation time 245358911468 ps
CPU time 3573.89 seconds
Started Feb 04 01:22:20 PM PST 24
Finished Feb 04 02:21:55 PM PST 24
Peak memory 289016 kb
Host smart-e12c1004-3063-409a-ab1f-43fcc9e452d5
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728469672 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_ha
ndler_stress_all.3728469672
Directory /workspace/41.alert_handler_stress_all/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all_with_rand_reset.1384686075
Short name T2
Test name
Test status
Simulation time 9609126519 ps
CPU time 544.2 seconds
Started Feb 04 01:22:22 PM PST 24
Finished Feb 04 01:31:28 PM PST 24
Peak memory 265080 kb
Host smart-ece43899-22d2-4dff-abc4-f3a64d7b046c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384686075 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 41.alert_handler_stress_all_with_rand_reset.1384686075
Directory /workspace/41.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.alert_handler_entropy.3240602167
Short name T401
Test name
Test status
Simulation time 101819900095 ps
CPU time 1880.16 seconds
Started Feb 04 01:22:26 PM PST 24
Finished Feb 04 01:53:48 PM PST 24
Peak memory 273128 kb
Host smart-9d3b6225-a6be-4a1b-9551-9bc58ec8686b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3240602167 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_entropy.3240602167
Directory /workspace/42.alert_handler_entropy/latest

Test location /workspace/coverage/default/42.alert_handler_esc_alert_accum.441297603
Short name T54
Test name
Test status
Simulation time 16222113748 ps
CPU time 236.04 seconds
Started Feb 04 01:22:17 PM PST 24
Finished Feb 04 01:26:16 PM PST 24
Peak memory 255816 kb
Host smart-5197d64f-d2a4-4567-8a01-211cbe77ec2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44129
7603 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_alert_accum.441297603
Directory /workspace/42.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/42.alert_handler_esc_intr_timeout.3003798843
Short name T519
Test name
Test status
Simulation time 432848426 ps
CPU time 16.39 seconds
Started Feb 04 01:22:19 PM PST 24
Finished Feb 04 01:22:37 PM PST 24
Peak memory 254788 kb
Host smart-611e164b-a30b-4f96-bfc4-10b5e01f9b60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30037
98843 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_intr_timeout.3003798843
Directory /workspace/42.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_lpg.3518591116
Short name T418
Test name
Test status
Simulation time 39082287822 ps
CPU time 807.71 seconds
Started Feb 04 01:22:22 PM PST 24
Finished Feb 04 01:35:51 PM PST 24
Peak memory 271924 kb
Host smart-498f7d1e-0280-4400-9e16-a7e4332769ba
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518591116 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg.3518591116
Directory /workspace/42.alert_handler_lpg/latest

Test location /workspace/coverage/default/42.alert_handler_lpg_stub_clk.3778346089
Short name T531
Test name
Test status
Simulation time 104735341999 ps
CPU time 1377.69 seconds
Started Feb 04 01:22:24 PM PST 24
Finished Feb 04 01:45:23 PM PST 24
Peak memory 286616 kb
Host smart-51b4cb2d-5c22-4265-8c9d-d1a35bf304f4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778346089 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg_stub_clk.3778346089
Directory /workspace/42.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/42.alert_handler_ping_timeout.1000312028
Short name T264
Test name
Test status
Simulation time 83615157507 ps
CPU time 229.52 seconds
Started Feb 04 01:22:22 PM PST 24
Finished Feb 04 01:26:13 PM PST 24
Peak memory 248376 kb
Host smart-5fee3a56-701b-44f2-ad94-789e5327d5c6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000312028 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_ping_timeout.1000312028
Directory /workspace/42.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_random_alerts.4145932701
Short name T538
Test name
Test status
Simulation time 3599534568 ps
CPU time 30.73 seconds
Started Feb 04 01:22:19 PM PST 24
Finished Feb 04 01:22:51 PM PST 24
Peak memory 248464 kb
Host smart-ae64e96b-9070-4994-ad1f-828224c48457
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41459
32701 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_alerts.4145932701
Directory /workspace/42.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/42.alert_handler_random_classes.3960925759
Short name T460
Test name
Test status
Simulation time 968901650 ps
CPU time 58.07 seconds
Started Feb 04 01:22:20 PM PST 24
Finished Feb 04 01:23:19 PM PST 24
Peak memory 255172 kb
Host smart-7d3c1639-94e9-4359-b2a0-b7810033182c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39609
25759 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_classes.3960925759
Directory /workspace/42.alert_handler_random_classes/latest

Test location /workspace/coverage/default/42.alert_handler_sig_int_fail.1899852018
Short name T556
Test name
Test status
Simulation time 4017221335 ps
CPU time 61.87 seconds
Started Feb 04 01:22:30 PM PST 24
Finished Feb 04 01:23:33 PM PST 24
Peak memory 248420 kb
Host smart-57c068ed-ce6c-4a6c-8888-101cb6316d61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18998
52018 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_sig_int_fail.1899852018
Directory /workspace/42.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/42.alert_handler_smoke.839911180
Short name T79
Test name
Test status
Simulation time 91275591 ps
CPU time 9.26 seconds
Started Feb 04 01:22:16 PM PST 24
Finished Feb 04 01:22:29 PM PST 24
Peak memory 248424 kb
Host smart-ca3ce411-28a0-4ed9-972c-342985867e8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83991
1180 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_smoke.839911180
Directory /workspace/42.alert_handler_smoke/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all_with_rand_reset.636821568
Short name T664
Test name
Test status
Simulation time 177300758405 ps
CPU time 4784.18 seconds
Started Feb 04 01:22:32 PM PST 24
Finished Feb 04 02:42:17 PM PST 24
Peak memory 305704 kb
Host smart-43b17c0f-9f08-4de5-87e6-b07fe3b605e6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636821568 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 42.alert_handler_stress_all_with_rand_reset.636821568
Directory /workspace/42.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.alert_handler_entropy.1461890560
Short name T82
Test name
Test status
Simulation time 93935181997 ps
CPU time 2898.54 seconds
Started Feb 04 01:22:24 PM PST 24
Finished Feb 04 02:10:44 PM PST 24
Peak memory 287072 kb
Host smart-4f4b3c74-7cdb-4d17-8eb7-2f4c93fb6940
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461890560 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_entropy.1461890560
Directory /workspace/43.alert_handler_entropy/latest

Test location /workspace/coverage/default/43.alert_handler_esc_alert_accum.1103374599
Short name T625
Test name
Test status
Simulation time 7666017516 ps
CPU time 116.2 seconds
Started Feb 04 01:22:23 PM PST 24
Finished Feb 04 01:24:20 PM PST 24
Peak memory 256780 kb
Host smart-6585aefd-9314-499a-b3db-d7ca655d86f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11033
74599 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_alert_accum.1103374599
Directory /workspace/43.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/43.alert_handler_esc_intr_timeout.1921463823
Short name T368
Test name
Test status
Simulation time 161956616 ps
CPU time 12.47 seconds
Started Feb 04 01:22:22 PM PST 24
Finished Feb 04 01:22:36 PM PST 24
Peak memory 254884 kb
Host smart-8bb40ee9-3286-4fda-b8a3-595f601260cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19214
63823 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_intr_timeout.1921463823
Directory /workspace/43.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_lpg.3793149883
Short name T324
Test name
Test status
Simulation time 101767226230 ps
CPU time 982.28 seconds
Started Feb 04 01:22:23 PM PST 24
Finished Feb 04 01:38:46 PM PST 24
Peak memory 272736 kb
Host smart-138b989b-fa8b-4477-b21f-1a8530642787
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793149883 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg.3793149883
Directory /workspace/43.alert_handler_lpg/latest

Test location /workspace/coverage/default/43.alert_handler_lpg_stub_clk.3250305372
Short name T489
Test name
Test status
Simulation time 31173531372 ps
CPU time 1260.26 seconds
Started Feb 04 01:22:24 PM PST 24
Finished Feb 04 01:43:26 PM PST 24
Peak memory 288720 kb
Host smart-d5b49506-7f26-44bd-beae-bf040128d307
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250305372 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg_stub_clk.3250305372
Directory /workspace/43.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/43.alert_handler_ping_timeout.1616935081
Short name T262
Test name
Test status
Simulation time 24780609212 ps
CPU time 340.95 seconds
Started Feb 04 01:22:23 PM PST 24
Finished Feb 04 01:28:05 PM PST 24
Peak memory 247452 kb
Host smart-606c1169-e367-4b8c-bc18-07d474193d7b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616935081 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_ping_timeout.1616935081
Directory /workspace/43.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_random_alerts.2942364284
Short name T723
Test name
Test status
Simulation time 48884210 ps
CPU time 4.35 seconds
Started Feb 04 01:22:24 PM PST 24
Finished Feb 04 01:22:29 PM PST 24
Peak memory 240164 kb
Host smart-82c3fec9-7380-4d3f-bd26-f2bccb31b9a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29423
64284 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_alerts.2942364284
Directory /workspace/43.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/43.alert_handler_random_classes.4149233409
Short name T108
Test name
Test status
Simulation time 735829372 ps
CPU time 53.12 seconds
Started Feb 04 01:22:30 PM PST 24
Finished Feb 04 01:23:25 PM PST 24
Peak memory 255052 kb
Host smart-2cc01b92-fa06-4b02-b5ab-dbd01b0c7ab5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41492
33409 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_classes.4149233409
Directory /workspace/43.alert_handler_random_classes/latest

Test location /workspace/coverage/default/43.alert_handler_sig_int_fail.3396972412
Short name T343
Test name
Test status
Simulation time 55782986 ps
CPU time 2.82 seconds
Started Feb 04 01:22:30 PM PST 24
Finished Feb 04 01:22:34 PM PST 24
Peak memory 238348 kb
Host smart-fc713804-942d-4b86-8f01-a9ae9cd17ae8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33969
72412 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_sig_int_fail.3396972412
Directory /workspace/43.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/43.alert_handler_smoke.2905116897
Short name T581
Test name
Test status
Simulation time 2115369767 ps
CPU time 24.05 seconds
Started Feb 04 01:22:30 PM PST 24
Finished Feb 04 01:22:55 PM PST 24
Peak memory 248504 kb
Host smart-0f1aae8d-6ae8-4a0b-9b62-f8df0e011029
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29051
16897 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_smoke.2905116897
Directory /workspace/43.alert_handler_smoke/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all.2645849723
Short name T416
Test name
Test status
Simulation time 67590154990 ps
CPU time 1679.02 seconds
Started Feb 04 01:22:22 PM PST 24
Finished Feb 04 01:50:22 PM PST 24
Peak memory 272128 kb
Host smart-218dcb6d-d972-42c2-8679-f2c96ce77221
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645849723 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_ha
ndler_stress_all.2645849723
Directory /workspace/43.alert_handler_stress_all/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all_with_rand_reset.736015389
Short name T236
Test name
Test status
Simulation time 71908394081 ps
CPU time 4374.9 seconds
Started Feb 04 01:22:30 PM PST 24
Finished Feb 04 02:35:26 PM PST 24
Peak memory 305404 kb
Host smart-17258d31-470b-4208-9151-7a9b47c84b1c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736015389 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 43.alert_handler_stress_all_with_rand_reset.736015389
Directory /workspace/43.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.alert_handler_entropy.3784797308
Short name T635
Test name
Test status
Simulation time 165807534378 ps
CPU time 2412.74 seconds
Started Feb 04 01:22:31 PM PST 24
Finished Feb 04 02:02:45 PM PST 24
Peak memory 281124 kb
Host smart-1358d51a-5763-4478-abf6-96ed01944be9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3784797308 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_entropy.3784797308
Directory /workspace/44.alert_handler_entropy/latest

Test location /workspace/coverage/default/44.alert_handler_esc_alert_accum.1830788670
Short name T454
Test name
Test status
Simulation time 5186051875 ps
CPU time 36.74 seconds
Started Feb 04 01:22:26 PM PST 24
Finished Feb 04 01:23:04 PM PST 24
Peak memory 248140 kb
Host smart-7d38a525-4817-4518-a7a3-3a55ed1753cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18307
88670 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_alert_accum.1830788670
Directory /workspace/44.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/44.alert_handler_esc_intr_timeout.3936140644
Short name T716
Test name
Test status
Simulation time 189836713 ps
CPU time 10.51 seconds
Started Feb 04 01:22:27 PM PST 24
Finished Feb 04 01:22:38 PM PST 24
Peak memory 254096 kb
Host smart-e0b02640-1c03-4358-ad5a-5e8d3446d6b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39361
40644 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_intr_timeout.3936140644
Directory /workspace/44.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_lpg.3931569048
Short name T318
Test name
Test status
Simulation time 34615925288 ps
CPU time 1875.04 seconds
Started Feb 04 01:22:31 PM PST 24
Finished Feb 04 01:53:47 PM PST 24
Peak memory 272292 kb
Host smart-2b1aad48-1c94-4877-93dd-31c5ad1bf8bf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3931569048 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg.3931569048
Directory /workspace/44.alert_handler_lpg/latest

Test location /workspace/coverage/default/44.alert_handler_lpg_stub_clk.2324688502
Short name T560
Test name
Test status
Simulation time 15373369117 ps
CPU time 1174.61 seconds
Started Feb 04 01:22:21 PM PST 24
Finished Feb 04 01:41:57 PM PST 24
Peak memory 286124 kb
Host smart-22cf252f-7833-4151-be68-b7002d4ad8ac
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324688502 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg_stub_clk.2324688502
Directory /workspace/44.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/44.alert_handler_ping_timeout.4149647374
Short name T9
Test name
Test status
Simulation time 11646727484 ps
CPU time 241.78 seconds
Started Feb 04 01:22:24 PM PST 24
Finished Feb 04 01:26:26 PM PST 24
Peak memory 246872 kb
Host smart-58150e3b-9219-4731-8faa-f3d790dfca12
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149647374 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_ping_timeout.4149647374
Directory /workspace/44.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_random_alerts.2712494794
Short name T600
Test name
Test status
Simulation time 98827381 ps
CPU time 8.27 seconds
Started Feb 04 01:22:21 PM PST 24
Finished Feb 04 01:22:30 PM PST 24
Peak memory 248448 kb
Host smart-357d3d54-83dd-442d-9495-8f35059174c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27124
94794 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_alerts.2712494794
Directory /workspace/44.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/44.alert_handler_random_classes.916546483
Short name T47
Test name
Test status
Simulation time 94299530 ps
CPU time 7.17 seconds
Started Feb 04 01:22:32 PM PST 24
Finished Feb 04 01:22:40 PM PST 24
Peak memory 252192 kb
Host smart-c0ac4b28-2854-4f4c-a8b5-c244e262ce0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91654
6483 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_classes.916546483
Directory /workspace/44.alert_handler_random_classes/latest

Test location /workspace/coverage/default/44.alert_handler_sig_int_fail.1911733787
Short name T543
Test name
Test status
Simulation time 52223758 ps
CPU time 4.25 seconds
Started Feb 04 01:22:23 PM PST 24
Finished Feb 04 01:22:28 PM PST 24
Peak memory 238504 kb
Host smart-ef87245c-ed5f-45c5-b806-0010d2a2faab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19117
33787 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_sig_int_fail.1911733787
Directory /workspace/44.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/44.alert_handler_smoke.71632936
Short name T493
Test name
Test status
Simulation time 683237972 ps
CPU time 40.43 seconds
Started Feb 04 01:22:23 PM PST 24
Finished Feb 04 01:23:04 PM PST 24
Peak memory 248444 kb
Host smart-557c5f82-c6d4-412a-96f9-1a8b9e7e5264
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71632
936 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_smoke.71632936
Directory /workspace/44.alert_handler_smoke/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all.2469824811
Short name T92
Test name
Test status
Simulation time 28656079514 ps
CPU time 1177.83 seconds
Started Feb 04 01:22:30 PM PST 24
Finished Feb 04 01:42:09 PM PST 24
Peak memory 281400 kb
Host smart-46e93294-6441-4e04-9ce5-10183963933e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469824811 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_ha
ndler_stress_all.2469824811
Directory /workspace/44.alert_handler_stress_all/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all_with_rand_reset.2946058916
Short name T584
Test name
Test status
Simulation time 19241666488 ps
CPU time 1372.36 seconds
Started Feb 04 01:22:26 PM PST 24
Finished Feb 04 01:45:20 PM PST 24
Peak memory 270472 kb
Host smart-0a9d4a8e-b5a1-4c0c-8026-b0949b40b738
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946058916 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 44.alert_handler_stress_all_with_rand_reset.2946058916
Directory /workspace/44.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.alert_handler_entropy.897070219
Short name T682
Test name
Test status
Simulation time 68622676373 ps
CPU time 1929.61 seconds
Started Feb 04 01:22:36 PM PST 24
Finished Feb 04 01:54:48 PM PST 24
Peak memory 272676 kb
Host smart-b73b06ce-4cce-4cca-beaa-bce418a3c07b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897070219 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_entropy.897070219
Directory /workspace/45.alert_handler_entropy/latest

Test location /workspace/coverage/default/45.alert_handler_esc_alert_accum.1026625810
Short name T371
Test name
Test status
Simulation time 7480372129 ps
CPU time 111.94 seconds
Started Feb 04 01:22:37 PM PST 24
Finished Feb 04 01:24:31 PM PST 24
Peak memory 256244 kb
Host smart-1323647a-7f99-400a-a4cb-3443fc3f2782
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10266
25810 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_alert_accum.1026625810
Directory /workspace/45.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/45.alert_handler_esc_intr_timeout.2282337777
Short name T361
Test name
Test status
Simulation time 1688867547 ps
CPU time 58.84 seconds
Started Feb 04 01:22:39 PM PST 24
Finished Feb 04 01:23:45 PM PST 24
Peak memory 254948 kb
Host smart-077358e5-a83d-4fc9-9318-9176fae46656
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22823
37777 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_intr_timeout.2282337777
Directory /workspace/45.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_lpg.2946547692
Short name T495
Test name
Test status
Simulation time 66897463956 ps
CPU time 1329.11 seconds
Started Feb 04 01:22:36 PM PST 24
Finished Feb 04 01:44:48 PM PST 24
Peak memory 284024 kb
Host smart-50e3aeac-0b5b-4b31-b5b7-2e87070ebf4e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946547692 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg.2946547692
Directory /workspace/45.alert_handler_lpg/latest

Test location /workspace/coverage/default/45.alert_handler_lpg_stub_clk.1208340377
Short name T705
Test name
Test status
Simulation time 29279808301 ps
CPU time 1760.48 seconds
Started Feb 04 01:22:37 PM PST 24
Finished Feb 04 01:52:00 PM PST 24
Peak memory 281896 kb
Host smart-9e8a6272-309a-4f84-8f06-d4bfe779c779
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1208340377 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg_stub_clk.1208340377
Directory /workspace/45.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/45.alert_handler_ping_timeout.1670468667
Short name T637
Test name
Test status
Simulation time 3762700059 ps
CPU time 154.19 seconds
Started Feb 04 01:22:38 PM PST 24
Finished Feb 04 01:25:14 PM PST 24
Peak memory 246416 kb
Host smart-43a18c83-b6f6-479e-9e91-7dcc8aba199f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670468667 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_ping_timeout.1670468667
Directory /workspace/45.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_random_alerts.4269198365
Short name T685
Test name
Test status
Simulation time 293916027 ps
CPU time 29.85 seconds
Started Feb 04 01:22:30 PM PST 24
Finished Feb 04 01:23:01 PM PST 24
Peak memory 248460 kb
Host smart-9a52a320-bb4e-4c84-898c-80aed45d597c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42691
98365 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_alerts.4269198365
Directory /workspace/45.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/45.alert_handler_random_classes.1921455682
Short name T442
Test name
Test status
Simulation time 607491524 ps
CPU time 11.59 seconds
Started Feb 04 01:22:30 PM PST 24
Finished Feb 04 01:22:42 PM PST 24
Peak memory 251628 kb
Host smart-236fe8fd-b8fa-436f-a455-7e81865a27b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19214
55682 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_classes.1921455682
Directory /workspace/45.alert_handler_random_classes/latest

Test location /workspace/coverage/default/45.alert_handler_sig_int_fail.3684496293
Short name T245
Test name
Test status
Simulation time 3046076233 ps
CPU time 41.14 seconds
Started Feb 04 01:22:41 PM PST 24
Finished Feb 04 01:23:28 PM PST 24
Peak memory 255236 kb
Host smart-b23e1114-f44a-4356-ae82-8a37aec5709f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36844
96293 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_sig_int_fail.3684496293
Directory /workspace/45.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/45.alert_handler_smoke.149556089
Short name T44
Test name
Test status
Simulation time 608510871 ps
CPU time 16.06 seconds
Started Feb 04 01:22:31 PM PST 24
Finished Feb 04 01:22:48 PM PST 24
Peak memory 248316 kb
Host smart-331bfb88-1fc9-4c34-9300-43392ab420a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14955
6089 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_smoke.149556089
Directory /workspace/45.alert_handler_smoke/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all_with_rand_reset.1849484589
Short name T288
Test name
Test status
Simulation time 112259285670 ps
CPU time 2497.63 seconds
Started Feb 04 01:22:37 PM PST 24
Finished Feb 04 02:04:17 PM PST 24
Peak memory 302240 kb
Host smart-113e3975-6eb4-4dc4-b6ab-882be6e62d10
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849484589 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 45.alert_handler_stress_all_with_rand_reset.1849484589
Directory /workspace/45.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.alert_handler_entropy.797175153
Short name T286
Test name
Test status
Simulation time 170201730582 ps
CPU time 956.07 seconds
Started Feb 04 01:22:42 PM PST 24
Finished Feb 04 01:38:43 PM PST 24
Peak memory 272596 kb
Host smart-9f392ada-95c6-4c84-ab20-4c40b09edd0a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797175153 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_entropy.797175153
Directory /workspace/46.alert_handler_entropy/latest

Test location /workspace/coverage/default/46.alert_handler_esc_alert_accum.1191370387
Short name T526
Test name
Test status
Simulation time 1844339548 ps
CPU time 143.34 seconds
Started Feb 04 01:22:41 PM PST 24
Finished Feb 04 01:25:10 PM PST 24
Peak memory 255624 kb
Host smart-e78f19bd-a76c-4dd0-bc2c-4adad9956d70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11913
70387 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_alert_accum.1191370387
Directory /workspace/46.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/46.alert_handler_esc_intr_timeout.3107483915
Short name T18
Test name
Test status
Simulation time 807385434 ps
CPU time 52.26 seconds
Started Feb 04 01:22:36 PM PST 24
Finished Feb 04 01:23:31 PM PST 24
Peak memory 254896 kb
Host smart-9900b99d-4763-4a3c-a2c4-b6fcf776cb20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31074
83915 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_intr_timeout.3107483915
Directory /workspace/46.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_lpg.3852384952
Short name T511
Test name
Test status
Simulation time 27704526380 ps
CPU time 1487.08 seconds
Started Feb 04 01:22:38 PM PST 24
Finished Feb 04 01:47:32 PM PST 24
Peak memory 272804 kb
Host smart-03bc6ef4-ff3d-4276-a5f6-a6e20cbc3b31
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852384952 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg.3852384952
Directory /workspace/46.alert_handler_lpg/latest

Test location /workspace/coverage/default/46.alert_handler_lpg_stub_clk.2566453467
Short name T448
Test name
Test status
Simulation time 100703737349 ps
CPU time 1160.73 seconds
Started Feb 04 01:22:34 PM PST 24
Finished Feb 04 01:41:57 PM PST 24
Peak memory 288432 kb
Host smart-0b525036-48b8-4186-b6c5-ac839a45ef9b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566453467 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg_stub_clk.2566453467
Directory /workspace/46.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/46.alert_handler_ping_timeout.2591304140
Short name T739
Test name
Test status
Simulation time 18735879895 ps
CPU time 219.32 seconds
Started Feb 04 01:22:39 PM PST 24
Finished Feb 04 01:26:25 PM PST 24
Peak memory 247460 kb
Host smart-066063ad-30d4-444a-8019-de7cbf85a7b6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591304140 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_ping_timeout.2591304140
Directory /workspace/46.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_random_alerts.333080439
Short name T436
Test name
Test status
Simulation time 628831476 ps
CPU time 15.45 seconds
Started Feb 04 01:22:38 PM PST 24
Finished Feb 04 01:22:59 PM PST 24
Peak memory 248448 kb
Host smart-75ff4fab-8e08-4ddd-b832-a32d62010c03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33308
0439 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_alerts.333080439
Directory /workspace/46.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/46.alert_handler_random_classes.2130434615
Short name T604
Test name
Test status
Simulation time 3436038980 ps
CPU time 19.22 seconds
Started Feb 04 01:22:38 PM PST 24
Finished Feb 04 01:22:59 PM PST 24
Peak memory 247976 kb
Host smart-b672f422-e533-4d1f-a846-34407b202d6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21304
34615 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_classes.2130434615
Directory /workspace/46.alert_handler_random_classes/latest

Test location /workspace/coverage/default/46.alert_handler_sig_int_fail.3707991294
Short name T490
Test name
Test status
Simulation time 336754231 ps
CPU time 11.66 seconds
Started Feb 04 01:22:35 PM PST 24
Finished Feb 04 01:22:49 PM PST 24
Peak memory 252100 kb
Host smart-1feea450-aa3d-4b57-a3c5-3327342a76dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37079
91294 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_sig_int_fail.3707991294
Directory /workspace/46.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/46.alert_handler_smoke.3934565331
Short name T567
Test name
Test status
Simulation time 432255947 ps
CPU time 33.54 seconds
Started Feb 04 01:22:38 PM PST 24
Finished Feb 04 01:23:13 PM PST 24
Peak memory 248492 kb
Host smart-574df284-1892-4ac3-8cb0-b7ef4c9da680
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39345
65331 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_smoke.3934565331
Directory /workspace/46.alert_handler_smoke/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all.1789747243
Short name T666
Test name
Test status
Simulation time 11062112360 ps
CPU time 224.23 seconds
Started Feb 04 01:22:39 PM PST 24
Finished Feb 04 01:26:30 PM PST 24
Peak memory 256788 kb
Host smart-0c7be8e5-ad7b-4582-9508-e0ee728559a2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789747243 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_ha
ndler_stress_all.1789747243
Directory /workspace/46.alert_handler_stress_all/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all_with_rand_reset.3470503957
Short name T91
Test name
Test status
Simulation time 96156046207 ps
CPU time 4471.05 seconds
Started Feb 04 01:22:37 PM PST 24
Finished Feb 04 02:37:11 PM PST 24
Peak memory 338004 kb
Host smart-d2b9f9a3-44a1-431d-822c-7defbcbac7aa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470503957 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 46.alert_handler_stress_all_with_rand_reset.3470503957
Directory /workspace/46.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.alert_handler_entropy.1878863241
Short name T476
Test name
Test status
Simulation time 42525386439 ps
CPU time 2424.25 seconds
Started Feb 04 01:22:33 PM PST 24
Finished Feb 04 02:02:59 PM PST 24
Peak memory 282912 kb
Host smart-725345fb-2fee-488b-bda2-0e18a435b368
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878863241 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_entropy.1878863241
Directory /workspace/47.alert_handler_entropy/latest

Test location /workspace/coverage/default/47.alert_handler_esc_alert_accum.3905518655
Short name T608
Test name
Test status
Simulation time 1683675278 ps
CPU time 140.14 seconds
Started Feb 04 01:22:39 PM PST 24
Finished Feb 04 01:25:06 PM PST 24
Peak memory 255884 kb
Host smart-2de23b82-5f50-46dc-b9e1-dc44f299407c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39055
18655 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_alert_accum.3905518655
Directory /workspace/47.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/47.alert_handler_esc_intr_timeout.1884657932
Short name T450
Test name
Test status
Simulation time 374505850 ps
CPU time 26.7 seconds
Started Feb 04 01:22:38 PM PST 24
Finished Feb 04 01:23:07 PM PST 24
Peak memory 254840 kb
Host smart-26417f39-c039-492b-a3d4-9b2655675185
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18846
57932 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_intr_timeout.1884657932
Directory /workspace/47.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_lpg.3361420624
Short name T322
Test name
Test status
Simulation time 39956636455 ps
CPU time 1427.75 seconds
Started Feb 04 01:22:35 PM PST 24
Finished Feb 04 01:46:25 PM PST 24
Peak memory 272836 kb
Host smart-4bbbbb7c-953e-49cf-99d8-99f23f76cec7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361420624 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg.3361420624
Directory /workspace/47.alert_handler_lpg/latest

Test location /workspace/coverage/default/47.alert_handler_lpg_stub_clk.3000442667
Short name T293
Test name
Test status
Simulation time 34055633981 ps
CPU time 1930.37 seconds
Started Feb 04 01:22:39 PM PST 24
Finished Feb 04 01:54:56 PM PST 24
Peak memory 272224 kb
Host smart-a0a8b142-4597-4e00-ad27-0b216a16f21c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000442667 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg_stub_clk.3000442667
Directory /workspace/47.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/47.alert_handler_random_alerts.3253339615
Short name T374
Test name
Test status
Simulation time 1069675693 ps
CPU time 56.41 seconds
Started Feb 04 01:22:45 PM PST 24
Finished Feb 04 01:23:43 PM PST 24
Peak memory 256632 kb
Host smart-04f92126-4748-4299-9516-4b71ff5bbd8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32533
39615 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_alerts.3253339615
Directory /workspace/47.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/47.alert_handler_random_classes.2133739723
Short name T391
Test name
Test status
Simulation time 957932095 ps
CPU time 23.51 seconds
Started Feb 04 01:22:39 PM PST 24
Finished Feb 04 01:23:09 PM PST 24
Peak memory 248444 kb
Host smart-98333c8a-7fa2-4405-a5ea-b39d35b5790d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21337
39723 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_classes.2133739723
Directory /workspace/47.alert_handler_random_classes/latest

Test location /workspace/coverage/default/47.alert_handler_sig_int_fail.1015746082
Short name T89
Test name
Test status
Simulation time 758048933 ps
CPU time 24.39 seconds
Started Feb 04 01:22:38 PM PST 24
Finished Feb 04 01:23:08 PM PST 24
Peak memory 246676 kb
Host smart-c5ab4597-aeb1-403f-b1fb-c48003941194
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10157
46082 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_sig_int_fail.1015746082
Directory /workspace/47.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/47.alert_handler_smoke.3369337965
Short name T345
Test name
Test status
Simulation time 381844223 ps
CPU time 20.09 seconds
Started Feb 04 01:22:39 PM PST 24
Finished Feb 04 01:23:06 PM PST 24
Peak memory 248472 kb
Host smart-f5d2c849-a9b7-43db-ad4a-55cf4a6753f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33693
37965 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_smoke.3369337965
Directory /workspace/47.alert_handler_smoke/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all_with_rand_reset.1855899902
Short name T575
Test name
Test status
Simulation time 181440023736 ps
CPU time 9104.66 seconds
Started Feb 04 01:22:39 PM PST 24
Finished Feb 04 03:54:32 PM PST 24
Peak memory 371080 kb
Host smart-6468791f-2181-4028-ae19-d5f0bfc37b28
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855899902 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 47.alert_handler_stress_all_with_rand_reset.1855899902
Directory /workspace/47.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.alert_handler_entropy.3537085057
Short name T287
Test name
Test status
Simulation time 29838805994 ps
CPU time 1757.36 seconds
Started Feb 04 01:22:37 PM PST 24
Finished Feb 04 01:51:57 PM PST 24
Peak memory 272836 kb
Host smart-281132bf-619d-4c05-90ec-9628066e592b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537085057 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_entropy.3537085057
Directory /workspace/48.alert_handler_entropy/latest

Test location /workspace/coverage/default/48.alert_handler_esc_alert_accum.497130723
Short name T695
Test name
Test status
Simulation time 8873958378 ps
CPU time 116.64 seconds
Started Feb 04 01:22:39 PM PST 24
Finished Feb 04 01:24:42 PM PST 24
Peak memory 248416 kb
Host smart-af6b3f7b-7d79-4b85-b63f-a0d40b5d701e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49713
0723 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_alert_accum.497130723
Directory /workspace/48.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/48.alert_handler_esc_intr_timeout.852498377
Short name T711
Test name
Test status
Simulation time 374503499 ps
CPU time 23 seconds
Started Feb 04 01:22:38 PM PST 24
Finished Feb 04 01:23:03 PM PST 24
Peak memory 248156 kb
Host smart-4a2a1cbd-933f-4ccc-acc7-c580075d35ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85249
8377 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_intr_timeout.852498377
Directory /workspace/48.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_lpg.1620505114
Short name T698
Test name
Test status
Simulation time 26485910607 ps
CPU time 1207.74 seconds
Started Feb 04 01:22:38 PM PST 24
Finished Feb 04 01:42:47 PM PST 24
Peak memory 273140 kb
Host smart-6a691a32-cdda-4116-aeed-95b149784584
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620505114 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg.1620505114
Directory /workspace/48.alert_handler_lpg/latest

Test location /workspace/coverage/default/48.alert_handler_lpg_stub_clk.3511099339
Short name T451
Test name
Test status
Simulation time 41637223531 ps
CPU time 2407.23 seconds
Started Feb 04 01:22:55 PM PST 24
Finished Feb 04 02:03:03 PM PST 24
Peak memory 283308 kb
Host smart-2d060727-459a-471d-ae69-18d452ca1795
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511099339 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg_stub_clk.3511099339
Directory /workspace/48.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/48.alert_handler_ping_timeout.507709147
Short name T275
Test name
Test status
Simulation time 4534318171 ps
CPU time 180.87 seconds
Started Feb 04 01:22:38 PM PST 24
Finished Feb 04 01:25:41 PM PST 24
Peak memory 246492 kb
Host smart-f86e22ad-4c6a-497d-b709-559c48849bf3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507709147 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_ping_timeout.507709147
Directory /workspace/48.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_random_alerts.1103923793
Short name T479
Test name
Test status
Simulation time 1599297736 ps
CPU time 15.32 seconds
Started Feb 04 01:22:45 PM PST 24
Finished Feb 04 01:23:02 PM PST 24
Peak memory 248456 kb
Host smart-519701f1-0c3a-4cce-b8e0-4cf199877c95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11039
23793 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_alerts.1103923793
Directory /workspace/48.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/48.alert_handler_random_classes.2048340643
Short name T49
Test name
Test status
Simulation time 2356395637 ps
CPU time 43.62 seconds
Started Feb 04 01:22:38 PM PST 24
Finished Feb 04 01:23:23 PM PST 24
Peak memory 255348 kb
Host smart-8aa755b4-7b79-4e32-b714-ee455f7b069d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20483
40643 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_classes.2048340643
Directory /workspace/48.alert_handler_random_classes/latest

Test location /workspace/coverage/default/48.alert_handler_sig_int_fail.1293439414
Short name T404
Test name
Test status
Simulation time 911864509 ps
CPU time 22.06 seconds
Started Feb 04 01:22:37 PM PST 24
Finished Feb 04 01:23:01 PM PST 24
Peak memory 255208 kb
Host smart-0837dd42-87ca-43cb-b9e9-aa00e5310795
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12934
39414 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_sig_int_fail.1293439414
Directory /workspace/48.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/48.alert_handler_smoke.434970572
Short name T715
Test name
Test status
Simulation time 3043984180 ps
CPU time 49.99 seconds
Started Feb 04 01:22:38 PM PST 24
Finished Feb 04 01:23:30 PM PST 24
Peak memory 248544 kb
Host smart-bda04578-c11e-4fc9-97d8-ce03f6509772
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43497
0572 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_smoke.434970572
Directory /workspace/48.alert_handler_smoke/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all.3798757769
Short name T518
Test name
Test status
Simulation time 23542814740 ps
CPU time 2181.12 seconds
Started Feb 04 01:22:55 PM PST 24
Finished Feb 04 01:59:17 PM PST 24
Peak memory 297336 kb
Host smart-8c4974f3-aa34-4eeb-9d78-f799cdbc4df9
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798757769 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_ha
ndler_stress_all.3798757769
Directory /workspace/48.alert_handler_stress_all/latest

Test location /workspace/coverage/default/49.alert_handler_entropy.509068182
Short name T640
Test name
Test status
Simulation time 33604660542 ps
CPU time 1848.78 seconds
Started Feb 04 01:22:59 PM PST 24
Finished Feb 04 01:53:50 PM PST 24
Peak memory 288752 kb
Host smart-e4626608-6a48-4222-95cc-785987cbc0d1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509068182 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_entropy.509068182
Directory /workspace/49.alert_handler_entropy/latest

Test location /workspace/coverage/default/49.alert_handler_esc_alert_accum.568429486
Short name T207
Test name
Test status
Simulation time 558792437 ps
CPU time 53.06 seconds
Started Feb 04 01:22:58 PM PST 24
Finished Feb 04 01:23:53 PM PST 24
Peak memory 247760 kb
Host smart-8755771d-59f2-4517-a57b-bc0b3626a87b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56842
9486 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_alert_accum.568429486
Directory /workspace/49.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/49.alert_handler_esc_intr_timeout.2036096802
Short name T579
Test name
Test status
Simulation time 4544978812 ps
CPU time 26.95 seconds
Started Feb 04 01:22:56 PM PST 24
Finished Feb 04 01:23:26 PM PST 24
Peak memory 254896 kb
Host smart-080218f6-01b8-408c-a06f-26eb7d3ba022
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20360
96802 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_intr_timeout.2036096802
Directory /workspace/49.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_lpg.1751292690
Short name T321
Test name
Test status
Simulation time 24636890497 ps
CPU time 1461.99 seconds
Started Feb 04 01:22:55 PM PST 24
Finished Feb 04 01:47:18 PM PST 24
Peak memory 267364 kb
Host smart-c745d611-8fa2-4b01-8bbb-c9749615b13e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751292690 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg.1751292690
Directory /workspace/49.alert_handler_lpg/latest

Test location /workspace/coverage/default/49.alert_handler_lpg_stub_clk.2826267831
Short name T113
Test name
Test status
Simulation time 126522888890 ps
CPU time 1878.2 seconds
Started Feb 04 01:23:00 PM PST 24
Finished Feb 04 01:54:20 PM PST 24
Peak memory 272612 kb
Host smart-87776193-624b-4cae-b75e-4b58d0b6f7d5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826267831 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg_stub_clk.2826267831
Directory /workspace/49.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/49.alert_handler_ping_timeout.1714173757
Short name T671
Test name
Test status
Simulation time 73712958210 ps
CPU time 289.75 seconds
Started Feb 04 01:23:00 PM PST 24
Finished Feb 04 01:27:52 PM PST 24
Peak memory 247280 kb
Host smart-9037ca7e-915b-4390-a8ad-4fcee417cc15
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1714173757 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_ping_timeout.1714173757
Directory /workspace/49.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_random_alerts.3504417203
Short name T714
Test name
Test status
Simulation time 624403301 ps
CPU time 24.84 seconds
Started Feb 04 01:22:58 PM PST 24
Finished Feb 04 01:23:24 PM PST 24
Peak memory 248464 kb
Host smart-2aaa4946-3c44-48f0-acfc-b51db148d3af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35044
17203 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_alerts.3504417203
Directory /workspace/49.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/49.alert_handler_random_classes.3043934999
Short name T577
Test name
Test status
Simulation time 1081612100 ps
CPU time 35.43 seconds
Started Feb 04 01:22:53 PM PST 24
Finished Feb 04 01:23:30 PM PST 24
Peak memory 255068 kb
Host smart-d75f6871-2e4f-4c6b-9046-d2eb76b1624d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30439
34999 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_classes.3043934999
Directory /workspace/49.alert_handler_random_classes/latest

Test location /workspace/coverage/default/49.alert_handler_sig_int_fail.3914819609
Short name T631
Test name
Test status
Simulation time 1268186496 ps
CPU time 41.34 seconds
Started Feb 04 01:22:58 PM PST 24
Finished Feb 04 01:23:42 PM PST 24
Peak memory 247020 kb
Host smart-ea794486-c907-4817-895d-21f876eaac80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39148
19609 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_sig_int_fail.3914819609
Directory /workspace/49.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/49.alert_handler_smoke.530700073
Short name T456
Test name
Test status
Simulation time 571908086 ps
CPU time 35.37 seconds
Started Feb 04 01:22:56 PM PST 24
Finished Feb 04 01:23:34 PM PST 24
Peak memory 248452 kb
Host smart-c8169d12-71fd-4143-8355-080d26cad6d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53070
0073 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_smoke.530700073
Directory /workspace/49.alert_handler_smoke/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all.787155701
Short name T478
Test name
Test status
Simulation time 1315327750 ps
CPU time 71.79 seconds
Started Feb 04 01:23:01 PM PST 24
Finished Feb 04 01:24:14 PM PST 24
Peak memory 255856 kb
Host smart-2ad25475-ab70-4e14-91d8-82bb3bff3bf6
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787155701 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_han
dler_stress_all.787155701
Directory /workspace/49.alert_handler_stress_all/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all_with_rand_reset.1606957694
Short name T615
Test name
Test status
Simulation time 21828286452 ps
CPU time 2353.85 seconds
Started Feb 04 01:22:58 PM PST 24
Finished Feb 04 02:02:14 PM PST 24
Peak memory 322444 kb
Host smart-0326182b-8d23-44a6-9434-85d1780e5547
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606957694 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 49.alert_handler_stress_all_with_rand_reset.1606957694
Directory /workspace/49.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.alert_handler_alert_accum_saturation.2842112031
Short name T201
Test name
Test status
Simulation time 32313811 ps
CPU time 3 seconds
Started Feb 04 01:20:05 PM PST 24
Finished Feb 04 01:20:13 PM PST 24
Peak memory 248640 kb
Host smart-75c6f14b-2d7d-49cc-882b-3805edc2c53d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2842112031 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_alert_accum_saturation.2842112031
Directory /workspace/5.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/5.alert_handler_entropy.3218591857
Short name T734
Test name
Test status
Simulation time 51773653160 ps
CPU time 3105.32 seconds
Started Feb 04 01:19:56 PM PST 24
Finished Feb 04 02:11:43 PM PST 24
Peak memory 287688 kb
Host smart-6e62fa90-4c80-4130-afcb-0c6f58503494
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218591857 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy.3218591857
Directory /workspace/5.alert_handler_entropy/latest

Test location /workspace/coverage/default/5.alert_handler_entropy_stress.1139463089
Short name T624
Test name
Test status
Simulation time 5097413479 ps
CPU time 53.6 seconds
Started Feb 04 01:20:04 PM PST 24
Finished Feb 04 01:21:03 PM PST 24
Peak memory 240376 kb
Host smart-e61b46cb-0bb8-405a-80b6-1b824bdef337
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1139463089 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy_stress.1139463089
Directory /workspace/5.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/5.alert_handler_esc_alert_accum.2652362788
Short name T403
Test name
Test status
Simulation time 3849856833 ps
CPU time 49.17 seconds
Started Feb 04 01:19:58 PM PST 24
Finished Feb 04 01:20:48 PM PST 24
Peak memory 255848 kb
Host smart-5530a6a8-d19f-40c6-90a1-83299c18899c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26523
62788 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_alert_accum.2652362788
Directory /workspace/5.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/5.alert_handler_esc_intr_timeout.1379743050
Short name T398
Test name
Test status
Simulation time 293658654 ps
CPU time 15.52 seconds
Started Feb 04 01:19:55 PM PST 24
Finished Feb 04 01:20:12 PM PST 24
Peak memory 254884 kb
Host smart-1bacdf7e-9768-4179-a1f2-7ecd78cf0bed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13797
43050 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_intr_timeout.1379743050
Directory /workspace/5.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_lpg.1063391451
Short name T309
Test name
Test status
Simulation time 81269462710 ps
CPU time 2067.97 seconds
Started Feb 04 01:20:04 PM PST 24
Finished Feb 04 01:54:37 PM PST 24
Peak memory 271236 kb
Host smart-9ec0addb-10cd-4548-82b5-9e7247e534d5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1063391451 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg.1063391451
Directory /workspace/5.alert_handler_lpg/latest

Test location /workspace/coverage/default/5.alert_handler_lpg_stub_clk.2846741394
Short name T535
Test name
Test status
Simulation time 7604994615 ps
CPU time 706.03 seconds
Started Feb 04 01:20:06 PM PST 24
Finished Feb 04 01:31:57 PM PST 24
Peak memory 266036 kb
Host smart-8322a2e8-e91f-445e-a427-f27b9690a825
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846741394 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg_stub_clk.2846741394
Directory /workspace/5.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/5.alert_handler_ping_timeout.204317920
Short name T254
Test name
Test status
Simulation time 60730668987 ps
CPU time 704.73 seconds
Started Feb 04 01:19:52 PM PST 24
Finished Feb 04 01:31:39 PM PST 24
Peak memory 246456 kb
Host smart-bfb2e854-54cf-4b09-b7ca-27decd00d6ed
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204317920 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_ping_timeout.204317920
Directory /workspace/5.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_random_alerts.1972366308
Short name T367
Test name
Test status
Simulation time 4246588836 ps
CPU time 32.94 seconds
Started Feb 04 01:19:52 PM PST 24
Finished Feb 04 01:20:27 PM PST 24
Peak memory 248628 kb
Host smart-5724db5a-a793-4774-a039-6b8ef0770a72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19723
66308 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_alerts.1972366308
Directory /workspace/5.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/5.alert_handler_random_classes.3909659273
Short name T700
Test name
Test status
Simulation time 4222162120 ps
CPU time 19.94 seconds
Started Feb 04 01:19:52 PM PST 24
Finished Feb 04 01:20:13 PM PST 24
Peak memory 254620 kb
Host smart-9cde9ab9-0f3c-4183-8517-b9a71466f966
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39096
59273 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_classes.3909659273
Directory /workspace/5.alert_handler_random_classes/latest

Test location /workspace/coverage/default/5.alert_handler_sig_int_fail.3674318581
Short name T672
Test name
Test status
Simulation time 157197522 ps
CPU time 10.15 seconds
Started Feb 04 01:19:54 PM PST 24
Finished Feb 04 01:20:05 PM PST 24
Peak memory 246572 kb
Host smart-0b2e6a1a-f1db-4258-840f-c97e1750e0e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36743
18581 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_sig_int_fail.3674318581
Directory /workspace/5.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/5.alert_handler_smoke.2752538357
Short name T644
Test name
Test status
Simulation time 120082401 ps
CPU time 9.09 seconds
Started Feb 04 01:19:53 PM PST 24
Finished Feb 04 01:20:03 PM PST 24
Peak memory 248428 kb
Host smart-f3215f00-8072-42ef-8188-e5b3593cda12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27525
38357 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_smoke.2752538357
Directory /workspace/5.alert_handler_smoke/latest

Test location /workspace/coverage/default/6.alert_handler_alert_accum_saturation.483603808
Short name T192
Test name
Test status
Simulation time 43047308 ps
CPU time 2.1 seconds
Started Feb 04 01:20:04 PM PST 24
Finished Feb 04 01:20:11 PM PST 24
Peak memory 248664 kb
Host smart-fe828fb3-0a2f-4d10-94a3-8059070097f3
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=483603808 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_alert_accum_saturation.483603808
Directory /workspace/6.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/6.alert_handler_entropy.2545243854
Short name T283
Test name
Test status
Simulation time 44099521791 ps
CPU time 2698.08 seconds
Started Feb 04 01:20:04 PM PST 24
Finished Feb 04 02:05:07 PM PST 24
Peak memory 283772 kb
Host smart-504a200a-0431-4de2-a62c-d5ecd2f7de2a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545243854 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy.2545243854
Directory /workspace/6.alert_handler_entropy/latest

Test location /workspace/coverage/default/6.alert_handler_entropy_stress.1526862433
Short name T557
Test name
Test status
Simulation time 461913194 ps
CPU time 9.91 seconds
Started Feb 04 01:20:04 PM PST 24
Finished Feb 04 01:20:19 PM PST 24
Peak memory 248316 kb
Host smart-58658009-e4c7-4e8c-8ebb-5c63d47751bb
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1526862433 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy_stress.1526862433
Directory /workspace/6.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/6.alert_handler_esc_alert_accum.2135837427
Short name T455
Test name
Test status
Simulation time 391171331 ps
CPU time 16.54 seconds
Started Feb 04 01:20:03 PM PST 24
Finished Feb 04 01:20:24 PM PST 24
Peak memory 248432 kb
Host smart-0731f44b-5385-4c84-8885-eef1fdf0a973
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21358
37427 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_alert_accum.2135837427
Directory /workspace/6.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/6.alert_handler_esc_intr_timeout.1828462279
Short name T369
Test name
Test status
Simulation time 1502130344 ps
CPU time 55.93 seconds
Started Feb 04 01:20:04 PM PST 24
Finished Feb 04 01:21:05 PM PST 24
Peak memory 254976 kb
Host smart-cd37772b-1344-48ea-8572-ab51e2445fca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18284
62279 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_intr_timeout.1828462279
Directory /workspace/6.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_lpg_stub_clk.3026401214
Short name T650
Test name
Test status
Simulation time 73182574625 ps
CPU time 1479.34 seconds
Started Feb 04 01:20:05 PM PST 24
Finished Feb 04 01:44:50 PM PST 24
Peak memory 288944 kb
Host smart-31bf87c0-856f-4cee-ae9e-c38978a1d49b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026401214 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg_stub_clk.3026401214
Directory /workspace/6.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/6.alert_handler_ping_timeout.2026274013
Short name T738
Test name
Test status
Simulation time 13672075351 ps
CPU time 527.3 seconds
Started Feb 04 01:20:04 PM PST 24
Finished Feb 04 01:28:56 PM PST 24
Peak memory 247452 kb
Host smart-b81ba58a-37ce-43d3-ba0b-6fb9ee61753a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026274013 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_ping_timeout.2026274013
Directory /workspace/6.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_random_alerts.4238904263
Short name T676
Test name
Test status
Simulation time 14612353192 ps
CPU time 58.33 seconds
Started Feb 04 01:20:05 PM PST 24
Finished Feb 04 01:21:08 PM PST 24
Peak memory 255720 kb
Host smart-f406681f-c725-4849-a76c-f0eb33d7e13d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42389
04263 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_alerts.4238904263
Directory /workspace/6.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/6.alert_handler_random_classes.2455007553
Short name T506
Test name
Test status
Simulation time 93570012 ps
CPU time 11.03 seconds
Started Feb 04 01:20:04 PM PST 24
Finished Feb 04 01:20:20 PM PST 24
Peak memory 252372 kb
Host smart-9f9d9090-a8b6-4ea0-901b-41e9de6a9099
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24550
07553 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_classes.2455007553
Directory /workspace/6.alert_handler_random_classes/latest

Test location /workspace/coverage/default/6.alert_handler_sig_int_fail.1269918660
Short name T234
Test name
Test status
Simulation time 139970056 ps
CPU time 15.23 seconds
Started Feb 04 01:20:08 PM PST 24
Finished Feb 04 01:20:28 PM PST 24
Peak memory 246348 kb
Host smart-a6f53b6f-0ca5-462d-9dd2-695361ae85f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12699
18660 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_sig_int_fail.1269918660
Directory /workspace/6.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/6.alert_handler_smoke.2530932871
Short name T648
Test name
Test status
Simulation time 1467119635 ps
CPU time 22.65 seconds
Started Feb 04 01:20:08 PM PST 24
Finished Feb 04 01:20:36 PM PST 24
Peak memory 254076 kb
Host smart-4fe84e60-b549-4b31-85be-19dfab4a3dba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25309
32871 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_smoke.2530932871
Directory /workspace/6.alert_handler_smoke/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all.4257414391
Short name T294
Test name
Test status
Simulation time 132453814882 ps
CPU time 1925.5 seconds
Started Feb 04 01:20:06 PM PST 24
Finished Feb 04 01:52:17 PM PST 24
Peak memory 285832 kb
Host smart-a5d0af99-f57c-490a-b081-9a4fafc20b8f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257414391 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_han
dler_stress_all.4257414391
Directory /workspace/6.alert_handler_stress_all/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all_with_rand_reset.2521077455
Short name T62
Test name
Test status
Simulation time 26938105112 ps
CPU time 1715.13 seconds
Started Feb 04 01:20:07 PM PST 24
Finished Feb 04 01:48:48 PM PST 24
Peak memory 284304 kb
Host smart-d1622583-3fb8-4dfb-9248-8f45e8836133
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521077455 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 6.alert_handler_stress_all_with_rand_reset.2521077455
Directory /workspace/6.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.alert_handler_alert_accum_saturation.1650903124
Short name T188
Test name
Test status
Simulation time 41456829 ps
CPU time 2.42 seconds
Started Feb 04 01:20:12 PM PST 24
Finished Feb 04 01:20:22 PM PST 24
Peak memory 248688 kb
Host smart-6c09c036-293f-4297-b96d-088fe79f378c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1650903124 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_alert_accum_saturation.1650903124
Directory /workspace/7.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/7.alert_handler_entropy.1298321462
Short name T385
Test name
Test status
Simulation time 11596514620 ps
CPU time 1064.94 seconds
Started Feb 04 01:20:04 PM PST 24
Finished Feb 04 01:37:54 PM PST 24
Peak memory 289332 kb
Host smart-e862feaf-8773-4341-80a5-0785a6758840
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298321462 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy.1298321462
Directory /workspace/7.alert_handler_entropy/latest

Test location /workspace/coverage/default/7.alert_handler_entropy_stress.2526544256
Short name T525
Test name
Test status
Simulation time 555870255 ps
CPU time 13.47 seconds
Started Feb 04 01:20:07 PM PST 24
Finished Feb 04 01:20:26 PM PST 24
Peak memory 240200 kb
Host smart-b0930114-5af1-49d7-b26b-cf8d442243ec
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2526544256 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy_stress.2526544256
Directory /workspace/7.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/7.alert_handler_esc_alert_accum.3867182798
Short name T732
Test name
Test status
Simulation time 5066113534 ps
CPU time 105.06 seconds
Started Feb 04 01:20:04 PM PST 24
Finished Feb 04 01:21:53 PM PST 24
Peak memory 256748 kb
Host smart-0df9574b-4bc0-43b0-b725-d7514d034191
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38671
82798 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_alert_accum.3867182798
Directory /workspace/7.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/7.alert_handler_esc_intr_timeout.3602957809
Short name T393
Test name
Test status
Simulation time 312820866 ps
CPU time 10.63 seconds
Started Feb 04 01:20:07 PM PST 24
Finished Feb 04 01:20:23 PM PST 24
Peak memory 252156 kb
Host smart-e56aad04-303d-4a3d-ab06-d96873497dd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36029
57809 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_intr_timeout.3602957809
Directory /workspace/7.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_lpg.917615634
Short name T250
Test name
Test status
Simulation time 52854159055 ps
CPU time 992.48 seconds
Started Feb 04 01:20:10 PM PST 24
Finished Feb 04 01:36:47 PM PST 24
Peak memory 273148 kb
Host smart-231410d8-b9c1-402f-bfb3-da326b00bc61
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917615634 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg.917615634
Directory /workspace/7.alert_handler_lpg/latest

Test location /workspace/coverage/default/7.alert_handler_lpg_stub_clk.2904672539
Short name T553
Test name
Test status
Simulation time 30345978695 ps
CPU time 2129.11 seconds
Started Feb 04 01:20:10 PM PST 24
Finished Feb 04 01:55:43 PM PST 24
Peak memory 281376 kb
Host smart-b90321a1-250a-4886-a31b-904b959bab17
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904672539 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg_stub_clk.2904672539
Directory /workspace/7.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/7.alert_handler_ping_timeout.3220936954
Short name T260
Test name
Test status
Simulation time 2976489684 ps
CPU time 119.27 seconds
Started Feb 04 01:20:04 PM PST 24
Finished Feb 04 01:22:08 PM PST 24
Peak memory 247192 kb
Host smart-962715d4-8fc1-4fe5-a62c-c0c8fd427955
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220936954 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_ping_timeout.3220936954
Directory /workspace/7.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_random_alerts.2730494493
Short name T501
Test name
Test status
Simulation time 884856729 ps
CPU time 62.72 seconds
Started Feb 04 01:20:10 PM PST 24
Finished Feb 04 01:21:17 PM PST 24
Peak memory 248488 kb
Host smart-ef3908db-d22d-40e5-b24f-7f37a6efe31d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27304
94493 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_alerts.2730494493
Directory /workspace/7.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/7.alert_handler_random_classes.4123468685
Short name T306
Test name
Test status
Simulation time 1782607353 ps
CPU time 48.37 seconds
Started Feb 04 01:20:04 PM PST 24
Finished Feb 04 01:20:56 PM PST 24
Peak memory 254624 kb
Host smart-a7b28d52-8b2f-463a-ac3f-688c40bb8915
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41234
68685 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_classes.4123468685
Directory /workspace/7.alert_handler_random_classes/latest

Test location /workspace/coverage/default/7.alert_handler_sig_int_fail.1650633985
Short name T247
Test name
Test status
Simulation time 4519232020 ps
CPU time 49.12 seconds
Started Feb 04 01:20:08 PM PST 24
Finished Feb 04 01:21:02 PM PST 24
Peak memory 248532 kb
Host smart-c540a4c6-213a-48c8-acfe-595e40e50fa4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16506
33985 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_sig_int_fail.1650633985
Directory /workspace/7.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/7.alert_handler_smoke.1253089828
Short name T673
Test name
Test status
Simulation time 757459599 ps
CPU time 47.35 seconds
Started Feb 04 01:20:07 PM PST 24
Finished Feb 04 01:21:00 PM PST 24
Peak memory 256572 kb
Host smart-683bb0cb-43d0-478b-8b96-1742b5efbe71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12530
89828 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_smoke.1253089828
Directory /workspace/7.alert_handler_smoke/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all.3080771238
Short name T534
Test name
Test status
Simulation time 46959306373 ps
CPU time 1271.96 seconds
Started Feb 04 01:20:07 PM PST 24
Finished Feb 04 01:41:24 PM PST 24
Peak memory 289116 kb
Host smart-c6a7d997-d9d7-4add-b3f9-f523034b3eb3
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080771238 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_han
dler_stress_all.3080771238
Directory /workspace/7.alert_handler_stress_all/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all_with_rand_reset.2757197383
Short name T111
Test name
Test status
Simulation time 90529023782 ps
CPU time 2945.16 seconds
Started Feb 04 01:20:08 PM PST 24
Finished Feb 04 02:09:18 PM PST 24
Peak memory 305800 kb
Host smart-aa06c956-8473-4bc4-b883-65ba1325eba4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757197383 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.alert_handler_stress_all_with_rand_reset.2757197383
Directory /workspace/7.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.alert_handler_alert_accum_saturation.3423467921
Short name T53
Test name
Test status
Simulation time 40964218 ps
CPU time 2.4 seconds
Started Feb 04 01:20:11 PM PST 24
Finished Feb 04 01:20:21 PM PST 24
Peak memory 248600 kb
Host smart-98746ff2-3170-4882-832b-e7d3b720f995
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3423467921 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_alert_accum_saturation.3423467921
Directory /workspace/8.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/8.alert_handler_entropy.31859644
Short name T741
Test name
Test status
Simulation time 222653202634 ps
CPU time 2328.99 seconds
Started Feb 04 01:20:10 PM PST 24
Finished Feb 04 01:59:03 PM PST 24
Peak memory 282640 kb
Host smart-160559b8-e4b1-4ba1-9a82-9fc83bf03f11
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31859644 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy.31859644
Directory /workspace/8.alert_handler_entropy/latest

Test location /workspace/coverage/default/8.alert_handler_entropy_stress.3480973180
Short name T353
Test name
Test status
Simulation time 729374178 ps
CPU time 11.37 seconds
Started Feb 04 01:20:10 PM PST 24
Finished Feb 04 01:20:25 PM PST 24
Peak memory 240244 kb
Host smart-96b3a070-da63-45ca-81db-52ed330a330f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3480973180 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy_stress.3480973180
Directory /workspace/8.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/8.alert_handler_esc_alert_accum.1156473380
Short name T601
Test name
Test status
Simulation time 1660883890 ps
CPU time 143.98 seconds
Started Feb 04 01:20:12 PM PST 24
Finished Feb 04 01:22:44 PM PST 24
Peak memory 250300 kb
Host smart-0d196f80-bec0-466e-bf7c-c23ed723d8b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11564
73380 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_alert_accum.1156473380
Directory /workspace/8.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/8.alert_handler_esc_intr_timeout.523413903
Short name T657
Test name
Test status
Simulation time 458394008 ps
CPU time 14.33 seconds
Started Feb 04 01:20:09 PM PST 24
Finished Feb 04 01:20:28 PM PST 24
Peak memory 253984 kb
Host smart-68da3fcb-9106-45d2-ab1d-3420d9315d89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52341
3903 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_intr_timeout.523413903
Directory /workspace/8.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_lpg.2524727286
Short name T317
Test name
Test status
Simulation time 23565071221 ps
CPU time 1241.14 seconds
Started Feb 04 01:20:09 PM PST 24
Finished Feb 04 01:40:55 PM PST 24
Peak memory 288032 kb
Host smart-8cb5cc59-eaf6-4ff3-86d2-7382c16171dd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524727286 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg.2524727286
Directory /workspace/8.alert_handler_lpg/latest

Test location /workspace/coverage/default/8.alert_handler_lpg_stub_clk.3945242333
Short name T686
Test name
Test status
Simulation time 87729603205 ps
CPU time 1278.91 seconds
Started Feb 04 01:20:05 PM PST 24
Finished Feb 04 01:41:28 PM PST 24
Peak memory 272924 kb
Host smart-34e0f796-3c8c-4ce5-88f9-7dcd4a60fdd5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945242333 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg_stub_clk.3945242333
Directory /workspace/8.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/8.alert_handler_ping_timeout.3697232136
Short name T101
Test name
Test status
Simulation time 12850014978 ps
CPU time 135.72 seconds
Started Feb 04 01:20:07 PM PST 24
Finished Feb 04 01:22:28 PM PST 24
Peak memory 247192 kb
Host smart-d48b4959-7f19-4dc0-8b29-081aa574043e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697232136 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_ping_timeout.3697232136
Directory /workspace/8.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_random_alerts.579279351
Short name T597
Test name
Test status
Simulation time 537515881 ps
CPU time 12.08 seconds
Started Feb 04 01:20:10 PM PST 24
Finished Feb 04 01:20:26 PM PST 24
Peak memory 248504 kb
Host smart-d196c683-8c3e-455d-8906-25dbd7e44b32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57927
9351 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_alerts.579279351
Directory /workspace/8.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/8.alert_handler_random_classes.2625903884
Short name T464
Test name
Test status
Simulation time 1143130207 ps
CPU time 20.13 seconds
Started Feb 04 01:20:09 PM PST 24
Finished Feb 04 01:20:34 PM PST 24
Peak memory 252208 kb
Host smart-07817ec2-bc86-432b-ba0a-4a8e9ca75f56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26259
03884 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_classes.2625903884
Directory /workspace/8.alert_handler_random_classes/latest

Test location /workspace/coverage/default/8.alert_handler_sig_int_fail.3271394970
Short name T105
Test name
Test status
Simulation time 96208428 ps
CPU time 6.69 seconds
Started Feb 04 01:20:10 PM PST 24
Finished Feb 04 01:20:21 PM PST 24
Peak memory 250648 kb
Host smart-b7059b2d-e30b-46d9-8954-37d8b3120f78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32713
94970 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_sig_int_fail.3271394970
Directory /workspace/8.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/8.alert_handler_smoke.3837001188
Short name T514
Test name
Test status
Simulation time 128504477 ps
CPU time 2.66 seconds
Started Feb 04 01:20:09 PM PST 24
Finished Feb 04 01:20:16 PM PST 24
Peak memory 240184 kb
Host smart-27592a49-aa22-479e-9171-c7900ea51e17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38370
01188 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_smoke.3837001188
Directory /workspace/8.alert_handler_smoke/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all_with_rand_reset.1102643914
Short name T298
Test name
Test status
Simulation time 56116274334 ps
CPU time 2972.92 seconds
Started Feb 04 01:20:08 PM PST 24
Finished Feb 04 02:09:46 PM PST 24
Peak memory 297824 kb
Host smart-f768f1c2-7399-4c32-b8ac-25f1bf5655a7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102643914 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 8.alert_handler_stress_all_with_rand_reset.1102643914
Directory /workspace/8.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.alert_handler_alert_accum_saturation.3251578060
Short name T202
Test name
Test status
Simulation time 744479279 ps
CPU time 3.32 seconds
Started Feb 04 01:20:10 PM PST 24
Finished Feb 04 01:20:17 PM PST 24
Peak memory 248664 kb
Host smart-84b5fbac-727e-4e0b-984c-8acfedb12321
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3251578060 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_alert_accum_saturation.3251578060
Directory /workspace/9.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/9.alert_handler_entropy.97422780
Short name T466
Test name
Test status
Simulation time 16626723555 ps
CPU time 721.55 seconds
Started Feb 04 01:20:08 PM PST 24
Finished Feb 04 01:32:14 PM PST 24
Peak memory 272148 kb
Host smart-4c88c50e-6383-4583-9dcc-99cfad806c1a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97422780 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy.97422780
Directory /workspace/9.alert_handler_entropy/latest

Test location /workspace/coverage/default/9.alert_handler_entropy_stress.1123820978
Short name T365
Test name
Test status
Simulation time 348752302 ps
CPU time 17.93 seconds
Started Feb 04 01:20:08 PM PST 24
Finished Feb 04 01:20:31 PM PST 24
Peak memory 240232 kb
Host smart-e34c0acf-33de-4b4d-9764-ee6da102d8da
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1123820978 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy_stress.1123820978
Directory /workspace/9.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/9.alert_handler_esc_alert_accum.593017863
Short name T295
Test name
Test status
Simulation time 3664563911 ps
CPU time 217.94 seconds
Started Feb 04 01:20:10 PM PST 24
Finished Feb 04 01:23:52 PM PST 24
Peak memory 250496 kb
Host smart-54cc013d-ed33-46a6-99ca-68b3620b1b64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59301
7863 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_alert_accum.593017863
Directory /workspace/9.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/9.alert_handler_esc_intr_timeout.3969603861
Short name T617
Test name
Test status
Simulation time 466012137 ps
CPU time 31.12 seconds
Started Feb 04 01:20:11 PM PST 24
Finished Feb 04 01:20:50 PM PST 24
Peak memory 255424 kb
Host smart-165fcacc-eee8-4774-8609-bc63b9fc4465
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39696
03861 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_intr_timeout.3969603861
Directory /workspace/9.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_lpg.3625649061
Short name T315
Test name
Test status
Simulation time 57446591652 ps
CPU time 3407.64 seconds
Started Feb 04 01:20:06 PM PST 24
Finished Feb 04 02:16:59 PM PST 24
Peak memory 289072 kb
Host smart-44c27431-54db-449a-bab6-9068c2e6440c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625649061 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg.3625649061
Directory /workspace/9.alert_handler_lpg/latest

Test location /workspace/coverage/default/9.alert_handler_lpg_stub_clk.2406587465
Short name T712
Test name
Test status
Simulation time 17494888149 ps
CPU time 998.93 seconds
Started Feb 04 01:20:08 PM PST 24
Finished Feb 04 01:36:52 PM PST 24
Peak memory 284124 kb
Host smart-dee6cb57-1a3b-4c56-96bc-4383e4a4b268
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406587465 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg_stub_clk.2406587465
Directory /workspace/9.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/9.alert_handler_random_alerts.1972647579
Short name T555
Test name
Test status
Simulation time 972840320 ps
CPU time 10.91 seconds
Started Feb 04 01:20:09 PM PST 24
Finished Feb 04 01:20:25 PM PST 24
Peak memory 248436 kb
Host smart-219d07e1-42a1-424b-9346-c5d30262ed70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19726
47579 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_alerts.1972647579
Directory /workspace/9.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/9.alert_handler_random_classes.853765382
Short name T507
Test name
Test status
Simulation time 523151976 ps
CPU time 19.83 seconds
Started Feb 04 01:20:08 PM PST 24
Finished Feb 04 01:20:33 PM PST 24
Peak memory 255892 kb
Host smart-9a2665e6-4d16-4ba6-a0e8-2d4a539390ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85376
5382 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_classes.853765382
Directory /workspace/9.alert_handler_random_classes/latest

Test location /workspace/coverage/default/9.alert_handler_sig_int_fail.191226248
Short name T363
Test name
Test status
Simulation time 109445242 ps
CPU time 4.72 seconds
Started Feb 04 01:20:09 PM PST 24
Finished Feb 04 01:20:18 PM PST 24
Peak memory 238376 kb
Host smart-32f38d53-9eb6-4082-b8c3-9a848be58a4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19122
6248 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_sig_int_fail.191226248
Directory /workspace/9.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/9.alert_handler_smoke.130757000
Short name T419
Test name
Test status
Simulation time 733857433 ps
CPU time 48.01 seconds
Started Feb 04 01:20:09 PM PST 24
Finished Feb 04 01:21:02 PM PST 24
Peak memory 248276 kb
Host smart-f05a0ae3-2101-4f63-9325-34ee19ff919c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13075
7000 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_smoke.130757000
Directory /workspace/9.alert_handler_smoke/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all.2179052288
Short name T675
Test name
Test status
Simulation time 6758143585 ps
CPU time 234.43 seconds
Started Feb 04 01:20:11 PM PST 24
Finished Feb 04 01:24:13 PM PST 24
Peak memory 256692 kb
Host smart-79813aa3-da7a-4314-87f0-a67c46dd7c8c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179052288 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_han
dler_stress_all.2179052288
Directory /workspace/9.alert_handler_stress_all/latest
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