Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
esc_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	8	0	8	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	90662	1			T1	7		T2	3719		T3	111
class_i[0x1]	89557	1			T1	8		T2	2		T310	7
class_i[0x2]	55016	1			T2	5		T3	3		T60	15
class_i[0x3]	53571	1			T1	2		T35	67		T60	2

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Summary for Variable esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	72985	1			T1	8		T2	943		T5	1
alert[0x1]	74160	1			T1	6		T2	950		T3	1
alert[0x2]	68243	1			T1	3		T2	865		T3	3
alert[0x3]	73418	1			T2	968		T3	110		T5	7

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Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

esc_integrity_fail

288519

1

T1

10

T2

3726

T3

114

esc_ping_fail

287

1

T1

7

T9

7

T10

5

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Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	esc_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	alert[0x0]	72902	1			T1	5		T2	943		T5	1
esc_integrity_fail	alert[0x1]	74086	1			T1	3		T2	950		T3	1
esc_integrity_fail	alert[0x2]	68176	1			T1	2		T2	865		T3	3
esc_integrity_fail	alert[0x3]	73355	1			T2	968		T3	110		T5	7
esc_ping_fail	alert[0x0]	83	1			T1	3		T9	4		T10	2
esc_ping_fail	alert[0x1]	74	1			T1	3		T9	2		T10	2
esc_ping_fail	alert[0x2]	67	1			T1	1		T9	1		T10	1
esc_ping_fail	alert[0x3]	63	1			T241	1		T309	2		T307	2

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Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	class_i[0x0]	90548	1			T2	3719		T3	111		T5	8
esc_integrity_fail	class_i[0x1]	89520	1			T1	8		T2	2		T310	7
esc_integrity_fail	class_i[0x2]	54942	1			T2	5		T3	3		T60	15
esc_integrity_fail	class_i[0x3]	53509	1			T1	2		T35	67		T60	2
esc_ping_fail	class_i[0x0]	114	1			T1	7		T10	1		T242	8
esc_ping_fail	class_i[0x1]	37	1			T9	1		T241	2		T242	1
esc_ping_fail	class_i[0x2]	74	1			T10	4		T309	6		T308	5
esc_ping_fail	class_i[0x3]	62	1			T9	6		T309	1		T307	6