Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_edn_req.u_prim_packer_fifo.DataOStableWhenPending_A	0	0	758595158	0	0	643
tb.dut.u_edn_req.u_prim_packer_fifo.ValidOPairedWithReadyI_A	0	0	758595158	0	0	0

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.AckPKnownO_A	0	0	758595158	758407872	0	0
tb.dut.CheckAccuCntDw	0	0	643	643	0	0
tb.dut.CheckEscCntDw	0	0	643	643	0	0
tb.dut.CheckNAlerts	0	0	643	643	0	0
tb.dut.CheckNClasses	0	0	643	643	0	0
tb.dut.CheckNEscSev	0	0	643	643	0	0
tb.dut.CrashdumpKnownO_A	0	0	758595158	758407872	0	0
tb.dut.EdnKnownO_A	0	0	758595158	758407872	0	0
tb.dut.EscPKnownO_A	0	0	758595158	758407872	0	0
tb.dut.FpvSecCmPingTimerCnterCheck_A	0	0	758595158	90	0	0
tb.dut.FpvSecCmPingTimerDoubleLfsrCheck_A	0	0	758595158	90	0	0
tb.dut.FpvSecCmPingTimerEscCnterCheck_A	0	0	758595158	90	0	0
tb.dut.FpvSecCmPingTimerFsmCheck_A	0	0	758595158	90	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	758595158	90	0	0
tb.dut.IrqAKnownO_A	0	0	758595158	758407872	0	0
tb.dut.IrqBKnownO_A	0	0	758595158	758407872	0	0
tb.dut.IrqCKnownO_A	0	0	758595158	758407872	0	0
tb.dut.IrqDKnownO_A	0	0	758595158	758407872	0	0
tb.dut.TlAReadyKnownO_A	0	0	758595158	758407872	0	0
tb.dut.TlDValidKnownO_A	0	0	758595158	758407872	0	0
tb.dut.alert_handler_csr_assert.TlulOOBAddrErr_A	0	0	786415114	3754172	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_0_rd_A	0	0	786415114	19397	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_10_rd_A	0	0	786415114	18705	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_11_rd_A	0	0	786415114	19257	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_12_rd_A	0	0	786415114	19203	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_13_rd_A	0	0	786415114	18588	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_14_rd_A	0	0	786415114	18544	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_15_rd_A	0	0	786415114	19328	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_16_rd_A	0	0	786415114	18775	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_17_rd_A	0	0	786415114	18981	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_18_rd_A	0	0	786415114	18743	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_19_rd_A	0	0	786415114	18668	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_1_rd_A	0	0	786415114	18914	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_20_rd_A	0	0	786415114	18957	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_21_rd_A	0	0	786415114	18985	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_22_rd_A	0	0	786415114	18905	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_23_rd_A	0	0	786415114	18823	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_24_rd_A	0	0	786415114	19558	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_25_rd_A	0	0	786415114	19399	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_26_rd_A	0	0	786415114	18763	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_27_rd_A	0	0	786415114	19044	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_28_rd_A	0	0	786415114	18894	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_29_rd_A	0	0	786415114	19234	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_2_rd_A	0	0	786415114	18844	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_30_rd_A	0	0	786415114	19512	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_31_rd_A	0	0	786415114	18522	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_32_rd_A	0	0	786415114	19441	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_33_rd_A	0	0	786415114	18957	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_34_rd_A	0	0	786415114	20144	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_35_rd_A	0	0	786415114	19110	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_36_rd_A	0	0	786415114	19099	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_37_rd_A	0	0	786415114	18886	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_38_rd_A	0	0	786415114	18137	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_39_rd_A	0	0	786415114	18591	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_3_rd_A	0	0	786415114	19562	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_40_rd_A	0	0	786415114	18709	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_41_rd_A	0	0	786415114	18575	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_42_rd_A	0	0	786415114	19062	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_43_rd_A	0	0	786415114	18421	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_44_rd_A	0	0	786415114	19084	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_45_rd_A	0	0	786415114	18875	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_46_rd_A	0	0	786415114	19336	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_47_rd_A	0	0	786415114	18827	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_48_rd_A	0	0	786415114	19743	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_49_rd_A	0	0	786415114	19220	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_4_rd_A	0	0	786415114	19684	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_50_rd_A	0	0	786415114	18917	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_51_rd_A	0	0	786415114	19535	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_52_rd_A	0	0	786415114	19066	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_53_rd_A	0	0	786415114	19066	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_54_rd_A	0	0	786415114	18733	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_55_rd_A	0	0	786415114	18663	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_56_rd_A	0	0	786415114	18870	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_57_rd_A	0	0	786415114	19758	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_58_rd_A	0	0	786415114	19096	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_59_rd_A	0	0	786415114	19794	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_5_rd_A	0	0	786415114	18458	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_60_rd_A	0	0	786415114	18218	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_61_rd_A	0	0	786415114	18420	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_62_rd_A	0	0	786415114	19278	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_63_rd_A	0	0	786415114	18882	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_64_rd_A	0	0	786415114	19586	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_6_rd_A	0	0	786415114	18906	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_7_rd_A	0	0	786415114	18891	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_8_rd_A	0	0	786415114	18831	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_9_rd_A	0	0	786415114	18807	0	0
tb.dut.alert_handler_csr_assert.classa_regwen_rd_A	0	0	786415114	18667	0	0
tb.dut.alert_handler_csr_assert.classb_regwen_rd_A	0	0	786415114	19262	0	0
tb.dut.alert_handler_csr_assert.classc_regwen_rd_A	0	0	786415114	19546	0	0
tb.dut.alert_handler_csr_assert.classd_regwen_rd_A	0	0	786415114	19467	0	0
tb.dut.alert_handler_csr_assert.intr_enable_rd_A	0	0	786415114	36566	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_0_rd_A	0	0	786415114	18798	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_1_rd_A	0	0	786415114	19368	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_2_rd_A	0	0	786415114	18838	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_3_rd_A	0	0	786415114	18789	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_4_rd_A	0	0	786415114	19103	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_5_rd_A	0	0	786415114	19394	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_6_rd_A	0	0	786415114	18783	0	0
tb.dut.alert_handler_csr_assert.ping_timer_regwen_rd_A	0	0	786415114	18947	0	0
tb.dut.gen_classes[0].FpvSecCmAccuCnterCheck_A	0	0	758595158	90	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerCnterCheck_A	0	0	758595158	90	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerFsmCheck_A	0	0	758595158	90	0	0
tb.dut.gen_classes[0].u_accu.CountSaturateStable_A	0	0	758595158	1256	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigBkwd_A	0	0	758595158	276031	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigFwd_A	0	0	758595158	388338396	0	0
tb.dut.gen_classes[0].u_esc_timer.AccuFailToFsmError_A	0	0	758595158	336	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig0_A	0	0	758595158	933	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig1_A	0	0	758595158	48	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckClr_A	0	0	758595158	433	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckEn_A	0	0	758325757	290067825	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase0_A	0	0	758595158	1029	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase1_A	0	0	758595158	1012	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase2_A	0	0	758595158	997	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase3_A	0	0	758595158	986	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeout0_A	0	0	758595158	909	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt1_A	0	0	758595158	108521	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt2_A	0	0	758595158	795	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutStTrig_A	0	0	758595158	66	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStAllEscAsserted_A	0	0	758595158	1645	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStIsTerminal_A	0	0	758595158	1375	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs.AssertConnected_A	0	0	643	643	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs_A	0	0	758595158	758407872	0	0
tb.dut.gen_classes[1].FpvSecCmAccuCnterCheck_A	0	0	758595158	90	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerCnterCheck_A	0	0	758595158	90	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerFsmCheck_A	0	0	758595158	90	0	0
tb.dut.gen_classes[1].u_accu.CountSaturateStable_A	0	0	758595158	1116	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigBkwd_A	0	0	758595158	190747	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigFwd_A	0	0	758595158	451554874	0	0
tb.dut.gen_classes[1].u_esc_timer.AccuFailToFsmError_A	0	0	758595158	331	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig0_A	0	0	758595158	525	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig1_A	0	0	758595158	27	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckClr_A	0	0	758595158	237	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckEn_A	0	0	758325757	359405200	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase0_A	0	0	758595158	626	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase1_A	0	0	758595158	615	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase2_A	0	0	758595158	607	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase3_A	0	0	758595158	597	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeout0_A	0	0	758595158	1149	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt1_A	0	0	758595158	154039	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt2_A	0	0	758595158	1045	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutStTrig_A	0	0	758595158	77	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStAllEscAsserted_A	0	0	758595158	1661	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStIsTerminal_A	0	0	758595158	1391	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs.AssertConnected_A	0	0	643	643	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs_A	0	0	758595158	758407872	0	0
tb.dut.gen_classes[2].FpvSecCmAccuCnterCheck_A	0	0	758595158	90	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerCnterCheck_A	0	0	758595158	90	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerFsmCheck_A	0	0	758595158	90	0	0
tb.dut.gen_classes[2].u_accu.CountSaturateStable_A	0	0	758595158	5560	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigBkwd_A	0	0	758595158	205208	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigFwd_A	0	0	758595158	405471692	0	0
tb.dut.gen_classes[2].u_esc_timer.AccuFailToFsmError_A	0	0	758595158	322	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig0_A	0	0	758595158	547	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig1_A	0	0	758595158	27	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckClr_A	0	0	758595158	271	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckEn_A	0	0	758325757	331460193	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase0_A	0	0	758595158	633	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase1_A	0	0	758595158	623	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase2_A	0	0	758595158	614	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase3_A	0	0	758595158	598	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeout0_A	0	0	758595158	1083	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt1_A	0	0	758595158	113345	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt2_A	0	0	758595158	990	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutStTrig_A	0	0	758595158	66	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStAllEscAsserted_A	0	0	758595158	1611	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStIsTerminal_A	0	0	758595158	1341	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs.AssertConnected_A	0	0	643	643	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs_A	0	0	758595158	758407872	0	0
tb.dut.gen_classes[3].FpvSecCmAccuCnterCheck_A	0	0	758595158	90	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerCnterCheck_A	0	0	758595158	90	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerFsmCheck_A	0	0	758595158	90	0	0
tb.dut.gen_classes[3].u_accu.CountSaturateStable_A	0	0	758595158	6425	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigBkwd_A	0	0	758595158	204644	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigFwd_A	0	0	758595158	417435477	0	0
tb.dut.gen_classes[3].u_esc_timer.AccuFailToFsmError_A	0	0	758595158	304	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig0_A	0	0	758595158	592	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig1_A	0	0	758595158	32	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckClr_A	0	0	758595158	289	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckEn_A	0	0	758325757	332957220	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase0_A	0	0	758595158	703	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase1_A	0	0	758595158	694	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase2_A	0	0	758595158	680	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase3_A	0	0	758595158	672	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeout0_A	0	0	758595158	1358	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt1_A	0	0	758595158	157127	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt2_A	0	0	758595158	1242	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutStTrig_A	0	0	758595158	84	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStAllEscAsserted_A	0	0	758595158	1609	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStIsTerminal_A	0	0	758595158	1339	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs.AssertConnected_A	0	0	643	643	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs_A	0	0	758595158	758407872	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	786415114	140146803	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	786415114	785680758	0	0
tb.dut.tlul_assert_device.aReadyKnown_A	0	0	786415114	785680758	0	0
tb.dut.tlul_assert_device.dKnown_A	0	0	786415114	209520642	0	0
tb.dut.tlul_assert_device.dKnown_AKnownEnable	0	0	786415114	785680758	0	0
tb.dut.tlul_assert_device.dReadyKnown_A	0	0	786415114	785680758	0	0
tb.dut.tlul_assert_device.gen_assert_final[0].noOutstandingReqsAtEndOfSim_A	0	0	848	848	0	0
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