Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.31	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	44	1	43	97.73

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_sig_index_cp	4	0	4	100.00	100	1	1	0
esc_sig_len_cp	11	0	11	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
len_per_esc_sig	44	1	43	97.73	100	1	1	0

Summary for Variable esc_sig_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_sig_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	150	1			T23	1		T15	1		T103	1
index[0x1]	194	1			T2	1		T8	2		T15	1
index[0x2]	184	1			T3	1		T6	1		T34	1
index[0x3]	173	1			T4	1		T34	1		T94	1

---

Summary for Variable esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for esc_sig_len_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
lens_less_than_1000[0]	231	1			T8	2		T34	1		T95	1
lens_less_than_1000[1]	145	1			T2	1		T3	1		T15	1
lens_less_than_1000[2]	108	1			T4	1		T6	1		T78	1
lens_less_than_1000[3]	67	1			T23	1		T15	1		T103	1
lens_less_than_1000[4]	36	1			T42	1		T36	1		T113	1
lens_less_than_1000[5]	35	1			T41	1		T42	1		T113	1
lens_less_than_1000[6]	27	1			T285	1		T70	2		T118	1
lens_less_than_1000[7]	27	1			T41	2		T9	1		T98	1
lens_less_than_1000[8]	10	1			T240	1		T123	1		T133	3
lens_less_than_1000[9]	4	1			T118	1		T286	2		T287	1
len_2	11	1			T110	6		T262	1		T288	1

---

Summary for Cross len_per_esc_sig

Samples crossed: esc_sig_index_cp esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	44	1	43	97.73	1

Automatically Generated Cross Bins for len_per_esc_sig

Uncovered bins

esc_sig_index_cp	esc_sig_len_cp	COUNT	AT LEAST	NUMBER	STATUS
[index[0x3]]	[lens_less_than_1000[9]]	0	1	1

Covered bins

esc_sig_index_cp	esc_sig_len_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	lens_less_than_1000[0]	58	1			T103	1		T239	1		T39	3
index[0x0]	lens_less_than_1000[1]	28	1			T40	1		T39	1		T64	1
index[0x0]	lens_less_than_1000[2]	19	1			T78	1		T289	1		T290	1
index[0x0]	lens_less_than_1000[3]	13	1			T23	1		T15	1		T41	1
index[0x0]	lens_less_than_1000[4]	8	1			T42	1		T98	1		T107	1
index[0x0]	lens_less_than_1000[5]	5	1			T39	2		T280	1		T271	1
index[0x0]	lens_less_than_1000[6]	4	1			T118	1		T291	1		T76	1
index[0x0]	lens_less_than_1000[7]	4	1			T9	1		T292	1		T125	1
index[0x0]	lens_less_than_1000[8]	4	1			T240	1		T133	1		T269	1
index[0x0]	lens_less_than_1000[9]	1	1			T286	1		-	-		-	-
index[0x0]	len_2	6	1			T110	6		-	-		-	-
index[0x1]	lens_less_than_1000[0]	66	1			T8	2		T95	1		T94	2
index[0x1]	lens_less_than_1000[1]	34	1			T2	1		T15	1		T94	1
index[0x1]	lens_less_than_1000[2]	24	1			T98	2		T108	1		T139	1
index[0x1]	lens_less_than_1000[3]	25	1			T36	1		T242	1		T62	1
index[0x1]	lens_less_than_1000[4]	11	1			T36	1		T113	1		T244	1
index[0x1]	lens_less_than_1000[5]	14	1			T42	1		T113	1		T53	1
index[0x1]	lens_less_than_1000[6]	7	1			T285	1		T73	1		T74	1
index[0x1]	lens_less_than_1000[7]	10	1			T112	1		T70	1		T127	1
index[0x1]	lens_less_than_1000[8]	1	1			T288	1		-	-		-	-
index[0x1]	lens_less_than_1000[9]	1	1			T286	1		-	-		-	-
index[0x1]	len_2	1	1			T288	1		-	-		-	-
index[0x2]	lens_less_than_1000[0]	54	1			T38	1		T39	2		T101	1
index[0x2]	lens_less_than_1000[1]	36	1			T3	1		T34	1		T94	1
index[0x2]	lens_less_than_1000[2]	44	1			T6	1		T62	1		T293	1
index[0x2]	lens_less_than_1000[3]	13	1			T103	1		T42	1		T110	1
index[0x2]	lens_less_than_1000[4]	6	1			T39	1		T70	1		T133	2
index[0x2]	lens_less_than_1000[5]	4	1			T264	1		T294	1		T295	1
index[0x2]	lens_less_than_1000[6]	9	1			T73	6		T296	1		T297	1
index[0x2]	lens_less_than_1000[7]	10	1			T41	2		T98	1		T139	1
index[0x2]	lens_less_than_1000[8]	4	1			T123	1		T133	2		T298	1
index[0x2]	lens_less_than_1000[9]	2	1			T118	1		T287	1		-	-
index[0x2]	len_2	2	1			T299	1		T256	1		-	-
index[0x3]	lens_less_than_1000[0]	53	1			T34	1		T94	1		T98	1
index[0x3]	lens_less_than_1000[1]	47	1			T41	1		T84	1		T108	1
index[0x3]	lens_less_than_1000[2]	21	1			T4	1		T62	2		T300	1
index[0x3]	lens_less_than_1000[3]	16	1			T104	1		T70	1		T118	1
index[0x3]	lens_less_than_1000[4]	11	1			T253	1		T108	1		T139	1
index[0x3]	lens_less_than_1000[5]	12	1			T41	1		T301	1		T134	2
index[0x3]	lens_less_than_1000[6]	7	1			T70	2		T260	1		T124	1
index[0x3]	lens_less_than_1000[7]	3	1			T118	1		T125	1		T302	1
index[0x3]	lens_less_than_1000[8]	1	1			T303	1		-	-		-	-
index[0x3]	len_2	2	1			T262	1		T299	1		-	-