Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.15	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	40	1	39	97.50

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
intr_timeout_cnt_cp	10	0	10	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	40	1	39	97.50	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	66	1			T4	2		T34	1		T95	1
class_index[0x1]	77	1			T4	1		T36	1		T98	1
class_index[0x2]	66	1			T3	1		T94	3		T98	2
class_index[0x3]	84	1			T4	1		T96	1		T94	1

---

Summary for Variable intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for intr_timeout_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
intr_timeout_cnt[0]	102	1			T4	2		T34	1		T95	1
intr_timeout_cnt[1]	67	1			T94	2		T98	1		T100	1
intr_timeout_cnt[2]	38	1			T3	1		T4	1		T94	1
intr_timeout_cnt[3]	13	1			T100	1		T89	1		T118	1
intr_timeout_cnt[4]	16	1			T36	1		T107	1		T134	1
intr_timeout_cnt[5]	13	1			T62	1		T69	1		T119	1
intr_timeout_cnt[6]	9	1			T94	1		T119	1		T127	1
intr_timeout_cnt[7]	18	1			T105	1		T69	6		T260	1
intr_timeout_cnt[8]	9	1			T4	1		T101	1		T73	1
intr_timeout_cnt[9]	8	1			T112	1		T119	1		T261	1

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	1	39	97.50	1

Automatically Generated Cross Bins for class_cnt_cross

Uncovered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	NUMBER	STATUS
[class_index[0x0]]	[intr_timeout_cnt[9]]	0	1	1

Covered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	intr_timeout_cnt[0]	23	1			T4	1		T34	1		T95	1
class_index[0x0]	intr_timeout_cnt[1]	16	1			T94	2		T100	1		T137	1
class_index[0x0]	intr_timeout_cnt[2]	9	1			T72	1		T127	1		T262	2
class_index[0x0]	intr_timeout_cnt[3]	3	1			T89	1		T263	1		T33	1
class_index[0x0]	intr_timeout_cnt[4]	4	1			T109	1		T262	1		T264	1
class_index[0x0]	intr_timeout_cnt[5]	3	1			T62	1		T69	1		T255	1
class_index[0x0]	intr_timeout_cnt[6]	4	1			T119	1		T127	1		T265	1
class_index[0x0]	intr_timeout_cnt[7]	1	1			T261	1		-	-		-	-
class_index[0x0]	intr_timeout_cnt[8]	3	1			T4	1		T101	1		T73	1
class_index[0x1]	intr_timeout_cnt[0]	24	1			T4	1		T109	1		T110	1
class_index[0x1]	intr_timeout_cnt[1]	24	1			T98	1		T108	1		T119	1
class_index[0x1]	intr_timeout_cnt[2]	8	1			T111	1		T69	1		T266	1
class_index[0x1]	intr_timeout_cnt[3]	4	1			T100	1		T267	1		T268	1
class_index[0x1]	intr_timeout_cnt[4]	2	1			T36	1		T112	1		-	-
class_index[0x1]	intr_timeout_cnt[5]	5	1			T119	1		T264	2		T265	1
class_index[0x1]	intr_timeout_cnt[6]	2	1			T269	1		T265	1		-	-
class_index[0x1]	intr_timeout_cnt[7]	4	1			T270	3		T271	1		-	-
class_index[0x1]	intr_timeout_cnt[8]	2	1			T125	1		T272	1		-	-
class_index[0x1]	intr_timeout_cnt[9]	2	1			T273	1		T274	1		-	-
class_index[0x2]	intr_timeout_cnt[0]	29	1			T94	2		T98	2		T62	1
class_index[0x2]	intr_timeout_cnt[1]	9	1			T62	1		T73	1		T275	1
class_index[0x2]	intr_timeout_cnt[2]	8	1			T3	1		T264	1		T274	1
class_index[0x2]	intr_timeout_cnt[3]	4	1			T118	1		T127	1		T276	1
class_index[0x2]	intr_timeout_cnt[4]	6	1			T110	6		-	-		-	-
class_index[0x2]	intr_timeout_cnt[5]	2	1			T127	1		T277	1		-	-
class_index[0x2]	intr_timeout_cnt[6]	2	1			T94	1		T278	1		-	-
class_index[0x2]	intr_timeout_cnt[7]	2	1			T105	1		T73	1		-	-
class_index[0x2]	intr_timeout_cnt[8]	3	1			T279	1		T280	1		T281	1
class_index[0x2]	intr_timeout_cnt[9]	1	1			T261	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[0]	26	1			T96	1		T98	1		T38	1
class_index[0x3]	intr_timeout_cnt[1]	18	1			T62	1		T69	1		T133	1
class_index[0x3]	intr_timeout_cnt[2]	13	1			T4	1		T94	1		T38	1
class_index[0x3]	intr_timeout_cnt[3]	2	1			T278	1		T282	1		-	-
class_index[0x3]	intr_timeout_cnt[4]	4	1			T107	1		T134	1		T109	1
class_index[0x3]	intr_timeout_cnt[5]	3	1			T72	1		T283	1		T265	1
class_index[0x3]	intr_timeout_cnt[6]	1	1			T280	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[7]	11	1			T69	6		T260	1		T281	1
class_index[0x3]	intr_timeout_cnt[8]	1	1			T284	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[9]	5	1			T112	1		T119	1		T280	1