Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	362481	1			T14	8		T29	8		T30	1
all_values[1]	362481	1			T14	8		T29	8		T30	1
all_values[2]	362481	1			T14	8		T29	8		T30	1
all_values[3]	362481	1			T14	8		T29	8		T30	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

722615

1

T14

11

T29

16

T30

4

auto[1]

727309

1

T14

21

T29

16

T31

9

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

858071

1

T14

15

T29

23

T30

4

auto[1]

591853

1

T14

17

T29

9

T31

11

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	102319	1			T30	1		T32	4		T201	1
all_values[0]	auto[0]	auto[1]	77584	1			T14	2		T29	1		T31	1
all_values[0]	auto[1]	auto[0]	104700	1			T14	3		T29	4		T31	1
all_values[0]	auto[1]	auto[1]	77878	1			T14	3		T29	3		T31	3
all_values[1]	auto[0]	auto[0]	106505	1			T14	6		T29	3		T30	1
all_values[1]	auto[0]	auto[1]	74614	1			T14	1		T32	1		T201	2
all_values[1]	auto[1]	auto[0]	107343	1			T29	1		T31	1		T32	6
all_values[1]	auto[1]	auto[1]	74019	1			T14	1		T29	4		T31	1
all_values[2]	auto[0]	auto[0]	109866	1			T14	1		T29	7		T30	1
all_values[2]	auto[0]	auto[1]	71289	1			T32	2		T201	2		T202	2
all_values[2]	auto[1]	auto[0]	110639	1			T14	3		T29	1		T31	1
all_values[2]	auto[1]	auto[1]	70687	1			T14	4		T31	2		T32	2
all_values[3]	auto[0]	auto[0]	107712	1			T29	5		T30	1		T31	1
all_values[3]	auto[0]	auto[1]	72726	1			T14	1		T31	4		T32	4
all_values[3]	auto[1]	auto[0]	108987	1			T14	2		T29	2		T32	1
all_values[3]	auto[1]	auto[1]	73056	1			T14	5		T29	1		T32	2