Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	4	0	4	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	362481	1			T14	8		T29	8		T30	1
all_pins[1]	362481	1			T14	8		T29	8		T30	1
all_pins[2]	362481	1			T14	8		T29	8		T30	1
all_pins[3]	362481	1			T14	8		T29	8		T30	1

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1154284	1			T14	19		T29	24		T30	4
values[0x1]	295640	1			T14	13		T29	8		T31	6
transitions[0x0=>0x1]	196753	1			T14	6		T29	7		T31	5
transitions[0x1=>0x0]	197034	1			T14	6		T29	7		T31	5

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	284603	1			T14	5		T29	5		T30	1
all_pins[0]	values[0x1]	77878	1			T14	3		T29	3		T31	3
all_pins[0]	transitions[0x0=>0x1]	77185	1			T29	2		T31	3		T32	2
all_pins[0]	transitions[0x1=>0x0]	72644	1			T14	2		T32	2		T201	1
all_pins[1]	values[0x0]	288462	1			T14	7		T29	4		T30	1
all_pins[1]	values[0x1]	74019	1			T14	1		T29	4		T31	1
all_pins[1]	transitions[0x0=>0x1]	40594	1			T14	1		T29	4		T202	2
all_pins[1]	transitions[0x1=>0x0]	44453	1			T14	3		T29	3		T31	2
all_pins[2]	values[0x0]	291794	1			T14	4		T29	8		T30	1
all_pins[2]	values[0x1]	70687	1			T14	4		T31	2		T32	2
all_pins[2]	transitions[0x0=>0x1]	38317	1			T14	3		T31	2		T32	2
all_pins[2]	transitions[0x1=>0x0]	41649	1			T29	4		T31	1		T202	2
all_pins[3]	values[0x0]	289425	1			T14	3		T29	7		T30	1
all_pins[3]	values[0x1]	73056	1			T14	5		T29	1		T32	2
all_pins[3]	transitions[0x0=>0x1]	40657	1			T14	2		T29	1		T201	1
all_pins[3]	transitions[0x1=>0x0]	38288	1			T14	1		T31	2		T250	3