Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	263	1			T14	7		T29	7		T31	4
all_values[1]	263	1			T14	7		T29	7		T31	4
all_values[2]	263	1			T14	7		T29	7		T31	4
all_values[3]	263	1			T14	7		T29	7		T31	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

574

1

T14

10

T29

15

T31

9

auto[1]

478

1

T14

18

T29

13

T31

7

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

394

1

T14

8

T29

16

T31

5

auto[1]

658

1

T14

20

T29

12

T31

11

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

638

1

T14

14

T29

21

T31

9

auto[1]

414

1

T14

14

T29

7

T31

7

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	24	0	24	100.00
Automatically Generated Cross Bins	24	0	24	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr

cp_intr_test

cp_intr_en

cp_intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_values[0]

auto[0]

auto[0]

auto[0]

49

1

T32

3

T202

4

T348

2

all_values[0]

auto[0]

auto[0]

auto[1]

29

1

T14

1

T32

1

T201

1

all_values[0]

auto[0]

auto[1]

auto[0]

46

1

T29

1

T201

1

T249

2

all_values[0]

auto[0]

auto[1]

auto[1]

34

1

T14

2

T29

3

T31

1

all_values[0]

auto[1]

auto[0]

auto[1]

55

1

T14

1

T29

1

T31

1

all_values[0]

auto[1]

auto[1]

auto[1]

50

1

T14

3

T29

2

T31

2

all_values[1]

auto[0]

auto[0]

auto[0]

67

1

T14

4

T29

2

T31

2

all_values[1]

auto[0]

auto[0]

auto[1]

25

1

T14

1

T32

1

T201

1

all_values[1]

auto[0]

auto[1]

auto[0]

32

1

T31

1

T32

3

T249

1

all_values[1]

auto[0]

auto[1]

auto[1]

37

1

T29

2

T202

2

T349

1

all_values[1]

auto[1]

auto[0]

auto[1]

62

1

T29

2

T32

1

T201

1

all_values[1]

auto[1]

auto[1]

auto[1]

40

1

T14

2

T29

1

T31

1

all_values[2]

auto[0]

auto[0]

auto[0]

69

1

T14

1

T29

7

T31

2

all_values[2]

auto[0]

auto[0]

auto[1]

29

1

T32

1

T201

1

T202

2

all_values[2]

auto[0]

auto[1]

auto[0]

40

1

T14

2

T32

2

T348

1

all_values[2]

auto[0]

auto[1]

auto[1]

30

1

T14

1

T31

1

T32

1

all_values[2]

auto[1]

auto[0]

auto[1]

49

1

T14

1

T32

2

T201

1

all_values[2]

auto[1]

auto[1]

auto[1]

46

1

T14

2

T31

1

T32

1

all_values[3]

auto[0]

auto[0]

auto[0]

48

1

T29

3

T201

1

T348

1

all_values[3]

auto[0]

auto[0]

auto[1]

28

1

T31

2

T32

1

T201

1

all_values[3]

auto[0]

auto[1]

auto[0]

43

1

T14

1

T29

3

T202

1

all_values[3]

auto[0]

auto[1]

auto[1]

32

1

T14

1

T32

2

T201

1

all_values[3]

auto[1]

auto[0]

auto[1]

64

1

T14

1

T31

2

T32

4

all_values[3]

auto[1]

auto[1]

auto[1]

48

1

T14

4

T29

1

T201

1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal