Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
accum_cnt_cp	6	0	6	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	24	0	24	100.00	100	1	1	0

Summary for Variable accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for accum_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
accum_cnt_2000	100379	1			T2	973		T4	550		T5	271
accum_cnt_1000	238037	1			T2	1073		T3	19		T4	902
accum_cnt_100	29023	1			T2	66		T3	45		T4	33
accum_cnt_50	63013	1			T2	1140		T3	116		T4	36
accum_cnt_10	179870	1			T1	36		T2	1103		T3	129
accum_cnt_0	411243	1			T1	132		T2	5		T3	331

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Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	267020	1			T1	42		T2	1090		T3	160
class_index[0x1]	267020	1			T1	42		T2	1090		T3	160
class_index[0x2]	267020	1			T1	42		T2	1090		T3	160
class_index[0x3]	267020	1			T1	42		T2	1090		T3	160

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Summary for Cross class_cnt_cross

Samples crossed: class_index_cp accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for class_cnt_cross

Bins

class_index_cp	accum_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	accum_cnt_2000	27520	1			T5	132		T16	419		T18	596
class_index[0x0]	accum_cnt_1000	61496	1			T5	168		T16	580		T59	13
class_index[0x0]	accum_cnt_100	8185	1			T3	3		T4	9		T5	12
class_index[0x0]	accum_cnt_50	20961	1			T3	1		T4	20		T5	9
class_index[0x0]	accum_cnt_10	42207	1			T2	1089		T3	51		T19	12
class_index[0x0]	accum_cnt_0	91846	1			T1	42		T2	1		T3	105
class_index[0x1]	accum_cnt_2000	21088	1			T2	465		T16	360		T94	805
class_index[0x1]	accum_cnt_1000	56612	1			T2	557		T3	19		T21	50
class_index[0x1]	accum_cnt_100	6681	1			T2	31		T3	42		T21	15
class_index[0x1]	accum_cnt_50	15549	1			T2	28		T3	28		T21	11
class_index[0x1]	accum_cnt_10	49446	1			T2	6		T3	39		T4	1498
class_index[0x1]	accum_cnt_0	107457	1			T1	42		T2	3		T3	32
class_index[0x2]	accum_cnt_2000	27551	1			T6	568		T16	496		T103	520
class_index[0x2]	accum_cnt_1000	60349	1			T21	50		T6	533		T16	514
class_index[0x2]	accum_cnt_100	6871	1			T21	16		T6	34		T57	2
class_index[0x2]	accum_cnt_50	13169	1			T2	1087		T3	87		T21	12
class_index[0x2]	accum_cnt_10	40313	1			T2	2		T3	11		T4	1498
class_index[0x2]	accum_cnt_0	107892	1			T1	42		T2	1		T3	62
class_index[0x3]	accum_cnt_2000	24220	1			T2	508		T4	550		T5	139
class_index[0x3]	accum_cnt_1000	59580	1			T2	516		T4	902		T5	421
class_index[0x3]	accum_cnt_100	7286	1			T2	35		T4	24		T5	25
class_index[0x3]	accum_cnt_50	13334	1			T2	25		T4	16		T5	22
class_index[0x3]	accum_cnt_10	47904	1			T1	36		T2	6		T3	28
class_index[0x3]	accum_cnt_0	104048	1			T1	6		T3	132		T19	17