Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	71	0	71	100.00
Crosses	138	0	138	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
alert_index_cp	65	0	65	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	130	0	130	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for alert_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	4710	1			T60	177		T61	49		T38	181
alert[0x1]	9369	1			T5	808		T42	25		T61	183
alert[0x2]	5761	1			T1	1		T60	10		T94	538
alert[0x3]	6632	1			T35	25		T42	14		T61	17
alert[0x4]	4962	1			T1	1		T94	928		T84	298
alert[0x5]	9140	1			T1	1		T60	25		T42	70
alert[0x6]	9727	1			T1	1		T5	135		T60	9
alert[0x7]	2685	1			T1	1		T35	2		T60	13
alert[0x8]	2640	1			T5	311		T9	1		T61	88
alert[0x9]	8123	1			T42	110		T61	360		T84	16
alert[0xa]	3175	1			T1	1		T8	1		T60	145
alert[0xb]	3517	1			T1	1		T60	81		T94	1
alert[0xc]	3260	1			T5	1		T60	37		T10	1
alert[0xd]	18961	1			T5	1210		T60	1		T42	8
alert[0xe]	6805	1			T5	562		T60	153		T94	340
alert[0xf]	6310	1			T5	155		T60	2		T94	168
alert[0x10]	6017	1			T5	164		T35	2		T60	15
alert[0x11]	7737	1			T60	20		T10	1		T61	265
alert[0x12]	7159	1			T94	87		T61	14		T100	8
alert[0x13]	5655	1			T5	182		T60	14		T42	34
alert[0x14]	5568	1			T35	1		T60	8		T42	3
alert[0x15]	20621	1			T5	276		T60	6		T42	3
alert[0x16]	13442	1			T42	71		T10	2		T84	50
alert[0x17]	3419	1			T60	91		T42	33		T38	265
alert[0x18]	6398	1			T1	1		T5	79		T60	35
alert[0x19]	8207	1			T60	837		T42	5		T9	1
alert[0x1a]	6172	1			T1	1		T5	22		T60	11
alert[0x1b]	6605	1			T1	2		T5	204		T35	3
alert[0x1c]	8129	1			T1	1		T60	57		T85	1
alert[0x1d]	7133	1			T1	1		T5	7		T35	3
alert[0x1e]	8515	1			T42	194		T241	1		T307	1
alert[0x1f]	6679	1			T42	26		T9	1		T61	527
alert[0x20]	8689	1			T5	73		T42	100		T79	1
alert[0x21]	9051	1			T5	11		T9	1		T84	4
alert[0x22]	18172	1			T5	7		T42	946		T61	1146
alert[0x23]	6016	1			T1	1		T5	21		T60	6
alert[0x24]	3745	1			T5	167		T42	226		T39	50
alert[0x25]	8207	1			T5	112		T60	22		T61	175
alert[0x26]	3849	1			T60	56		T42	216		T61	197
alert[0x27]	3914	1			T5	208		T60	10		T42	682
alert[0x28]	3688	1			T1	1		T8	1		T94	12
alert[0x29]	11417	1			T5	17		T60	22		T42	110
alert[0x2a]	6700	1			T60	30		T42	1369		T61	314
alert[0x2b]	2328	1			T5	34		T308	1		T122	58
alert[0x2c]	4901	1			T1	1		T61	11		T84	154
alert[0x2d]	2543	1			T3	4		T35	2		T10	1
alert[0x2e]	5791	1			T60	468		T42	29		T10	2
alert[0x2f]	8200	1			T5	13		T94	75		T42	259
alert[0x30]	8886	1			T1	1		T94	4263		T309	1
alert[0x31]	6227	1			T1	1		T3	7		T5	164
alert[0x32]	2644	1			T35	1		T94	126		T42	40
alert[0x33]	3697	1			T1	1		T5	35		T61	34
alert[0x34]	15466	1			T5	7		T60	19		T84	52
alert[0x35]	5400	1			T1	1		T5	42		T60	11
alert[0x36]	8445	1			T5	77		T60	2		T42	216
alert[0x37]	5916	1			T5	267		T310	9		T42	414
alert[0x38]	2887	1			T60	12		T61	27		T63	89
alert[0x39]	3293	1			T5	12		T10	1		T61	221
alert[0x3a]	6204	1			T5	114		T42	757		T84	56
alert[0x3b]	3327	1			T1	1		T5	37		T60	5
alert[0x3c]	11990	1			T310	1		T61	3503		T308	2
alert[0x3d]	19186	1			T42	70		T241	1		T38	199
alert[0x3e]	5471	1			T41	4		T42	3		T38	26
alert[0x3f]	5366	1			T94	496		T310	5		T42	572
alert[0x40]	2825	1			T5	32		T41	4		T9	1

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	191543	1			T1	1		T3	4		T5	5563
class_i[0x1]	88377	1			T1	16		T5	3		T60	2
class_i[0x2]	93905	1			T3	7		T94	24		T42	1
class_i[0x3]	83849	1			T1	4		T60	2764		T94	7460

---

Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

alert_integrity_fail

457017

1

T3

11

T5

5566

T35

39

alert_ping_fail

657

1

T1

21

T8

2

T9

14

---

Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	0	130	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	alert_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	alert[0x0]	4701	1			T60	177		T61	49		T38	181
alert_integrity_fail	alert[0x1]	9356	1			T5	808		T42	25		T61	183
alert_integrity_fail	alert[0x2]	5745	1			T60	10		T94	538		T42	48
alert_integrity_fail	alert[0x3]	6625	1			T35	25		T42	14		T61	17
alert_integrity_fail	alert[0x4]	4952	1			T94	928		T84	298		T38	4
alert_integrity_fail	alert[0x5]	9125	1			T60	25		T42	70		T61	21
alert_integrity_fail	alert[0x6]	9717	1			T5	135		T60	9		T61	2195
alert_integrity_fail	alert[0x7]	2669	1			T35	2		T60	13		T122	51
alert_integrity_fail	alert[0x8]	2628	1			T5	311		T61	88		T84	14
alert_integrity_fail	alert[0x9]	8115	1			T42	110		T61	360		T84	16
alert_integrity_fail	alert[0xa]	3165	1			T60	145		T36	1		T61	19
alert_integrity_fail	alert[0xb]	3507	1			T60	81		T94	1		T42	12
alert_integrity_fail	alert[0xc]	3249	1			T5	1		T60	37		T61	214
alert_integrity_fail	alert[0xd]	18953	1			T5	1210		T60	1		T42	8
alert_integrity_fail	alert[0xe]	6800	1			T5	562		T60	153		T94	340
alert_integrity_fail	alert[0xf]	6303	1			T5	155		T60	2		T94	168
alert_integrity_fail	alert[0x10]	6004	1			T5	164		T35	2		T60	15
alert_integrity_fail	alert[0x11]	7727	1			T60	20		T61	265		T84	45
alert_integrity_fail	alert[0x12]	7154	1			T94	87		T61	14		T100	8
alert_integrity_fail	alert[0x13]	5643	1			T5	182		T60	14		T42	34
alert_integrity_fail	alert[0x14]	5556	1			T35	1		T60	8		T42	3
alert_integrity_fail	alert[0x15]	20607	1			T5	276		T60	6		T42	3
alert_integrity_fail	alert[0x16]	13430	1			T42	71		T84	50		T62	3
alert_integrity_fail	alert[0x17]	3415	1			T60	91		T42	33		T38	265
alert_integrity_fail	alert[0x18]	6391	1			T5	79		T60	35		T84	449
alert_integrity_fail	alert[0x19]	8196	1			T60	837		T42	5		T38	89
alert_integrity_fail	alert[0x1a]	6164	1			T5	22		T60	11		T61	594
alert_integrity_fail	alert[0x1b]	6596	1			T5	204		T35	3		T60	11
alert_integrity_fail	alert[0x1c]	8116	1			T60	57		T38	173		T100	23
alert_integrity_fail	alert[0x1d]	7118	1			T5	7		T35	3		T60	297
alert_integrity_fail	alert[0x1e]	8504	1			T42	194		T100	40		T104	83
alert_integrity_fail	alert[0x1f]	6664	1			T42	26		T61	527		T84	1
alert_integrity_fail	alert[0x20]	8677	1			T5	73		T42	100		T79	1
alert_integrity_fail	alert[0x21]	9036	1			T5	11		T84	4		T38	51
alert_integrity_fail	alert[0x22]	18161	1			T5	7		T42	946		T61	1146
alert_integrity_fail	alert[0x23]	6008	1			T5	21		T60	6		T84	19
alert_integrity_fail	alert[0x24]	3736	1			T5	167		T42	226		T39	50
alert_integrity_fail	alert[0x25]	8199	1			T5	112		T60	22		T61	175
alert_integrity_fail	alert[0x26]	3839	1			T60	56		T42	216		T61	197
alert_integrity_fail	alert[0x27]	3909	1			T5	208		T60	10		T42	682
alert_integrity_fail	alert[0x28]	3671	1			T94	12		T38	355		T122	371
alert_integrity_fail	alert[0x29]	11409	1			T5	17		T60	22		T42	110
alert_integrity_fail	alert[0x2a]	6688	1			T60	30		T42	1369		T61	314
alert_integrity_fail	alert[0x2b]	2319	1			T5	34		T122	58		T246	43
alert_integrity_fail	alert[0x2c]	4883	1			T61	11		T84	154		T39	6
alert_integrity_fail	alert[0x2d]	2530	1			T3	4		T35	2		T38	108
alert_integrity_fail	alert[0x2e]	5780	1			T60	468		T42	29		T61	5
alert_integrity_fail	alert[0x2f]	8187	1			T5	13		T94	75		T42	259
alert_integrity_fail	alert[0x30]	8873	1			T94	4263		T100	124		T101	2
alert_integrity_fail	alert[0x31]	6220	1			T3	7		T5	164		T60	48
alert_integrity_fail	alert[0x32]	2630	1			T35	1		T94	126		T42	40
alert_integrity_fail	alert[0x33]	3687	1			T5	35		T61	34		T84	209
alert_integrity_fail	alert[0x34]	15459	1			T5	7		T60	19		T84	52
alert_integrity_fail	alert[0x35]	5392	1			T5	42		T60	11		T61	3
alert_integrity_fail	alert[0x36]	8440	1			T5	77		T60	2		T42	216
alert_integrity_fail	alert[0x37]	5908	1			T5	267		T310	9		T42	414
alert_integrity_fail	alert[0x38]	2878	1			T60	12		T61	27		T63	89
alert_integrity_fail	alert[0x39]	3285	1			T5	12		T61	221		T84	147
alert_integrity_fail	alert[0x3a]	6197	1			T5	114		T42	757		T84	56
alert_integrity_fail	alert[0x3b]	3317	1			T5	37		T60	5		T94	408
alert_integrity_fail	alert[0x3c]	11982	1			T310	1		T61	3503		T122	57
alert_integrity_fail	alert[0x3d]	19178	1			T42	70		T38	199		T122	11623
alert_integrity_fail	alert[0x3e]	5463	1			T41	4		T42	3		T38	26
alert_integrity_fail	alert[0x3f]	5362	1			T94	496		T310	5		T42	572
alert_integrity_fail	alert[0x40]	2819	1			T5	32		T41	4		T61	31
alert_ping_fail	alert[0x0]	9	1			T311	1		T52	2		T312	1
alert_ping_fail	alert[0x1]	13	1			T311	1		T87	1		T292	1
alert_ping_fail	alert[0x2]	16	1			T1	1		T9	1		T10	1
alert_ping_fail	alert[0x3]	7	1			T52	1		T313	1		T236	1
alert_ping_fail	alert[0x4]	10	1			T1	1		T311	1		T87	1
alert_ping_fail	alert[0x5]	15	1			T1	1		T9	2		T306	2
alert_ping_fail	alert[0x6]	10	1			T1	1		T306	1		T242	1
alert_ping_fail	alert[0x7]	16	1			T1	1		T309	1		T307	3
alert_ping_fail	alert[0x8]	12	1			T9	1		T307	1		T242	1
alert_ping_fail	alert[0x9]	8	1			T242	1		T87	1		T312	1
alert_ping_fail	alert[0xa]	10	1			T1	1		T8	1		T9	1
alert_ping_fail	alert[0xb]	10	1			T1	1		T87	1		T312	2
alert_ping_fail	alert[0xc]	11	1			T10	1		T52	1		T312	1
alert_ping_fail	alert[0xd]	8	1			T309	1		T87	1		T314	1
alert_ping_fail	alert[0xe]	5	1			T307	1		T315	1		T316	1
alert_ping_fail	alert[0xf]	7	1			T307	2		T317	1		T318	1
alert_ping_fail	alert[0x10]	13	1			T241	1		T242	1		T292	1
alert_ping_fail	alert[0x11]	10	1			T10	1		T312	1		T319	1
alert_ping_fail	alert[0x12]	5	1			T87	1		T320	1		T235	2
alert_ping_fail	alert[0x13]	12	1			T9	1		T304	2		T52	1
alert_ping_fail	alert[0x14]	12	1			T238	1		T309	1		T307	1
alert_ping_fail	alert[0x15]	14	1			T241	1		T321	1		T314	1
alert_ping_fail	alert[0x16]	12	1			T10	2		T241	1		T93	1
alert_ping_fail	alert[0x17]	4	1			T312	1		T319	1		T322	1
alert_ping_fail	alert[0x18]	7	1			T1	1		T312	1		T320	1
alert_ping_fail	alert[0x19]	11	1			T9	1		T241	1		T309	1
alert_ping_fail	alert[0x1a]	8	1			T1	1		T52	1		T323	1
alert_ping_fail	alert[0x1b]	9	1			T1	2		T312	1		T236	1
alert_ping_fail	alert[0x1c]	13	1			T1	1		T85	1		T307	1
alert_ping_fail	alert[0x1d]	15	1			T1	1		T307	2		T308	1
alert_ping_fail	alert[0x1e]	11	1			T241	1		T307	1		T308	1
alert_ping_fail	alert[0x1f]	15	1			T9	1		T93	2		T52	1
alert_ping_fail	alert[0x20]	12	1			T308	1		T242	1		T292	1
alert_ping_fail	alert[0x21]	15	1			T9	1		T311	1		T312	1
alert_ping_fail	alert[0x22]	11	1			T85	1		T308	1		T312	1
alert_ping_fail	alert[0x23]	8	1			T1	1		T9	2		T308	1
alert_ping_fail	alert[0x24]	9	1			T320	1		T314	1		T313	1
alert_ping_fail	alert[0x25]	8	1			T241	1		T87	1		T318	1
alert_ping_fail	alert[0x26]	10	1			T242	1		T319	1		T318	1
alert_ping_fail	alert[0x27]	5	1			T292	1		T324	1		T315	1
alert_ping_fail	alert[0x28]	17	1			T1	1		T8	1		T10	1
alert_ping_fail	alert[0x29]	8	1			T9	2		T10	1		T311	1
alert_ping_fail	alert[0x2a]	12	1			T241	1		T243	1		T87	1
alert_ping_fail	alert[0x2b]	9	1			T308	1		T242	1		T311	1
alert_ping_fail	alert[0x2c]	18	1			T1	1		T305	1		T309	1
alert_ping_fail	alert[0x2d]	13	1			T10	1		T304	1		T308	1
alert_ping_fail	alert[0x2e]	11	1			T10	2		T241	1		T309	1
alert_ping_fail	alert[0x2f]	13	1			T10	1		T292	1		T319	1
alert_ping_fail	alert[0x30]	13	1			T1	1		T309	1		T308	1
alert_ping_fail	alert[0x31]	7	1			T1	1		T309	1		T308	1
alert_ping_fail	alert[0x32]	14	1			T309	2		T312	1		T319	2
alert_ping_fail	alert[0x33]	10	1			T1	1		T321	1		T314	1
alert_ping_fail	alert[0x34]	7	1			T325	1		T323	1		T235	1
alert_ping_fail	alert[0x35]	8	1			T1	1		T241	1		T292	1
alert_ping_fail	alert[0x36]	5	1			T309	1		T308	1		T314	1
alert_ping_fail	alert[0x37]	8	1			T10	1		T242	1		T52	1
alert_ping_fail	alert[0x38]	9	1			T87	1		T319	1		T320	1
alert_ping_fail	alert[0x39]	8	1			T10	1		T242	1		T312	1
alert_ping_fail	alert[0x3a]	7	1			T87	1		T235	1		T326	1
alert_ping_fail	alert[0x3b]	10	1			T1	1		T307	1		T311	1
alert_ping_fail	alert[0x3c]	8	1			T308	2		T326	1		T327	1
alert_ping_fail	alert[0x3d]	8	1			T241	1		T309	1		T318	1
alert_ping_fail	alert[0x3e]	8	1			T307	1		T52	1		T320	1
alert_ping_fail	alert[0x3f]	4	1			T308	1		T323	1		T313	1
alert_ping_fail	alert[0x40]	6	1			T9	1		T307	1		T328	1

---

Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	class_i[0x0]	191365	1			T3	4		T5	5563		T35	39
alert_integrity_fail	class_i[0x1]	88156	1			T5	3		T60	2		T41	8
alert_integrity_fail	class_i[0x2]	93775	1			T3	7		T94	24		T42	1
alert_integrity_fail	class_i[0x3]	83721	1			T60	2764		T94	7460		T36	1
alert_ping_fail	class_i[0x0]	178	1			T1	1		T8	2		T304	3
alert_ping_fail	class_i[0x1]	221	1			T1	16		T9	14		T10	10
alert_ping_fail	class_i[0x2]	130	1			T85	2		T238	1		T241	10
alert_ping_fail	class_i[0x3]	128	1			T1	4		T10	3		T309	1