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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.69 99.99 98.71 100.00 100.00 100.00 99.38 99.76


Total test records in report: 848
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T774 /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.3340966595 Feb 07 12:43:55 PM PST 24 Feb 07 12:44:00 PM PST 24 74398378 ps
T775 /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.1245227752 Feb 07 12:43:32 PM PST 24 Feb 07 12:45:26 PM PST 24 6801981815 ps
T173 /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.3775027620 Feb 07 12:43:52 PM PST 24 Feb 07 12:51:09 PM PST 24 21832993924 ps
T776 /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.3438305660 Feb 07 12:43:43 PM PST 24 Feb 07 12:43:50 PM PST 24 33636850 ps
T166 /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.2299635846 Feb 07 12:43:33 PM PST 24 Feb 07 12:59:01 PM PST 24 80226564246 ps
T777 /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.3477923903 Feb 07 12:43:40 PM PST 24 Feb 07 12:43:53 PM PST 24 1188264871 ps
T778 /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.1705766371 Feb 07 12:43:32 PM PST 24 Feb 07 12:43:43 PM PST 24 186572290 ps
T779 /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.1708487260 Feb 07 12:44:07 PM PST 24 Feb 07 12:44:30 PM PST 24 170607405 ps
T780 /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.4109177428 Feb 07 12:44:02 PM PST 24 Feb 07 12:44:07 PM PST 24 30985963 ps
T781 /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.792181257 Feb 07 12:43:52 PM PST 24 Feb 07 12:44:01 PM PST 24 253527024 ps
T782 /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.2955197566 Feb 07 12:43:56 PM PST 24 Feb 07 12:43:58 PM PST 24 7316728 ps
T783 /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.1013043261 Feb 07 12:44:09 PM PST 24 Feb 07 12:44:11 PM PST 24 7373212 ps
T784 /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.3843819332 Feb 07 12:44:22 PM PST 24 Feb 07 12:44:25 PM PST 24 8237512 ps
T785 /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.658460917 Feb 07 12:43:29 PM PST 24 Feb 07 12:45:34 PM PST 24 7746184463 ps
T786 /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.1240395491 Feb 07 12:44:24 PM PST 24 Feb 07 12:45:03 PM PST 24 1287428036 ps
T259 /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.1484198231 Feb 07 12:43:59 PM PST 24 Feb 07 12:44:23 PM PST 24 629457495 ps
T787 /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.2786353360 Feb 07 12:44:23 PM PST 24 Feb 07 12:44:29 PM PST 24 87871966 ps
T788 /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.124302173 Feb 07 12:44:25 PM PST 24 Feb 07 12:44:31 PM PST 24 35730255 ps
T789 /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.2255093255 Feb 07 12:44:03 PM PST 24 Feb 07 12:44:16 PM PST 24 360928145 ps
T790 /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.902804185 Feb 07 12:43:45 PM PST 24 Feb 07 12:47:51 PM PST 24 13213220419 ps
T351 /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.1254137127 Feb 07 12:44:13 PM PST 24 Feb 07 01:01:21 PM PST 24 15644926782 ps
T791 /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.1842880857 Feb 07 12:44:22 PM PST 24 Feb 07 12:44:25 PM PST 24 18612147 ps
T792 /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.2805489335 Feb 07 12:44:22 PM PST 24 Feb 07 12:44:25 PM PST 24 19021847 ps
T793 /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.3830918343 Feb 07 12:44:22 PM PST 24 Feb 07 12:45:00 PM PST 24 513503347 ps
T164 /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.1281000874 Feb 07 12:44:17 PM PST 24 Feb 07 12:47:14 PM PST 24 3172826860 ps
T794 /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.282461473 Feb 07 12:43:27 PM PST 24 Feb 07 12:43:34 PM PST 24 13197618 ps
T171 /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.1231645452 Feb 07 12:43:46 PM PST 24 Feb 07 12:47:54 PM PST 24 2252580365 ps
T795 /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.215504254 Feb 07 12:44:20 PM PST 24 Feb 07 12:44:22 PM PST 24 15046193 ps
T796 /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.2543009607 Feb 07 12:44:11 PM PST 24 Feb 07 12:44:18 PM PST 24 28084412 ps
T797 /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.2343207915 Feb 07 12:44:05 PM PST 24 Feb 07 12:44:17 PM PST 24 88229500 ps
T798 /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.4141879265 Feb 07 12:43:56 PM PST 24 Feb 07 12:44:18 PM PST 24 185802547 ps
T799 /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.3620466524 Feb 07 12:44:20 PM PST 24 Feb 07 12:44:23 PM PST 24 8262485 ps
T800 /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.6721230 Feb 07 12:44:02 PM PST 24 Feb 07 12:44:06 PM PST 24 70113488 ps
T801 /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.2534536490 Feb 07 12:44:20 PM PST 24 Feb 07 12:44:22 PM PST 24 10541745 ps
T192 /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.2044563213 Feb 07 12:44:19 PM PST 24 Feb 07 12:44:23 PM PST 24 34589775 ps
T802 /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.1138593146 Feb 07 12:44:12 PM PST 24 Feb 07 12:44:22 PM PST 24 359880638 ps
T803 /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.2670863656 Feb 07 12:43:30 PM PST 24 Feb 07 12:45:24 PM PST 24 837952788 ps
T804 /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.958495605 Feb 07 12:44:19 PM PST 24 Feb 07 12:44:21 PM PST 24 17419650 ps
T805 /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.2736731442 Feb 07 12:44:06 PM PST 24 Feb 07 12:44:16 PM PST 24 71262462 ps
T806 /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.681125204 Feb 07 12:44:24 PM PST 24 Feb 07 12:44:26 PM PST 24 9575255 ps
T177 /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.120361561 Feb 07 12:44:07 PM PST 24 Feb 07 12:47:41 PM PST 24 2374233702 ps
T807 /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.821450462 Feb 07 12:43:58 PM PST 24 Feb 07 12:44:39 PM PST 24 541279770 ps
T808 /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.2291835458 Feb 07 12:43:32 PM PST 24 Feb 07 12:43:37 PM PST 24 26294803 ps
T809 /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.3808568064 Feb 07 12:44:07 PM PST 24 Feb 07 12:44:12 PM PST 24 39926488 ps
T810 /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.1703844505 Feb 07 12:43:49 PM PST 24 Feb 07 12:44:02 PM PST 24 330988054 ps
T178 /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.1373326121 Feb 07 12:43:57 PM PST 24 Feb 07 12:49:53 PM PST 24 5436198059 ps
T350 /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.2886422558 Feb 07 12:43:44 PM PST 24 Feb 07 12:51:08 PM PST 24 5935196579 ps
T811 /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.2089733462 Feb 07 12:44:24 PM PST 24 Feb 07 12:44:27 PM PST 24 10674600 ps
T812 /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.2867529941 Feb 07 12:44:04 PM PST 24 Feb 07 12:44:12 PM PST 24 59737835 ps
T174 /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.2259157996 Feb 07 12:44:05 PM PST 24 Feb 07 01:02:04 PM PST 24 97056244284 ps
T813 /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.3897604429 Feb 07 12:44:28 PM PST 24 Feb 07 12:44:30 PM PST 24 24463775 ps
T814 /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.707854157 Feb 07 12:44:02 PM PST 24 Feb 07 12:44:08 PM PST 24 268752908 ps
T815 /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.4165669435 Feb 07 12:44:28 PM PST 24 Feb 07 12:44:30 PM PST 24 9577673 ps
T816 /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.1032744736 Feb 07 12:44:01 PM PST 24 Feb 07 12:44:12 PM PST 24 290694092 ps
T817 /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.185574155 Feb 07 12:44:05 PM PST 24 Feb 07 12:44:07 PM PST 24 8139290 ps
T818 /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.3098751657 Feb 07 12:44:23 PM PST 24 Feb 07 12:44:26 PM PST 24 8236104 ps
T819 /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.630006821 Feb 07 12:43:35 PM PST 24 Feb 07 12:50:33 PM PST 24 29647558171 ps
T820 /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.2068729035 Feb 07 12:44:19 PM PST 24 Feb 07 12:44:20 PM PST 24 6428734 ps
T821 /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.2072296293 Feb 07 12:44:05 PM PST 24 Feb 07 12:44:10 PM PST 24 142799752 ps
T822 /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.2399293579 Feb 07 12:44:21 PM PST 24 Feb 07 12:44:25 PM PST 24 9979707 ps
T175 /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.3763831241 Feb 07 12:43:51 PM PST 24 Feb 07 12:49:01 PM PST 24 2270523267 ps
T179 /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.1223769786 Feb 07 12:43:28 PM PST 24 Feb 07 12:58:48 PM PST 24 52081640776 ps
T823 /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.3305291321 Feb 07 12:44:24 PM PST 24 Feb 07 12:44:27 PM PST 24 17334795 ps
T824 /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.2433231120 Feb 07 12:43:25 PM PST 24 Feb 07 12:43:34 PM PST 24 52904008 ps
T825 /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.2370065203 Feb 07 12:43:55 PM PST 24 Feb 07 12:44:00 PM PST 24 638258841 ps
T209 /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.3046657239 Feb 07 12:44:26 PM PST 24 Feb 07 12:45:55 PM PST 24 5514483449 ps
T826 /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.3329819599 Feb 07 12:43:47 PM PST 24 Feb 07 12:43:58 PM PST 24 34190186 ps
T827 /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.1705734311 Feb 07 12:44:13 PM PST 24 Feb 07 12:44:18 PM PST 24 117787638 ps
T828 /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.2936493126 Feb 07 12:43:58 PM PST 24 Feb 07 12:44:08 PM PST 24 511193379 ps
T829 /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.1219219620 Feb 07 12:44:21 PM PST 24 Feb 07 12:44:25 PM PST 24 8164639 ps
T830 /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.594037421 Feb 07 12:43:46 PM PST 24 Feb 07 12:44:09 PM PST 24 3179614433 ps
T831 /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.67684162 Feb 07 12:43:35 PM PST 24 Feb 07 12:44:39 PM PST 24 1142845995 ps
T190 /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.1060834018 Feb 07 12:44:03 PM PST 24 Feb 07 12:45:12 PM PST 24 888236810 ps
T832 /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.3578959685 Feb 07 12:44:16 PM PST 24 Feb 07 12:53:47 PM PST 24 33022814191 ps
T833 /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.3528228116 Feb 07 12:44:14 PM PST 24 Feb 07 12:44:58 PM PST 24 659178220 ps
T194 /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.671631792 Feb 07 12:44:21 PM PST 24 Feb 07 12:44:58 PM PST 24 1839330318 ps
T834 /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.2387523312 Feb 07 12:44:21 PM PST 24 Feb 07 12:44:28 PM PST 24 57011491 ps
T352 /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.1690686848 Feb 07 12:44:10 PM PST 24 Feb 07 12:48:41 PM PST 24 4452856519 ps
T835 /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.2396314775 Feb 07 12:43:32 PM PST 24 Feb 07 12:43:57 PM PST 24 469651007 ps
T836 /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.806887270 Feb 07 12:44:24 PM PST 24 Feb 07 12:44:27 PM PST 24 7919203 ps
T837 /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.579156044 Feb 07 12:43:50 PM PST 24 Feb 07 12:43:57 PM PST 24 158228840 ps
T838 /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.2729287070 Feb 07 12:44:13 PM PST 24 Feb 07 12:44:22 PM PST 24 144329057 ps
T191 /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.2868204306 Feb 07 12:43:50 PM PST 24 Feb 07 12:44:40 PM PST 24 1197937496 ps
T839 /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.725771198 Feb 07 12:43:29 PM PST 24 Feb 07 12:43:41 PM PST 24 272565214 ps
T840 /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.3072832894 Feb 07 12:43:33 PM PST 24 Feb 07 12:43:39 PM PST 24 64013366 ps
T841 /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.1678324087 Feb 07 12:44:20 PM PST 24 Feb 07 12:44:29 PM PST 24 496728997 ps
T842 /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.1811092011 Feb 07 12:43:52 PM PST 24 Feb 07 12:44:03 PM PST 24 72686028 ps
T843 /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.1916124374 Feb 07 12:43:46 PM PST 24 Feb 07 12:45:35 PM PST 24 9073916899 ps
T182 /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.3294184213 Feb 07 12:43:47 PM PST 24 Feb 07 12:49:17 PM PST 24 30546105428 ps
T844 /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.3371531771 Feb 07 12:43:34 PM PST 24 Feb 07 12:43:38 PM PST 24 10990847 ps
T845 /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.2415978787 Feb 07 12:43:43 PM PST 24 Feb 07 12:43:52 PM PST 24 93474247 ps
T846 /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.2352101559 Feb 07 12:43:33 PM PST 24 Feb 07 12:47:25 PM PST 24 4466872068 ps
T847 /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.2523487086 Feb 07 12:44:22 PM PST 24 Feb 07 12:44:30 PM PST 24 32081790 ps
T195 /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.1763430481 Feb 07 12:43:45 PM PST 24 Feb 07 12:43:49 PM PST 24 89966543 ps
T180 /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.3386868235 Feb 07 12:43:29 PM PST 24 Feb 07 12:46:48 PM PST 24 1753496536 ps
T181 /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.1441162353 Feb 07 12:44:22 PM PST 24 Feb 07 12:59:26 PM PST 24 25262426098 ps
T848 /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.3862967673 Feb 07 12:44:25 PM PST 24 Feb 07 12:44:28 PM PST 24 19319932 ps
T176 /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.21367385 Feb 07 12:44:04 PM PST 24 Feb 07 12:47:15 PM PST 24 6394418381 ps

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.2791712643
Short name T26
Test name
Test status
Simulation time 321673930 ps
CPU time 20.21 seconds
Started Feb 07 12:44:12 PM PST 24
Finished Feb 07 12:44:33 PM PST 24
Peak memory 239752 kb
Host smart-e7ec2b29-574d-4362-9f66-3f05ad60a47c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2791712643 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_intg_err.2791712643
Directory /workspace/16.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all_with_rand_reset.3131066580
Short name T3
Test name
Test status
Simulation time 14099231021 ps
CPU time 813.46 seconds
Started Feb 07 01:12:41 PM PST 24
Finished Feb 07 01:26:15 PM PST 24
Peak memory 265716 kb
Host smart-aede561a-c229-4a2e-889c-e69c0c03dd2b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131066580 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 40.alert_handler_stress_all_with_rand_reset.3131066580
Directory /workspace/40.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.2949356309
Short name T14
Test name
Test status
Simulation time 10891504 ps
CPU time 1.7 seconds
Started Feb 07 12:44:25 PM PST 24
Finished Feb 07 12:44:28 PM PST 24
Peak memory 235804 kb
Host smart-e60da936-20c1-43aa-9d94-20d3ea59591a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2949356309 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_intr_test.2949356309
Directory /workspace/17.alert_handler_intr_test/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all.253289524
Short name T42
Test name
Test status
Simulation time 60994688001 ps
CPU time 3373.24 seconds
Started Feb 07 01:09:20 PM PST 24
Finished Feb 07 02:05:40 PM PST 24
Peak memory 304736 kb
Host smart-d7b2ff80-24d0-4b4e-859c-600219a1c073
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253289524 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_hand
ler_stress_all.253289524
Directory /workspace/9.alert_handler_stress_all/latest

Test location /workspace/coverage/default/3.alert_handler_sec_cm.2594124645
Short name T11
Test name
Test status
Simulation time 1490968716 ps
CPU time 20.73 seconds
Started Feb 07 01:08:58 PM PST 24
Finished Feb 07 01:09:20 PM PST 24
Peak memory 276516 kb
Host smart-e09c7388-9fdd-4e15-a591-290ebdd79cbd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2594124645 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sec_cm.2594124645
Directory /workspace/3.alert_handler_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.2682078817
Short name T143
Test name
Test status
Simulation time 4516845621 ps
CPU time 295.87 seconds
Started Feb 07 12:43:33 PM PST 24
Finished Feb 07 12:48:32 PM PST 24
Peak memory 264748 kb
Host smart-5c9347b0-fe05-4054-94be-96e76a5917c9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2682078817 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shadow_reg_erro
rs.2682078817
Directory /workspace/2.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/0.alert_handler_lpg.2200512453
Short name T8
Test name
Test status
Simulation time 42544637092 ps
CPU time 2356.93 seconds
Started Feb 07 01:08:51 PM PST 24
Finished Feb 07 01:48:11 PM PST 24
Peak memory 288384 kb
Host smart-362b7c20-38a8-4fe1-9580-44771bd21e20
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2200512453 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg.2200512453
Directory /workspace/0.alert_handler_lpg/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all.2164432840
Short name T4
Test name
Test status
Simulation time 58452388311 ps
CPU time 1239.09 seconds
Started Feb 07 01:09:31 PM PST 24
Finished Feb 07 01:30:11 PM PST 24
Peak memory 289440 kb
Host smart-b1ec232d-4000-49e9-bf32-fe7798fdb638
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164432840 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_ha
ndler_stress_all.2164432840
Directory /workspace/13.alert_handler_stress_all/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all.4187630302
Short name T39
Test name
Test status
Simulation time 167206542219 ps
CPU time 2576.64 seconds
Started Feb 07 01:09:58 PM PST 24
Finished Feb 07 01:52:56 PM PST 24
Peak memory 289456 kb
Host smart-19dd4d6f-9ad8-4bbe-adb8-59c7b288bf52
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187630302 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_ha
ndler_stress_all.4187630302
Directory /workspace/18.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.3210357191
Short name T148
Test name
Test status
Simulation time 66089977378 ps
CPU time 586.23 seconds
Started Feb 07 12:44:03 PM PST 24
Finished Feb 07 12:53:50 PM PST 24
Peak memory 264472 kb
Host smart-644c55bb-0896-41e4-a3d2-dc9665f08399
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210357191 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.alert_handler_shadow_reg_errors_with_csr_rw.3210357191
Directory /workspace/9.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.3689168429
Short name T149
Test name
Test status
Simulation time 57790944054 ps
CPU time 933.14 seconds
Started Feb 07 12:44:18 PM PST 24
Finished Feb 07 12:59:52 PM PST 24
Peak memory 264884 kb
Host smart-aa554461-b06c-4a57-91d9-c7d97bd73347
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689168429 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 19.alert_handler_shadow_reg_errors_with_csr_rw.3689168429
Directory /workspace/19.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/31.alert_handler_ping_timeout.1226211987
Short name T1
Test name
Test status
Simulation time 25653620947 ps
CPU time 546.87 seconds
Started Feb 07 01:11:19 PM PST 24
Finished Feb 07 01:20:27 PM PST 24
Peak memory 246408 kb
Host smart-b64e2a5a-5062-4be6-8f12-db2329842a58
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226211987 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_ping_timeout.1226211987
Directory /workspace/31.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all_with_rand_reset.2643824358
Short name T60
Test name
Test status
Simulation time 508184121037 ps
CPU time 3129.73 seconds
Started Feb 07 01:13:30 PM PST 24
Finished Feb 07 02:05:44 PM PST 24
Peak memory 305652 kb
Host smart-07c08a89-b0b5-4194-87e4-c6554cdd4d66
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643824358 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 42.alert_handler_stress_all_with_rand_reset.2643824358
Directory /workspace/42.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.1692168500
Short name T28
Test name
Test status
Simulation time 67243587100 ps
CPU time 1046.05 seconds
Started Feb 07 12:43:56 PM PST 24
Finished Feb 07 01:01:24 PM PST 24
Peak memory 264888 kb
Host smart-82bf91e2-65c5-41cf-8650-ce967e611673
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692168500 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 14.alert_handler_shadow_reg_errors_with_csr_rw.1692168500
Directory /workspace/14.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/9.alert_handler_lpg.2047816521
Short name T238
Test name
Test status
Simulation time 60951832012 ps
CPU time 1625.57 seconds
Started Feb 07 01:09:17 PM PST 24
Finished Feb 07 01:36:28 PM PST 24
Peak memory 264948 kb
Host smart-4963f318-0784-4446-8da3-7b65776797dc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047816521 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg.2047816521
Directory /workspace/9.alert_handler_lpg/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all_with_rand_reset.3382071254
Short name T108
Test name
Test status
Simulation time 440804546380 ps
CPU time 7571.61 seconds
Started Feb 07 01:08:51 PM PST 24
Finished Feb 07 03:15:07 PM PST 24
Peak memory 354532 kb
Host smart-ba1dfe97-b77e-48a0-a156-0adf3ac01974
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382071254 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.alert_handler_stress_all_with_rand_reset.3382071254
Directory /workspace/1.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.165129519
Short name T165
Test name
Test status
Simulation time 15501691986 ps
CPU time 308.53 seconds
Started Feb 07 12:43:48 PM PST 24
Finished Feb 07 12:49:00 PM PST 24
Peak memory 264652 kb
Host smart-5370efdb-39d0-4489-920d-ba3bb31d53ab
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=165129519 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shadow_reg_error
s.165129519
Directory /workspace/5.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.334884
Short name T196
Test name
Test status
Simulation time 1107023669 ps
CPU time 70.24 seconds
Started Feb 07 12:43:51 PM PST 24
Finished Feb 07 12:45:03 PM PST 24
Peak memory 244192 kb
Host smart-0819e6ac-a608-4190-809a-19240e6dc9e7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=334884 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_intg_err.334884
Directory /workspace/6.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/11.alert_handler_lpg.2453839986
Short name T85
Test name
Test status
Simulation time 184068081744 ps
CPU time 2531.64 seconds
Started Feb 07 01:09:15 PM PST 24
Finished Feb 07 01:51:33 PM PST 24
Peak memory 283820 kb
Host smart-a4f568f0-118d-47b9-883e-ccf3a0fd3b63
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453839986 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg.2453839986
Directory /workspace/11.alert_handler_lpg/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all_with_rand_reset.3877341238
Short name T70
Test name
Test status
Simulation time 20365437328 ps
CPU time 2116.23 seconds
Started Feb 07 01:09:04 PM PST 24
Finished Feb 07 01:44:21 PM PST 24
Peak memory 289656 kb
Host smart-8ae58fc6-b34f-4893-abc4-f951fabe4ab6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877341238 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 6.alert_handler_stress_all_with_rand_reset.3877341238
Directory /workspace/6.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.alert_handler_ping_timeout.2253105544
Short name T242
Test name
Test status
Simulation time 62793889554 ps
CPU time 614.95 seconds
Started Feb 07 01:11:22 PM PST 24
Finished Feb 07 01:21:39 PM PST 24
Peak memory 247220 kb
Host smart-1c8b41ae-407c-4d39-a2e1-1e5e92165f7d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253105544 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_ping_timeout.2253105544
Directory /workspace/32.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.2342489516
Short name T163
Test name
Test status
Simulation time 69688595849 ps
CPU time 1245.72 seconds
Started Feb 07 12:43:47 PM PST 24
Finished Feb 07 01:04:37 PM PST 24
Peak memory 271344 kb
Host smart-cc1c06ed-1769-49d6-95be-1d6956e0a84b
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342489516 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.alert_handler_shadow_reg_errors_with_csr_rw.2342489516
Directory /workspace/4.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all.1091629483
Short name T94
Test name
Test status
Simulation time 80013185683 ps
CPU time 4594.1 seconds
Started Feb 07 01:12:02 PM PST 24
Finished Feb 07 02:28:37 PM PST 24
Peak memory 305172 kb
Host smart-0ea16a90-ea3c-468c-bf1e-a8ba112223cd
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091629483 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_ha
ndler_stress_all.1091629483
Directory /workspace/35.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.2299635846
Short name T166
Test name
Test status
Simulation time 80226564246 ps
CPU time 924.46 seconds
Started Feb 07 12:43:33 PM PST 24
Finished Feb 07 12:59:01 PM PST 24
Peak memory 264804 kb
Host smart-1f1c3630-6198-4421-a44b-2b66cf499331
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299635846 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.alert_handler_shadow_reg_errors_with_csr_rw.2299635846
Directory /workspace/0.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/13.alert_handler_lpg.4152491565
Short name T88
Test name
Test status
Simulation time 126475911964 ps
CPU time 1643.69 seconds
Started Feb 07 01:09:40 PM PST 24
Finished Feb 07 01:37:05 PM PST 24
Peak memory 271116 kb
Host smart-e1481690-eded-42f7-b2f8-c1696dbc7013
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152491565 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg.4152491565
Directory /workspace/13.alert_handler_lpg/latest

Test location /workspace/coverage/default/12.alert_handler_ping_timeout.2318792205
Short name T9
Test name
Test status
Simulation time 148475178599 ps
CPU time 388.78 seconds
Started Feb 07 01:09:41 PM PST 24
Finished Feb 07 01:16:11 PM PST 24
Peak memory 247352 kb
Host smart-98bf824d-ddec-42f4-b363-8c70c0d03037
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318792205 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_ping_timeout.2318792205
Directory /workspace/12.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_lpg.3219782894
Short name T347
Test name
Test status
Simulation time 153453246829 ps
CPU time 2185.78 seconds
Started Feb 07 01:09:40 PM PST 24
Finished Feb 07 01:46:07 PM PST 24
Peak memory 286036 kb
Host smart-02ba89a2-2e1d-4ae0-a542-e56e90423dc4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219782894 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg.3219782894
Directory /workspace/16.alert_handler_lpg/latest

Test location /workspace/coverage/default/3.alert_handler_ping_timeout.3631096960
Short name T726
Test name
Test status
Simulation time 30866766030 ps
CPU time 581.86 seconds
Started Feb 07 01:08:59 PM PST 24
Finished Feb 07 01:18:42 PM PST 24
Peak memory 247332 kb
Host smart-2af5e93f-178f-4c77-b27f-838ac08325d3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631096960 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_ping_timeout.3631096960
Directory /workspace/3.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all.3328495202
Short name T127
Test name
Test status
Simulation time 158749878488 ps
CPU time 2381.35 seconds
Started Feb 07 01:09:27 PM PST 24
Finished Feb 07 01:49:10 PM PST 24
Peak memory 289212 kb
Host smart-f4f0ffd5-86c7-4e8e-aff6-c589beae3ebc
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328495202 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_ha
ndler_stress_all.3328495202
Directory /workspace/11.alert_handler_stress_all/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all_with_rand_reset.727485457
Short name T73
Test name
Test status
Simulation time 34459198415 ps
CPU time 2338.36 seconds
Started Feb 07 01:10:34 PM PST 24
Finished Feb 07 01:49:33 PM PST 24
Peak memory 289644 kb
Host smart-59c9b1ad-92b6-4463-8f41-6197f6fbc31e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727485457 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 26.alert_handler_stress_all_with_rand_reset.727485457
Directory /workspace/26.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.2259157996
Short name T174
Test name
Test status
Simulation time 97056244284 ps
CPU time 1078.93 seconds
Started Feb 07 12:44:05 PM PST 24
Finished Feb 07 01:02:04 PM PST 24
Peak memory 264620 kb
Host smart-97e9f6b5-f655-4f96-b4b2-ec9c19734dc6
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259157996 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 12.alert_handler_shadow_reg_errors_with_csr_rw.2259157996
Directory /workspace/12.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all_with_rand_reset.418465299
Short name T264
Test name
Test status
Simulation time 360140164289 ps
CPU time 5573.67 seconds
Started Feb 07 01:09:44 PM PST 24
Finished Feb 07 02:42:39 PM PST 24
Peak memory 305192 kb
Host smart-da0be81a-bce5-4184-8e13-36a66bf10257
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418465299 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 16.alert_handler_stress_all_with_rand_reset.418465299
Directory /workspace/16.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.alert_handler_ping_timeout.2803673736
Short name T309
Test name
Test status
Simulation time 33942208654 ps
CPU time 361.12 seconds
Started Feb 07 01:09:21 PM PST 24
Finished Feb 07 01:15:28 PM PST 24
Peak memory 246460 kb
Host smart-d3e529d8-e380-4e8d-9f86-d6f2693d3910
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803673736 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_ping_timeout.2803673736
Directory /workspace/11.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.1182910787
Short name T150
Test name
Test status
Simulation time 12407567219 ps
CPU time 902.99 seconds
Started Feb 07 12:43:51 PM PST 24
Finished Feb 07 12:58:55 PM PST 24
Peak memory 264780 kb
Host smart-a1bd1d86-f9d1-4186-8f29-f441542a78fb
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182910787 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.alert_handler_shadow_reg_errors_with_csr_rw.1182910787
Directory /workspace/8.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.920314374
Short name T201
Test name
Test status
Simulation time 11776104 ps
CPU time 1.42 seconds
Started Feb 07 12:43:57 PM PST 24
Finished Feb 07 12:44:00 PM PST 24
Peak memory 235776 kb
Host smart-a3e4f5a6-8318-4859-acbf-b40c9a869e37
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=920314374 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_intr_test.920314374
Directory /workspace/10.alert_handler_intr_test/latest

Test location /workspace/coverage/default/20.alert_handler_lpg.1289802627
Short name T306
Test name
Test status
Simulation time 30755880102 ps
CPU time 1714.97 seconds
Started Feb 07 01:10:14 PM PST 24
Finished Feb 07 01:38:50 PM PST 24
Peak memory 272596 kb
Host smart-91c884ed-aded-491c-a3fe-0cd4935f9135
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289802627 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg.1289802627
Directory /workspace/20.alert_handler_lpg/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all_with_rand_reset.1836871037
Short name T133
Test name
Test status
Simulation time 135771420173 ps
CPU time 4820.27 seconds
Started Feb 07 01:11:21 PM PST 24
Finished Feb 07 02:31:42 PM PST 24
Peak memory 304520 kb
Host smart-efd35fb0-c9e1-4861-a14d-261ddfd4e08e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836871037 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 31.alert_handler_stress_all_with_rand_reset.1836871037
Directory /workspace/31.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.1238215686
Short name T160
Test name
Test status
Simulation time 2024988923 ps
CPU time 150.91 seconds
Started Feb 07 12:44:22 PM PST 24
Finished Feb 07 12:46:54 PM PST 24
Peak memory 256316 kb
Host smart-92e1e879-8f45-459b-b1e6-b44320e6b51c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1238215686 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shadow_reg_err
ors.1238215686
Directory /workspace/18.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/26.alert_handler_ping_timeout.908128496
Short name T235
Test name
Test status
Simulation time 131065077606 ps
CPU time 389.83 seconds
Started Feb 07 01:10:34 PM PST 24
Finished Feb 07 01:17:04 PM PST 24
Peak memory 247304 kb
Host smart-a139e5bc-82e9-4b88-aac0-b8956c2917cf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908128496 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_ping_timeout.908128496
Directory /workspace/26.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all.3105919565
Short name T286
Test name
Test status
Simulation time 235142778943 ps
CPU time 3343.52 seconds
Started Feb 07 01:12:04 PM PST 24
Finished Feb 07 02:07:49 PM PST 24
Peak memory 289016 kb
Host smart-6e9205be-2335-4786-9ef4-6e7c1add35e7
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105919565 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_ha
ndler_stress_all.3105919565
Directory /workspace/34.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.2297651128
Short name T187
Test name
Test status
Simulation time 121820682 ps
CPU time 6.65 seconds
Started Feb 07 12:44:10 PM PST 24
Finished Feb 07 12:44:17 PM PST 24
Peak memory 236796 kb
Host smart-4ef59b7c-3842-4f8f-bd0a-45ca24796a7c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2297651128 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_intg_err.2297651128
Directory /workspace/15.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.2215872904
Short name T153
Test name
Test status
Simulation time 11613321180 ps
CPU time 187.37 seconds
Started Feb 07 12:43:56 PM PST 24
Finished Feb 07 12:47:04 PM PST 24
Peak memory 264740 kb
Host smart-36869c97-2470-4f36-9072-f4214dbc2760
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2215872904 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shadow_reg_erro
rs.2215872904
Directory /workspace/8.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/10.alert_handler_lpg.4280179588
Short name T334
Test name
Test status
Simulation time 151238228764 ps
CPU time 2365.56 seconds
Started Feb 07 01:09:17 PM PST 24
Finished Feb 07 01:48:48 PM PST 24
Peak memory 288692 kb
Host smart-4df85480-268a-4507-8d70-0239f992062e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280179588 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg.4280179588
Directory /workspace/10.alert_handler_lpg/latest

Test location /workspace/coverage/default/19.alert_handler_ping_timeout.306824957
Short name T316
Test name
Test status
Simulation time 13917468894 ps
CPU time 573.58 seconds
Started Feb 07 01:10:06 PM PST 24
Finished Feb 07 01:19:40 PM PST 24
Peak memory 247440 kb
Host smart-eac38aab-f188-408c-9d72-4a33094de5b9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306824957 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_ping_timeout.306824957
Directory /workspace/19.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all.1429330111
Short name T118
Test name
Test status
Simulation time 51879132373 ps
CPU time 2500.44 seconds
Started Feb 07 01:11:20 PM PST 24
Finished Feb 07 01:53:02 PM PST 24
Peak memory 289080 kb
Host smart-64423c3c-59e7-42b9-9321-236f68948f85
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429330111 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_ha
ndler_stress_all.1429330111
Directory /workspace/30.alert_handler_stress_all/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all.2244447647
Short name T110
Test name
Test status
Simulation time 32582743044 ps
CPU time 1772.77 seconds
Started Feb 07 01:11:24 PM PST 24
Finished Feb 07 01:40:58 PM PST 24
Peak memory 272836 kb
Host smart-bb29dba8-fc93-43d5-9ee3-2eb27acc2177
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244447647 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_ha
ndler_stress_all.2244447647
Directory /workspace/31.alert_handler_stress_all/latest

Test location /workspace/coverage/default/8.alert_handler_lpg.3206068132
Short name T81
Test name
Test status
Simulation time 151480737461 ps
CPU time 1991.99 seconds
Started Feb 07 01:09:15 PM PST 24
Finished Feb 07 01:42:33 PM PST 24
Peak memory 288468 kb
Host smart-5804004d-e7f3-4eaa-8551-b0fc683781c9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206068132 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg.3206068132
Directory /workspace/8.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.21367385
Short name T176
Test name
Test status
Simulation time 6394418381 ps
CPU time 190.06 seconds
Started Feb 07 12:44:04 PM PST 24
Finished Feb 07 12:47:15 PM PST 24
Peak memory 270892 kb
Host smart-1fbf8cfe-7175-46a1-bbb9-1b7f4ebe311d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=21367385 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shadow_reg_error
s.21367385
Directory /workspace/12.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/0.alert_handler_alert_accum_saturation.2729476744
Short name T83
Test name
Test status
Simulation time 124502065 ps
CPU time 2.57 seconds
Started Feb 07 01:08:51 PM PST 24
Finished Feb 07 01:08:57 PM PST 24
Peak memory 248676 kb
Host smart-969f76bc-a09c-42d4-8445-0f825d7c16ef
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2729476744 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_alert_accum_saturation.2729476744
Directory /workspace/0.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/1.alert_handler_alert_accum_saturation.3456307793
Short name T215
Test name
Test status
Simulation time 57414760 ps
CPU time 2.32 seconds
Started Feb 07 01:08:53 PM PST 24
Finished Feb 07 01:08:57 PM PST 24
Peak memory 248584 kb
Host smart-47d48066-6f49-409f-9625-c36b89efe326
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3456307793 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_alert_accum_saturation.3456307793
Directory /workspace/1.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/12.alert_handler_alert_accum_saturation.2018872030
Short name T226
Test name
Test status
Simulation time 133377196 ps
CPU time 3.08 seconds
Started Feb 07 01:09:32 PM PST 24
Finished Feb 07 01:09:36 PM PST 24
Peak memory 248672 kb
Host smart-90b661d7-9f13-4e58-b04d-2a04136a80eb
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2018872030 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_alert_accum_saturation.2018872030
Directory /workspace/12.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/13.alert_handler_alert_accum_saturation.2624701894
Short name T221
Test name
Test status
Simulation time 21711818 ps
CPU time 2.93 seconds
Started Feb 07 01:09:30 PM PST 24
Finished Feb 07 01:09:34 PM PST 24
Peak memory 248652 kb
Host smart-f7f50b10-de12-4819-b012-b6a6102c1ceb
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2624701894 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_alert_accum_saturation.2624701894
Directory /workspace/13.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.166297730
Short name T202
Test name
Test status
Simulation time 11113934 ps
CPU time 1.6 seconds
Started Feb 07 12:44:26 PM PST 24
Finished Feb 07 12:44:28 PM PST 24
Peak memory 234864 kb
Host smart-916e2646-7360-4e0b-ae93-b377e5399a69
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=166297730 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.alert_handler_intr_test.166297730
Directory /workspace/21.alert_handler_intr_test/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all_with_rand_reset.2802991927
Short name T274
Test name
Test status
Simulation time 78646924725 ps
CPU time 4824.58 seconds
Started Feb 07 01:08:52 PM PST 24
Finished Feb 07 02:29:19 PM PST 24
Peak memory 305516 kb
Host smart-aa1247f8-4881-4a4b-bcef-457995f1b032
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802991927 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.alert_handler_stress_all_with_rand_reset.2802991927
Directory /workspace/0.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.alert_handler_random_classes.2535987478
Short name T23
Test name
Test status
Simulation time 12913235394 ps
CPU time 46.42 seconds
Started Feb 07 01:09:41 PM PST 24
Finished Feb 07 01:10:29 PM PST 24
Peak memory 254748 kb
Host smart-d327dd72-3eb1-4737-9a76-87f48691be27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25359
87478 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_classes.2535987478
Directory /workspace/16.alert_handler_random_classes/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all.2197973134
Short name T271
Test name
Test status
Simulation time 131040861596 ps
CPU time 2356.31 seconds
Started Feb 07 01:11:07 PM PST 24
Finished Feb 07 01:50:25 PM PST 24
Peak memory 286468 kb
Host smart-4c839aef-99da-4cb9-8124-a878664c9c60
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197973134 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_ha
ndler_stress_all.2197973134
Directory /workspace/29.alert_handler_stress_all/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all_with_rand_reset.1231298471
Short name T265
Test name
Test status
Simulation time 230438086335 ps
CPU time 3899.7 seconds
Started Feb 07 01:12:01 PM PST 24
Finished Feb 07 02:17:02 PM PST 24
Peak memory 305960 kb
Host smart-232784c5-7867-4690-aa5c-08b312efd071
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231298471 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.alert_handler_stress_all_with_rand_reset.1231298471
Directory /workspace/34.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all_with_rand_reset.2058675535
Short name T280
Test name
Test status
Simulation time 49933376513 ps
CPU time 2267.22 seconds
Started Feb 07 01:09:00 PM PST 24
Finished Feb 07 01:46:48 PM PST 24
Peak memory 285816 kb
Host smart-89427aaf-19a9-47d3-846f-db3492e4973e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058675535 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.alert_handler_stress_all_with_rand_reset.2058675535
Directory /workspace/4.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.alert_handler_lpg.3638983365
Short name T53
Test name
Test status
Simulation time 9789936730 ps
CPU time 962.95 seconds
Started Feb 07 01:12:41 PM PST 24
Finished Feb 07 01:28:45 PM PST 24
Peak memory 272828 kb
Host smart-6e707b88-a9b9-4857-aeb9-5f23b43324b3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638983365 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg.3638983365
Directory /workspace/40.alert_handler_lpg/latest

Test location /workspace/coverage/default/41.alert_handler_sig_int_fail.1820625256
Short name T261
Test name
Test status
Simulation time 634973295 ps
CPU time 40.64 seconds
Started Feb 07 01:13:26 PM PST 24
Finished Feb 07 01:14:09 PM PST 24
Peak memory 248404 kb
Host smart-e878eab7-a8fb-44e9-a8aa-f689d6e17b60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18206
25256 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_sig_int_fail.1820625256
Directory /workspace/41.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/43.alert_handler_random_classes.2732119813
Short name T288
Test name
Test status
Simulation time 2231629077 ps
CPU time 60.6 seconds
Started Feb 07 01:13:43 PM PST 24
Finished Feb 07 01:14:45 PM PST 24
Peak memory 254932 kb
Host smart-cd8d30b6-a2b3-4798-8617-36b71513167c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27321
19813 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_classes.2732119813
Directory /workspace/43.alert_handler_random_classes/latest

Test location /workspace/coverage/default/45.alert_handler_random_alerts.2664812945
Short name T299
Test name
Test status
Simulation time 318697406 ps
CPU time 10.83 seconds
Started Feb 07 01:14:02 PM PST 24
Finished Feb 07 01:14:13 PM PST 24
Peak memory 248376 kb
Host smart-da065c5c-5783-432e-8f0c-84fbb352763c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26648
12945 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_alerts.2664812945
Directory /workspace/45.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all_with_rand_reset.3959132803
Short name T125
Test name
Test status
Simulation time 405408116146 ps
CPU time 6673.76 seconds
Started Feb 07 01:14:00 PM PST 24
Finished Feb 07 03:05:15 PM PST 24
Peak memory 322388 kb
Host smart-746e488f-5a38-439c-989d-1c4846bade16
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959132803 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 46.alert_handler_stress_all_with_rand_reset.3959132803
Directory /workspace/46.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.alert_handler_ping_timeout.3393178620
Short name T318
Test name
Test status
Simulation time 185220183978 ps
CPU time 615.12 seconds
Started Feb 07 01:09:20 PM PST 24
Finished Feb 07 01:19:38 PM PST 24
Peak memory 246740 kb
Host smart-410f5a3a-c5ef-4e76-b105-908524448648
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393178620 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_ping_timeout.3393178620
Directory /workspace/9.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.1441162353
Short name T181
Test name
Test status
Simulation time 25262426098 ps
CPU time 901.98 seconds
Started Feb 07 12:44:22 PM PST 24
Finished Feb 07 12:59:26 PM PST 24
Peak memory 264684 kb
Host smart-18fef20e-883e-4e82-8f19-41793f26822f
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441162353 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 18.alert_handler_shadow_reg_errors_with_csr_rw.1441162353
Directory /workspace/18.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.3046657239
Short name T209
Test name
Test status
Simulation time 5514483449 ps
CPU time 87.4 seconds
Started Feb 07 12:44:26 PM PST 24
Finished Feb 07 12:45:55 PM PST 24
Peak memory 255208 kb
Host smart-fabf915e-457f-4bec-9407-7cd01ec404be
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3046657239 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shadow_reg_err
ors.3046657239
Directory /workspace/19.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all_with_rand_reset.3286851252
Short name T33
Test name
Test status
Simulation time 229979051190 ps
CPU time 2581.65 seconds
Started Feb 07 01:14:03 PM PST 24
Finished Feb 07 01:57:05 PM PST 24
Peak memory 288320 kb
Host smart-6bf634ef-e742-4dab-ae19-92360270c01b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286851252 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 44.alert_handler_stress_all_with_rand_reset.3286851252
Directory /workspace/44.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.3619870467
Short name T772
Test name
Test status
Simulation time 58032751 ps
CPU time 1.42 seconds
Started Feb 07 12:44:12 PM PST 24
Finished Feb 07 12:44:15 PM PST 24
Peak memory 235636 kb
Host smart-07c54487-8885-4353-af03-87a02d556d56
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3619870467 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_intr_test.3619870467
Directory /workspace/12.alert_handler_intr_test/latest

Test location /workspace/coverage/default/1.alert_handler_ping_timeout.2481785129
Short name T308
Test name
Test status
Simulation time 33049439988 ps
CPU time 352.46 seconds
Started Feb 07 01:08:50 PM PST 24
Finished Feb 07 01:14:47 PM PST 24
Peak memory 247440 kb
Host smart-7a2ca521-de55-427f-91e8-ba1c53d75164
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481785129 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_ping_timeout.2481785129
Directory /workspace/1.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all.2088665685
Short name T303
Test name
Test status
Simulation time 65633870438 ps
CPU time 1251.64 seconds
Started Feb 07 01:09:33 PM PST 24
Finished Feb 07 01:30:25 PM PST 24
Peak memory 289512 kb
Host smart-8097a316-b9d7-4372-8eb0-a1d15d654ce6
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088665685 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_ha
ndler_stress_all.2088665685
Directory /workspace/12.alert_handler_stress_all/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all_with_rand_reset.2651110670
Short name T278
Test name
Test status
Simulation time 60414973296 ps
CPU time 5464.17 seconds
Started Feb 07 01:09:30 PM PST 24
Finished Feb 07 02:40:35 PM PST 24
Peak memory 338800 kb
Host smart-2f30164e-e567-4031-94b8-502c0eaf0434
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651110670 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.alert_handler_stress_all_with_rand_reset.2651110670
Directory /workspace/12.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all_with_rand_reset.2892941666
Short name T255
Test name
Test status
Simulation time 65424370727 ps
CPU time 1060.75 seconds
Started Feb 07 01:09:38 PM PST 24
Finished Feb 07 01:27:19 PM PST 24
Peak memory 285652 kb
Host smart-3beeab51-0cd7-4815-b890-051f4f7de3d8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892941666 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 14.alert_handler_stress_all_with_rand_reset.2892941666
Directory /workspace/14.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all_with_rand_reset.3001461496
Short name T480
Test name
Test status
Simulation time 503556496564 ps
CPU time 3652.48 seconds
Started Feb 07 01:09:40 PM PST 24
Finished Feb 07 02:10:34 PM PST 24
Peak memory 305268 kb
Host smart-65bbcaa6-3f7b-4114-bdd6-77580d323b4b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001461496 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.alert_handler_stress_all_with_rand_reset.3001461496
Directory /workspace/15.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all_with_rand_reset.3541640090
Short name T284
Test name
Test status
Simulation time 808425343736 ps
CPU time 5009.8 seconds
Started Feb 07 01:10:17 PM PST 24
Finished Feb 07 02:33:48 PM PST 24
Peak memory 338372 kb
Host smart-280147d0-8e1b-4cca-967a-e54a5850d8d4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541640090 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 20.alert_handler_stress_all_with_rand_reset.3541640090
Directory /workspace/20.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.alert_handler_lpg.1967549210
Short name T140
Test name
Test status
Simulation time 22696635136 ps
CPU time 972.82 seconds
Started Feb 07 01:10:29 PM PST 24
Finished Feb 07 01:26:43 PM PST 24
Peak memory 272996 kb
Host smart-a11d7850-e1ea-4704-98be-4229210bd4a8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967549210 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg.1967549210
Directory /workspace/23.alert_handler_lpg/latest

Test location /workspace/coverage/default/35.alert_handler_sig_int_fail.3120244917
Short name T36
Test name
Test status
Simulation time 1191570686 ps
CPU time 67.67 seconds
Started Feb 07 01:12:00 PM PST 24
Finished Feb 07 01:13:09 PM PST 24
Peak memory 254208 kb
Host smart-7420bc92-4a72-4941-912c-e4df14219437
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31202
44917 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_sig_int_fail.3120244917
Directory /workspace/35.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/13.alert_handler_entropy.1258497165
Short name T128
Test name
Test status
Simulation time 99619333767 ps
CPU time 1375.11 seconds
Started Feb 07 01:09:29 PM PST 24
Finished Feb 07 01:32:25 PM PST 24
Peak memory 283668 kb
Host smart-c1397ab6-a8a7-4eeb-b975-605f7a481b03
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258497165 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy.1258497165
Directory /workspace/13.alert_handler_entropy/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all_with_rand_reset.1791832543
Short name T115
Test name
Test status
Simulation time 12825106104 ps
CPU time 882.35 seconds
Started Feb 07 01:12:06 PM PST 24
Finished Feb 07 01:26:49 PM PST 24
Peak memory 273236 kb
Host smart-5d865368-273f-46ae-8b78-af985c344f80
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791832543 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 37.alert_handler_stress_all_with_rand_reset.1791832543
Directory /workspace/37.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.1355911660
Short name T170
Test name
Test status
Simulation time 1495774042 ps
CPU time 39.68 seconds
Started Feb 07 12:44:20 PM PST 24
Finished Feb 07 12:45:00 PM PST 24
Peak memory 239756 kb
Host smart-5b9c57ab-65a2-4cfe-8140-879425d1c605
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1355911660 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_intg_err.1355911660
Directory /workspace/19.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.378848583
Short name T189
Test name
Test status
Simulation time 259274309 ps
CPU time 4.09 seconds
Started Feb 07 12:44:02 PM PST 24
Finished Feb 07 12:44:07 PM PST 24
Peak memory 235856 kb
Host smart-060839e8-1b0a-43e3-b125-b0897c55799e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=378848583 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_intg_err.378848583
Directory /workspace/12.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.4144627208
Short name T155
Test name
Test status
Simulation time 44721611826 ps
CPU time 336.77 seconds
Started Feb 07 12:43:48 PM PST 24
Finished Feb 07 12:49:28 PM PST 24
Peak memory 271632 kb
Host smart-e457a25b-6fb0-4e73-b88d-d878f04137e6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4144627208 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shadow_reg_erro
rs.4144627208
Directory /workspace/6.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.671631792
Short name T194
Test name
Test status
Simulation time 1839330318 ps
CPU time 35.54 seconds
Started Feb 07 12:44:21 PM PST 24
Finished Feb 07 12:44:58 PM PST 24
Peak memory 239752 kb
Host smart-90698281-aa85-4f25-b6e3-b32823132934
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=671631792 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_intg_err.671631792
Directory /workspace/17.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.2864861034
Short name T188
Test name
Test status
Simulation time 248703535 ps
CPU time 3.77 seconds
Started Feb 07 12:43:44 PM PST 24
Finished Feb 07 12:43:49 PM PST 24
Peak memory 236672 kb
Host smart-d51b2a03-bb82-4e89-87ef-34fdb7d73403
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2864861034 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_intg_err.2864861034
Directory /workspace/2.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.143731253
Short name T193
Test name
Test status
Simulation time 93488385 ps
CPU time 3.99 seconds
Started Feb 07 12:43:40 PM PST 24
Finished Feb 07 12:43:45 PM PST 24
Peak memory 234872 kb
Host smart-161d93bc-702c-4c93-bc42-a783b58c21f3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=143731253 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_intg_err.143731253
Directory /workspace/0.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.1846805407
Short name T199
Test name
Test status
Simulation time 406590559 ps
CPU time 2.62 seconds
Started Feb 07 12:44:05 PM PST 24
Finished Feb 07 12:44:08 PM PST 24
Peak memory 235984 kb
Host smart-1cdd0c36-259c-4a4a-bbf5-fe1d61abb360
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1846805407 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_intg_err.1846805407
Directory /workspace/10.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.249903316
Short name T197
Test name
Test status
Simulation time 342658861 ps
CPU time 3.4 seconds
Started Feb 07 12:43:46 PM PST 24
Finished Feb 07 12:43:54 PM PST 24
Peak memory 236220 kb
Host smart-7b6cc3d9-1e32-49ee-984b-5c8d2aca21a5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=249903316 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_intg_err.249903316
Directory /workspace/4.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.1060834018
Short name T190
Test name
Test status
Simulation time 888236810 ps
CPU time 68.1 seconds
Started Feb 07 12:44:03 PM PST 24
Finished Feb 07 12:45:12 PM PST 24
Peak memory 238796 kb
Host smart-16c4fbff-7a82-4b8c-9823-55274e6341db
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1060834018 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_intg_err.1060834018
Directory /workspace/8.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.194921421
Short name T200
Test name
Test status
Simulation time 36618364 ps
CPU time 2.31 seconds
Started Feb 07 12:43:40 PM PST 24
Finished Feb 07 12:43:43 PM PST 24
Peak memory 236220 kb
Host smart-d3ff03cf-9058-4137-b79c-43b6c3da8dfc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=194921421 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_intg_err.194921421
Directory /workspace/1.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.975772214
Short name T198
Test name
Test status
Simulation time 37436953 ps
CPU time 2.5 seconds
Started Feb 07 12:44:12 PM PST 24
Finished Feb 07 12:44:15 PM PST 24
Peak memory 235780 kb
Host smart-616783e6-262e-491b-a2c6-747006448643
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=975772214 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_intg_err.975772214
Directory /workspace/14.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.2044563213
Short name T192
Test name
Test status
Simulation time 34589775 ps
CPU time 2.43 seconds
Started Feb 07 12:44:19 PM PST 24
Finished Feb 07 12:44:23 PM PST 24
Peak memory 235748 kb
Host smart-63bdd757-5b35-4e36-81d9-d04a15a1361c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2044563213 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_intg_err.2044563213
Directory /workspace/18.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.2868204306
Short name T191
Test name
Test status
Simulation time 1197937496 ps
CPU time 48.27 seconds
Started Feb 07 12:43:50 PM PST 24
Finished Feb 07 12:44:40 PM PST 24
Peak memory 238724 kb
Host smart-a6ceecf1-f017-4900-9164-e1587f11078d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2868204306 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_intg_err.2868204306
Directory /workspace/5.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/26.alert_handler_random_alerts.3457099024
Short name T37
Test name
Test status
Simulation time 3925842192 ps
CPU time 33.48 seconds
Started Feb 07 01:10:35 PM PST 24
Finished Feb 07 01:11:09 PM PST 24
Peak memory 248496 kb
Host smart-a35641bf-f153-42ca-99c6-f9860d512eed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34570
99024 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_alerts.3457099024
Directory /workspace/26.alert_handler_random_alerts/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.1245227752
Short name T775
Test name
Test status
Simulation time 6801981815 ps
CPU time 111.69 seconds
Started Feb 07 12:43:32 PM PST 24
Finished Feb 07 12:45:26 PM PST 24
Peak memory 239840 kb
Host smart-a15be677-5f91-4523-8373-a7949c826c9d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1245227752 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_aliasing.1245227752
Directory /workspace/0.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.2352101559
Short name T846
Test name
Test status
Simulation time 4466872068 ps
CPU time 228.15 seconds
Started Feb 07 12:43:33 PM PST 24
Finished Feb 07 12:47:25 PM PST 24
Peak memory 235872 kb
Host smart-ba1e7665-5ab1-4ab6-ad70-d18415cb766a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2352101559 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_bit_bash.2352101559
Directory /workspace/0.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.2889764423
Short name T768
Test name
Test status
Simulation time 375414957 ps
CPU time 7.92 seconds
Started Feb 07 12:43:23 PM PST 24
Finished Feb 07 12:43:37 PM PST 24
Peak memory 239768 kb
Host smart-05eea191-7268-41ca-88fd-29ae9a9884ac
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2889764423 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_hw_reset.2889764423
Directory /workspace/0.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.725771198
Short name T839
Test name
Test status
Simulation time 272565214 ps
CPU time 7.71 seconds
Started Feb 07 12:43:29 PM PST 24
Finished Feb 07 12:43:41 PM PST 24
Peak memory 255952 kb
Host smart-d3550b0b-333c-4822-9366-18dbb3df1c5a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725771198 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 0.alert_handler_csr_mem_rw_with_rand_reset.725771198
Directory /workspace/0.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.1343717570
Short name T208
Test name
Test status
Simulation time 58907287 ps
CPU time 5.04 seconds
Started Feb 07 12:43:41 PM PST 24
Finished Feb 07 12:43:48 PM PST 24
Peak memory 239760 kb
Host smart-e0109e14-84bd-4562-a378-60c1b422a77d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1343717570 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_rw.1343717570
Directory /workspace/0.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.2291835458
Short name T808
Test name
Test status
Simulation time 26294803 ps
CPU time 1.41 seconds
Started Feb 07 12:43:32 PM PST 24
Finished Feb 07 12:43:37 PM PST 24
Peak memory 235820 kb
Host smart-893c6a1a-ffb1-4b70-adf0-ce1dca43c059
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2291835458 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_intr_test.2291835458
Directory /workspace/0.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.3687036499
Short name T172
Test name
Test status
Simulation time 393301416 ps
CPU time 29.07 seconds
Started Feb 07 12:43:42 PM PST 24
Finished Feb 07 12:44:12 PM PST 24
Peak memory 239560 kb
Host smart-988cc1a4-2828-45c9-b423-bde9896a56e7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3687036499 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_same_csr_out
standing.3687036499
Directory /workspace/0.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.2820822390
Short name T156
Test name
Test status
Simulation time 9218703043 ps
CPU time 148.78 seconds
Started Feb 07 12:43:40 PM PST 24
Finished Feb 07 12:46:10 PM PST 24
Peak memory 256508 kb
Host smart-94dbab6e-c6a9-464a-9694-5f35c8fe8c44
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2820822390 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shadow_reg_erro
rs.2820822390
Directory /workspace/0.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.3477923903
Short name T777
Test name
Test status
Simulation time 1188264871 ps
CPU time 11.38 seconds
Started Feb 07 12:43:40 PM PST 24
Finished Feb 07 12:43:53 PM PST 24
Peak memory 247940 kb
Host smart-5f4f0c33-fe31-41d2-a00d-6df850af5506
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3477923903 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_errors.3477923903
Directory /workspace/0.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.658460917
Short name T785
Test name
Test status
Simulation time 7746184463 ps
CPU time 120.32 seconds
Started Feb 07 12:43:29 PM PST 24
Finished Feb 07 12:45:34 PM PST 24
Peak memory 239864 kb
Host smart-0aebc4f3-0c72-4809-b30b-7cf3743109e0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=658460917 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_aliasing.658460917
Directory /workspace/1.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.1332030260
Short name T754
Test name
Test status
Simulation time 20404379175 ps
CPU time 199.64 seconds
Started Feb 07 12:43:27 PM PST 24
Finished Feb 07 12:46:52 PM PST 24
Peak memory 239664 kb
Host smart-25810bc9-d0c7-46ba-a8d8-60d83c20752a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1332030260 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_bit_bash.1332030260
Directory /workspace/1.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.2433231120
Short name T824
Test name
Test status
Simulation time 52904008 ps
CPU time 5.04 seconds
Started Feb 07 12:43:25 PM PST 24
Finished Feb 07 12:43:34 PM PST 24
Peak memory 239672 kb
Host smart-bd3e730d-ce0f-43f3-8feb-273b084d0410
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2433231120 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_hw_reset.2433231120
Directory /workspace/1.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.3675157635
Short name T749
Test name
Test status
Simulation time 252527082 ps
CPU time 7.09 seconds
Started Feb 07 12:43:32 PM PST 24
Finished Feb 07 12:43:42 PM PST 24
Peak memory 250836 kb
Host smart-651edaaa-4e5b-4f0e-a6c1-24af324d8b98
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675157635 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 1.alert_handler_csr_mem_rw_with_rand_reset.3675157635
Directory /workspace/1.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.3072832894
Short name T840
Test name
Test status
Simulation time 64013366 ps
CPU time 3.03 seconds
Started Feb 07 12:43:33 PM PST 24
Finished Feb 07 12:43:39 PM PST 24
Peak memory 235776 kb
Host smart-cb7826cc-dc3a-473f-8277-b081c1ef5993
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3072832894 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_rw.3072832894
Directory /workspace/1.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.282461473
Short name T794
Test name
Test status
Simulation time 13197618 ps
CPU time 1.63 seconds
Started Feb 07 12:43:27 PM PST 24
Finished Feb 07 12:43:34 PM PST 24
Peak memory 234768 kb
Host smart-40ed0100-5f31-4fc9-9068-92a9b2d25441
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=282461473 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_intr_test.282461473
Directory /workspace/1.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.2396314775
Short name T835
Test name
Test status
Simulation time 469651007 ps
CPU time 21.58 seconds
Started Feb 07 12:43:32 PM PST 24
Finished Feb 07 12:43:57 PM PST 24
Peak memory 243952 kb
Host smart-70135eb8-9dea-490e-a52e-269f6294e829
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2396314775 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_same_csr_out
standing.2396314775
Directory /workspace/1.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.3386868235
Short name T180
Test name
Test status
Simulation time 1753496536 ps
CPU time 194.95 seconds
Started Feb 07 12:43:29 PM PST 24
Finished Feb 07 12:46:48 PM PST 24
Peak memory 264412 kb
Host smart-86044387-5c4a-49ce-95f8-bf0b9a73f8ea
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3386868235 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shadow_reg_erro
rs.3386868235
Directory /workspace/1.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.1223769786
Short name T179
Test name
Test status
Simulation time 52081640776 ps
CPU time 915.12 seconds
Started Feb 07 12:43:28 PM PST 24
Finished Feb 07 12:58:48 PM PST 24
Peak memory 270932 kb
Host smart-980b687d-5a8d-4349-95fe-86504428e31f
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223769786 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.alert_handler_shadow_reg_errors_with_csr_rw.1223769786
Directory /workspace/1.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.4152712531
Short name T773
Test name
Test status
Simulation time 826270906 ps
CPU time 14.05 seconds
Started Feb 07 12:43:28 PM PST 24
Finished Feb 07 12:43:46 PM PST 24
Peak memory 247768 kb
Host smart-ebb139ea-1ef8-42e3-9253-3ac5b95b1526
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4152712531 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_errors.4152712531
Directory /workspace/1.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.333831984
Short name T142
Test name
Test status
Simulation time 33874492 ps
CPU time 6.91 seconds
Started Feb 07 12:44:16 PM PST 24
Finished Feb 07 12:44:24 PM PST 24
Peak memory 255740 kb
Host smart-55baf726-42ee-44f4-984e-de8ff4b25483
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333831984 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 10.alert_handler_csr_mem_rw_with_rand_reset.333831984
Directory /workspace/10.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.6721230
Short name T800
Test name
Test status
Simulation time 70113488 ps
CPU time 3.18 seconds
Started Feb 07 12:44:02 PM PST 24
Finished Feb 07 12:44:06 PM PST 24
Peak memory 235708 kb
Host smart-80f2b4c1-2010-474c-9741-67e45e96ce06
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=6721230 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_rw.6721230
Directory /workspace/10.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.2343207915
Short name T797
Test name
Test status
Simulation time 88229500 ps
CPU time 11.33 seconds
Started Feb 07 12:44:05 PM PST 24
Finished Feb 07 12:44:17 PM PST 24
Peak memory 239760 kb
Host smart-3c489fcf-58fc-4a7b-91fd-6a16ba0885f3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2343207915 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_same_csr_ou
tstanding.2343207915
Directory /workspace/10.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.270690294
Short name T152
Test name
Test status
Simulation time 5101898315 ps
CPU time 274.82 seconds
Started Feb 07 12:44:04 PM PST 24
Finished Feb 07 12:48:40 PM PST 24
Peak memory 264768 kb
Host smart-c7b112dc-a41b-4a15-b8ef-610ddfe0f11c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=270690294 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shadow_reg_erro
rs.270690294
Directory /workspace/10.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.3578959685
Short name T832
Test name
Test status
Simulation time 33022814191 ps
CPU time 570.39 seconds
Started Feb 07 12:44:16 PM PST 24
Finished Feb 07 12:53:47 PM PST 24
Peak memory 266240 kb
Host smart-282da56b-7a2f-4bc6-ac2d-0638593534fe
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578959685 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 10.alert_handler_shadow_reg_errors_with_csr_rw.3578959685
Directory /workspace/10.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.2255093255
Short name T789
Test name
Test status
Simulation time 360928145 ps
CPU time 12.22 seconds
Started Feb 07 12:44:03 PM PST 24
Finished Feb 07 12:44:16 PM PST 24
Peak memory 252588 kb
Host smart-216212a6-0310-4e0d-be93-dbd53cae15e7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2255093255 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_errors.2255093255
Directory /workspace/10.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.4109177428
Short name T780
Test name
Test status
Simulation time 30985963 ps
CPU time 3.99 seconds
Started Feb 07 12:44:02 PM PST 24
Finished Feb 07 12:44:07 PM PST 24
Peak memory 236864 kb
Host smart-c550d44c-cbbb-4153-a56b-c984dde94e85
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109177428 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 11.alert_handler_csr_mem_rw_with_rand_reset.4109177428
Directory /workspace/11.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.513896032
Short name T354
Test name
Test status
Simulation time 35026479 ps
CPU time 5.35 seconds
Started Feb 07 12:44:06 PM PST 24
Finished Feb 07 12:44:12 PM PST 24
Peak memory 234904 kb
Host smart-120cbd3e-6a00-4f68-90b7-f29ea28b98de
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=513896032 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_rw.513896032
Directory /workspace/11.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.185574155
Short name T817
Test name
Test status
Simulation time 8139290 ps
CPU time 1.43 seconds
Started Feb 07 12:44:05 PM PST 24
Finished Feb 07 12:44:07 PM PST 24
Peak memory 233976 kb
Host smart-8fa6a413-444f-402f-9c0f-97ea6a1a6813
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=185574155 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_intr_test.185574155
Directory /workspace/11.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.1037940017
Short name T27
Test name
Test status
Simulation time 202313622 ps
CPU time 21.14 seconds
Started Feb 07 12:44:17 PM PST 24
Finished Feb 07 12:44:39 PM PST 24
Peak memory 243792 kb
Host smart-cba0e909-9a85-41bf-aeab-edbedac426ba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1037940017 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_same_csr_ou
tstanding.1037940017
Directory /workspace/11.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.120361561
Short name T177
Test name
Test status
Simulation time 2374233702 ps
CPU time 213 seconds
Started Feb 07 12:44:07 PM PST 24
Finished Feb 07 12:47:41 PM PST 24
Peak memory 264640 kb
Host smart-00fc6459-6c12-4c7a-9b82-a2493e02c4f0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=120361561 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shadow_reg_erro
rs.120361561
Directory /workspace/11.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.1254137127
Short name T351
Test name
Test status
Simulation time 15644926782 ps
CPU time 1027.29 seconds
Started Feb 07 12:44:13 PM PST 24
Finished Feb 07 01:01:21 PM PST 24
Peak memory 264792 kb
Host smart-b335ba1e-481b-4209-8403-8131e8d9c25b
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254137127 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 11.alert_handler_shadow_reg_errors_with_csr_rw.1254137127
Directory /workspace/11.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.2261412673
Short name T184
Test name
Test status
Simulation time 174816789 ps
CPU time 13.93 seconds
Started Feb 07 12:44:17 PM PST 24
Finished Feb 07 12:44:32 PM PST 24
Peak memory 245780 kb
Host smart-9aa57201-caaf-4721-8f74-75857368ef5e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2261412673 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_errors.2261412673
Directory /workspace/11.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.1484198231
Short name T259
Test name
Test status
Simulation time 629457495 ps
CPU time 21.52 seconds
Started Feb 07 12:43:59 PM PST 24
Finished Feb 07 12:44:23 PM PST 24
Peak memory 239796 kb
Host smart-0c2438dd-7ca1-4d9d-babb-c9b4e0e2a8c6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1484198231 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_intg_err.1484198231
Directory /workspace/11.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.3808568064
Short name T809
Test name
Test status
Simulation time 39926488 ps
CPU time 4.49 seconds
Started Feb 07 12:44:07 PM PST 24
Finished Feb 07 12:44:12 PM PST 24
Peak memory 237872 kb
Host smart-3e69ebd4-5dbb-4fd4-903a-e478b69fdbf4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808568064 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 12.alert_handler_csr_mem_rw_with_rand_reset.3808568064
Directory /workspace/12.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.1138593146
Short name T802
Test name
Test status
Simulation time 359880638 ps
CPU time 8.91 seconds
Started Feb 07 12:44:12 PM PST 24
Finished Feb 07 12:44:22 PM PST 24
Peak memory 235748 kb
Host smart-db0c4b67-0bcb-4757-8dae-4ee7695ae03d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1138593146 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_rw.1138593146
Directory /workspace/12.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.1708487260
Short name T779
Test name
Test status
Simulation time 170607405 ps
CPU time 22.9 seconds
Started Feb 07 12:44:07 PM PST 24
Finished Feb 07 12:44:30 PM PST 24
Peak memory 243972 kb
Host smart-a4f7df95-a35e-4a27-9427-9f81bdca13a0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1708487260 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_same_csr_ou
tstanding.1708487260
Directory /workspace/12.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.2742134448
Short name T739
Test name
Test status
Simulation time 1313882245 ps
CPU time 25.93 seconds
Started Feb 07 12:44:17 PM PST 24
Finished Feb 07 12:44:44 PM PST 24
Peak memory 239536 kb
Host smart-110bbe47-aed8-46af-b1d8-164e02052292
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2742134448 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_errors.2742134448
Directory /workspace/12.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.2729287070
Short name T838
Test name
Test status
Simulation time 144329057 ps
CPU time 7.85 seconds
Started Feb 07 12:44:13 PM PST 24
Finished Feb 07 12:44:22 PM PST 24
Peak memory 252792 kb
Host smart-31058792-8411-4626-a872-bae480be7fc2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729287070 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 13.alert_handler_csr_mem_rw_with_rand_reset.2729287070
Directory /workspace/13.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.707854157
Short name T814
Test name
Test status
Simulation time 268752908 ps
CPU time 5.03 seconds
Started Feb 07 12:44:02 PM PST 24
Finished Feb 07 12:44:08 PM PST 24
Peak memory 235852 kb
Host smart-b15ac696-9b1b-41a5-8655-9674a396fd9f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=707854157 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_rw.707854157
Directory /workspace/13.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.1471657690
Short name T746
Test name
Test status
Simulation time 17664837 ps
CPU time 1.3 seconds
Started Feb 07 12:44:12 PM PST 24
Finished Feb 07 12:44:14 PM PST 24
Peak memory 235772 kb
Host smart-51da659d-e16b-45db-ac1e-80c480553a57
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1471657690 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_intr_test.1471657690
Directory /workspace/13.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.2960895300
Short name T207
Test name
Test status
Simulation time 293801871 ps
CPU time 14.62 seconds
Started Feb 07 12:44:11 PM PST 24
Finished Feb 07 12:44:27 PM PST 24
Peak memory 239696 kb
Host smart-5844f40f-f8c1-44ff-8bc9-e81129718144
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2960895300 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_same_csr_ou
tstanding.2960895300
Directory /workspace/13.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.1373326121
Short name T178
Test name
Test status
Simulation time 5436198059 ps
CPU time 355.32 seconds
Started Feb 07 12:43:57 PM PST 24
Finished Feb 07 12:49:53 PM PST 24
Peak memory 270432 kb
Host smart-b05f086b-4a2a-44fc-ab2b-cf6f47072f12
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1373326121 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shadow_reg_err
ors.1373326121
Directory /workspace/13.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.1578615362
Short name T167
Test name
Test status
Simulation time 24894833500 ps
CPU time 429.89 seconds
Started Feb 07 12:44:04 PM PST 24
Finished Feb 07 12:51:15 PM PST 24
Peak memory 264640 kb
Host smart-e2c1ae4b-13ca-4764-8c55-b73b12b53eb0
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578615362 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 13.alert_handler_shadow_reg_errors_with_csr_rw.1578615362
Directory /workspace/13.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.1760282041
Short name T146
Test name
Test status
Simulation time 70508520 ps
CPU time 9.78 seconds
Started Feb 07 12:44:12 PM PST 24
Finished Feb 07 12:44:23 PM PST 24
Peak memory 247564 kb
Host smart-af0785c0-ce7d-489f-aa1b-29d539796df8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1760282041 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_errors.1760282041
Directory /workspace/13.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.2887175420
Short name T145
Test name
Test status
Simulation time 2388417271 ps
CPU time 39.24 seconds
Started Feb 07 12:44:17 PM PST 24
Finished Feb 07 12:44:57 PM PST 24
Peak memory 238376 kb
Host smart-ee75d059-f316-4427-ac93-7ee44531d499
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2887175420 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_intg_err.2887175420
Directory /workspace/13.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.1705734311
Short name T827
Test name
Test status
Simulation time 117787638 ps
CPU time 3.93 seconds
Started Feb 07 12:44:13 PM PST 24
Finished Feb 07 12:44:18 PM PST 24
Peak memory 237580 kb
Host smart-1dbf134d-ba74-44ad-a878-c2d5cd0139d8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705734311 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 14.alert_handler_csr_mem_rw_with_rand_reset.1705734311
Directory /workspace/14.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.3680370922
Short name T752
Test name
Test status
Simulation time 174692496 ps
CPU time 4.94 seconds
Started Feb 07 12:44:16 PM PST 24
Finished Feb 07 12:44:21 PM PST 24
Peak memory 239752 kb
Host smart-44f9b3e3-f0d4-4c1e-8809-6964a7284173
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3680370922 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_rw.3680370922
Directory /workspace/14.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.3807337232
Short name T753
Test name
Test status
Simulation time 19030985 ps
CPU time 1.32 seconds
Started Feb 07 12:44:13 PM PST 24
Finished Feb 07 12:44:15 PM PST 24
Peak memory 235852 kb
Host smart-366668e8-e853-48ec-ae6f-657cee833f21
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3807337232 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_intr_test.3807337232
Directory /workspace/14.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.3528228116
Short name T833
Test name
Test status
Simulation time 659178220 ps
CPU time 42.66 seconds
Started Feb 07 12:44:14 PM PST 24
Finished Feb 07 12:44:58 PM PST 24
Peak memory 243948 kb
Host smart-783240c9-9ba2-41f4-9fb7-60f6cb5b9b93
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3528228116 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_same_csr_ou
tstanding.3528228116
Directory /workspace/14.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.36111933
Short name T159
Test name
Test status
Simulation time 4959991428 ps
CPU time 310.9 seconds
Started Feb 07 12:44:04 PM PST 24
Finished Feb 07 12:49:16 PM PST 24
Peak memory 264724 kb
Host smart-4866d5ef-d370-4eb1-96aa-2e4fdeebe998
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=36111933 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shadow_reg_error
s.36111933
Directory /workspace/14.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.966476206
Short name T141
Test name
Test status
Simulation time 215655117 ps
CPU time 15.24 seconds
Started Feb 07 12:43:59 PM PST 24
Finished Feb 07 12:44:15 PM PST 24
Peak memory 247636 kb
Host smart-c8bbd068-4914-4f45-955c-6291a63eeb60
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=966476206 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_errors.966476206
Directory /workspace/14.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.2543009607
Short name T796
Test name
Test status
Simulation time 28084412 ps
CPU time 5.33 seconds
Started Feb 07 12:44:11 PM PST 24
Finished Feb 07 12:44:18 PM PST 24
Peak memory 252088 kb
Host smart-197ce435-794d-4ac8-bcbd-d580888aca2d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543009607 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 15.alert_handler_csr_mem_rw_with_rand_reset.2543009607
Directory /workspace/15.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.1841305066
Short name T168
Test name
Test status
Simulation time 524308181 ps
CPU time 9.4 seconds
Started Feb 07 12:44:10 PM PST 24
Finished Feb 07 12:44:20 PM PST 24
Peak memory 235828 kb
Host smart-7268a464-0941-4346-8998-f844bde9b1d2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1841305066 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_rw.1841305066
Directory /workspace/15.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.1013043261
Short name T783
Test name
Test status
Simulation time 7373212 ps
CPU time 1.42 seconds
Started Feb 07 12:44:09 PM PST 24
Finished Feb 07 12:44:11 PM PST 24
Peak memory 234972 kb
Host smart-dafb2f1a-5eaf-490f-bda2-9b747de5259a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1013043261 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_intr_test.1013043261
Directory /workspace/15.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.4236082343
Short name T206
Test name
Test status
Simulation time 173113315 ps
CPU time 13 seconds
Started Feb 07 12:44:10 PM PST 24
Finished Feb 07 12:44:23 PM PST 24
Peak memory 239720 kb
Host smart-4169074e-6448-4f15-b68f-ab1a765121ef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4236082343 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_same_csr_ou
tstanding.4236082343
Directory /workspace/15.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.739707899
Short name T161
Test name
Test status
Simulation time 22487360364 ps
CPU time 371.97 seconds
Started Feb 07 12:44:06 PM PST 24
Finished Feb 07 12:50:19 PM PST 24
Peak memory 264724 kb
Host smart-02df4bb8-294a-44eb-bf9b-8d01b9492de3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=739707899 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shadow_reg_erro
rs.739707899
Directory /workspace/15.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.1690686848
Short name T352
Test name
Test status
Simulation time 4452856519 ps
CPU time 269.9 seconds
Started Feb 07 12:44:10 PM PST 24
Finished Feb 07 12:48:41 PM PST 24
Peak memory 264796 kb
Host smart-fe5c398a-73a5-4d4b-ae19-1332bdcd0326
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690686848 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 15.alert_handler_shadow_reg_errors_with_csr_rw.1690686848
Directory /workspace/15.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.2736731442
Short name T805
Test name
Test status
Simulation time 71262462 ps
CPU time 9.57 seconds
Started Feb 07 12:44:06 PM PST 24
Finished Feb 07 12:44:16 PM PST 24
Peak memory 246208 kb
Host smart-23a90c9e-b3bc-4364-b1dd-24497fdf0959
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2736731442 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_errors.2736731442
Directory /workspace/15.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.2072296293
Short name T821
Test name
Test status
Simulation time 142799752 ps
CPU time 4.09 seconds
Started Feb 07 12:44:05 PM PST 24
Finished Feb 07 12:44:10 PM PST 24
Peak memory 238924 kb
Host smart-5da5a37c-03f3-4615-a0ea-889642f273c2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072296293 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 16.alert_handler_csr_mem_rw_with_rand_reset.2072296293
Directory /workspace/16.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.1904397785
Short name T738
Test name
Test status
Simulation time 399629303 ps
CPU time 7.66 seconds
Started Feb 07 12:44:08 PM PST 24
Finished Feb 07 12:44:16 PM PST 24
Peak memory 235812 kb
Host smart-5bd0c3f8-1d14-48a8-9513-138e450fbbd3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1904397785 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_rw.1904397785
Directory /workspace/16.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.3682081087
Short name T31
Test name
Test status
Simulation time 9367855 ps
CPU time 1.27 seconds
Started Feb 07 12:44:13 PM PST 24
Finished Feb 07 12:44:15 PM PST 24
Peak memory 234976 kb
Host smart-c2b167a4-dbb0-4382-8242-18c9e5b2073b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3682081087 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_intr_test.3682081087
Directory /workspace/16.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.3256246588
Short name T204
Test name
Test status
Simulation time 177812672 ps
CPU time 13.18 seconds
Started Feb 07 12:44:12 PM PST 24
Finished Feb 07 12:44:26 PM PST 24
Peak memory 243948 kb
Host smart-a2fd4bed-736f-4b41-b981-98eb6c2b3d96
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3256246588 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_same_csr_ou
tstanding.3256246588
Directory /workspace/16.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.1281000874
Short name T164
Test name
Test status
Simulation time 3172826860 ps
CPU time 176.33 seconds
Started Feb 07 12:44:17 PM PST 24
Finished Feb 07 12:47:14 PM PST 24
Peak memory 264868 kb
Host smart-d9df78b4-1edc-4a44-89d7-35d988da53dc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1281000874 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shadow_reg_err
ors.1281000874
Directory /workspace/16.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.267750620
Short name T158
Test name
Test status
Simulation time 4352152183 ps
CPU time 599.75 seconds
Started Feb 07 12:44:17 PM PST 24
Finished Feb 07 12:54:18 PM PST 24
Peak memory 264844 kb
Host smart-5d1c975d-1f7e-47ad-8b4e-a4db2c117948
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267750620 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 16.alert_handler_shadow_reg_errors_with_csr_rw.267750620
Directory /workspace/16.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.4115929397
Short name T766
Test name
Test status
Simulation time 45817126 ps
CPU time 6.33 seconds
Started Feb 07 12:44:13 PM PST 24
Finished Feb 07 12:44:20 PM PST 24
Peak memory 247972 kb
Host smart-d81195b5-9b1c-46d6-9e13-fe2653fc184e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4115929397 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_errors.4115929397
Directory /workspace/16.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.2523487086
Short name T847
Test name
Test status
Simulation time 32081790 ps
CPU time 5.92 seconds
Started Feb 07 12:44:22 PM PST 24
Finished Feb 07 12:44:30 PM PST 24
Peak memory 242984 kb
Host smart-5388238a-ef99-40a2-bac1-669708592a5c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523487086 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 17.alert_handler_csr_mem_rw_with_rand_reset.2523487086
Directory /workspace/17.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.2387523312
Short name T834
Test name
Test status
Simulation time 57011491 ps
CPU time 5.42 seconds
Started Feb 07 12:44:21 PM PST 24
Finished Feb 07 12:44:28 PM PST 24
Peak memory 235800 kb
Host smart-a09203f6-5c52-4140-8b78-8a0a12a1c758
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2387523312 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_rw.2387523312
Directory /workspace/17.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.1240395491
Short name T786
Test name
Test status
Simulation time 1287428036 ps
CPU time 37.63 seconds
Started Feb 07 12:44:24 PM PST 24
Finished Feb 07 12:45:03 PM PST 24
Peak memory 243976 kb
Host smart-98c2cfee-7f53-4b37-aa76-a790185d5529
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1240395491 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_same_csr_ou
tstanding.1240395491
Directory /workspace/17.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.3454237245
Short name T147
Test name
Test status
Simulation time 4949357069 ps
CPU time 313.75 seconds
Started Feb 07 12:44:10 PM PST 24
Finished Feb 07 12:49:24 PM PST 24
Peak memory 272052 kb
Host smart-2682452e-b529-451a-9e68-22e114dd201e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3454237245 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shadow_reg_err
ors.3454237245
Directory /workspace/17.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.477528472
Short name T144
Test name
Test status
Simulation time 8790657761 ps
CPU time 311.88 seconds
Started Feb 07 12:44:07 PM PST 24
Finished Feb 07 12:49:20 PM PST 24
Peak memory 264764 kb
Host smart-b35eb172-b91e-4dac-979a-8cfcf4c6d47a
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477528472 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 17.alert_handler_shadow_reg_errors_with_csr_rw.477528472
Directory /workspace/17.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.3248335695
Short name T742
Test name
Test status
Simulation time 421424294 ps
CPU time 10.15 seconds
Started Feb 07 12:44:06 PM PST 24
Finished Feb 07 12:44:17 PM PST 24
Peak memory 253424 kb
Host smart-460eb8ea-cb21-4876-9c04-bed1ed170578
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3248335695 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_errors.3248335695
Directory /workspace/17.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.2988489733
Short name T248
Test name
Test status
Simulation time 76958264 ps
CPU time 7.21 seconds
Started Feb 07 12:44:23 PM PST 24
Finished Feb 07 12:44:32 PM PST 24
Peak memory 250480 kb
Host smart-91d5902c-15a5-4772-8f88-29526875ba8e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988489733 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 18.alert_handler_csr_mem_rw_with_rand_reset.2988489733
Directory /workspace/18.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.648595630
Short name T758
Test name
Test status
Simulation time 20329310 ps
CPU time 3.6 seconds
Started Feb 07 12:44:21 PM PST 24
Finished Feb 07 12:44:26 PM PST 24
Peak memory 239640 kb
Host smart-3f109912-54d7-4c1c-b012-c3cc5768a3fd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=648595630 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_rw.648595630
Directory /workspace/18.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.958495605
Short name T804
Test name
Test status
Simulation time 17419650 ps
CPU time 1.35 seconds
Started Feb 07 12:44:19 PM PST 24
Finished Feb 07 12:44:21 PM PST 24
Peak memory 235732 kb
Host smart-ead55fc9-daf0-4abb-a37e-048201d4b703
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=958495605 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_intr_test.958495605
Directory /workspace/18.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.979196355
Short name T205
Test name
Test status
Simulation time 182894971 ps
CPU time 27.36 seconds
Started Feb 07 12:44:33 PM PST 24
Finished Feb 07 12:45:02 PM PST 24
Peak memory 243796 kb
Host smart-aba73887-f683-43b4-a8f2-701314dad007
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=979196355 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_same_csr_out
standing.979196355
Directory /workspace/18.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.1678324087
Short name T841
Test name
Test status
Simulation time 496728997 ps
CPU time 7.59 seconds
Started Feb 07 12:44:20 PM PST 24
Finished Feb 07 12:44:29 PM PST 24
Peak memory 252048 kb
Host smart-83162022-c691-461d-9c0f-92202e37d7af
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1678324087 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_errors.1678324087
Directory /workspace/18.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.2786353360
Short name T787
Test name
Test status
Simulation time 87871966 ps
CPU time 5.23 seconds
Started Feb 07 12:44:23 PM PST 24
Finished Feb 07 12:44:29 PM PST 24
Peak memory 243340 kb
Host smart-ebca7567-f774-45e8-bd5e-0b1da451492e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786353360 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 19.alert_handler_csr_mem_rw_with_rand_reset.2786353360
Directory /workspace/19.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.124302173
Short name T788
Test name
Test status
Simulation time 35730255 ps
CPU time 5.05 seconds
Started Feb 07 12:44:25 PM PST 24
Finished Feb 07 12:44:31 PM PST 24
Peak memory 239668 kb
Host smart-ae5bcf88-9d48-47d8-bfa6-73f66cc27440
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=124302173 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_rw.124302173
Directory /workspace/19.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.2167320760
Short name T763
Test name
Test status
Simulation time 8930282 ps
CPU time 1.36 seconds
Started Feb 07 12:44:24 PM PST 24
Finished Feb 07 12:44:26 PM PST 24
Peak memory 235836 kb
Host smart-3081dc53-c79b-4986-bf9c-f69f9ae95989
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2167320760 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_intr_test.2167320760
Directory /workspace/19.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.3830918343
Short name T793
Test name
Test status
Simulation time 513503347 ps
CPU time 35.97 seconds
Started Feb 07 12:44:22 PM PST 24
Finished Feb 07 12:45:00 PM PST 24
Peak memory 247972 kb
Host smart-655729e0-f26c-4a3e-8a9c-9f413bee361e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3830918343 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_same_csr_ou
tstanding.3830918343
Directory /workspace/19.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.2503651887
Short name T747
Test name
Test status
Simulation time 281750583 ps
CPU time 8.17 seconds
Started Feb 07 12:44:24 PM PST 24
Finished Feb 07 12:44:34 PM PST 24
Peak memory 248036 kb
Host smart-9c41f9d2-a233-493a-affc-63d5dd343c49
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2503651887 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_errors.2503651887
Directory /workspace/19.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.67684162
Short name T831
Test name
Test status
Simulation time 1142845995 ps
CPU time 61.35 seconds
Started Feb 07 12:43:35 PM PST 24
Finished Feb 07 12:44:39 PM PST 24
Peak memory 235924 kb
Host smart-f25e771a-2c21-4223-a3f6-2d74de46b2bb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=67684162 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_aliasing.67684162
Directory /workspace/2.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.630006821
Short name T819
Test name
Test status
Simulation time 29647558171 ps
CPU time 415.22 seconds
Started Feb 07 12:43:35 PM PST 24
Finished Feb 07 12:50:33 PM PST 24
Peak memory 234992 kb
Host smart-87b9d7df-d9c8-4484-b1db-ba2124a0c19a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=630006821 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_bit_bash.630006821
Directory /workspace/2.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.1056846774
Short name T748
Test name
Test status
Simulation time 76019548 ps
CPU time 6.07 seconds
Started Feb 07 12:43:31 PM PST 24
Finished Feb 07 12:43:41 PM PST 24
Peak memory 239724 kb
Host smart-93779b08-8b52-4601-8b59-5080908c7284
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1056846774 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_hw_reset.1056846774
Directory /workspace/2.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.3438305660
Short name T776
Test name
Test status
Simulation time 33636850 ps
CPU time 5.97 seconds
Started Feb 07 12:43:43 PM PST 24
Finished Feb 07 12:43:50 PM PST 24
Peak memory 247876 kb
Host smart-276605bc-7941-4234-9663-8c937702b98d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438305660 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 2.alert_handler_csr_mem_rw_with_rand_reset.3438305660
Directory /workspace/2.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.2415978787
Short name T845
Test name
Test status
Simulation time 93474247 ps
CPU time 7.97 seconds
Started Feb 07 12:43:43 PM PST 24
Finished Feb 07 12:43:52 PM PST 24
Peak memory 239600 kb
Host smart-6b2cd365-fb9b-423e-8e24-0de295d06d47
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2415978787 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_rw.2415978787
Directory /workspace/2.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.3962624913
Short name T250
Test name
Test status
Simulation time 15301558 ps
CPU time 1.56 seconds
Started Feb 07 12:43:44 PM PST 24
Finished Feb 07 12:43:47 PM PST 24
Peak memory 235668 kb
Host smart-6d01eb49-29bf-439e-bd3b-994762ebfd89
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3962624913 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_intr_test.3962624913
Directory /workspace/2.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.652790574
Short name T750
Test name
Test status
Simulation time 1634203338 ps
CPU time 40.97 seconds
Started Feb 07 12:43:44 PM PST 24
Finished Feb 07 12:44:26 PM PST 24
Peak memory 243832 kb
Host smart-c1d7c42e-327f-42c6-9442-657a159edac0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=652790574 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_same_csr_outs
tanding.652790574
Directory /workspace/2.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.2299529746
Short name T151
Test name
Test status
Simulation time 41986975355 ps
CPU time 1052.72 seconds
Started Feb 07 12:43:23 PM PST 24
Finished Feb 07 01:01:02 PM PST 24
Peak memory 264780 kb
Host smart-8b28d03d-460f-4541-9d4c-5fe11a3028f7
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299529746 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.alert_handler_shadow_reg_errors_with_csr_rw.2299529746
Directory /workspace/2.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.4150430162
Short name T757
Test name
Test status
Simulation time 326735369 ps
CPU time 17.17 seconds
Started Feb 07 12:43:30 PM PST 24
Finished Feb 07 12:43:51 PM PST 24
Peak memory 248104 kb
Host smart-befa3c17-d376-4bea-b800-9885d039346f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4150430162 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_errors.4150430162
Directory /workspace/2.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.2534536490
Short name T801
Test name
Test status
Simulation time 10541745 ps
CPU time 1.3 seconds
Started Feb 07 12:44:20 PM PST 24
Finished Feb 07 12:44:22 PM PST 24
Peak memory 234008 kb
Host smart-f0498d9a-bb3b-4f24-99f1-461363444944
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2534536490 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.alert_handler_intr_test.2534536490
Directory /workspace/20.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.538591814
Short name T770
Test name
Test status
Simulation time 12164919 ps
CPU time 1.65 seconds
Started Feb 07 12:44:21 PM PST 24
Finished Feb 07 12:44:25 PM PST 24
Peak memory 235816 kb
Host smart-0c85eaa5-bbd2-467d-943b-9481b3ef51de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=538591814 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.alert_handler_intr_test.538591814
Directory /workspace/22.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.3620466524
Short name T799
Test name
Test status
Simulation time 8262485 ps
CPU time 1.49 seconds
Started Feb 07 12:44:20 PM PST 24
Finished Feb 07 12:44:23 PM PST 24
Peak memory 235804 kb
Host smart-0883e3bf-d9cc-4274-b782-6fca3d5d5c94
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3620466524 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.alert_handler_intr_test.3620466524
Directory /workspace/23.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.2840684604
Short name T29
Test name
Test status
Simulation time 21765433 ps
CPU time 1.46 seconds
Started Feb 07 12:44:20 PM PST 24
Finished Feb 07 12:44:22 PM PST 24
Peak memory 235788 kb
Host smart-18a1a7b3-74a6-4663-949a-a475b52ac504
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2840684604 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.alert_handler_intr_test.2840684604
Directory /workspace/24.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.3269449513
Short name T740
Test name
Test status
Simulation time 10574448 ps
CPU time 1.33 seconds
Started Feb 07 12:44:22 PM PST 24
Finished Feb 07 12:44:25 PM PST 24
Peak memory 235816 kb
Host smart-04cb1270-976c-4ba6-8cd2-6ebd0ae7d303
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3269449513 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.alert_handler_intr_test.3269449513
Directory /workspace/25.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.215504254
Short name T795
Test name
Test status
Simulation time 15046193 ps
CPU time 1.63 seconds
Started Feb 07 12:44:20 PM PST 24
Finished Feb 07 12:44:22 PM PST 24
Peak memory 235792 kb
Host smart-731d75ca-daa9-49a6-8182-7ad52a9a0825
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=215504254 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.alert_handler_intr_test.215504254
Directory /workspace/26.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.3873917894
Short name T756
Test name
Test status
Simulation time 8595199 ps
CPU time 1.61 seconds
Started Feb 07 12:44:28 PM PST 24
Finished Feb 07 12:44:30 PM PST 24
Peak memory 235824 kb
Host smart-a64187c4-7d5b-4183-bada-f79b0a2670b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3873917894 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.alert_handler_intr_test.3873917894
Directory /workspace/27.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.806887270
Short name T836
Test name
Test status
Simulation time 7919203 ps
CPU time 1.44 seconds
Started Feb 07 12:44:24 PM PST 24
Finished Feb 07 12:44:27 PM PST 24
Peak memory 234968 kb
Host smart-e782b759-f91e-4c34-965f-42c1488bee29
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=806887270 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.alert_handler_intr_test.806887270
Directory /workspace/28.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.1842880857
Short name T791
Test name
Test status
Simulation time 18612147 ps
CPU time 1.38 seconds
Started Feb 07 12:44:22 PM PST 24
Finished Feb 07 12:44:25 PM PST 24
Peak memory 235816 kb
Host smart-75f5a7dd-7df8-4883-9f05-0b5efb5400bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1842880857 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.alert_handler_intr_test.1842880857
Directory /workspace/29.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.902804185
Short name T790
Test name
Test status
Simulation time 13213220419 ps
CPU time 244.68 seconds
Started Feb 07 12:43:45 PM PST 24
Finished Feb 07 12:47:51 PM PST 24
Peak memory 239912 kb
Host smart-2d62b58d-44d6-4908-96e3-c51624fe657c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=902804185 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_aliasing.902804185
Directory /workspace/3.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.2670863656
Short name T803
Test name
Test status
Simulation time 837952788 ps
CPU time 110.36 seconds
Started Feb 07 12:43:30 PM PST 24
Finished Feb 07 12:45:24 PM PST 24
Peak memory 239756 kb
Host smart-eea13903-8c66-4e46-bb23-3fc9d5ab9b52
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2670863656 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_bit_bash.2670863656
Directory /workspace/3.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.3145070515
Short name T203
Test name
Test status
Simulation time 84522624 ps
CPU time 3.63 seconds
Started Feb 07 12:43:37 PM PST 24
Finished Feb 07 12:43:42 PM PST 24
Peak memory 239728 kb
Host smart-d9043f53-f6c3-406a-bdb3-4d95f48e0fb5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3145070515 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_hw_reset.3145070515
Directory /workspace/3.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.386533885
Short name T743
Test name
Test status
Simulation time 33174254 ps
CPU time 6.59 seconds
Started Feb 07 12:43:48 PM PST 24
Finished Feb 07 12:43:58 PM PST 24
Peak memory 251584 kb
Host smart-52b0239b-31b5-4f49-8dbe-03eb3480413d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386533885 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 3.alert_handler_csr_mem_rw_with_rand_reset.386533885
Directory /workspace/3.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.1705766371
Short name T778
Test name
Test status
Simulation time 186572290 ps
CPU time 8.45 seconds
Started Feb 07 12:43:32 PM PST 24
Finished Feb 07 12:43:43 PM PST 24
Peak memory 235748 kb
Host smart-ca9f4e3a-d05d-487e-8f97-d1f8529e2074
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1705766371 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_rw.1705766371
Directory /workspace/3.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.3371531771
Short name T844
Test name
Test status
Simulation time 10990847 ps
CPU time 1.29 seconds
Started Feb 07 12:43:34 PM PST 24
Finished Feb 07 12:43:38 PM PST 24
Peak memory 235764 kb
Host smart-b9c6a24f-c286-4eae-a473-6abccecc8ba3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3371531771 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_intr_test.3371531771
Directory /workspace/3.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.594037421
Short name T830
Test name
Test status
Simulation time 3179614433 ps
CPU time 19.31 seconds
Started Feb 07 12:43:46 PM PST 24
Finished Feb 07 12:44:09 PM PST 24
Peak memory 243864 kb
Host smart-ef7c0fed-d56b-4506-9838-25a55cb4ed1a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=594037421 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_same_csr_outs
tanding.594037421
Directory /workspace/3.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.426140751
Short name T157
Test name
Test status
Simulation time 4191183060 ps
CPU time 137.33 seconds
Started Feb 07 12:43:44 PM PST 24
Finished Feb 07 12:46:03 PM PST 24
Peak memory 256388 kb
Host smart-61efba8c-081d-4c7f-9074-3cd7eaac2219
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=426140751 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shadow_reg_error
s.426140751
Directory /workspace/3.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.2886422558
Short name T350
Test name
Test status
Simulation time 5935196579 ps
CPU time 443.01 seconds
Started Feb 07 12:43:44 PM PST 24
Finished Feb 07 12:51:08 PM PST 24
Peak memory 264528 kb
Host smart-6e1c6721-bed7-49f7-8dd5-ffd7bdcd9337
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886422558 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.alert_handler_shadow_reg_errors_with_csr_rw.2886422558
Directory /workspace/3.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.1981623978
Short name T764
Test name
Test status
Simulation time 128037364 ps
CPU time 5.69 seconds
Started Feb 07 12:43:31 PM PST 24
Finished Feb 07 12:43:40 PM PST 24
Peak memory 247708 kb
Host smart-0cb7ebb5-a90c-48dd-8065-904cab6b30b6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1981623978 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_errors.1981623978
Directory /workspace/3.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.1763430481
Short name T195
Test name
Test status
Simulation time 89966543 ps
CPU time 2.53 seconds
Started Feb 07 12:43:45 PM PST 24
Finished Feb 07 12:43:49 PM PST 24
Peak memory 235644 kb
Host smart-b302afbd-3da0-47af-a625-45ac317a1635
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1763430481 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_intg_err.1763430481
Directory /workspace/3.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.536075501
Short name T357
Test name
Test status
Simulation time 9360485 ps
CPU time 1.53 seconds
Started Feb 07 12:44:26 PM PST 24
Finished Feb 07 12:44:28 PM PST 24
Peak memory 235712 kb
Host smart-3b545317-8511-404b-bdf8-4f23e2286f08
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=536075501 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.alert_handler_intr_test.536075501
Directory /workspace/30.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.3862967673
Short name T848
Test name
Test status
Simulation time 19319932 ps
CPU time 1.36 seconds
Started Feb 07 12:44:25 PM PST 24
Finished Feb 07 12:44:28 PM PST 24
Peak memory 234864 kb
Host smart-c5d6bf88-67ac-4235-91b8-233a4c257edd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3862967673 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.alert_handler_intr_test.3862967673
Directory /workspace/31.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.3490447514
Short name T751
Test name
Test status
Simulation time 8575990 ps
CPU time 1.34 seconds
Started Feb 07 12:44:26 PM PST 24
Finished Feb 07 12:44:28 PM PST 24
Peak memory 235676 kb
Host smart-976dead0-416f-46ee-9376-5b1e3e54ecb2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3490447514 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.alert_handler_intr_test.3490447514
Directory /workspace/32.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.3843819332
Short name T784
Test name
Test status
Simulation time 8237512 ps
CPU time 1.51 seconds
Started Feb 07 12:44:22 PM PST 24
Finished Feb 07 12:44:25 PM PST 24
Peak memory 235784 kb
Host smart-343eb382-4f4c-47f7-b7d2-3d67c98f6a94
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3843819332 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.alert_handler_intr_test.3843819332
Directory /workspace/33.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.1219219620
Short name T829
Test name
Test status
Simulation time 8164639 ps
CPU time 1.47 seconds
Started Feb 07 12:44:21 PM PST 24
Finished Feb 07 12:44:25 PM PST 24
Peak memory 235824 kb
Host smart-5683d878-105a-42d6-ac31-7dda2fb7ea31
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1219219620 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.alert_handler_intr_test.1219219620
Directory /workspace/34.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.3897604429
Short name T813
Test name
Test status
Simulation time 24463775 ps
CPU time 1.51 seconds
Started Feb 07 12:44:28 PM PST 24
Finished Feb 07 12:44:30 PM PST 24
Peak memory 235824 kb
Host smart-7e888eb6-2079-43ab-838c-1905c0044e7c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3897604429 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.alert_handler_intr_test.3897604429
Directory /workspace/35.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.686342711
Short name T353
Test name
Test status
Simulation time 12796167 ps
CPU time 1.33 seconds
Started Feb 07 12:44:19 PM PST 24
Finished Feb 07 12:44:21 PM PST 24
Peak memory 235776 kb
Host smart-faed727d-9bfc-487a-bf01-b147785dafda
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=686342711 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.alert_handler_intr_test.686342711
Directory /workspace/36.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.382478701
Short name T760
Test name
Test status
Simulation time 10317689 ps
CPU time 1.33 seconds
Started Feb 07 12:44:22 PM PST 24
Finished Feb 07 12:44:25 PM PST 24
Peak memory 235836 kb
Host smart-a190cddb-957d-4d51-a947-f692dc3c0249
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=382478701 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.alert_handler_intr_test.382478701
Directory /workspace/37.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.3061423956
Short name T759
Test name
Test status
Simulation time 15591300 ps
CPU time 1.29 seconds
Started Feb 07 12:44:20 PM PST 24
Finished Feb 07 12:44:22 PM PST 24
Peak memory 235816 kb
Host smart-f4b94e42-910b-4130-97ac-2158f70f2987
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3061423956 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.alert_handler_intr_test.3061423956
Directory /workspace/38.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.3098751657
Short name T818
Test name
Test status
Simulation time 8236104 ps
CPU time 1.67 seconds
Started Feb 07 12:44:23 PM PST 24
Finished Feb 07 12:44:26 PM PST 24
Peak memory 235828 kb
Host smart-9558b7ff-da89-452c-8e52-74e2f030042d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3098751657 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.alert_handler_intr_test.3098751657
Directory /workspace/39.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.1164405917
Short name T744
Test name
Test status
Simulation time 2245270300 ps
CPU time 157.27 seconds
Started Feb 07 12:43:49 PM PST 24
Finished Feb 07 12:46:29 PM PST 24
Peak memory 239824 kb
Host smart-fa5a1c5f-99b3-4da7-a153-781eb0d535ce
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1164405917 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_aliasing.1164405917
Directory /workspace/4.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.1916124374
Short name T843
Test name
Test status
Simulation time 9073916899 ps
CPU time 105.45 seconds
Started Feb 07 12:43:46 PM PST 24
Finished Feb 07 12:45:35 PM PST 24
Peak memory 235856 kb
Host smart-a43cd2ab-298b-4c04-a226-96794f44524b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1916124374 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_bit_bash.1916124374
Directory /workspace/4.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.557061930
Short name T25
Test name
Test status
Simulation time 74430000 ps
CPU time 6.6 seconds
Started Feb 07 12:43:58 PM PST 24
Finished Feb 07 12:44:06 PM PST 24
Peak memory 239764 kb
Host smart-85d15ff1-038a-4bb8-8ece-337b53e01bf3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=557061930 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_hw_reset.557061930
Directory /workspace/4.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.3329819599
Short name T826
Test name
Test status
Simulation time 34190186 ps
CPU time 6.71 seconds
Started Feb 07 12:43:47 PM PST 24
Finished Feb 07 12:43:58 PM PST 24
Peak memory 256196 kb
Host smart-c74fb0a4-575d-485e-beec-b9a826571b9b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329819599 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 4.alert_handler_csr_mem_rw_with_rand_reset.3329819599
Directory /workspace/4.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.3636872660
Short name T24
Test name
Test status
Simulation time 260257396 ps
CPU time 9.06 seconds
Started Feb 07 12:43:56 PM PST 24
Finished Feb 07 12:44:06 PM PST 24
Peak memory 235732 kb
Host smart-ce2d0d5c-ac77-4270-b714-f1e0051f903a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3636872660 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_rw.3636872660
Directory /workspace/4.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.44136736
Short name T348
Test name
Test status
Simulation time 12103176 ps
CPU time 1.3 seconds
Started Feb 07 12:43:45 PM PST 24
Finished Feb 07 12:43:47 PM PST 24
Peak memory 233880 kb
Host smart-979a23cd-9b69-4134-b2f9-dbff14a81ff0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=44136736 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_intr_test.44136736
Directory /workspace/4.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.1296866603
Short name T761
Test name
Test status
Simulation time 90345852 ps
CPU time 13.09 seconds
Started Feb 07 12:43:48 PM PST 24
Finished Feb 07 12:44:04 PM PST 24
Peak memory 239776 kb
Host smart-92ad8239-6f7e-45be-834c-74b119174566
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1296866603 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_same_csr_out
standing.1296866603
Directory /workspace/4.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.1231645452
Short name T171
Test name
Test status
Simulation time 2252580365 ps
CPU time 244.45 seconds
Started Feb 07 12:43:46 PM PST 24
Finished Feb 07 12:47:54 PM PST 24
Peak memory 264656 kb
Host smart-ea1ec67a-8071-454a-9468-4035706ba54c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1231645452 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shadow_reg_erro
rs.1231645452
Directory /workspace/4.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.1703844505
Short name T810
Test name
Test status
Simulation time 330988054 ps
CPU time 10.2 seconds
Started Feb 07 12:43:49 PM PST 24
Finished Feb 07 12:44:02 PM PST 24
Peak memory 252208 kb
Host smart-cf2c73f0-424d-49a7-9ccb-3e6459367e01
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1703844505 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_errors.1703844505
Directory /workspace/4.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.656451084
Short name T355
Test name
Test status
Simulation time 10568417 ps
CPU time 1.39 seconds
Started Feb 07 12:44:20 PM PST 24
Finished Feb 07 12:44:22 PM PST 24
Peak memory 235804 kb
Host smart-6d9d35b8-d071-4916-a0e9-44dfa878722b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=656451084 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.alert_handler_intr_test.656451084
Directory /workspace/40.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.681125204
Short name T806
Test name
Test status
Simulation time 9575255 ps
CPU time 1.51 seconds
Started Feb 07 12:44:24 PM PST 24
Finished Feb 07 12:44:26 PM PST 24
Peak memory 234056 kb
Host smart-e4f5232a-ac60-472f-a289-bd53a6497a44
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=681125204 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.alert_handler_intr_test.681125204
Directory /workspace/41.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.3650732361
Short name T767
Test name
Test status
Simulation time 9556466 ps
CPU time 1.46 seconds
Started Feb 07 12:44:28 PM PST 24
Finished Feb 07 12:44:30 PM PST 24
Peak memory 235824 kb
Host smart-766eb162-2c6f-497a-81d0-9d7a6ea39d05
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3650732361 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.alert_handler_intr_test.3650732361
Directory /workspace/42.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.2068729035
Short name T820
Test name
Test status
Simulation time 6428734 ps
CPU time 1.33 seconds
Started Feb 07 12:44:19 PM PST 24
Finished Feb 07 12:44:20 PM PST 24
Peak memory 235776 kb
Host smart-cfe64f9e-8409-48af-ab7d-88133e3523cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2068729035 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.alert_handler_intr_test.2068729035
Directory /workspace/43.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.2399293579
Short name T822
Test name
Test status
Simulation time 9979707 ps
CPU time 1.51 seconds
Started Feb 07 12:44:21 PM PST 24
Finished Feb 07 12:44:25 PM PST 24
Peak memory 234928 kb
Host smart-6be876b7-e4ef-4393-8d61-4d0b148a96cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2399293579 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.alert_handler_intr_test.2399293579
Directory /workspace/44.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.2664896350
Short name T349
Test name
Test status
Simulation time 10468960 ps
CPU time 1.29 seconds
Started Feb 07 12:44:28 PM PST 24
Finished Feb 07 12:44:30 PM PST 24
Peak memory 233940 kb
Host smart-81d71089-fab9-4d4b-a0d5-8d73fe8a5f05
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2664896350 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.alert_handler_intr_test.2664896350
Directory /workspace/45.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.2805489335
Short name T792
Test name
Test status
Simulation time 19021847 ps
CPU time 1.27 seconds
Started Feb 07 12:44:22 PM PST 24
Finished Feb 07 12:44:25 PM PST 24
Peak memory 234992 kb
Host smart-c1fb320e-2671-4415-9396-ae8c90a41f30
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2805489335 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.alert_handler_intr_test.2805489335
Directory /workspace/46.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.2089733462
Short name T811
Test name
Test status
Simulation time 10674600 ps
CPU time 1.58 seconds
Started Feb 07 12:44:24 PM PST 24
Finished Feb 07 12:44:27 PM PST 24
Peak memory 233940 kb
Host smart-ab21619e-717e-47b3-9828-bc5f4f5b997e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2089733462 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.alert_handler_intr_test.2089733462
Directory /workspace/47.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.4165669435
Short name T815
Test name
Test status
Simulation time 9577673 ps
CPU time 1.21 seconds
Started Feb 07 12:44:28 PM PST 24
Finished Feb 07 12:44:30 PM PST 24
Peak memory 234948 kb
Host smart-d3006f78-24f4-407a-b6ed-f4c45f81bd44
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4165669435 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.alert_handler_intr_test.4165669435
Directory /workspace/48.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.3305291321
Short name T823
Test name
Test status
Simulation time 17334795 ps
CPU time 1.31 seconds
Started Feb 07 12:44:24 PM PST 24
Finished Feb 07 12:44:27 PM PST 24
Peak memory 235832 kb
Host smart-255a00b6-f418-4de1-b23d-ac18aed16538
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3305291321 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.alert_handler_intr_test.3305291321
Directory /workspace/49.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.579156044
Short name T837
Test name
Test status
Simulation time 158228840 ps
CPU time 4.55 seconds
Started Feb 07 12:43:50 PM PST 24
Finished Feb 07 12:43:57 PM PST 24
Peak memory 239764 kb
Host smart-70df5fbb-94df-4f8d-81f8-b6413709cb1f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579156044 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 5.alert_handler_csr_mem_rw_with_rand_reset.579156044
Directory /workspace/5.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.2630499253
Short name T169
Test name
Test status
Simulation time 125844337 ps
CPU time 4.92 seconds
Started Feb 07 12:43:49 PM PST 24
Finished Feb 07 12:43:56 PM PST 24
Peak memory 235760 kb
Host smart-cf676e62-4bcf-46ce-bad6-32b98b618bc6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2630499253 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_rw.2630499253
Directory /workspace/5.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.1345721900
Short name T765
Test name
Test status
Simulation time 8534039 ps
CPU time 1.49 seconds
Started Feb 07 12:43:50 PM PST 24
Finished Feb 07 12:43:53 PM PST 24
Peak memory 235812 kb
Host smart-667c5de6-c090-4323-b270-bbf7325cb9ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1345721900 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_intr_test.1345721900
Directory /workspace/5.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.3012253979
Short name T745
Test name
Test status
Simulation time 1445515794 ps
CPU time 19.48 seconds
Started Feb 07 12:43:48 PM PST 24
Finished Feb 07 12:44:11 PM PST 24
Peak memory 244012 kb
Host smart-7c423b84-2626-4e1c-af1a-24a46484724a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3012253979 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_same_csr_out
standing.3012253979
Directory /workspace/5.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.3294184213
Short name T182
Test name
Test status
Simulation time 30546105428 ps
CPU time 325.54 seconds
Started Feb 07 12:43:47 PM PST 24
Finished Feb 07 12:49:17 PM PST 24
Peak memory 264728 kb
Host smart-daf13c08-4bec-42af-8f80-1b489237e602
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294184213 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.alert_handler_shadow_reg_errors_with_csr_rw.3294184213
Directory /workspace/5.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.1811092011
Short name T842
Test name
Test status
Simulation time 72686028 ps
CPU time 9.78 seconds
Started Feb 07 12:43:52 PM PST 24
Finished Feb 07 12:44:03 PM PST 24
Peak memory 247976 kb
Host smart-f0b61ada-e4a9-4706-832d-6d6885bedf00
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1811092011 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_errors.1811092011
Directory /workspace/5.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.2370065203
Short name T825
Test name
Test status
Simulation time 638258841 ps
CPU time 4.56 seconds
Started Feb 07 12:43:55 PM PST 24
Finished Feb 07 12:44:00 PM PST 24
Peak memory 238752 kb
Host smart-11d2721d-bc7f-439c-ba2d-be6632fad653
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370065203 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 6.alert_handler_csr_mem_rw_with_rand_reset.2370065203
Directory /workspace/6.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.3340966595
Short name T774
Test name
Test status
Simulation time 74398378 ps
CPU time 4.72 seconds
Started Feb 07 12:43:55 PM PST 24
Finished Feb 07 12:44:00 PM PST 24
Peak memory 239520 kb
Host smart-5621be44-7f96-4851-aaf0-32c6904ed19e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3340966595 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_rw.3340966595
Directory /workspace/6.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.1932498753
Short name T32
Test name
Test status
Simulation time 6623729 ps
CPU time 1.47 seconds
Started Feb 07 12:43:54 PM PST 24
Finished Feb 07 12:43:56 PM PST 24
Peak memory 234908 kb
Host smart-d963fc3e-6715-4148-9b6f-3761df3bf115
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1932498753 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_intr_test.1932498753
Directory /workspace/6.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.821450462
Short name T807
Test name
Test status
Simulation time 541279770 ps
CPU time 40.51 seconds
Started Feb 07 12:43:58 PM PST 24
Finished Feb 07 12:44:39 PM PST 24
Peak memory 243980 kb
Host smart-1f1bd651-0673-48ab-9f70-532edc18d671
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=821450462 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_same_csr_outs
tanding.821450462
Directory /workspace/6.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.3775027620
Short name T173
Test name
Test status
Simulation time 21832993924 ps
CPU time 435.39 seconds
Started Feb 07 12:43:52 PM PST 24
Finished Feb 07 12:51:09 PM PST 24
Peak memory 264732 kb
Host smart-f096425c-9108-4fe6-9b43-9b0e1e7a2da0
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775027620 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.alert_handler_shadow_reg_errors_with_csr_rw.3775027620
Directory /workspace/6.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.3553205568
Short name T30
Test name
Test status
Simulation time 1080463514 ps
CPU time 18.03 seconds
Started Feb 07 12:43:47 PM PST 24
Finished Feb 07 12:44:09 PM PST 24
Peak memory 247344 kb
Host smart-e69cab0c-220e-4417-98f1-d0fe565600ce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3553205568 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_errors.3553205568
Directory /workspace/6.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.792181257
Short name T781
Test name
Test status
Simulation time 253527024 ps
CPU time 6.85 seconds
Started Feb 07 12:43:52 PM PST 24
Finished Feb 07 12:44:01 PM PST 24
Peak memory 250960 kb
Host smart-bce41dd0-f35e-433f-b704-8a666e2ab062
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792181257 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 7.alert_handler_csr_mem_rw_with_rand_reset.792181257
Directory /workspace/7.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.2936493126
Short name T828
Test name
Test status
Simulation time 511193379 ps
CPU time 9.18 seconds
Started Feb 07 12:43:58 PM PST 24
Finished Feb 07 12:44:08 PM PST 24
Peak memory 235740 kb
Host smart-e8b22f47-2a11-447c-be4c-c33e03a62efd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2936493126 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_rw.2936493126
Directory /workspace/7.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.3921101169
Short name T249
Test name
Test status
Simulation time 21764798 ps
CPU time 1.41 seconds
Started Feb 07 12:43:58 PM PST 24
Finished Feb 07 12:44:00 PM PST 24
Peak memory 234908 kb
Host smart-1b5acd86-d708-46d5-9e61-054e5cf53757
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3921101169 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_intr_test.3921101169
Directory /workspace/7.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.4141879265
Short name T798
Test name
Test status
Simulation time 185802547 ps
CPU time 20.7 seconds
Started Feb 07 12:43:56 PM PST 24
Finished Feb 07 12:44:18 PM PST 24
Peak memory 243100 kb
Host smart-af87aa36-86ee-40ec-98c4-41e2ffbfe562
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4141879265 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_same_csr_out
standing.4141879265
Directory /workspace/7.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.2611356250
Short name T154
Test name
Test status
Simulation time 3756602070 ps
CPU time 140.16 seconds
Started Feb 07 12:43:55 PM PST 24
Finished Feb 07 12:46:16 PM PST 24
Peak memory 256460 kb
Host smart-3c70cea5-c055-491f-a4a8-3a2df0d9df05
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2611356250 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shadow_reg_erro
rs.2611356250
Directory /workspace/7.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.3763831241
Short name T175
Test name
Test status
Simulation time 2270523267 ps
CPU time 308.48 seconds
Started Feb 07 12:43:51 PM PST 24
Finished Feb 07 12:49:01 PM PST 24
Peak memory 268424 kb
Host smart-75a7935b-d14f-4bf4-8a0f-852d204b5481
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763831241 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.alert_handler_shadow_reg_errors_with_csr_rw.3763831241
Directory /workspace/7.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.3230972280
Short name T183
Test name
Test status
Simulation time 33293607 ps
CPU time 5.09 seconds
Started Feb 07 12:43:50 PM PST 24
Finished Feb 07 12:43:57 PM PST 24
Peak memory 248032 kb
Host smart-268f8ebf-e934-4031-9df4-76871cfef879
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3230972280 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_errors.3230972280
Directory /workspace/7.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.4214874390
Short name T186
Test name
Test status
Simulation time 116804138 ps
CPU time 2.15 seconds
Started Feb 07 12:43:56 PM PST 24
Finished Feb 07 12:43:59 PM PST 24
Peak memory 236052 kb
Host smart-4b44fe98-7107-446e-a6e0-14db10cbedd6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4214874390 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_intg_err.4214874390
Directory /workspace/7.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.2867529941
Short name T812
Test name
Test status
Simulation time 59737835 ps
CPU time 6.74 seconds
Started Feb 07 12:44:04 PM PST 24
Finished Feb 07 12:44:12 PM PST 24
Peak memory 250988 kb
Host smart-6bfd9249-68f8-4a0f-88b9-4a69009270a0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867529941 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 8.alert_handler_csr_mem_rw_with_rand_reset.2867529941
Directory /workspace/8.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.3273347074
Short name T771
Test name
Test status
Simulation time 21191808 ps
CPU time 3.87 seconds
Started Feb 07 12:43:57 PM PST 24
Finished Feb 07 12:44:02 PM PST 24
Peak memory 235792 kb
Host smart-aff1c539-64e3-49f6-b7c3-319f0142e920
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3273347074 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_rw.3273347074
Directory /workspace/8.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.3268038971
Short name T356
Test name
Test status
Simulation time 9125359 ps
CPU time 1.35 seconds
Started Feb 07 12:43:59 PM PST 24
Finished Feb 07 12:44:01 PM PST 24
Peak memory 234928 kb
Host smart-2d2ce04b-c247-4ee9-b386-76ce8516580b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3268038971 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_intr_test.3268038971
Directory /workspace/8.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.2676110263
Short name T741
Test name
Test status
Simulation time 182652369 ps
CPU time 12.3 seconds
Started Feb 07 12:44:04 PM PST 24
Finished Feb 07 12:44:17 PM PST 24
Peak memory 239648 kb
Host smart-c72cca3e-6bad-47aa-9d46-bf5f2154baef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2676110263 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_same_csr_out
standing.2676110263
Directory /workspace/8.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.1032744736
Short name T816
Test name
Test status
Simulation time 290694092 ps
CPU time 9.33 seconds
Started Feb 07 12:44:01 PM PST 24
Finished Feb 07 12:44:12 PM PST 24
Peak memory 251628 kb
Host smart-d1286a0b-6519-499e-8831-e8f23d9284a1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1032744736 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_errors.1032744736
Directory /workspace/8.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.970833878
Short name T762
Test name
Test status
Simulation time 20142997 ps
CPU time 3.5 seconds
Started Feb 07 12:43:56 PM PST 24
Finished Feb 07 12:44:01 PM PST 24
Peak memory 238424 kb
Host smart-67a6e85c-78b7-4f52-af63-bf85a0ec41a5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970833878 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 9.alert_handler_csr_mem_rw_with_rand_reset.970833878
Directory /workspace/9.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.1301198711
Short name T769
Test name
Test status
Simulation time 20102495 ps
CPU time 3.67 seconds
Started Feb 07 12:44:04 PM PST 24
Finished Feb 07 12:44:09 PM PST 24
Peak memory 238716 kb
Host smart-a64578ff-7c34-4fd9-a70c-420dda306ba1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1301198711 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_rw.1301198711
Directory /workspace/9.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.2955197566
Short name T782
Test name
Test status
Simulation time 7316728 ps
CPU time 1.36 seconds
Started Feb 07 12:43:56 PM PST 24
Finished Feb 07 12:43:58 PM PST 24
Peak memory 234940 kb
Host smart-ac9c5501-7fce-4443-b237-30b122534cac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2955197566 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_intr_test.2955197566
Directory /workspace/9.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.1558221574
Short name T755
Test name
Test status
Simulation time 192108457 ps
CPU time 21.32 seconds
Started Feb 07 12:44:13 PM PST 24
Finished Feb 07 12:44:35 PM PST 24
Peak memory 247900 kb
Host smart-076ae00a-a7c8-4a37-bdaa-443b4c0cd98e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1558221574 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_same_csr_out
standing.1558221574
Directory /workspace/9.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.2965067218
Short name T162
Test name
Test status
Simulation time 3407929046 ps
CPU time 95.36 seconds
Started Feb 07 12:44:12 PM PST 24
Finished Feb 07 12:45:48 PM PST 24
Peak memory 256472 kb
Host smart-493db2ce-ad78-48f1-a06f-5fa20d094bb2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2965067218 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shadow_reg_erro
rs.2965067218
Directory /workspace/9.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.1133891448
Short name T185
Test name
Test status
Simulation time 142618947 ps
CPU time 10.71 seconds
Started Feb 07 12:44:03 PM PST 24
Finished Feb 07 12:44:14 PM PST 24
Peak memory 248012 kb
Host smart-fe8610d7-b6a1-4cc0-afa5-ef60b6d595dd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1133891448 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_errors.1133891448
Directory /workspace/9.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.1956905038
Short name T258
Test name
Test status
Simulation time 23583305 ps
CPU time 2.48 seconds
Started Feb 07 12:43:58 PM PST 24
Finished Feb 07 12:44:01 PM PST 24
Peak memory 235672 kb
Host smart-d49058fc-1360-4cbd-831b-204076ccebf1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1956905038 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_intg_err.1956905038
Directory /workspace/9.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/0.alert_handler_entropy.2253671795
Short name T665
Test name
Test status
Simulation time 217356003689 ps
CPU time 2263.35 seconds
Started Feb 07 01:08:52 PM PST 24
Finished Feb 07 01:46:38 PM PST 24
Peak memory 282536 kb
Host smart-54ec7b66-8493-4879-9d31-f2d26fd179bd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253671795 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy.2253671795
Directory /workspace/0.alert_handler_entropy/latest

Test location /workspace/coverage/default/0.alert_handler_entropy_stress.2308533894
Short name T227
Test name
Test status
Simulation time 412454517 ps
CPU time 11.51 seconds
Started Feb 07 01:08:52 PM PST 24
Finished Feb 07 01:09:06 PM PST 24
Peak memory 240184 kb
Host smart-eccd4e24-410d-479e-a208-849fb9d62776
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2308533894 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy_stress.2308533894
Directory /workspace/0.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/0.alert_handler_esc_alert_accum.1170693655
Short name T627
Test name
Test status
Simulation time 4260931098 ps
CPU time 127.88 seconds
Started Feb 07 01:08:51 PM PST 24
Finished Feb 07 01:11:02 PM PST 24
Peak memory 255860 kb
Host smart-4054d87c-b0c0-4b3a-927d-a3ae05da6014
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11706
93655 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_alert_accum.1170693655
Directory /workspace/0.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/0.alert_handler_esc_intr_timeout.279420746
Short name T650
Test name
Test status
Simulation time 245404087 ps
CPU time 26.8 seconds
Started Feb 07 01:08:50 PM PST 24
Finished Feb 07 01:09:21 PM PST 24
Peak memory 255104 kb
Host smart-bde533ff-0a7b-4c6d-b2b0-3ac801768965
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27942
0746 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_intr_timeout.279420746
Directory /workspace/0.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_lpg_stub_clk.2567976074
Short name T16
Test name
Test status
Simulation time 28394891273 ps
CPU time 1916.71 seconds
Started Feb 07 01:08:50 PM PST 24
Finished Feb 07 01:40:51 PM PST 24
Peak memory 281944 kb
Host smart-84234514-bf65-45ac-b327-40d08b18bb9c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567976074 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg_stub_clk.2567976074
Directory /workspace/0.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/0.alert_handler_ping_timeout.224596166
Short name T317
Test name
Test status
Simulation time 20945552256 ps
CPU time 243.96 seconds
Started Feb 07 01:08:52 PM PST 24
Finished Feb 07 01:12:58 PM PST 24
Peak memory 247332 kb
Host smart-f9d8f7fa-9f36-4929-ac4b-3b9ac026d844
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224596166 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_ping_timeout.224596166
Directory /workspace/0.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_random_alerts.906263760
Short name T585
Test name
Test status
Simulation time 2610648245 ps
CPU time 41.09 seconds
Started Feb 07 01:08:50 PM PST 24
Finished Feb 07 01:09:35 PM PST 24
Peak memory 255292 kb
Host smart-819797c9-7653-4c4f-b7ad-c5c62474ae04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90626
3760 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_alerts.906263760
Directory /workspace/0.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/0.alert_handler_random_classes.4095391482
Short name T551
Test name
Test status
Simulation time 217622868 ps
CPU time 18.55 seconds
Started Feb 07 01:08:51 PM PST 24
Finished Feb 07 01:09:13 PM PST 24
Peak memory 254532 kb
Host smart-7bb7bc62-8ea6-43d8-8280-bf9f2201b39e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40953
91482 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_classes.4095391482
Directory /workspace/0.alert_handler_random_classes/latest

Test location /workspace/coverage/default/0.alert_handler_sec_cm.2434917883
Short name T44
Test name
Test status
Simulation time 1338035977 ps
CPU time 59.7 seconds
Started Feb 07 01:08:49 PM PST 24
Finished Feb 07 01:09:54 PM PST 24
Peak memory 275956 kb
Host smart-31855872-d68b-4e68-a58f-a392294b53af
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2434917883 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sec_cm.2434917883
Directory /workspace/0.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/0.alert_handler_sig_int_fail.4081444083
Short name T707
Test name
Test status
Simulation time 790644537 ps
CPU time 43.47 seconds
Started Feb 07 01:08:52 PM PST 24
Finished Feb 07 01:09:38 PM PST 24
Peak memory 255352 kb
Host smart-6dcde734-f86f-4a5d-8edd-089ee09d7800
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40814
44083 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sig_int_fail.4081444083
Directory /workspace/0.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/0.alert_handler_smoke.153107204
Short name T401
Test name
Test status
Simulation time 509201941 ps
CPU time 8.8 seconds
Started Feb 07 01:08:52 PM PST 24
Finished Feb 07 01:09:03 PM PST 24
Peak memory 240180 kb
Host smart-ee08d3ef-810e-42d6-bd94-e24e6530b157
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15310
7204 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_smoke.153107204
Directory /workspace/0.alert_handler_smoke/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all.3638859857
Short name T631
Test name
Test status
Simulation time 2640056560 ps
CPU time 212.54 seconds
Started Feb 07 01:08:50 PM PST 24
Finished Feb 07 01:12:27 PM PST 24
Peak memory 253752 kb
Host smart-9e88c860-304b-4ee1-ab2d-8e5e52f13dc5
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638859857 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_han
dler_stress_all.3638859857
Directory /workspace/0.alert_handler_stress_all/latest

Test location /workspace/coverage/default/1.alert_handler_entropy.558294042
Short name T66
Test name
Test status
Simulation time 23670315491 ps
CPU time 1475.64 seconds
Started Feb 07 01:08:51 PM PST 24
Finished Feb 07 01:33:30 PM PST 24
Peak memory 273060 kb
Host smart-63bfe22b-6157-4ce9-9327-1f5e78a6c233
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558294042 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy.558294042
Directory /workspace/1.alert_handler_entropy/latest

Test location /workspace/coverage/default/1.alert_handler_entropy_stress.1180852033
Short name T517
Test name
Test status
Simulation time 984915502 ps
CPU time 16.95 seconds
Started Feb 07 01:08:50 PM PST 24
Finished Feb 07 01:09:11 PM PST 24
Peak memory 240208 kb
Host smart-0194596f-7880-4527-888e-b5d80e31b055
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1180852033 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy_stress.1180852033
Directory /workspace/1.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/1.alert_handler_esc_alert_accum.2677682134
Short name T239
Test name
Test status
Simulation time 10162223791 ps
CPU time 149.69 seconds
Started Feb 07 01:08:49 PM PST 24
Finished Feb 07 01:11:23 PM PST 24
Peak memory 249556 kb
Host smart-bdbf7b13-7aba-4533-8fac-f93d196e8935
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26776
82134 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_alert_accum.2677682134
Directory /workspace/1.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/1.alert_handler_esc_intr_timeout.3006944639
Short name T410
Test name
Test status
Simulation time 382407568 ps
CPU time 14.61 seconds
Started Feb 07 01:08:54 PM PST 24
Finished Feb 07 01:09:10 PM PST 24
Peak memory 254032 kb
Host smart-9908eacc-fe37-4efe-a1b8-5036f0dea846
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30069
44639 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_intr_timeout.3006944639
Directory /workspace/1.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_lpg.815072311
Short name T345
Test name
Test status
Simulation time 8372185411 ps
CPU time 793.15 seconds
Started Feb 07 01:08:52 PM PST 24
Finished Feb 07 01:22:08 PM PST 24
Peak memory 272376 kb
Host smart-29e1d748-bffb-4b8f-9813-3b9be98dea56
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815072311 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg.815072311
Directory /workspace/1.alert_handler_lpg/latest

Test location /workspace/coverage/default/1.alert_handler_lpg_stub_clk.3213075801
Short name T395
Test name
Test status
Simulation time 48573762369 ps
CPU time 2806.22 seconds
Started Feb 07 01:08:54 PM PST 24
Finished Feb 07 01:55:42 PM PST 24
Peak memory 286028 kb
Host smart-b20fc9d7-d53c-479c-975e-60bdadfd9420
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213075801 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg_stub_clk.3213075801
Directory /workspace/1.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/1.alert_handler_random_alerts.1226241428
Short name T252
Test name
Test status
Simulation time 386851587 ps
CPU time 9.09 seconds
Started Feb 07 01:08:49 PM PST 24
Finished Feb 07 01:09:02 PM PST 24
Peak memory 248408 kb
Host smart-84d20e99-dce2-4126-b5f7-c674e00e4967
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12262
41428 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_alerts.1226241428
Directory /workspace/1.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/1.alert_handler_random_classes.2756304167
Short name T405
Test name
Test status
Simulation time 681748683 ps
CPU time 44.02 seconds
Started Feb 07 01:08:53 PM PST 24
Finished Feb 07 01:09:38 PM PST 24
Peak memory 254604 kb
Host smart-cd4dfd9e-6d66-47eb-a121-e12c6d2fe664
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27563
04167 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_classes.2756304167
Directory /workspace/1.alert_handler_random_classes/latest

Test location /workspace/coverage/default/1.alert_handler_sec_cm.220472917
Short name T13
Test name
Test status
Simulation time 490408903 ps
CPU time 14.49 seconds
Started Feb 07 01:08:47 PM PST 24
Finished Feb 07 01:09:03 PM PST 24
Peak memory 264520 kb
Host smart-02776e21-cb18-418b-83eb-ce95e45e1215
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=220472917 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sec_cm.220472917
Directory /workspace/1.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/1.alert_handler_sig_int_fail.3743205565
Short name T270
Test name
Test status
Simulation time 1263494689 ps
CPU time 43.52 seconds
Started Feb 07 01:08:50 PM PST 24
Finished Feb 07 01:09:38 PM PST 24
Peak memory 254940 kb
Host smart-5a946723-e258-46fb-9536-39700e6d6eb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37432
05565 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sig_int_fail.3743205565
Directory /workspace/1.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/1.alert_handler_smoke.791949476
Short name T285
Test name
Test status
Simulation time 2387182903 ps
CPU time 22.24 seconds
Started Feb 07 01:08:49 PM PST 24
Finished Feb 07 01:09:15 PM PST 24
Peak memory 248728 kb
Host smart-d131af8d-7440-493a-bbaf-d8bdefe826a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79194
9476 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_smoke.791949476
Directory /workspace/1.alert_handler_smoke/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all.3908578777
Short name T446
Test name
Test status
Simulation time 2696000802 ps
CPU time 152.09 seconds
Started Feb 07 01:08:50 PM PST 24
Finished Feb 07 01:11:26 PM PST 24
Peak memory 256724 kb
Host smart-14e03d90-7569-4f7e-bee0-b70180036dbf
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908578777 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_han
dler_stress_all.3908578777
Directory /workspace/1.alert_handler_stress_all/latest

Test location /workspace/coverage/default/10.alert_handler_alert_accum_saturation.2491763891
Short name T212
Test name
Test status
Simulation time 92336961 ps
CPU time 4.24 seconds
Started Feb 07 01:09:22 PM PST 24
Finished Feb 07 01:09:31 PM PST 24
Peak memory 248472 kb
Host smart-0189d85c-6666-4e76-b1cb-d7c7a0cba356
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2491763891 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_alert_accum_saturation.2491763891
Directory /workspace/10.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/10.alert_handler_entropy.2180355798
Short name T485
Test name
Test status
Simulation time 97657474450 ps
CPU time 2747.51 seconds
Started Feb 07 01:09:15 PM PST 24
Finished Feb 07 01:55:09 PM PST 24
Peak memory 288936 kb
Host smart-5a56ebe8-01a3-4a90-96b6-a055a2e3abb8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180355798 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy.2180355798
Directory /workspace/10.alert_handler_entropy/latest

Test location /workspace/coverage/default/10.alert_handler_entropy_stress.398081450
Short name T247
Test name
Test status
Simulation time 733107918 ps
CPU time 12.3 seconds
Started Feb 07 01:09:16 PM PST 24
Finished Feb 07 01:09:34 PM PST 24
Peak memory 240264 kb
Host smart-714eadca-624a-4c50-8a83-34b452fe37b2
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=398081450 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy_stress.398081450
Directory /workspace/10.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/10.alert_handler_esc_alert_accum.2550015793
Short name T463
Test name
Test status
Simulation time 5769514115 ps
CPU time 155.87 seconds
Started Feb 07 01:09:21 PM PST 24
Finished Feb 07 01:12:03 PM PST 24
Peak memory 256728 kb
Host smart-d6a6adc1-67cf-4769-af11-b6ffb8133f84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25500
15793 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_alert_accum.2550015793
Directory /workspace/10.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/10.alert_handler_esc_intr_timeout.3430191715
Short name T374
Test name
Test status
Simulation time 559794115 ps
CPU time 39.37 seconds
Started Feb 07 01:09:21 PM PST 24
Finished Feb 07 01:10:06 PM PST 24
Peak memory 254736 kb
Host smart-377713be-6ce0-413a-94b4-6c815dca0421
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34301
91715 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_intr_timeout.3430191715
Directory /workspace/10.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_lpg_stub_clk.2502887698
Short name T121
Test name
Test status
Simulation time 15334640332 ps
CPU time 1438.45 seconds
Started Feb 07 01:09:16 PM PST 24
Finished Feb 07 01:33:20 PM PST 24
Peak memory 281340 kb
Host smart-5f93abbe-2422-4855-988b-fa7ca3d65ece
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502887698 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg_stub_clk.2502887698
Directory /workspace/10.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/10.alert_handler_ping_timeout.1456285904
Short name T548
Test name
Test status
Simulation time 14664121649 ps
CPU time 161.98 seconds
Started Feb 07 01:09:27 PM PST 24
Finished Feb 07 01:12:10 PM PST 24
Peak memory 247236 kb
Host smart-f7e78582-6730-42fc-949c-d9c977f71deb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456285904 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_ping_timeout.1456285904
Directory /workspace/10.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_random_alerts.2843454957
Short name T633
Test name
Test status
Simulation time 1205134193 ps
CPU time 20.51 seconds
Started Feb 07 01:09:20 PM PST 24
Finished Feb 07 01:09:46 PM PST 24
Peak memory 255196 kb
Host smart-4c0898e1-0d4d-43c1-8b3d-a8aa3571fb92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28434
54957 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_alerts.2843454957
Directory /workspace/10.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/10.alert_handler_random_classes.2276348893
Short name T391
Test name
Test status
Simulation time 4732968111 ps
CPU time 72.56 seconds
Started Feb 07 01:09:13 PM PST 24
Finished Feb 07 01:10:33 PM PST 24
Peak memory 254920 kb
Host smart-73b58dd1-924e-46c7-a192-8a15bc9e0471
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22763
48893 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_classes.2276348893
Directory /workspace/10.alert_handler_random_classes/latest

Test location /workspace/coverage/default/10.alert_handler_sig_int_fail.3618332853
Short name T461
Test name
Test status
Simulation time 503830569 ps
CPU time 20.68 seconds
Started Feb 07 01:09:12 PM PST 24
Finished Feb 07 01:09:37 PM PST 24
Peak memory 246708 kb
Host smart-7ffc7e86-0f2b-4ba2-84ad-181ff1b182f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36183
32853 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_sig_int_fail.3618332853
Directory /workspace/10.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/10.alert_handler_smoke.3799887103
Short name T439
Test name
Test status
Simulation time 2084107520 ps
CPU time 26.66 seconds
Started Feb 07 01:09:21 PM PST 24
Finished Feb 07 01:09:54 PM PST 24
Peak memory 248532 kb
Host smart-22bca14b-49bd-423d-9cd3-2b8061ed3240
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37998
87103 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_smoke.3799887103
Directory /workspace/10.alert_handler_smoke/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all.3405915020
Short name T113
Test name
Test status
Simulation time 9805917161 ps
CPU time 387.8 seconds
Started Feb 07 01:09:15 PM PST 24
Finished Feb 07 01:15:49 PM PST 24
Peak memory 253132 kb
Host smart-593c9762-1331-46e0-8f13-2b255a61330f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405915020 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_ha
ndler_stress_all.3405915020
Directory /workspace/10.alert_handler_stress_all/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all_with_rand_reset.4278189397
Short name T619
Test name
Test status
Simulation time 44411921052 ps
CPU time 3028.67 seconds
Started Feb 07 01:09:18 PM PST 24
Finished Feb 07 01:59:51 PM PST 24
Peak memory 305468 kb
Host smart-417ae19a-0d08-4e42-a10d-89691a94f80e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278189397 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 10.alert_handler_stress_all_with_rand_reset.4278189397
Directory /workspace/10.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.alert_handler_alert_accum_saturation.2991215498
Short name T223
Test name
Test status
Simulation time 87806733 ps
CPU time 3.61 seconds
Started Feb 07 01:09:13 PM PST 24
Finished Feb 07 01:09:25 PM PST 24
Peak memory 248660 kb
Host smart-60176350-0b6e-4741-80c6-2f3601406275
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2991215498 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_alert_accum_saturation.2991215498
Directory /workspace/11.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/11.alert_handler_entropy.2332945388
Short name T61
Test name
Test status
Simulation time 89402122577 ps
CPU time 1303.4 seconds
Started Feb 07 01:09:16 PM PST 24
Finished Feb 07 01:31:05 PM PST 24
Peak memory 289484 kb
Host smart-38626586-35da-41f2-b230-8a41242bd4eb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332945388 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy.2332945388
Directory /workspace/11.alert_handler_entropy/latest

Test location /workspace/coverage/default/11.alert_handler_entropy_stress.1630936189
Short name T504
Test name
Test status
Simulation time 901661690 ps
CPU time 39.31 seconds
Started Feb 07 01:09:28 PM PST 24
Finished Feb 07 01:10:08 PM PST 24
Peak memory 248456 kb
Host smart-b2d788b5-191a-4520-991e-73178e5314ce
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1630936189 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy_stress.1630936189
Directory /workspace/11.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/11.alert_handler_esc_alert_accum.1552792886
Short name T387
Test name
Test status
Simulation time 4476215995 ps
CPU time 109.29 seconds
Started Feb 07 01:09:14 PM PST 24
Finished Feb 07 01:11:10 PM PST 24
Peak memory 256008 kb
Host smart-469d9f09-355f-4095-9fb3-b39249f6f427
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15527
92886 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_alert_accum.1552792886
Directory /workspace/11.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/11.alert_handler_esc_intr_timeout.4089471074
Short name T229
Test name
Test status
Simulation time 90654798 ps
CPU time 3.6 seconds
Started Feb 07 01:09:27 PM PST 24
Finished Feb 07 01:09:32 PM PST 24
Peak memory 238560 kb
Host smart-8f65a75b-6312-4e24-b3de-9dabf0e81120
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40894
71074 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_intr_timeout.4089471074
Directory /workspace/11.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_lpg_stub_clk.3548959361
Short name T131
Test name
Test status
Simulation time 128508888321 ps
CPU time 1937.39 seconds
Started Feb 07 01:09:27 PM PST 24
Finished Feb 07 01:41:46 PM PST 24
Peak memory 267032 kb
Host smart-625bde32-3ff2-4092-9013-fb56295f80be
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548959361 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg_stub_clk.3548959361
Directory /workspace/11.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/11.alert_handler_random_alerts.4125808419
Short name T599
Test name
Test status
Simulation time 128249630 ps
CPU time 8.87 seconds
Started Feb 07 01:09:15 PM PST 24
Finished Feb 07 01:09:30 PM PST 24
Peak memory 248292 kb
Host smart-bc0bcfca-e7bd-48fe-8d4f-0e13417f31ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41258
08419 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_alerts.4125808419
Directory /workspace/11.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/11.alert_handler_random_classes.194522093
Short name T426
Test name
Test status
Simulation time 97088736 ps
CPU time 3.64 seconds
Started Feb 07 01:09:27 PM PST 24
Finished Feb 07 01:09:32 PM PST 24
Peak memory 238564 kb
Host smart-10e357a1-48bd-4516-b6cd-8a6546afa81a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19452
2093 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_classes.194522093
Directory /workspace/11.alert_handler_random_classes/latest

Test location /workspace/coverage/default/11.alert_handler_sig_int_fail.1580683291
Short name T283
Test name
Test status
Simulation time 1559777181 ps
CPU time 21.83 seconds
Started Feb 07 01:09:21 PM PST 24
Finished Feb 07 01:09:49 PM PST 24
Peak memory 246692 kb
Host smart-932b2c29-12c1-4f59-a8c5-8d1624dffde1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15806
83291 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_sig_int_fail.1580683291
Directory /workspace/11.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/11.alert_handler_smoke.1856145983
Short name T397
Test name
Test status
Simulation time 273135546 ps
CPU time 16.83 seconds
Started Feb 07 01:09:21 PM PST 24
Finished Feb 07 01:09:43 PM PST 24
Peak memory 248396 kb
Host smart-8ef3d857-a4e3-496b-a36a-7ba49572189c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18561
45983 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_smoke.1856145983
Directory /workspace/11.alert_handler_smoke/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all_with_rand_reset.2026293501
Short name T272
Test name
Test status
Simulation time 42128558884 ps
CPU time 2596.82 seconds
Started Feb 07 01:09:20 PM PST 24
Finished Feb 07 01:52:40 PM PST 24
Peak memory 299420 kb
Host smart-c3f2ba9d-c072-4923-b68f-7272ad80fa11
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026293501 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 11.alert_handler_stress_all_with_rand_reset.2026293501
Directory /workspace/11.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.alert_handler_entropy.2561147004
Short name T84
Test name
Test status
Simulation time 29143785619 ps
CPU time 1618.18 seconds
Started Feb 07 01:09:31 PM PST 24
Finished Feb 07 01:36:30 PM PST 24
Peak memory 272816 kb
Host smart-75a47a02-bc47-499e-a044-10946e88e223
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561147004 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy.2561147004
Directory /workspace/12.alert_handler_entropy/latest

Test location /workspace/coverage/default/12.alert_handler_entropy_stress.2617808746
Short name T380
Test name
Test status
Simulation time 496172728 ps
CPU time 20.96 seconds
Started Feb 07 01:09:35 PM PST 24
Finished Feb 07 01:09:57 PM PST 24
Peak memory 240116 kb
Host smart-09cd6129-4efe-495e-b7e2-03f01b277d5e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2617808746 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy_stress.2617808746
Directory /workspace/12.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/12.alert_handler_esc_alert_accum.721088855
Short name T622
Test name
Test status
Simulation time 815357605 ps
CPU time 39.07 seconds
Started Feb 07 01:09:34 PM PST 24
Finished Feb 07 01:10:14 PM PST 24
Peak memory 255440 kb
Host smart-d38d3006-2da3-43b6-b2c8-89b0a1850c12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72108
8855 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_alert_accum.721088855
Directory /workspace/12.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/12.alert_handler_esc_intr_timeout.3932848396
Short name T568
Test name
Test status
Simulation time 516919941 ps
CPU time 12.81 seconds
Started Feb 07 01:09:32 PM PST 24
Finished Feb 07 01:09:46 PM PST 24
Peak memory 254684 kb
Host smart-556b05e8-5332-415e-a132-92671dad5140
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39328
48396 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_intr_timeout.3932848396
Directory /workspace/12.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_lpg.2482827164
Short name T582
Test name
Test status
Simulation time 92710235806 ps
CPU time 933.39 seconds
Started Feb 07 01:09:36 PM PST 24
Finished Feb 07 01:25:10 PM PST 24
Peak memory 271080 kb
Host smart-acfa2578-7af5-4e15-88d7-0d237016a2e3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482827164 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg.2482827164
Directory /workspace/12.alert_handler_lpg/latest

Test location /workspace/coverage/default/12.alert_handler_lpg_stub_clk.2896898495
Short name T462
Test name
Test status
Simulation time 10625209647 ps
CPU time 1209.68 seconds
Started Feb 07 01:09:32 PM PST 24
Finished Feb 07 01:29:42 PM PST 24
Peak memory 288992 kb
Host smart-80ae956f-fbc0-4e58-bc50-331d0e73b81a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896898495 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg_stub_clk.2896898495
Directory /workspace/12.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/12.alert_handler_random_alerts.2111307202
Short name T370
Test name
Test status
Simulation time 8413056661 ps
CPU time 34.99 seconds
Started Feb 07 01:09:36 PM PST 24
Finished Feb 07 01:10:12 PM PST 24
Peak memory 256772 kb
Host smart-64ae204c-f54b-47f0-9a60-243f6515ac4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21113
07202 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_alerts.2111307202
Directory /workspace/12.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/12.alert_handler_random_classes.1870301440
Short name T497
Test name
Test status
Simulation time 40307909 ps
CPU time 5.75 seconds
Started Feb 07 01:09:36 PM PST 24
Finished Feb 07 01:09:42 PM PST 24
Peak memory 252172 kb
Host smart-fd57defb-31ce-463d-bab9-dae25a4de8cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18703
01440 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_classes.1870301440
Directory /workspace/12.alert_handler_random_classes/latest

Test location /workspace/coverage/default/12.alert_handler_sig_int_fail.82707745
Short name T310
Test name
Test status
Simulation time 193258620 ps
CPU time 5.76 seconds
Started Feb 07 01:09:38 PM PST 24
Finished Feb 07 01:09:44 PM PST 24
Peak memory 248432 kb
Host smart-5acac9d5-c95e-46d7-ad8f-5067245d1a44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82707
745 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_sig_int_fail.82707745
Directory /workspace/12.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/12.alert_handler_smoke.2976704830
Short name T403
Test name
Test status
Simulation time 435445808 ps
CPU time 38.55 seconds
Started Feb 07 01:09:16 PM PST 24
Finished Feb 07 01:10:00 PM PST 24
Peak memory 248432 kb
Host smart-a7342a55-56c0-4b4e-a52b-18e6440b44ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29767
04830 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_smoke.2976704830
Directory /workspace/12.alert_handler_smoke/latest

Test location /workspace/coverage/default/13.alert_handler_entropy_stress.2466544499
Short name T709
Test name
Test status
Simulation time 3072024277 ps
CPU time 19.96 seconds
Started Feb 07 01:09:32 PM PST 24
Finished Feb 07 01:09:52 PM PST 24
Peak memory 248556 kb
Host smart-4f1464eb-d1bc-425b-8bd8-dfdc5714980e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2466544499 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy_stress.2466544499
Directory /workspace/13.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/13.alert_handler_esc_alert_accum.2101650555
Short name T557
Test name
Test status
Simulation time 1244240852 ps
CPU time 50.98 seconds
Started Feb 07 01:09:36 PM PST 24
Finished Feb 07 01:10:28 PM PST 24
Peak memory 256028 kb
Host smart-68d69607-09f6-49ef-aee0-3fe8904d75d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21016
50555 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_alert_accum.2101650555
Directory /workspace/13.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/13.alert_handler_esc_intr_timeout.1703224233
Short name T417
Test name
Test status
Simulation time 561864168 ps
CPU time 21.69 seconds
Started Feb 07 01:09:31 PM PST 24
Finished Feb 07 01:09:54 PM PST 24
Peak memory 254228 kb
Host smart-7e047a5e-2a2d-4b32-9316-acfd72dcf5ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17032
24233 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_intr_timeout.1703224233
Directory /workspace/13.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_lpg_stub_clk.1077086917
Short name T419
Test name
Test status
Simulation time 37803454349 ps
CPU time 2139.73 seconds
Started Feb 07 01:09:36 PM PST 24
Finished Feb 07 01:45:16 PM PST 24
Peak memory 272916 kb
Host smart-e9c75364-b9e9-4356-9c05-ecc27631c6c9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077086917 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg_stub_clk.1077086917
Directory /workspace/13.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/13.alert_handler_ping_timeout.3239980552
Short name T313
Test name
Test status
Simulation time 7148285721 ps
CPU time 227.92 seconds
Started Feb 07 01:09:35 PM PST 24
Finished Feb 07 01:13:24 PM PST 24
Peak memory 247324 kb
Host smart-68bceb13-2c76-41ae-a7f9-502506dab7ec
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239980552 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_ping_timeout.3239980552
Directory /workspace/13.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_random_alerts.3948905336
Short name T443
Test name
Test status
Simulation time 1339448548 ps
CPU time 31.68 seconds
Started Feb 07 01:09:33 PM PST 24
Finished Feb 07 01:10:05 PM PST 24
Peak memory 254896 kb
Host smart-0249e4a4-fd62-42f4-a4fe-de9233dec011
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39489
05336 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_alerts.3948905336
Directory /workspace/13.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/13.alert_handler_random_classes.3743898649
Short name T245
Test name
Test status
Simulation time 331731720 ps
CPU time 38.3 seconds
Started Feb 07 01:09:40 PM PST 24
Finished Feb 07 01:10:19 PM PST 24
Peak memory 248420 kb
Host smart-3313603e-f249-45b3-9ab6-985f12433eaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37438
98649 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_classes.3743898649
Directory /workspace/13.alert_handler_random_classes/latest

Test location /workspace/coverage/default/13.alert_handler_sig_int_fail.2218818400
Short name T105
Test name
Test status
Simulation time 697669240 ps
CPU time 12.94 seconds
Started Feb 07 01:09:38 PM PST 24
Finished Feb 07 01:09:52 PM PST 24
Peak memory 248428 kb
Host smart-cf8dab44-4445-4590-abf3-ab41350cda9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22188
18400 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_sig_int_fail.2218818400
Directory /workspace/13.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/13.alert_handler_smoke.1834118187
Short name T366
Test name
Test status
Simulation time 482600462 ps
CPU time 29.98 seconds
Started Feb 07 01:09:36 PM PST 24
Finished Feb 07 01:10:07 PM PST 24
Peak memory 248412 kb
Host smart-fc14b062-8c28-4937-b619-45cd675ac7ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18341
18187 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_smoke.1834118187
Directory /workspace/13.alert_handler_smoke/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all_with_rand_reset.2064612437
Short name T257
Test name
Test status
Simulation time 57804553367 ps
CPU time 5379.5 seconds
Started Feb 07 01:09:37 PM PST 24
Finished Feb 07 02:39:18 PM PST 24
Peak memory 338096 kb
Host smart-21b41d4b-6103-49c3-b6f4-4c407e1e8309
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064612437 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.alert_handler_stress_all_with_rand_reset.2064612437
Directory /workspace/13.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.alert_handler_alert_accum_saturation.3287525958
Short name T211
Test name
Test status
Simulation time 63824086 ps
CPU time 3.51 seconds
Started Feb 07 01:09:36 PM PST 24
Finished Feb 07 01:09:40 PM PST 24
Peak memory 248652 kb
Host smart-447ef7e4-e5d8-43cc-b797-0995db087b20
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3287525958 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_alert_accum_saturation.3287525958
Directory /workspace/14.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/14.alert_handler_entropy.4120090402
Short name T641
Test name
Test status
Simulation time 64418057823 ps
CPU time 1420.1 seconds
Started Feb 07 01:09:33 PM PST 24
Finished Feb 07 01:33:14 PM PST 24
Peak memory 285288 kb
Host smart-3fd93e2b-5515-47cf-86d9-d602fadc6629
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4120090402 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy.4120090402
Directory /workspace/14.alert_handler_entropy/latest

Test location /workspace/coverage/default/14.alert_handler_entropy_stress.2800239976
Short name T7
Test name
Test status
Simulation time 379920730 ps
CPU time 11.28 seconds
Started Feb 07 01:09:30 PM PST 24
Finished Feb 07 01:09:42 PM PST 24
Peak memory 240192 kb
Host smart-72430e63-da84-49de-a5d1-1dc8069ff8e4
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2800239976 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy_stress.2800239976
Directory /workspace/14.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/14.alert_handler_esc_alert_accum.3809309261
Short name T511
Test name
Test status
Simulation time 19829700528 ps
CPU time 191.18 seconds
Started Feb 07 01:09:32 PM PST 24
Finished Feb 07 01:12:44 PM PST 24
Peak memory 256732 kb
Host smart-aedbbd2a-0de5-4168-b123-b66885e0ad6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38093
09261 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_alert_accum.3809309261
Directory /workspace/14.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/14.alert_handler_esc_intr_timeout.2258890702
Short name T675
Test name
Test status
Simulation time 761228346 ps
CPU time 50.59 seconds
Started Feb 07 01:09:29 PM PST 24
Finished Feb 07 01:10:20 PM PST 24
Peak memory 248028 kb
Host smart-eed86348-9f12-4a73-be2a-f615bab1a968
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22588
90702 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_intr_timeout.2258890702
Directory /workspace/14.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_lpg.3026110935
Short name T305
Test name
Test status
Simulation time 26293208478 ps
CPU time 1680.59 seconds
Started Feb 07 01:09:31 PM PST 24
Finished Feb 07 01:37:33 PM PST 24
Peak memory 272724 kb
Host smart-cf42fd01-1f47-4120-821e-ed3c4f0d30e5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026110935 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg.3026110935
Directory /workspace/14.alert_handler_lpg/latest

Test location /workspace/coverage/default/14.alert_handler_lpg_stub_clk.3503875291
Short name T636
Test name
Test status
Simulation time 119296358027 ps
CPU time 1870.18 seconds
Started Feb 07 01:09:36 PM PST 24
Finished Feb 07 01:40:48 PM PST 24
Peak memory 272452 kb
Host smart-9e9d4dc0-8f19-4e38-9fdf-6c47d495dd75
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503875291 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg_stub_clk.3503875291
Directory /workspace/14.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/14.alert_handler_ping_timeout.3401609457
Short name T320
Test name
Test status
Simulation time 10992434710 ps
CPU time 446.64 seconds
Started Feb 07 01:09:42 PM PST 24
Finished Feb 07 01:17:09 PM PST 24
Peak memory 248500 kb
Host smart-dcd00190-b30a-4e69-a894-c5d16b2bb915
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401609457 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_ping_timeout.3401609457
Directory /workspace/14.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_random_alerts.3053021387
Short name T678
Test name
Test status
Simulation time 408684416 ps
CPU time 23.35 seconds
Started Feb 07 01:09:36 PM PST 24
Finished Feb 07 01:10:00 PM PST 24
Peak memory 248328 kb
Host smart-01db3979-f6f1-4f56-959f-137365d6bb8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30530
21387 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_alerts.3053021387
Directory /workspace/14.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/14.alert_handler_random_classes.2053046631
Short name T513
Test name
Test status
Simulation time 346035468 ps
CPU time 13.66 seconds
Started Feb 07 01:09:36 PM PST 24
Finished Feb 07 01:09:51 PM PST 24
Peak memory 251860 kb
Host smart-94b7268b-2401-4522-b420-c0736d20e9b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20530
46631 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_classes.2053046631
Directory /workspace/14.alert_handler_random_classes/latest

Test location /workspace/coverage/default/14.alert_handler_sig_int_fail.959893248
Short name T510
Test name
Test status
Simulation time 494777317 ps
CPU time 9.24 seconds
Started Feb 07 01:09:36 PM PST 24
Finished Feb 07 01:09:46 PM PST 24
Peak memory 240128 kb
Host smart-3267c1bf-cc42-43b2-bde8-132cd2f27d4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95989
3248 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_sig_int_fail.959893248
Directory /workspace/14.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/14.alert_handler_smoke.3568486577
Short name T505
Test name
Test status
Simulation time 1489675448 ps
CPU time 28.57 seconds
Started Feb 07 01:09:40 PM PST 24
Finished Feb 07 01:10:10 PM PST 24
Peak memory 248440 kb
Host smart-a2e259a4-7a63-4818-ab40-5680ab2e552e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35684
86577 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_smoke.3568486577
Directory /workspace/14.alert_handler_smoke/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all.579629878
Short name T74
Test name
Test status
Simulation time 94339105471 ps
CPU time 1583.64 seconds
Started Feb 07 01:09:31 PM PST 24
Finished Feb 07 01:35:55 PM PST 24
Peak memory 281332 kb
Host smart-bc61ca72-5643-4934-af1e-537f48577944
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579629878 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_han
dler_stress_all.579629878
Directory /workspace/14.alert_handler_stress_all/latest

Test location /workspace/coverage/default/15.alert_handler_alert_accum_saturation.410562053
Short name T214
Test name
Test status
Simulation time 176422962 ps
CPU time 3.41 seconds
Started Feb 07 01:09:40 PM PST 24
Finished Feb 07 01:09:45 PM PST 24
Peak memory 248656 kb
Host smart-f0b65e44-4605-436d-adef-59a0a534db68
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=410562053 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_alert_accum_saturation.410562053
Directory /workspace/15.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/15.alert_handler_entropy.81775307
Short name T444
Test name
Test status
Simulation time 18653501833 ps
CPU time 1003.27 seconds
Started Feb 07 01:09:38 PM PST 24
Finished Feb 07 01:26:22 PM PST 24
Peak memory 283860 kb
Host smart-e814bbc5-88be-46fe-8da2-83bde2895d6a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81775307 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy.81775307
Directory /workspace/15.alert_handler_entropy/latest

Test location /workspace/coverage/default/15.alert_handler_entropy_stress.3128299680
Short name T544
Test name
Test status
Simulation time 208578526 ps
CPU time 11.1 seconds
Started Feb 07 01:09:40 PM PST 24
Finished Feb 07 01:09:52 PM PST 24
Peak memory 240224 kb
Host smart-1291d3d4-0a96-4569-9239-29dca678e6a5
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3128299680 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy_stress.3128299680
Directory /workspace/15.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/15.alert_handler_esc_alert_accum.3974509836
Short name T479
Test name
Test status
Simulation time 5311004591 ps
CPU time 269.79 seconds
Started Feb 07 01:09:40 PM PST 24
Finished Feb 07 01:14:10 PM PST 24
Peak memory 256296 kb
Host smart-9f46f662-3913-4787-835c-1e05236ca1b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39745
09836 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_alert_accum.3974509836
Directory /workspace/15.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/15.alert_handler_esc_intr_timeout.1719054042
Short name T97
Test name
Test status
Simulation time 382188955 ps
CPU time 32.33 seconds
Started Feb 07 01:09:44 PM PST 24
Finished Feb 07 01:10:17 PM PST 24
Peak memory 253968 kb
Host smart-9f966cff-bd22-48bf-a0f7-f4030473d059
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17190
54042 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_intr_timeout.1719054042
Directory /workspace/15.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_lpg.3990380724
Short name T588
Test name
Test status
Simulation time 39982733589 ps
CPU time 2321.09 seconds
Started Feb 07 01:09:41 PM PST 24
Finished Feb 07 01:48:23 PM PST 24
Peak memory 286084 kb
Host smart-a67f3e79-c68c-4823-b03d-469612b9aac6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990380724 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg.3990380724
Directory /workspace/15.alert_handler_lpg/latest

Test location /workspace/coverage/default/15.alert_handler_lpg_stub_clk.3911308090
Short name T717
Test name
Test status
Simulation time 103588824460 ps
CPU time 1590.68 seconds
Started Feb 07 01:09:41 PM PST 24
Finished Feb 07 01:36:13 PM PST 24
Peak memory 272368 kb
Host smart-50ea1e5b-ccda-4d00-b9d8-2f7943217e2e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911308090 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg_stub_clk.3911308090
Directory /workspace/15.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/15.alert_handler_ping_timeout.1290529292
Short name T612
Test name
Test status
Simulation time 4362875661 ps
CPU time 177.7 seconds
Started Feb 07 01:09:40 PM PST 24
Finished Feb 07 01:12:39 PM PST 24
Peak memory 247400 kb
Host smart-b74857ea-fa30-4227-b135-e4b122a8d8f2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290529292 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_ping_timeout.1290529292
Directory /workspace/15.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_random_alerts.4215048736
Short name T657
Test name
Test status
Simulation time 3707145270 ps
CPU time 62.73 seconds
Started Feb 07 01:09:41 PM PST 24
Finished Feb 07 01:10:44 PM PST 24
Peak memory 248552 kb
Host smart-d9b70858-867c-44b7-9343-4cadaeb946d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42150
48736 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_alerts.4215048736
Directory /workspace/15.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/15.alert_handler_random_classes.589653772
Short name T530
Test name
Test status
Simulation time 445562016 ps
CPU time 16.53 seconds
Started Feb 07 01:09:44 PM PST 24
Finished Feb 07 01:10:01 PM PST 24
Peak memory 253876 kb
Host smart-c63ac9dc-4ebd-4832-8b3e-0a3ea0a61920
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58965
3772 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_classes.589653772
Directory /workspace/15.alert_handler_random_classes/latest

Test location /workspace/coverage/default/15.alert_handler_sig_int_fail.2192793358
Short name T416
Test name
Test status
Simulation time 2511822898 ps
CPU time 25.89 seconds
Started Feb 07 01:09:49 PM PST 24
Finished Feb 07 01:10:15 PM PST 24
Peak memory 246592 kb
Host smart-233b9158-81e4-4e58-ab1b-9d2a6b3d59bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21927
93358 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_sig_int_fail.2192793358
Directory /workspace/15.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/15.alert_handler_smoke.2008184315
Short name T449
Test name
Test status
Simulation time 2995700303 ps
CPU time 45.38 seconds
Started Feb 07 01:09:39 PM PST 24
Finished Feb 07 01:10:25 PM PST 24
Peak memory 248592 kb
Host smart-da23148e-e59c-4db6-9e8e-f3b13b50ce9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20081
84315 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_smoke.2008184315
Directory /workspace/15.alert_handler_smoke/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all.2412735201
Short name T100
Test name
Test status
Simulation time 295632157821 ps
CPU time 3233.27 seconds
Started Feb 07 01:09:49 PM PST 24
Finished Feb 07 02:03:43 PM PST 24
Peak memory 297236 kb
Host smart-aafb09fa-52dc-4cea-9bb5-c797d9a6caeb
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412735201 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_ha
ndler_stress_all.2412735201
Directory /workspace/15.alert_handler_stress_all/latest

Test location /workspace/coverage/default/16.alert_handler_alert_accum_saturation.1044585987
Short name T213
Test name
Test status
Simulation time 60546630 ps
CPU time 3.53 seconds
Started Feb 07 01:09:39 PM PST 24
Finished Feb 07 01:09:43 PM PST 24
Peak memory 248704 kb
Host smart-4be6eab5-b61a-4fe4-aa62-1db8053c5477
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1044585987 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_alert_accum_saturation.1044585987
Directory /workspace/16.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/16.alert_handler_entropy.1634286104
Short name T246
Test name
Test status
Simulation time 89549369470 ps
CPU time 2402.77 seconds
Started Feb 07 01:09:41 PM PST 24
Finished Feb 07 01:49:44 PM PST 24
Peak memory 287876 kb
Host smart-bb95ac11-5bfc-4d15-8f26-8d9ff1ae9e04
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634286104 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy.1634286104
Directory /workspace/16.alert_handler_entropy/latest

Test location /workspace/coverage/default/16.alert_handler_entropy_stress.2626425837
Short name T469
Test name
Test status
Simulation time 1072441112 ps
CPU time 45.56 seconds
Started Feb 07 01:09:38 PM PST 24
Finished Feb 07 01:10:24 PM PST 24
Peak memory 240184 kb
Host smart-455f238e-a6c6-43eb-85b4-883af9d2e3c2
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2626425837 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy_stress.2626425837
Directory /workspace/16.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/16.alert_handler_esc_alert_accum.3020451953
Short name T713
Test name
Test status
Simulation time 5632106322 ps
CPU time 183.18 seconds
Started Feb 07 01:09:44 PM PST 24
Finished Feb 07 01:12:47 PM PST 24
Peak memory 256176 kb
Host smart-3aa1591d-a13d-4874-96ea-a4f2b8edb363
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30204
51953 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_alert_accum.3020451953
Directory /workspace/16.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/16.alert_handler_esc_intr_timeout.3456011706
Short name T385
Test name
Test status
Simulation time 228235146 ps
CPU time 15.99 seconds
Started Feb 07 01:09:41 PM PST 24
Finished Feb 07 01:09:58 PM PST 24
Peak memory 254776 kb
Host smart-a8d4aabe-6fa6-4636-a98f-6b8a5846131a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34560
11706 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_intr_timeout.3456011706
Directory /workspace/16.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_lpg_stub_clk.2418538782
Short name T593
Test name
Test status
Simulation time 72939242654 ps
CPU time 2100.91 seconds
Started Feb 07 01:09:41 PM PST 24
Finished Feb 07 01:44:43 PM PST 24
Peak memory 270068 kb
Host smart-886318c0-4da9-40a3-bf20-520b6629932c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418538782 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg_stub_clk.2418538782
Directory /workspace/16.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/16.alert_handler_ping_timeout.1410855428
Short name T526
Test name
Test status
Simulation time 6161302152 ps
CPU time 255.05 seconds
Started Feb 07 01:09:39 PM PST 24
Finished Feb 07 01:13:55 PM PST 24
Peak memory 247164 kb
Host smart-e8dbc327-4ad3-45a4-9aeb-5444d7633b56
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410855428 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_ping_timeout.1410855428
Directory /workspace/16.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_random_alerts.2974609260
Short name T580
Test name
Test status
Simulation time 324166564 ps
CPU time 13.71 seconds
Started Feb 07 01:09:40 PM PST 24
Finished Feb 07 01:09:55 PM PST 24
Peak memory 255132 kb
Host smart-4c3d7493-008f-4a1f-bcf2-eb77737aca0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29746
09260 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_alerts.2974609260
Directory /workspace/16.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/16.alert_handler_sig_int_fail.1495512166
Short name T556
Test name
Test status
Simulation time 458369765 ps
CPU time 11.95 seconds
Started Feb 07 01:09:42 PM PST 24
Finished Feb 07 01:09:55 PM PST 24
Peak memory 255196 kb
Host smart-7dd9cdd0-9d57-495b-a96b-25ac9af18b49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14955
12166 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_sig_int_fail.1495512166
Directory /workspace/16.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/16.alert_handler_smoke.4235830527
Short name T677
Test name
Test status
Simulation time 833561851 ps
CPU time 24.76 seconds
Started Feb 07 01:09:41 PM PST 24
Finished Feb 07 01:10:07 PM PST 24
Peak memory 248448 kb
Host smart-426583fb-8ba2-435a-be58-aa71ea951f35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42358
30527 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_smoke.4235830527
Directory /workspace/16.alert_handler_smoke/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all.1189156387
Short name T537
Test name
Test status
Simulation time 8050322745 ps
CPU time 833.38 seconds
Started Feb 07 01:09:39 PM PST 24
Finished Feb 07 01:23:33 PM PST 24
Peak memory 273112 kb
Host smart-1b883b71-6b92-4185-ad83-c4a84c38c605
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189156387 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_ha
ndler_stress_all.1189156387
Directory /workspace/16.alert_handler_stress_all/latest

Test location /workspace/coverage/default/17.alert_handler_alert_accum_saturation.2501511797
Short name T210
Test name
Test status
Simulation time 55014506 ps
CPU time 4.49 seconds
Started Feb 07 01:10:03 PM PST 24
Finished Feb 07 01:10:08 PM PST 24
Peak memory 248660 kb
Host smart-751f67ab-b0d5-456d-be04-bcae81f28e96
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2501511797 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_alert_accum_saturation.2501511797
Directory /workspace/17.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/17.alert_handler_entropy.2362371525
Short name T438
Test name
Test status
Simulation time 52687135404 ps
CPU time 1621.11 seconds
Started Feb 07 01:09:57 PM PST 24
Finished Feb 07 01:36:58 PM PST 24
Peak memory 272684 kb
Host smart-fbb7f1e6-5459-4b33-89cb-62d115fc076f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2362371525 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy.2362371525
Directory /workspace/17.alert_handler_entropy/latest

Test location /workspace/coverage/default/17.alert_handler_entropy_stress.3793965433
Short name T383
Test name
Test status
Simulation time 2578724204 ps
CPU time 56.01 seconds
Started Feb 07 01:10:08 PM PST 24
Finished Feb 07 01:11:05 PM PST 24
Peak memory 240368 kb
Host smart-0e239221-a7cf-4c4b-92e8-2445f4fb3cc2
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3793965433 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy_stress.3793965433
Directory /workspace/17.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/17.alert_handler_esc_alert_accum.2384710474
Short name T696
Test name
Test status
Simulation time 3154211549 ps
CPU time 200.41 seconds
Started Feb 07 01:09:57 PM PST 24
Finished Feb 07 01:13:18 PM PST 24
Peak memory 256228 kb
Host smart-6021ee28-ec20-4f78-95ca-e63fcf9846c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23847
10474 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_alert_accum.2384710474
Directory /workspace/17.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/17.alert_handler_esc_intr_timeout.3057264829
Short name T503
Test name
Test status
Simulation time 519231855 ps
CPU time 13.26 seconds
Started Feb 07 01:09:58 PM PST 24
Finished Feb 07 01:10:12 PM PST 24
Peak memory 252476 kb
Host smart-0186f262-ff89-47c7-8e9d-58e53edd20b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30572
64829 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_intr_timeout.3057264829
Directory /workspace/17.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_lpg.4092148408
Short name T616
Test name
Test status
Simulation time 24463715521 ps
CPU time 1590.31 seconds
Started Feb 07 01:09:56 PM PST 24
Finished Feb 07 01:36:27 PM PST 24
Peak memory 270112 kb
Host smart-d20f8566-2311-4e62-bea5-7f0371916962
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092148408 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg.4092148408
Directory /workspace/17.alert_handler_lpg/latest

Test location /workspace/coverage/default/17.alert_handler_lpg_stub_clk.2316530276
Short name T293
Test name
Test status
Simulation time 128564240009 ps
CPU time 1812.52 seconds
Started Feb 07 01:09:57 PM PST 24
Finished Feb 07 01:40:10 PM PST 24
Peak memory 273060 kb
Host smart-1df9e3cb-7d6b-4aa6-a55f-2205085b50ab
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316530276 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg_stub_clk.2316530276
Directory /workspace/17.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/17.alert_handler_ping_timeout.2655261194
Short name T674
Test name
Test status
Simulation time 5085659982 ps
CPU time 198.94 seconds
Started Feb 07 01:09:56 PM PST 24
Finished Feb 07 01:13:16 PM PST 24
Peak memory 248536 kb
Host smart-859d4b8c-1c0d-4b58-81b3-0152278b4742
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655261194 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_ping_timeout.2655261194
Directory /workspace/17.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_random_alerts.3468989667
Short name T711
Test name
Test status
Simulation time 26735516 ps
CPU time 5.09 seconds
Started Feb 07 01:09:39 PM PST 24
Finished Feb 07 01:09:45 PM PST 24
Peak memory 240224 kb
Host smart-008be9d7-8114-44a9-8b9a-10c18325a42f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34689
89667 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_alerts.3468989667
Directory /workspace/17.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/17.alert_handler_random_classes.3783916146
Short name T719
Test name
Test status
Simulation time 1159872601 ps
CPU time 36.34 seconds
Started Feb 07 01:09:43 PM PST 24
Finished Feb 07 01:10:20 PM PST 24
Peak memory 246836 kb
Host smart-a0f73c2f-404a-490d-860f-102cdc78ca38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37839
16146 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_classes.3783916146
Directory /workspace/17.alert_handler_random_classes/latest

Test location /workspace/coverage/default/17.alert_handler_sig_int_fail.3418821901
Short name T273
Test name
Test status
Simulation time 540963285 ps
CPU time 35.15 seconds
Started Feb 07 01:10:06 PM PST 24
Finished Feb 07 01:10:42 PM PST 24
Peak memory 246668 kb
Host smart-e9dd7f6a-0c9d-4241-abf6-e00b4bd11cd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34188
21901 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_sig_int_fail.3418821901
Directory /workspace/17.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/17.alert_handler_smoke.4265417688
Short name T725
Test name
Test status
Simulation time 742258988 ps
CPU time 11.59 seconds
Started Feb 07 01:09:41 PM PST 24
Finished Feb 07 01:09:53 PM PST 24
Peak memory 248492 kb
Host smart-9fb39949-ebe1-427a-bba8-57d9aed4991e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42654
17688 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_smoke.4265417688
Directory /workspace/17.alert_handler_smoke/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all.2793279783
Short name T418
Test name
Test status
Simulation time 2843738942 ps
CPU time 85.38 seconds
Started Feb 07 01:09:58 PM PST 24
Finished Feb 07 01:11:24 PM PST 24
Peak memory 250304 kb
Host smart-1650fbd2-128b-4c9c-ab1f-2d1503f4f8d7
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793279783 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_ha
ndler_stress_all.2793279783
Directory /workspace/17.alert_handler_stress_all/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all_with_rand_reset.4028966211
Short name T490
Test name
Test status
Simulation time 50165180911 ps
CPU time 3481.23 seconds
Started Feb 07 01:10:06 PM PST 24
Finished Feb 07 02:08:08 PM PST 24
Peak memory 302580 kb
Host smart-7a367118-154e-4e19-94db-32562cc6cbba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028966211 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 17.alert_handler_stress_all_with_rand_reset.4028966211
Directory /workspace/17.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.alert_handler_alert_accum_saturation.1837439263
Short name T217
Test name
Test status
Simulation time 165762583 ps
CPU time 3.78 seconds
Started Feb 07 01:09:57 PM PST 24
Finished Feb 07 01:10:01 PM PST 24
Peak memory 248632 kb
Host smart-1e4600fd-5fd7-4aee-887f-b7bd5a1b8108
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1837439263 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_alert_accum_saturation.1837439263
Directory /workspace/18.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/18.alert_handler_entropy.738095343
Short name T615
Test name
Test status
Simulation time 10881591105 ps
CPU time 1046.5 seconds
Started Feb 07 01:09:56 PM PST 24
Finished Feb 07 01:27:24 PM PST 24
Peak memory 285472 kb
Host smart-fec15002-328b-490a-abdd-590267b42e0f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738095343 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy.738095343
Directory /workspace/18.alert_handler_entropy/latest

Test location /workspace/coverage/default/18.alert_handler_entropy_stress.4056564079
Short name T465
Test name
Test status
Simulation time 1684205999 ps
CPU time 21.91 seconds
Started Feb 07 01:09:59 PM PST 24
Finished Feb 07 01:10:22 PM PST 24
Peak memory 240228 kb
Host smart-402ea0e3-f081-4401-abef-30ca959f0de1
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4056564079 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy_stress.4056564079
Directory /workspace/18.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/18.alert_handler_esc_alert_accum.3151759890
Short name T253
Test name
Test status
Simulation time 5407885320 ps
CPU time 316.24 seconds
Started Feb 07 01:10:06 PM PST 24
Finished Feb 07 01:15:23 PM PST 24
Peak memory 256144 kb
Host smart-bcc93a75-5846-4a67-836f-976dfdb96a09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31517
59890 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_alert_accum.3151759890
Directory /workspace/18.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/18.alert_handler_esc_intr_timeout.974502725
Short name T578
Test name
Test status
Simulation time 3697844569 ps
CPU time 27.06 seconds
Started Feb 07 01:09:59 PM PST 24
Finished Feb 07 01:10:26 PM PST 24
Peak memory 254812 kb
Host smart-05211f2c-157e-4370-9a8d-8d5dad8007c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97450
2725 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_intr_timeout.974502725
Directory /workspace/18.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_lpg.4262976519
Short name T581
Test name
Test status
Simulation time 11732403350 ps
CPU time 871.16 seconds
Started Feb 07 01:09:57 PM PST 24
Finished Feb 07 01:24:29 PM PST 24
Peak memory 272928 kb
Host smart-c6b61894-c0ad-4373-808a-b89a2b98d73c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262976519 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg.4262976519
Directory /workspace/18.alert_handler_lpg/latest

Test location /workspace/coverage/default/18.alert_handler_lpg_stub_clk.1167194515
Short name T129
Test name
Test status
Simulation time 80113734527 ps
CPU time 2631.22 seconds
Started Feb 07 01:09:55 PM PST 24
Finished Feb 07 01:53:47 PM PST 24
Peak memory 288788 kb
Host smart-34f9acf8-abbc-4e21-9175-e0c7daf140de
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167194515 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg_stub_clk.1167194515
Directory /workspace/18.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/18.alert_handler_ping_timeout.3347967461
Short name T292
Test name
Test status
Simulation time 4805047901 ps
CPU time 186.13 seconds
Started Feb 07 01:09:56 PM PST 24
Finished Feb 07 01:13:03 PM PST 24
Peak memory 247464 kb
Host smart-0d03dffb-0160-4cde-893c-c577afd045f6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347967461 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_ping_timeout.3347967461
Directory /workspace/18.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_random_alerts.2479739195
Short name T65
Test name
Test status
Simulation time 2161793007 ps
CPU time 39.2 seconds
Started Feb 07 01:09:58 PM PST 24
Finished Feb 07 01:10:38 PM PST 24
Peak memory 248596 kb
Host smart-93a2cb3c-f370-43d0-896c-753a98d21e5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24797
39195 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_alerts.2479739195
Directory /workspace/18.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/18.alert_handler_random_classes.3701409446
Short name T728
Test name
Test status
Simulation time 355493150 ps
CPU time 23.93 seconds
Started Feb 07 01:09:59 PM PST 24
Finished Feb 07 01:10:24 PM PST 24
Peak memory 246640 kb
Host smart-e7c72695-353f-4624-a2b5-15f71cdea20d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37014
09446 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_classes.3701409446
Directory /workspace/18.alert_handler_random_classes/latest

Test location /workspace/coverage/default/18.alert_handler_sig_int_fail.1041217887
Short name T400
Test name
Test status
Simulation time 1159789075 ps
CPU time 38.64 seconds
Started Feb 07 01:09:55 PM PST 24
Finished Feb 07 01:10:34 PM PST 24
Peak memory 248504 kb
Host smart-46fa7e4e-d8c8-4284-af94-ef60a6d19143
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10412
17887 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_sig_int_fail.1041217887
Directory /workspace/18.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/18.alert_handler_smoke.2703799218
Short name T605
Test name
Test status
Simulation time 1538358694 ps
CPU time 39.76 seconds
Started Feb 07 01:09:55 PM PST 24
Finished Feb 07 01:10:35 PM PST 24
Peak memory 248440 kb
Host smart-ac0b1da3-2d62-4aa6-bb86-24cc31e96385
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27037
99218 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_smoke.2703799218
Directory /workspace/18.alert_handler_smoke/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all_with_rand_reset.1994615327
Short name T507
Test name
Test status
Simulation time 226498529328 ps
CPU time 3703.09 seconds
Started Feb 07 01:09:55 PM PST 24
Finished Feb 07 02:11:39 PM PST 24
Peak memory 306040 kb
Host smart-34be6303-aed7-49ff-a27b-46bd5233f404
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994615327 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.alert_handler_stress_all_with_rand_reset.1994615327
Directory /workspace/18.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.alert_handler_alert_accum_saturation.2848610296
Short name T56
Test name
Test status
Simulation time 35850714 ps
CPU time 3.49 seconds
Started Feb 07 01:10:18 PM PST 24
Finished Feb 07 01:10:22 PM PST 24
Peak memory 248632 kb
Host smart-d11977c5-744b-40d7-bb25-e1578630bf0b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2848610296 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_alert_accum_saturation.2848610296
Directory /workspace/19.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/19.alert_handler_entropy.238133256
Short name T632
Test name
Test status
Simulation time 337333250534 ps
CPU time 1947.02 seconds
Started Feb 07 01:09:59 PM PST 24
Finished Feb 07 01:42:27 PM PST 24
Peak memory 281600 kb
Host smart-4b39eb97-51bc-4b8d-92d0-071dcaa301d1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238133256 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy.238133256
Directory /workspace/19.alert_handler_entropy/latest

Test location /workspace/coverage/default/19.alert_handler_entropy_stress.1400396888
Short name T378
Test name
Test status
Simulation time 1405691193 ps
CPU time 48.28 seconds
Started Feb 07 01:09:59 PM PST 24
Finished Feb 07 01:10:48 PM PST 24
Peak memory 248412 kb
Host smart-05bf0367-be51-4d29-8f63-74bce15da580
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1400396888 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy_stress.1400396888
Directory /workspace/19.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/19.alert_handler_esc_alert_accum.3414061267
Short name T294
Test name
Test status
Simulation time 5117834547 ps
CPU time 116.9 seconds
Started Feb 07 01:09:59 PM PST 24
Finished Feb 07 01:11:56 PM PST 24
Peak memory 256800 kb
Host smart-3534b61f-5389-4065-ad58-e32e5e745027
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34140
61267 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_alert_accum.3414061267
Directory /workspace/19.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/19.alert_handler_esc_intr_timeout.3633595766
Short name T621
Test name
Test status
Simulation time 1191215555 ps
CPU time 73.21 seconds
Started Feb 07 01:10:07 PM PST 24
Finished Feb 07 01:11:21 PM PST 24
Peak memory 255916 kb
Host smart-8be46870-d8c7-4455-a583-3e52edc91b5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36335
95766 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_intr_timeout.3633595766
Directory /workspace/19.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_lpg.2605324398
Short name T584
Test name
Test status
Simulation time 18881146099 ps
CPU time 778.91 seconds
Started Feb 07 01:10:08 PM PST 24
Finished Feb 07 01:23:08 PM PST 24
Peak memory 272360 kb
Host smart-d6eebd0e-89bc-49e8-94a6-aabc519c8e41
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2605324398 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg.2605324398
Directory /workspace/19.alert_handler_lpg/latest

Test location /workspace/coverage/default/19.alert_handler_lpg_stub_clk.2039542204
Short name T720
Test name
Test status
Simulation time 82580928565 ps
CPU time 2408.99 seconds
Started Feb 07 01:10:05 PM PST 24
Finished Feb 07 01:50:15 PM PST 24
Peak memory 288464 kb
Host smart-d9b293d2-6bee-485b-8fe2-aec920c7fbae
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039542204 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg_stub_clk.2039542204
Directory /workspace/19.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/19.alert_handler_random_alerts.803578852
Short name T460
Test name
Test status
Simulation time 29489296 ps
CPU time 4.28 seconds
Started Feb 07 01:10:07 PM PST 24
Finished Feb 07 01:10:12 PM PST 24
Peak memory 248384 kb
Host smart-8806efac-c2cb-453d-bd41-86b345c2425c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80357
8852 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_alerts.803578852
Directory /workspace/19.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/19.alert_handler_random_classes.3523529771
Short name T423
Test name
Test status
Simulation time 492177315 ps
CPU time 7.65 seconds
Started Feb 07 01:09:58 PM PST 24
Finished Feb 07 01:10:06 PM PST 24
Peak memory 252308 kb
Host smart-6ab5fd1f-348f-4d80-ab6b-7525b8bb7760
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35235
29771 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_classes.3523529771
Directory /workspace/19.alert_handler_random_classes/latest

Test location /workspace/coverage/default/19.alert_handler_sig_int_fail.1366705610
Short name T266
Test name
Test status
Simulation time 606065210 ps
CPU time 48.85 seconds
Started Feb 07 01:09:54 PM PST 24
Finished Feb 07 01:10:44 PM PST 24
Peak memory 255196 kb
Host smart-c8d3f3c0-6d53-4987-acaf-ce0ae562e065
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13667
05610 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_sig_int_fail.1366705610
Directory /workspace/19.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/19.alert_handler_smoke.1710784213
Short name T301
Test name
Test status
Simulation time 5383844809 ps
CPU time 20.69 seconds
Started Feb 07 01:10:06 PM PST 24
Finished Feb 07 01:10:27 PM PST 24
Peak memory 248536 kb
Host smart-4de4cbac-138f-4864-ab77-a8ee5b3dca3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17107
84213 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_smoke.1710784213
Directory /workspace/19.alert_handler_smoke/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all.2188262225
Short name T458
Test name
Test status
Simulation time 316426580993 ps
CPU time 2444.61 seconds
Started Feb 07 01:10:14 PM PST 24
Finished Feb 07 01:50:59 PM PST 24
Peak memory 289380 kb
Host smart-836de6d1-bd23-47d2-b88c-87762e29154d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188262225 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_ha
ndler_stress_all.2188262225
Directory /workspace/19.alert_handler_stress_all/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all_with_rand_reset.245818381
Short name T77
Test name
Test status
Simulation time 128064280753 ps
CPU time 2066.82 seconds
Started Feb 07 01:10:14 PM PST 24
Finished Feb 07 01:44:41 PM PST 24
Peak memory 289292 kb
Host smart-a30c87f8-5cb1-45b8-bb11-5f89d639524c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245818381 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 19.alert_handler_stress_all_with_rand_reset.245818381
Directory /workspace/19.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.alert_handler_alert_accum_saturation.2469309603
Short name T222
Test name
Test status
Simulation time 17885831 ps
CPU time 2.66 seconds
Started Feb 07 01:08:59 PM PST 24
Finished Feb 07 01:09:02 PM PST 24
Peak memory 248604 kb
Host smart-e97ea5b4-c1dc-4b34-a941-0926a71884c8
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2469309603 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_alert_accum_saturation.2469309603
Directory /workspace/2.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/2.alert_handler_entropy.2684343333
Short name T122
Test name
Test status
Simulation time 66140258955 ps
CPU time 1187.11 seconds
Started Feb 07 01:08:59 PM PST 24
Finished Feb 07 01:28:47 PM PST 24
Peak memory 288904 kb
Host smart-7ea5a718-f9a3-4fea-8353-59aa06621b7f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2684343333 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy.2684343333
Directory /workspace/2.alert_handler_entropy/latest

Test location /workspace/coverage/default/2.alert_handler_entropy_stress.2075513269
Short name T407
Test name
Test status
Simulation time 1911857330 ps
CPU time 12.12 seconds
Started Feb 07 01:09:02 PM PST 24
Finished Feb 07 01:09:16 PM PST 24
Peak memory 248368 kb
Host smart-754eac08-f2ef-4e96-893f-8c1dba6c2058
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2075513269 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy_stress.2075513269
Directory /workspace/2.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/2.alert_handler_esc_alert_accum.3255094671
Short name T377
Test name
Test status
Simulation time 6802731478 ps
CPU time 197.48 seconds
Started Feb 07 01:08:59 PM PST 24
Finished Feb 07 01:12:18 PM PST 24
Peak memory 256156 kb
Host smart-92396747-4361-4e33-9b04-a5e4b6010ad4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32550
94671 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_alert_accum.3255094671
Directory /workspace/2.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/2.alert_handler_esc_intr_timeout.3689522892
Short name T468
Test name
Test status
Simulation time 633364723 ps
CPU time 38.09 seconds
Started Feb 07 01:08:58 PM PST 24
Finished Feb 07 01:09:37 PM PST 24
Peak memory 254888 kb
Host smart-6e20409c-cfc5-4e97-ab5e-7fcb61da4c4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36895
22892 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_intr_timeout.3689522892
Directory /workspace/2.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_lpg.2482094937
Short name T733
Test name
Test status
Simulation time 84081962082 ps
CPU time 1709.45 seconds
Started Feb 07 01:08:57 PM PST 24
Finished Feb 07 01:37:27 PM PST 24
Peak memory 289376 kb
Host smart-4cd529ea-195b-4a77-991f-75de13cde25b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482094937 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg.2482094937
Directory /workspace/2.alert_handler_lpg/latest

Test location /workspace/coverage/default/2.alert_handler_lpg_stub_clk.676027294
Short name T562
Test name
Test status
Simulation time 25521400533 ps
CPU time 1003.28 seconds
Started Feb 07 01:09:06 PM PST 24
Finished Feb 07 01:25:50 PM PST 24
Peak memory 281348 kb
Host smart-dce0923b-37bf-41ee-88fc-d99a7a7df469
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676027294 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg_stub_clk.676027294
Directory /workspace/2.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/2.alert_handler_ping_timeout.3921052531
Short name T613
Test name
Test status
Simulation time 9234752641 ps
CPU time 378.04 seconds
Started Feb 07 01:09:01 PM PST 24
Finished Feb 07 01:15:21 PM PST 24
Peak memory 247452 kb
Host smart-259d563a-c94f-46e8-b5b7-d4a5e4eccb3a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921052531 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_ping_timeout.3921052531
Directory /workspace/2.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_random_alerts.573511945
Short name T471
Test name
Test status
Simulation time 1629074726 ps
CPU time 24.57 seconds
Started Feb 07 01:08:54 PM PST 24
Finished Feb 07 01:09:20 PM PST 24
Peak memory 248348 kb
Host smart-08df2567-36b5-452b-aa0d-89c09b93084d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57351
1945 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_alerts.573511945
Directory /workspace/2.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/2.alert_handler_random_classes.4260809809
Short name T437
Test name
Test status
Simulation time 1157537182 ps
CPU time 41.51 seconds
Started Feb 07 01:08:59 PM PST 24
Finished Feb 07 01:09:41 PM PST 24
Peak memory 254652 kb
Host smart-5a4bcec7-05a7-479b-a1f5-4a1473d72890
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42608
09809 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_classes.4260809809
Directory /workspace/2.alert_handler_random_classes/latest

Test location /workspace/coverage/default/2.alert_handler_sec_cm.1195386566
Short name T43
Test name
Test status
Simulation time 464828907 ps
CPU time 26.95 seconds
Started Feb 07 01:09:06 PM PST 24
Finished Feb 07 01:09:34 PM PST 24
Peak memory 277368 kb
Host smart-e1f63964-cfb5-4f22-ada3-5fbd026b8616
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1195386566 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sec_cm.1195386566
Directory /workspace/2.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/2.alert_handler_sig_int_fail.1594085261
Short name T389
Test name
Test status
Simulation time 684974045 ps
CPU time 48.78 seconds
Started Feb 07 01:09:06 PM PST 24
Finished Feb 07 01:09:55 PM PST 24
Peak memory 254724 kb
Host smart-a1806495-9cc0-4bd6-b69c-1afb8a448d79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15940
85261 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sig_int_fail.1594085261
Directory /workspace/2.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/2.alert_handler_smoke.1627046127
Short name T106
Test name
Test status
Simulation time 3116065929 ps
CPU time 36.97 seconds
Started Feb 07 01:08:50 PM PST 24
Finished Feb 07 01:09:31 PM PST 24
Peak memory 248596 kb
Host smart-199d4d10-594a-4880-8130-e10374470b7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16270
46127 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_smoke.1627046127
Directory /workspace/2.alert_handler_smoke/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all.856052274
Short name T291
Test name
Test status
Simulation time 22331013675 ps
CPU time 286.83 seconds
Started Feb 07 01:09:00 PM PST 24
Finished Feb 07 01:13:48 PM PST 24
Peak memory 256744 kb
Host smart-c526ff82-245d-42c5-97cd-ef2e3c1e31e4
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856052274 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_hand
ler_stress_all.856052274
Directory /workspace/2.alert_handler_stress_all/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all_with_rand_reset.1935203935
Short name T429
Test name
Test status
Simulation time 42637461284 ps
CPU time 845.37 seconds
Started Feb 07 01:09:00 PM PST 24
Finished Feb 07 01:23:07 PM PST 24
Peak memory 268764 kb
Host smart-3514f614-7dc0-461a-a1b8-23bd67d4ca28
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935203935 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.alert_handler_stress_all_with_rand_reset.1935203935
Directory /workspace/2.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.alert_handler_entropy.444380992
Short name T104
Test name
Test status
Simulation time 702893597329 ps
CPU time 2142.39 seconds
Started Feb 07 01:10:18 PM PST 24
Finished Feb 07 01:46:01 PM PST 24
Peak memory 281316 kb
Host smart-bc34f2fb-e4f6-469f-a23e-2ea5a08f9034
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444380992 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_entropy.444380992
Directory /workspace/20.alert_handler_entropy/latest

Test location /workspace/coverage/default/20.alert_handler_esc_alert_accum.3900537268
Short name T538
Test name
Test status
Simulation time 4043856946 ps
CPU time 68.4 seconds
Started Feb 07 01:10:16 PM PST 24
Finished Feb 07 01:11:25 PM PST 24
Peak memory 248100 kb
Host smart-b7f39cff-97b5-41cb-92ab-5bf2cbf54a42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39005
37268 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_alert_accum.3900537268
Directory /workspace/20.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/20.alert_handler_esc_intr_timeout.525334393
Short name T20
Test name
Test status
Simulation time 226387168 ps
CPU time 5.13 seconds
Started Feb 07 01:10:15 PM PST 24
Finished Feb 07 01:10:21 PM PST 24
Peak memory 238504 kb
Host smart-9cca54cf-6fbd-4f3f-94b2-41c90e149870
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52533
4393 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_intr_timeout.525334393
Directory /workspace/20.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_lpg_stub_clk.390499492
Short name T368
Test name
Test status
Simulation time 18961765894 ps
CPU time 1197.18 seconds
Started Feb 07 01:10:17 PM PST 24
Finished Feb 07 01:30:15 PM PST 24
Peak memory 288952 kb
Host smart-7b708d58-20e2-489e-9136-c3293268fe49
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390499492 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg_stub_clk.390499492
Directory /workspace/20.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/20.alert_handler_ping_timeout.967247716
Short name T455
Test name
Test status
Simulation time 2954374161 ps
CPU time 121.34 seconds
Started Feb 07 01:10:16 PM PST 24
Finished Feb 07 01:12:18 PM PST 24
Peak memory 246388 kb
Host smart-88bc15ca-60f5-490d-af02-83f6129a4ea7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967247716 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_ping_timeout.967247716
Directory /workspace/20.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_random_alerts.75644596
Short name T244
Test name
Test status
Simulation time 2900798134 ps
CPU time 52.9 seconds
Started Feb 07 01:10:15 PM PST 24
Finished Feb 07 01:11:09 PM PST 24
Peak memory 248532 kb
Host smart-95173575-6c0c-4de6-8493-4f5a1fd697d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75644
596 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_alerts.75644596
Directory /workspace/20.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/20.alert_handler_random_classes.557093826
Short name T496
Test name
Test status
Simulation time 1592977230 ps
CPU time 30.02 seconds
Started Feb 07 01:10:18 PM PST 24
Finished Feb 07 01:10:48 PM PST 24
Peak memory 254724 kb
Host smart-8af932f2-9128-455a-ae16-a2b821d45cc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55709
3826 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_classes.557093826
Directory /workspace/20.alert_handler_random_classes/latest

Test location /workspace/coverage/default/20.alert_handler_sig_int_fail.3348187300
Short name T592
Test name
Test status
Simulation time 145377550 ps
CPU time 9.66 seconds
Started Feb 07 01:10:18 PM PST 24
Finished Feb 07 01:10:28 PM PST 24
Peak memory 248496 kb
Host smart-03f8df50-0440-4899-827d-7711a877b1a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33481
87300 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_sig_int_fail.3348187300
Directory /workspace/20.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/20.alert_handler_smoke.2445027137
Short name T583
Test name
Test status
Simulation time 1185696839 ps
CPU time 47.23 seconds
Started Feb 07 01:10:16 PM PST 24
Finished Feb 07 01:11:03 PM PST 24
Peak memory 248396 kb
Host smart-b18e6c3b-3ded-4379-b48e-96dfb7b60a50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24450
27137 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_smoke.2445027137
Directory /workspace/20.alert_handler_smoke/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all.2925296314
Short name T606
Test name
Test status
Simulation time 944147564661 ps
CPU time 3170.12 seconds
Started Feb 07 01:10:16 PM PST 24
Finished Feb 07 02:03:07 PM PST 24
Peak memory 289336 kb
Host smart-96f3f60d-be5e-4f19-afb6-4e36189bbb25
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925296314 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_ha
ndler_stress_all.2925296314
Directory /workspace/20.alert_handler_stress_all/latest

Test location /workspace/coverage/default/21.alert_handler_entropy.2631089964
Short name T441
Test name
Test status
Simulation time 48839614850 ps
CPU time 1136.49 seconds
Started Feb 07 01:10:13 PM PST 24
Finished Feb 07 01:29:10 PM PST 24
Peak memory 283360 kb
Host smart-c92ea985-94f1-432e-9526-a971f344d707
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631089964 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_entropy.2631089964
Directory /workspace/21.alert_handler_entropy/latest

Test location /workspace/coverage/default/21.alert_handler_esc_alert_accum.2871130248
Short name T54
Test name
Test status
Simulation time 367621243 ps
CPU time 29.5 seconds
Started Feb 07 01:10:15 PM PST 24
Finished Feb 07 01:10:45 PM PST 24
Peak memory 255528 kb
Host smart-7fc48389-13bb-46b4-834d-450547557ab9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28711
30248 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_alert_accum.2871130248
Directory /workspace/21.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/21.alert_handler_esc_intr_timeout.2033527139
Short name T652
Test name
Test status
Simulation time 146154832 ps
CPU time 9.79 seconds
Started Feb 07 01:10:15 PM PST 24
Finished Feb 07 01:10:25 PM PST 24
Peak memory 246548 kb
Host smart-44aa3cbc-d477-4832-a1f3-ffe3430e9355
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20335
27139 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_intr_timeout.2033527139
Directory /workspace/21.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_lpg.4144008769
Short name T723
Test name
Test status
Simulation time 11747989998 ps
CPU time 992.68 seconds
Started Feb 07 01:10:23 PM PST 24
Finished Feb 07 01:26:57 PM PST 24
Peak memory 273128 kb
Host smart-813f62e3-17f8-42b1-9ea6-038b4a16584c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144008769 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg.4144008769
Directory /workspace/21.alert_handler_lpg/latest

Test location /workspace/coverage/default/21.alert_handler_lpg_stub_clk.3055956375
Short name T18
Test name
Test status
Simulation time 112376316746 ps
CPU time 1426.66 seconds
Started Feb 07 01:10:34 PM PST 24
Finished Feb 07 01:34:22 PM PST 24
Peak memory 288864 kb
Host smart-a7cbd5f6-9ddd-480d-b01d-785bc119904d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055956375 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg_stub_clk.3055956375
Directory /workspace/21.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/21.alert_handler_ping_timeout.2968845875
Short name T672
Test name
Test status
Simulation time 24451723602 ps
CPU time 163 seconds
Started Feb 07 01:10:16 PM PST 24
Finished Feb 07 01:13:00 PM PST 24
Peak memory 247360 kb
Host smart-f1e516c2-13c3-45e2-9c41-e4de8c9c39b8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968845875 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_ping_timeout.2968845875
Directory /workspace/21.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_random_alerts.1493260872
Short name T597
Test name
Test status
Simulation time 911009495 ps
CPU time 39.37 seconds
Started Feb 07 01:10:17 PM PST 24
Finished Feb 07 01:10:57 PM PST 24
Peak memory 248428 kb
Host smart-54f1c0f7-d350-4e36-991f-1b1cac807dab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14932
60872 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_alerts.1493260872
Directory /workspace/21.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/21.alert_handler_random_classes.1754813192
Short name T699
Test name
Test status
Simulation time 1694591749 ps
CPU time 26.4 seconds
Started Feb 07 01:10:17 PM PST 24
Finished Feb 07 01:10:44 PM PST 24
Peak memory 254268 kb
Host smart-c6620f02-01f6-4bd3-a0aa-28a9f10abe87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17548
13192 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_classes.1754813192
Directory /workspace/21.alert_handler_random_classes/latest

Test location /workspace/coverage/default/21.alert_handler_sig_int_fail.4187345621
Short name T279
Test name
Test status
Simulation time 188478823 ps
CPU time 22.17 seconds
Started Feb 07 01:10:12 PM PST 24
Finished Feb 07 01:10:35 PM PST 24
Peak memory 246680 kb
Host smart-7edfe91b-ece6-46ba-89f5-97d35e2285ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41873
45621 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_sig_int_fail.4187345621
Directory /workspace/21.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/21.alert_handler_smoke.4246199341
Short name T360
Test name
Test status
Simulation time 821962220 ps
CPU time 51.89 seconds
Started Feb 07 01:10:13 PM PST 24
Finished Feb 07 01:11:05 PM PST 24
Peak memory 248432 kb
Host smart-a5458140-627a-4d1d-938c-34165470567b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42461
99341 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_smoke.4246199341
Directory /workspace/21.alert_handler_smoke/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all.3897757967
Short name T393
Test name
Test status
Simulation time 1202937601 ps
CPU time 69.31 seconds
Started Feb 07 01:10:28 PM PST 24
Finished Feb 07 01:11:38 PM PST 24
Peak memory 254632 kb
Host smart-08a8bc73-81ec-4248-929c-4d35298cf3af
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897757967 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_ha
ndler_stress_all.3897757967
Directory /workspace/21.alert_handler_stress_all/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all_with_rand_reset.1530674993
Short name T260
Test name
Test status
Simulation time 83768367579 ps
CPU time 1600.12 seconds
Started Feb 07 01:10:30 PM PST 24
Finished Feb 07 01:37:10 PM PST 24
Peak memory 288708 kb
Host smart-6ff873f1-ce82-4928-8075-670c930cd6a1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530674993 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.alert_handler_stress_all_with_rand_reset.1530674993
Directory /workspace/21.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.alert_handler_entropy.346880951
Short name T560
Test name
Test status
Simulation time 90665478039 ps
CPU time 2358 seconds
Started Feb 07 01:10:24 PM PST 24
Finished Feb 07 01:49:43 PM PST 24
Peak memory 288776 kb
Host smart-df7b764d-0fdb-460c-9ccd-235ec4fb1f8b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346880951 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_entropy.346880951
Directory /workspace/22.alert_handler_entropy/latest

Test location /workspace/coverage/default/22.alert_handler_esc_alert_accum.2607101679
Short name T364
Test name
Test status
Simulation time 6144535004 ps
CPU time 341.54 seconds
Started Feb 07 01:10:24 PM PST 24
Finished Feb 07 01:16:07 PM PST 24
Peak memory 256060 kb
Host smart-3b4c2544-af6d-438e-8aad-c4f13240e5b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26071
01679 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_alert_accum.2607101679
Directory /workspace/22.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/22.alert_handler_esc_intr_timeout.2735788698
Short name T730
Test name
Test status
Simulation time 205763942 ps
CPU time 20.01 seconds
Started Feb 07 01:10:22 PM PST 24
Finished Feb 07 01:10:43 PM PST 24
Peak memory 254832 kb
Host smart-2863d47c-8302-4047-bec7-02098619b4a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27357
88698 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_intr_timeout.2735788698
Directory /workspace/22.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_lpg.696321467
Short name T332
Test name
Test status
Simulation time 152824225488 ps
CPU time 2325.15 seconds
Started Feb 07 01:10:32 PM PST 24
Finished Feb 07 01:49:18 PM PST 24
Peak memory 288312 kb
Host smart-79a25e73-bbd5-451a-8f47-f6a509fa208e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696321467 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg.696321467
Directory /workspace/22.alert_handler_lpg/latest

Test location /workspace/coverage/default/22.alert_handler_lpg_stub_clk.1334967624
Short name T456
Test name
Test status
Simulation time 373769741090 ps
CPU time 1224.92 seconds
Started Feb 07 01:10:24 PM PST 24
Finished Feb 07 01:30:50 PM PST 24
Peak memory 271876 kb
Host smart-89ab848c-ed97-4ee0-a38c-a460f4d7dd0d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334967624 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg_stub_clk.1334967624
Directory /workspace/22.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/22.alert_handler_ping_timeout.3809888357
Short name T319
Test name
Test status
Simulation time 28962308126 ps
CPU time 608.1 seconds
Started Feb 07 01:10:26 PM PST 24
Finished Feb 07 01:20:34 PM PST 24
Peak memory 247164 kb
Host smart-d0b7d099-55dd-445a-90fa-fdbc41b5dc51
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809888357 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_ping_timeout.3809888357
Directory /workspace/22.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_random_alerts.4041986813
Short name T531
Test name
Test status
Simulation time 1624319835 ps
CPU time 55.75 seconds
Started Feb 07 01:10:30 PM PST 24
Finished Feb 07 01:11:26 PM PST 24
Peak memory 248392 kb
Host smart-b0d56f18-c852-4d36-b67b-e4db3f0092f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40419
86813 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_alerts.4041986813
Directory /workspace/22.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/22.alert_handler_random_classes.1556288159
Short name T237
Test name
Test status
Simulation time 1664317971 ps
CPU time 50.63 seconds
Started Feb 07 01:10:22 PM PST 24
Finished Feb 07 01:11:13 PM PST 24
Peak memory 247856 kb
Host smart-94fddd3a-19af-4b92-a9da-0a43acb555c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15562
88159 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_classes.1556288159
Directory /workspace/22.alert_handler_random_classes/latest

Test location /workspace/coverage/default/22.alert_handler_sig_int_fail.3490648680
Short name T440
Test name
Test status
Simulation time 216160258 ps
CPU time 7.74 seconds
Started Feb 07 01:10:24 PM PST 24
Finished Feb 07 01:10:33 PM PST 24
Peak memory 240272 kb
Host smart-a518e362-3314-4826-83fb-e3d9d465e991
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34906
48680 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_sig_int_fail.3490648680
Directory /workspace/22.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/22.alert_handler_smoke.242807956
Short name T230
Test name
Test status
Simulation time 3113089495 ps
CPU time 49.76 seconds
Started Feb 07 01:10:25 PM PST 24
Finished Feb 07 01:11:15 PM PST 24
Peak memory 248496 kb
Host smart-4b70ee58-b6dc-42c2-97f7-56a479bfa673
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24280
7956 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_smoke.242807956
Directory /workspace/22.alert_handler_smoke/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all.1158872443
Short name T298
Test name
Test status
Simulation time 218559206594 ps
CPU time 3234.92 seconds
Started Feb 07 01:10:32 PM PST 24
Finished Feb 07 02:04:28 PM PST 24
Peak memory 288916 kb
Host smart-7b2ef221-dda8-48a3-bad9-84b4cb8b9048
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158872443 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_ha
ndler_stress_all.1158872443
Directory /workspace/22.alert_handler_stress_all/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all_with_rand_reset.3455872172
Short name T655
Test name
Test status
Simulation time 19705603817 ps
CPU time 1349.41 seconds
Started Feb 07 01:10:22 PM PST 24
Finished Feb 07 01:32:53 PM PST 24
Peak memory 283084 kb
Host smart-2e80745b-cd94-4afa-9436-1f258c89c3fc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455872172 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 22.alert_handler_stress_all_with_rand_reset.3455872172
Directory /workspace/22.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.alert_handler_entropy.3860026052
Short name T596
Test name
Test status
Simulation time 9533547120 ps
CPU time 1096.55 seconds
Started Feb 07 01:10:24 PM PST 24
Finished Feb 07 01:28:41 PM PST 24
Peak memory 289560 kb
Host smart-e67ea2a2-24d1-46b7-9d70-b2d55516a6d7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860026052 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_entropy.3860026052
Directory /workspace/23.alert_handler_entropy/latest

Test location /workspace/coverage/default/23.alert_handler_esc_alert_accum.953127107
Short name T21
Test name
Test status
Simulation time 15779953972 ps
CPU time 213.9 seconds
Started Feb 07 01:10:24 PM PST 24
Finished Feb 07 01:13:59 PM PST 24
Peak memory 255948 kb
Host smart-b2e1ec22-e140-46b9-a8b9-f6bccf85c245
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95312
7107 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_alert_accum.953127107
Directory /workspace/23.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/23.alert_handler_esc_intr_timeout.139750611
Short name T608
Test name
Test status
Simulation time 1170565174 ps
CPU time 21.75 seconds
Started Feb 07 01:10:22 PM PST 24
Finished Feb 07 01:10:44 PM PST 24
Peak memory 248020 kb
Host smart-7ff6cc9a-03e3-4a6a-bfb7-74b6d69ca69c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13975
0611 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_intr_timeout.139750611
Directory /workspace/23.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_lpg_stub_clk.3788528677
Short name T447
Test name
Test status
Simulation time 11110535025 ps
CPU time 1049.18 seconds
Started Feb 07 01:10:31 PM PST 24
Finished Feb 07 01:28:01 PM PST 24
Peak memory 288776 kb
Host smart-f09c2d88-7330-4f5f-995a-6bcf4794064a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788528677 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg_stub_clk.3788528677
Directory /workspace/23.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/23.alert_handler_ping_timeout.3333525501
Short name T601
Test name
Test status
Simulation time 35303661372 ps
CPU time 380.82 seconds
Started Feb 07 01:10:24 PM PST 24
Finished Feb 07 01:16:46 PM PST 24
Peak memory 247320 kb
Host smart-f59dec03-6cf1-42f4-84fd-72337977483a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333525501 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_ping_timeout.3333525501
Directory /workspace/23.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_random_alerts.2942780664
Short name T295
Test name
Test status
Simulation time 4092391616 ps
CPU time 69.05 seconds
Started Feb 07 01:10:24 PM PST 24
Finished Feb 07 01:11:33 PM PST 24
Peak memory 248556 kb
Host smart-acace361-1d83-4c3d-b59a-d5e5442837d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29427
80664 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_alerts.2942780664
Directory /workspace/23.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/23.alert_handler_random_classes.2067611753
Short name T445
Test name
Test status
Simulation time 626681311 ps
CPU time 40.3 seconds
Started Feb 07 01:10:32 PM PST 24
Finished Feb 07 01:11:13 PM PST 24
Peak memory 247128 kb
Host smart-38eeac8a-b9dd-4df6-8899-0b7ac2c9d2fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20676
11753 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_classes.2067611753
Directory /workspace/23.alert_handler_random_classes/latest

Test location /workspace/coverage/default/23.alert_handler_sig_int_fail.1119919974
Short name T435
Test name
Test status
Simulation time 76055987 ps
CPU time 3.34 seconds
Started Feb 07 01:10:23 PM PST 24
Finished Feb 07 01:10:27 PM PST 24
Peak memory 238344 kb
Host smart-726cd37a-caae-47cc-99a4-8cb94f7619b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11199
19974 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_sig_int_fail.1119919974
Directory /workspace/23.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/23.alert_handler_smoke.4180094532
Short name T607
Test name
Test status
Simulation time 60272842 ps
CPU time 4.41 seconds
Started Feb 07 01:10:24 PM PST 24
Finished Feb 07 01:10:29 PM PST 24
Peak memory 240232 kb
Host smart-c4284963-0763-4334-80cc-3782cc4de08e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41800
94532 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_smoke.4180094532
Directory /workspace/23.alert_handler_smoke/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all.3134666154
Short name T708
Test name
Test status
Simulation time 45132926267 ps
CPU time 2595.93 seconds
Started Feb 07 01:10:26 PM PST 24
Finished Feb 07 01:53:42 PM PST 24
Peak memory 300472 kb
Host smart-c461a950-c7d7-4ed1-897d-e35fccae98db
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134666154 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_ha
ndler_stress_all.3134666154
Directory /workspace/23.alert_handler_stress_all/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all_with_rand_reset.926502716
Short name T667
Test name
Test status
Simulation time 97471073112 ps
CPU time 5675.67 seconds
Started Feb 07 01:10:30 PM PST 24
Finished Feb 07 02:45:07 PM PST 24
Peak memory 338140 kb
Host smart-182af996-9aaa-448e-9422-686c3ebda1f7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926502716 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 23.alert_handler_stress_all_with_rand_reset.926502716
Directory /workspace/23.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.alert_handler_entropy.2715369138
Short name T700
Test name
Test status
Simulation time 18434089144 ps
CPU time 1521.83 seconds
Started Feb 07 01:10:23 PM PST 24
Finished Feb 07 01:35:45 PM PST 24
Peak memory 288596 kb
Host smart-5f544cb1-c439-4711-899e-4c19c34426fb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715369138 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_entropy.2715369138
Directory /workspace/24.alert_handler_entropy/latest

Test location /workspace/coverage/default/24.alert_handler_esc_alert_accum.3128261280
Short name T687
Test name
Test status
Simulation time 5331556157 ps
CPU time 113.62 seconds
Started Feb 07 01:10:32 PM PST 24
Finished Feb 07 01:12:26 PM PST 24
Peak memory 256784 kb
Host smart-a2d89060-ef50-4205-815c-2030998237b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31282
61280 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_alert_accum.3128261280
Directory /workspace/24.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/24.alert_handler_esc_intr_timeout.2953782295
Short name T662
Test name
Test status
Simulation time 2241967727 ps
CPU time 33.76 seconds
Started Feb 07 01:10:23 PM PST 24
Finished Feb 07 01:10:58 PM PST 24
Peak memory 254856 kb
Host smart-b92ad87d-8ec2-4ac5-90f8-389163e4579a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29537
82295 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_intr_timeout.2953782295
Directory /workspace/24.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_lpg.2152354058
Short name T489
Test name
Test status
Simulation time 107324362626 ps
CPU time 1567.1 seconds
Started Feb 07 01:10:24 PM PST 24
Finished Feb 07 01:36:32 PM PST 24
Peak memory 269356 kb
Host smart-d2933c6d-b64f-4fdd-8cd9-816c0b7aecd1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152354058 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg.2152354058
Directory /workspace/24.alert_handler_lpg/latest

Test location /workspace/coverage/default/24.alert_handler_lpg_stub_clk.1933991713
Short name T411
Test name
Test status
Simulation time 21216355119 ps
CPU time 956.77 seconds
Started Feb 07 01:10:29 PM PST 24
Finished Feb 07 01:26:27 PM PST 24
Peak memory 272112 kb
Host smart-c2c70956-9163-4b1d-8161-e1a21408814c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933991713 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg_stub_clk.1933991713
Directory /workspace/24.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/24.alert_handler_ping_timeout.39245112
Short name T326
Test name
Test status
Simulation time 35688306944 ps
CPU time 373.25 seconds
Started Feb 07 01:10:32 PM PST 24
Finished Feb 07 01:16:46 PM PST 24
Peak memory 247492 kb
Host smart-38a86b2a-b4e7-4450-913b-2c7423b44c19
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39245112 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_ping_timeout.39245112
Directory /workspace/24.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_random_alerts.4037547187
Short name T528
Test name
Test status
Simulation time 1890526977 ps
CPU time 41.33 seconds
Started Feb 07 01:10:25 PM PST 24
Finished Feb 07 01:11:07 PM PST 24
Peak memory 248448 kb
Host smart-5717a8c7-edd0-4cb0-a9f6-a87c007517bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40375
47187 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_alerts.4037547187
Directory /workspace/24.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/24.alert_handler_random_classes.720488598
Short name T474
Test name
Test status
Simulation time 919984664 ps
CPU time 53.39 seconds
Started Feb 07 01:10:24 PM PST 24
Finished Feb 07 01:11:18 PM PST 24
Peak memory 247928 kb
Host smart-ba6fdcb4-ec24-4eca-9733-8d38dbec254f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72048
8598 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_classes.720488598
Directory /workspace/24.alert_handler_random_classes/latest

Test location /workspace/coverage/default/24.alert_handler_sig_int_fail.2834542231
Short name T457
Test name
Test status
Simulation time 1785740363 ps
CPU time 64.52 seconds
Started Feb 07 01:10:31 PM PST 24
Finished Feb 07 01:11:36 PM PST 24
Peak memory 246980 kb
Host smart-f5e228fa-7bfb-45fb-b8b5-10a764e0d3f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28345
42231 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_sig_int_fail.2834542231
Directory /workspace/24.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/24.alert_handler_smoke.3505022208
Short name T523
Test name
Test status
Simulation time 1652811839 ps
CPU time 52.76 seconds
Started Feb 07 01:10:32 PM PST 24
Finished Feb 07 01:11:25 PM PST 24
Peak memory 248504 kb
Host smart-4bee8a45-6f37-4904-ada4-435f7157bdf5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35050
22208 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_smoke.3505022208
Directory /workspace/24.alert_handler_smoke/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all.3050939489
Short name T281
Test name
Test status
Simulation time 276423661126 ps
CPU time 3830.19 seconds
Started Feb 07 01:10:25 PM PST 24
Finished Feb 07 02:14:16 PM PST 24
Peak memory 304852 kb
Host smart-6da55618-afbc-4fa9-a310-ae6cb7a39b26
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050939489 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_ha
ndler_stress_all.3050939489
Directory /workspace/24.alert_handler_stress_all/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all_with_rand_reset.953115213
Short name T69
Test name
Test status
Simulation time 48335409941 ps
CPU time 3323.33 seconds
Started Feb 07 01:10:32 PM PST 24
Finished Feb 07 02:05:56 PM PST 24
Peak memory 304412 kb
Host smart-b0318ec1-368a-4d02-87df-610aa18a2fb3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953115213 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 24.alert_handler_stress_all_with_rand_reset.953115213
Directory /workspace/24.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.alert_handler_entropy.1154001605
Short name T688
Test name
Test status
Simulation time 9852205006 ps
CPU time 997.81 seconds
Started Feb 07 01:10:35 PM PST 24
Finished Feb 07 01:27:13 PM PST 24
Peak memory 289308 kb
Host smart-3c5a0ef0-883b-47f1-b032-f204abcb62c9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1154001605 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_entropy.1154001605
Directory /workspace/25.alert_handler_entropy/latest

Test location /workspace/coverage/default/25.alert_handler_esc_alert_accum.3522043894
Short name T638
Test name
Test status
Simulation time 1282055991 ps
CPU time 104.53 seconds
Started Feb 07 01:10:36 PM PST 24
Finished Feb 07 01:12:21 PM PST 24
Peak memory 255692 kb
Host smart-0aaad0aa-e50a-4580-b657-ea8079c30ac5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35220
43894 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_alert_accum.3522043894
Directory /workspace/25.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/25.alert_handler_esc_intr_timeout.2763317940
Short name T467
Test name
Test status
Simulation time 979833227 ps
CPU time 22.7 seconds
Started Feb 07 01:10:34 PM PST 24
Finished Feb 07 01:10:57 PM PST 24
Peak memory 248456 kb
Host smart-d852b7f1-4464-46e8-bfb6-9dd74bfd9b2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27633
17940 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_intr_timeout.2763317940
Directory /workspace/25.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_lpg.930841448
Short name T243
Test name
Test status
Simulation time 158002865400 ps
CPU time 1023.87 seconds
Started Feb 07 01:10:33 PM PST 24
Finished Feb 07 01:27:38 PM PST 24
Peak memory 264968 kb
Host smart-92642c6e-ca7b-41bc-8218-ef85d28408ae
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930841448 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg.930841448
Directory /workspace/25.alert_handler_lpg/latest

Test location /workspace/coverage/default/25.alert_handler_lpg_stub_clk.478762899
Short name T651
Test name
Test status
Simulation time 11114671231 ps
CPU time 1063.4 seconds
Started Feb 07 01:10:37 PM PST 24
Finished Feb 07 01:28:21 PM PST 24
Peak memory 282040 kb
Host smart-4d94a2e1-8d60-4cb7-8e66-8eca37356c8f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478762899 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg_stub_clk.478762899
Directory /workspace/25.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/25.alert_handler_ping_timeout.2691447646
Short name T236
Test name
Test status
Simulation time 18351148768 ps
CPU time 378.26 seconds
Started Feb 07 01:10:35 PM PST 24
Finished Feb 07 01:16:54 PM PST 24
Peak memory 247316 kb
Host smart-2ad62bf9-367d-4631-bb90-1355d0731d86
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2691447646 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_ping_timeout.2691447646
Directory /workspace/25.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_random_alerts.4190204623
Short name T567
Test name
Test status
Simulation time 3843197181 ps
CPU time 56.26 seconds
Started Feb 07 01:10:32 PM PST 24
Finished Feb 07 01:11:28 PM PST 24
Peak memory 248628 kb
Host smart-0e1c5723-9af1-42aa-8939-42eff6c0598b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41902
04623 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_alerts.4190204623
Directory /workspace/25.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/25.alert_handler_random_classes.375828691
Short name T76
Test name
Test status
Simulation time 3465475460 ps
CPU time 47.67 seconds
Started Feb 07 01:10:37 PM PST 24
Finished Feb 07 01:11:25 PM PST 24
Peak memory 247128 kb
Host smart-35d7222b-2657-4903-bb71-240103d81e64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37582
8691 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_classes.375828691
Directory /workspace/25.alert_handler_random_classes/latest

Test location /workspace/coverage/default/25.alert_handler_sig_int_fail.1824783654
Short name T660
Test name
Test status
Simulation time 4084974913 ps
CPU time 32.44 seconds
Started Feb 07 01:10:32 PM PST 24
Finished Feb 07 01:11:05 PM PST 24
Peak memory 246788 kb
Host smart-a361df3e-3401-43b4-ad78-8fd5894ab4a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18247
83654 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_sig_int_fail.1824783654
Directory /workspace/25.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/25.alert_handler_smoke.2779918763
Short name T361
Test name
Test status
Simulation time 4851417308 ps
CPU time 64.88 seconds
Started Feb 07 01:10:23 PM PST 24
Finished Feb 07 01:11:28 PM PST 24
Peak memory 248556 kb
Host smart-84c351f5-d84b-441e-9045-07fda7c2593d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27799
18763 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_smoke.2779918763
Directory /workspace/25.alert_handler_smoke/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all.293152715
Short name T659
Test name
Test status
Simulation time 14889123488 ps
CPU time 1268.96 seconds
Started Feb 07 01:10:35 PM PST 24
Finished Feb 07 01:31:45 PM PST 24
Peak memory 289512 kb
Host smart-2134d567-750a-4712-afb7-de1299f83121
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293152715 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_han
dler_stress_all.293152715
Directory /workspace/25.alert_handler_stress_all/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all_with_rand_reset.2266648025
Short name T109
Test name
Test status
Simulation time 588045045936 ps
CPU time 9330.02 seconds
Started Feb 07 01:10:35 PM PST 24
Finished Feb 07 03:46:06 PM PST 24
Peak memory 420720 kb
Host smart-68217433-fdf9-4bdf-8d0b-11910187cb9f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266648025 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 25.alert_handler_stress_all_with_rand_reset.2266648025
Directory /workspace/25.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.alert_handler_entropy.696133904
Short name T666
Test name
Test status
Simulation time 504602105713 ps
CPU time 1917.69 seconds
Started Feb 07 01:10:33 PM PST 24
Finished Feb 07 01:42:31 PM PST 24
Peak memory 288612 kb
Host smart-12ae9a91-647d-4792-8aa9-cb3aad2d8251
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696133904 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_entropy.696133904
Directory /workspace/26.alert_handler_entropy/latest

Test location /workspace/coverage/default/26.alert_handler_esc_alert_accum.448650878
Short name T484
Test name
Test status
Simulation time 1460881821 ps
CPU time 107.51 seconds
Started Feb 07 01:10:34 PM PST 24
Finished Feb 07 01:12:22 PM PST 24
Peak memory 255952 kb
Host smart-e12fb149-eec3-41f1-8218-9bc459366fd2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44865
0878 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_alert_accum.448650878
Directory /workspace/26.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/26.alert_handler_esc_intr_timeout.2914199252
Short name T80
Test name
Test status
Simulation time 20707041 ps
CPU time 3.18 seconds
Started Feb 07 01:10:37 PM PST 24
Finished Feb 07 01:10:41 PM PST 24
Peak memory 238520 kb
Host smart-7c5ab166-6857-4a5b-bc9e-8d3f6d442688
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29141
99252 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_intr_timeout.2914199252
Directory /workspace/26.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_lpg.1308104652
Short name T335
Test name
Test status
Simulation time 31792109041 ps
CPU time 1229.33 seconds
Started Feb 07 01:10:34 PM PST 24
Finished Feb 07 01:31:04 PM PST 24
Peak memory 273128 kb
Host smart-7790c7a8-8563-40d1-a42d-bb4e27b690ed
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308104652 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg.1308104652
Directory /workspace/26.alert_handler_lpg/latest

Test location /workspace/coverage/default/26.alert_handler_lpg_stub_clk.1297427257
Short name T120
Test name
Test status
Simulation time 7411297221 ps
CPU time 773.79 seconds
Started Feb 07 01:10:35 PM PST 24
Finished Feb 07 01:23:30 PM PST 24
Peak memory 269040 kb
Host smart-6921a36d-9ba0-4842-8400-e4195dbf5737
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1297427257 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg_stub_clk.1297427257
Directory /workspace/26.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/26.alert_handler_random_classes.2662459035
Short name T679
Test name
Test status
Simulation time 792777644 ps
CPU time 42.83 seconds
Started Feb 07 01:10:35 PM PST 24
Finished Feb 07 01:11:18 PM PST 24
Peak memory 255312 kb
Host smart-a1ce18a9-110a-449a-87f9-1e0dc0a7ff47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26624
59035 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_classes.2662459035
Directory /workspace/26.alert_handler_random_classes/latest

Test location /workspace/coverage/default/26.alert_handler_sig_int_fail.1695058802
Short name T276
Test name
Test status
Simulation time 410393043 ps
CPU time 26.6 seconds
Started Feb 07 01:10:37 PM PST 24
Finished Feb 07 01:11:04 PM PST 24
Peak memory 254924 kb
Host smart-2cfcb23c-79f1-4ca4-ad23-9e95e212e638
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16950
58802 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_sig_int_fail.1695058802
Directory /workspace/26.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/26.alert_handler_smoke.4008023547
Short name T647
Test name
Test status
Simulation time 42276498 ps
CPU time 5.37 seconds
Started Feb 07 01:10:35 PM PST 24
Finished Feb 07 01:10:41 PM PST 24
Peak memory 248436 kb
Host smart-3b7f9212-f6c9-408d-96eb-dd2eadf37ebe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40080
23547 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_smoke.4008023547
Directory /workspace/26.alert_handler_smoke/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all.2535088243
Short name T637
Test name
Test status
Simulation time 2547537346 ps
CPU time 35.06 seconds
Started Feb 07 01:10:35 PM PST 24
Finished Feb 07 01:11:11 PM PST 24
Peak memory 254628 kb
Host smart-d6405c05-79c1-499c-a3ec-d6395a75d956
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535088243 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_ha
ndler_stress_all.2535088243
Directory /workspace/26.alert_handler_stress_all/latest

Test location /workspace/coverage/default/27.alert_handler_entropy.2039755226
Short name T68
Test name
Test status
Simulation time 58471100277 ps
CPU time 1283.12 seconds
Started Feb 07 01:10:48 PM PST 24
Finished Feb 07 01:32:12 PM PST 24
Peak memory 289252 kb
Host smart-d5b1ab6c-b292-4e7b-99e1-b01abc5c4f86
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039755226 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_entropy.2039755226
Directory /workspace/27.alert_handler_entropy/latest

Test location /workspace/coverage/default/27.alert_handler_esc_alert_accum.1283040971
Short name T57
Test name
Test status
Simulation time 2390735941 ps
CPU time 67.51 seconds
Started Feb 07 01:10:47 PM PST 24
Finished Feb 07 01:11:55 PM PST 24
Peak memory 255800 kb
Host smart-74ca73da-c578-4b9c-9aed-6f9a0c33ec47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12830
40971 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_alert_accum.1283040971
Directory /workspace/27.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/27.alert_handler_esc_intr_timeout.3984840705
Short name T555
Test name
Test status
Simulation time 936255813 ps
CPU time 28.82 seconds
Started Feb 07 01:10:50 PM PST 24
Finished Feb 07 01:11:19 PM PST 24
Peak memory 254416 kb
Host smart-074d124e-d033-4c64-a889-d397b51aeea7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39848
40705 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_intr_timeout.3984840705
Directory /workspace/27.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_lpg.3424273826
Short name T338
Test name
Test status
Simulation time 132180782016 ps
CPU time 1813.76 seconds
Started Feb 07 01:10:47 PM PST 24
Finished Feb 07 01:41:02 PM PST 24
Peak memory 273076 kb
Host smart-167e9f78-240f-4b38-ab5e-fe9a77323ffb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424273826 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg.3424273826
Directory /workspace/27.alert_handler_lpg/latest

Test location /workspace/coverage/default/27.alert_handler_lpg_stub_clk.2713966936
Short name T587
Test name
Test status
Simulation time 59210843514 ps
CPU time 2797.11 seconds
Started Feb 07 01:10:47 PM PST 24
Finished Feb 07 01:57:25 PM PST 24
Peak memory 288940 kb
Host smart-37bc668c-ca99-4f90-af7c-7490d260a002
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713966936 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg_stub_clk.2713966936
Directory /workspace/27.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/27.alert_handler_ping_timeout.3823150452
Short name T241
Test name
Test status
Simulation time 7821545201 ps
CPU time 331.25 seconds
Started Feb 07 01:10:46 PM PST 24
Finished Feb 07 01:16:18 PM PST 24
Peak memory 247148 kb
Host smart-674bd423-1d2c-4ce5-a73a-633a9022cb27
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823150452 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_ping_timeout.3823150452
Directory /workspace/27.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_random_alerts.3242676292
Short name T569
Test name
Test status
Simulation time 564042003 ps
CPU time 25.02 seconds
Started Feb 07 01:10:35 PM PST 24
Finished Feb 07 01:11:01 PM PST 24
Peak memory 248424 kb
Host smart-734736df-ef27-43f3-b5fe-96763c11cabe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32426
76292 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_alerts.3242676292
Directory /workspace/27.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/27.alert_handler_random_classes.1701553459
Short name T90
Test name
Test status
Simulation time 785984865 ps
CPU time 45.76 seconds
Started Feb 07 01:10:50 PM PST 24
Finished Feb 07 01:11:36 PM PST 24
Peak memory 247008 kb
Host smart-17cb4716-cad4-4526-9afa-3faae458096f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17015
53459 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_classes.1701553459
Directory /workspace/27.alert_handler_random_classes/latest

Test location /workspace/coverage/default/27.alert_handler_sig_int_fail.337371901
Short name T452
Test name
Test status
Simulation time 1737430438 ps
CPU time 52.27 seconds
Started Feb 07 01:10:46 PM PST 24
Finished Feb 07 01:11:39 PM PST 24
Peak memory 254996 kb
Host smart-82e8f378-1361-411b-a670-4102a21ac62d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33737
1901 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_sig_int_fail.337371901
Directory /workspace/27.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/27.alert_handler_smoke.3959352644
Short name T704
Test name
Test status
Simulation time 2422994106 ps
CPU time 75.13 seconds
Started Feb 07 01:10:34 PM PST 24
Finished Feb 07 01:11:50 PM PST 24
Peak memory 248572 kb
Host smart-93bfb22c-4628-4c6c-a66e-96dd40f3da32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39593
52644 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_smoke.3959352644
Directory /workspace/27.alert_handler_smoke/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all.962246080
Short name T506
Test name
Test status
Simulation time 46676004881 ps
CPU time 700.95 seconds
Started Feb 07 01:10:50 PM PST 24
Finished Feb 07 01:22:32 PM PST 24
Peak memory 264956 kb
Host smart-64dc0d9b-b2e7-43d4-9f10-51cc49effe89
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962246080 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_han
dler_stress_all.962246080
Directory /workspace/27.alert_handler_stress_all/latest

Test location /workspace/coverage/default/28.alert_handler_entropy.3354826867
Short name T629
Test name
Test status
Simulation time 47978928511 ps
CPU time 1624.34 seconds
Started Feb 07 01:10:51 PM PST 24
Finished Feb 07 01:37:56 PM PST 24
Peak memory 270288 kb
Host smart-90fd355a-06d9-44ea-9eb5-138ca988c4db
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354826867 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_entropy.3354826867
Directory /workspace/28.alert_handler_entropy/latest

Test location /workspace/coverage/default/28.alert_handler_esc_alert_accum.2712553442
Short name T362
Test name
Test status
Simulation time 737659485 ps
CPU time 44.07 seconds
Started Feb 07 01:10:48 PM PST 24
Finished Feb 07 01:11:32 PM PST 24
Peak memory 254992 kb
Host smart-14718583-f525-400a-a248-ef605d2a2fd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27125
53442 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_alert_accum.2712553442
Directory /workspace/28.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/28.alert_handler_esc_intr_timeout.2186664706
Short name T664
Test name
Test status
Simulation time 6873591857 ps
CPU time 21.24 seconds
Started Feb 07 01:10:46 PM PST 24
Finished Feb 07 01:11:07 PM PST 24
Peak memory 255044 kb
Host smart-d4c8761f-9f44-48f6-b1ab-36c71080c0dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21866
64706 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_intr_timeout.2186664706
Directory /workspace/28.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_lpg.1748174668
Short name T682
Test name
Test status
Simulation time 99823500965 ps
CPU time 2698.76 seconds
Started Feb 07 01:10:47 PM PST 24
Finished Feb 07 01:55:47 PM PST 24
Peak memory 286952 kb
Host smart-f7bae93f-05ac-4b80-844d-1935b50cd8b1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748174668 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg.1748174668
Directory /workspace/28.alert_handler_lpg/latest

Test location /workspace/coverage/default/28.alert_handler_lpg_stub_clk.91638052
Short name T493
Test name
Test status
Simulation time 36680716396 ps
CPU time 1312.07 seconds
Started Feb 07 01:10:48 PM PST 24
Finished Feb 07 01:32:41 PM PST 24
Peak memory 272472 kb
Host smart-33842005-8657-4c1f-8202-f291e761dc87
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91638052 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg_stub_clk.91638052
Directory /workspace/28.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/28.alert_handler_ping_timeout.1203586741
Short name T307
Test name
Test status
Simulation time 46672360500 ps
CPU time 488.92 seconds
Started Feb 07 01:10:49 PM PST 24
Finished Feb 07 01:18:59 PM PST 24
Peak memory 247244 kb
Host smart-b6b132bd-34fa-4084-96d0-b6a209c7dc63
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203586741 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_ping_timeout.1203586741
Directory /workspace/28.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_random_alerts.3499671034
Short name T732
Test name
Test status
Simulation time 984117043 ps
CPU time 23.44 seconds
Started Feb 07 01:10:49 PM PST 24
Finished Feb 07 01:11:13 PM PST 24
Peak memory 248448 kb
Host smart-7aa44c00-f88b-47eb-a44b-572eb0f2ce63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34996
71034 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_alerts.3499671034
Directory /workspace/28.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/28.alert_handler_random_classes.277162955
Short name T130
Test name
Test status
Simulation time 49915152 ps
CPU time 6.04 seconds
Started Feb 07 01:10:49 PM PST 24
Finished Feb 07 01:10:56 PM PST 24
Peak memory 249084 kb
Host smart-547665fd-2c05-444c-8daa-e9bbf91a14e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27716
2955 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_classes.277162955
Directory /workspace/28.alert_handler_random_classes/latest

Test location /workspace/coverage/default/28.alert_handler_sig_int_fail.3880187204
Short name T101
Test name
Test status
Simulation time 1250766543 ps
CPU time 18.44 seconds
Started Feb 07 01:10:49 PM PST 24
Finished Feb 07 01:11:08 PM PST 24
Peak memory 246648 kb
Host smart-9f5c32f6-66ef-4da2-975d-8dc6526a8344
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38801
87204 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_sig_int_fail.3880187204
Directory /workspace/28.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/28.alert_handler_smoke.2371261851
Short name T78
Test name
Test status
Simulation time 359559041 ps
CPU time 25.04 seconds
Started Feb 07 01:10:47 PM PST 24
Finished Feb 07 01:11:13 PM PST 24
Peak memory 248424 kb
Host smart-8078c222-b56f-4950-a62f-6ab61bee3183
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23712
61851 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_smoke.2371261851
Directory /workspace/28.alert_handler_smoke/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all_with_rand_reset.1088648346
Short name T63
Test name
Test status
Simulation time 113461745481 ps
CPU time 3017.5 seconds
Started Feb 07 01:11:06 PM PST 24
Finished Feb 07 02:01:27 PM PST 24
Peak memory 348968 kb
Host smart-5a31722d-9b97-4230-b802-c584019f929f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088648346 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.alert_handler_stress_all_with_rand_reset.1088648346
Directory /workspace/28.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.alert_handler_entropy.2500410401
Short name T681
Test name
Test status
Simulation time 37907533554 ps
CPU time 2287.66 seconds
Started Feb 07 01:11:06 PM PST 24
Finished Feb 07 01:49:17 PM PST 24
Peak memory 287564 kb
Host smart-35cd410e-aef9-41bf-89d5-006ca1129d07
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2500410401 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_entropy.2500410401
Directory /workspace/29.alert_handler_entropy/latest

Test location /workspace/coverage/default/29.alert_handler_esc_alert_accum.1806185972
Short name T240
Test name
Test status
Simulation time 28969856764 ps
CPU time 252.25 seconds
Started Feb 07 01:11:06 PM PST 24
Finished Feb 07 01:15:21 PM PST 24
Peak memory 256256 kb
Host smart-86beeeff-b2a1-412d-96d5-4f02b165f4d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18061
85972 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_alert_accum.1806185972
Directory /workspace/29.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/29.alert_handler_esc_intr_timeout.3134880043
Short name T492
Test name
Test status
Simulation time 507593427 ps
CPU time 23.8 seconds
Started Feb 07 01:11:08 PM PST 24
Finished Feb 07 01:11:33 PM PST 24
Peak memory 254692 kb
Host smart-2bbd63bf-8e74-4b55-ad0e-4b1e2890aa32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31348
80043 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_intr_timeout.3134880043
Directory /workspace/29.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_lpg.1030618766
Short name T333
Test name
Test status
Simulation time 69581508044 ps
CPU time 1962.14 seconds
Started Feb 07 01:11:05 PM PST 24
Finished Feb 07 01:43:51 PM PST 24
Peak memory 272688 kb
Host smart-b8f10eda-2e03-4b5e-a61c-580271e3f1ce
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1030618766 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg.1030618766
Directory /workspace/29.alert_handler_lpg/latest

Test location /workspace/coverage/default/29.alert_handler_lpg_stub_clk.1660873116
Short name T427
Test name
Test status
Simulation time 114303065872 ps
CPU time 2012.61 seconds
Started Feb 07 01:11:11 PM PST 24
Finished Feb 07 01:44:45 PM PST 24
Peak memory 272092 kb
Host smart-93bc7ef3-e1a0-4e4b-8d2c-12079267907c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660873116 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg_stub_clk.1660873116
Directory /workspace/29.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/29.alert_handler_ping_timeout.782698786
Short name T311
Test name
Test status
Simulation time 5602076065 ps
CPU time 229.03 seconds
Started Feb 07 01:11:08 PM PST 24
Finished Feb 07 01:14:58 PM PST 24
Peak memory 247040 kb
Host smart-6da610b9-878d-4517-ab43-4c0d7dc296f6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782698786 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_ping_timeout.782698786
Directory /workspace/29.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_random_alerts.2324685362
Short name T589
Test name
Test status
Simulation time 2343630235 ps
CPU time 76.07 seconds
Started Feb 07 01:11:05 PM PST 24
Finished Feb 07 01:12:25 PM PST 24
Peak memory 255404 kb
Host smart-522f86a2-72d4-4aaa-a157-511b7f2638bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23246
85362 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_alerts.2324685362
Directory /workspace/29.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/29.alert_handler_random_classes.708323690
Short name T482
Test name
Test status
Simulation time 53873583 ps
CPU time 7.2 seconds
Started Feb 07 01:11:05 PM PST 24
Finished Feb 07 01:11:16 PM PST 24
Peak memory 251320 kb
Host smart-0dfcdf34-09fd-49f7-808d-dc9803c8053e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70832
3690 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_classes.708323690
Directory /workspace/29.alert_handler_random_classes/latest

Test location /workspace/coverage/default/29.alert_handler_sig_int_fail.2248924208
Short name T47
Test name
Test status
Simulation time 137808574 ps
CPU time 5.71 seconds
Started Feb 07 01:11:07 PM PST 24
Finished Feb 07 01:11:15 PM PST 24
Peak memory 246708 kb
Host smart-a5111299-3540-4aaa-bb8e-f55bc4b4236d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22489
24208 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_sig_int_fail.2248924208
Directory /workspace/29.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/29.alert_handler_smoke.1012407689
Short name T228
Test name
Test status
Simulation time 480325943 ps
CPU time 14.71 seconds
Started Feb 07 01:11:07 PM PST 24
Finished Feb 07 01:11:24 PM PST 24
Peak memory 248328 kb
Host smart-c509ebd4-c6b8-4e5f-a6c5-9786c926ed0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10124
07689 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_smoke.1012407689
Directory /workspace/29.alert_handler_smoke/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all_with_rand_reset.1562882696
Short name T734
Test name
Test status
Simulation time 55506830178 ps
CPU time 2135.7 seconds
Started Feb 07 01:11:12 PM PST 24
Finished Feb 07 01:46:49 PM PST 24
Peak memory 289372 kb
Host smart-6e54d166-c022-46e4-8ddd-dd4d8a35d74e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562882696 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.alert_handler_stress_all_with_rand_reset.1562882696
Directory /workspace/29.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.alert_handler_alert_accum_saturation.662081605
Short name T45
Test name
Test status
Simulation time 169428108 ps
CPU time 3.91 seconds
Started Feb 07 01:09:00 PM PST 24
Finished Feb 07 01:09:05 PM PST 24
Peak memory 248612 kb
Host smart-5caa1f9c-66c4-4e98-8950-e6d1f0664b68
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=662081605 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_alert_accum_saturation.662081605
Directory /workspace/3.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/3.alert_handler_entropy.28673779
Short name T392
Test name
Test status
Simulation time 39099965066 ps
CPU time 910.49 seconds
Started Feb 07 01:09:01 PM PST 24
Finished Feb 07 01:24:14 PM PST 24
Peak memory 285504 kb
Host smart-621c0ec5-b151-4341-af56-8d83ec4a5614
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28673779 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy.28673779
Directory /workspace/3.alert_handler_entropy/latest

Test location /workspace/coverage/default/3.alert_handler_entropy_stress.1944745414
Short name T579
Test name
Test status
Simulation time 360416000 ps
CPU time 11.08 seconds
Started Feb 07 01:08:59 PM PST 24
Finished Feb 07 01:09:11 PM PST 24
Peak memory 240224 kb
Host smart-a876b8a8-4982-4f8f-9778-a714f9b7183e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1944745414 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy_stress.1944745414
Directory /workspace/3.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/3.alert_handler_esc_alert_accum.1532822318
Short name T390
Test name
Test status
Simulation time 1810021968 ps
CPU time 91.83 seconds
Started Feb 07 01:08:59 PM PST 24
Finished Feb 07 01:10:32 PM PST 24
Peak memory 255892 kb
Host smart-ec84189c-01a1-435c-8018-feb7a0bf0d2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15328
22318 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_alert_accum.1532822318
Directory /workspace/3.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/3.alert_handler_esc_intr_timeout.3114511472
Short name T451
Test name
Test status
Simulation time 482872528 ps
CPU time 27.46 seconds
Started Feb 07 01:08:59 PM PST 24
Finished Feb 07 01:09:28 PM PST 24
Peak memory 254824 kb
Host smart-c7262eb3-c304-4d13-b684-fcb223d3194e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31145
11472 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_intr_timeout.3114511472
Directory /workspace/3.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_lpg.3365096964
Short name T329
Test name
Test status
Simulation time 74403390466 ps
CPU time 2136.28 seconds
Started Feb 07 01:09:00 PM PST 24
Finished Feb 07 01:44:37 PM PST 24
Peak memory 284888 kb
Host smart-7c58654b-bf0e-4a2a-86fc-acc0975339b9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365096964 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg.3365096964
Directory /workspace/3.alert_handler_lpg/latest

Test location /workspace/coverage/default/3.alert_handler_lpg_stub_clk.3682930951
Short name T51
Test name
Test status
Simulation time 13331113894 ps
CPU time 1086.66 seconds
Started Feb 07 01:08:57 PM PST 24
Finished Feb 07 01:27:04 PM PST 24
Peak memory 271264 kb
Host smart-13b8c989-162f-42de-b299-836037e4a2d3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682930951 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg_stub_clk.3682930951
Directory /workspace/3.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/3.alert_handler_random_alerts.821825353
Short name T735
Test name
Test status
Simulation time 1075550771 ps
CPU time 29.63 seconds
Started Feb 07 01:08:57 PM PST 24
Finished Feb 07 01:09:27 PM PST 24
Peak memory 248428 kb
Host smart-91541e63-d0ba-459d-82a1-e0c106c69b46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82182
5353 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_alerts.821825353
Directory /workspace/3.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/3.alert_handler_random_classes.103822525
Short name T540
Test name
Test status
Simulation time 2041757201 ps
CPU time 30.98 seconds
Started Feb 07 01:09:02 PM PST 24
Finished Feb 07 01:09:35 PM PST 24
Peak memory 254228 kb
Host smart-f2174263-25cf-4f62-96b3-3b2513120451
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10382
2525 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_classes.103822525
Directory /workspace/3.alert_handler_random_classes/latest

Test location /workspace/coverage/default/3.alert_handler_sig_int_fail.1436136393
Short name T473
Test name
Test status
Simulation time 655367222 ps
CPU time 24.56 seconds
Started Feb 07 01:08:58 PM PST 24
Finished Feb 07 01:09:24 PM PST 24
Peak memory 254652 kb
Host smart-eeecf305-a679-48c3-9865-6e4988110b5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14361
36393 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sig_int_fail.1436136393
Directory /workspace/3.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/3.alert_handler_smoke.3055560559
Short name T91
Test name
Test status
Simulation time 887593127 ps
CPU time 52.43 seconds
Started Feb 07 01:08:56 PM PST 24
Finished Feb 07 01:09:50 PM PST 24
Peak memory 256536 kb
Host smart-4f706032-3431-40ac-a16c-d20919efcbb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30555
60559 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_smoke.3055560559
Directory /workspace/3.alert_handler_smoke/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all.433052964
Short name T533
Test name
Test status
Simulation time 16651767851 ps
CPU time 240.98 seconds
Started Feb 07 01:09:00 PM PST 24
Finished Feb 07 01:13:01 PM PST 24
Peak memory 256780 kb
Host smart-589ecdf0-2c5f-435a-a253-28472ad75c2e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433052964 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_hand
ler_stress_all.433052964
Directory /workspace/3.alert_handler_stress_all/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all_with_rand_reset.1241479316
Short name T254
Test name
Test status
Simulation time 51015710206 ps
CPU time 4314.87 seconds
Started Feb 07 01:09:00 PM PST 24
Finished Feb 07 02:20:56 PM PST 24
Peak memory 338380 kb
Host smart-22318ab7-ba88-4183-be10-416f35d0a78f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241479316 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.alert_handler_stress_all_with_rand_reset.1241479316
Directory /workspace/3.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.alert_handler_entropy.3601319559
Short name T470
Test name
Test status
Simulation time 238949172020 ps
CPU time 2759.77 seconds
Started Feb 07 01:11:15 PM PST 24
Finished Feb 07 01:57:16 PM PST 24
Peak memory 284528 kb
Host smart-f3952e67-998d-4f38-b5a0-017e948d20c0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601319559 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_entropy.3601319559
Directory /workspace/30.alert_handler_entropy/latest

Test location /workspace/coverage/default/30.alert_handler_esc_alert_accum.1905107128
Short name T472
Test name
Test status
Simulation time 6043479380 ps
CPU time 85.63 seconds
Started Feb 07 01:11:12 PM PST 24
Finished Feb 07 01:12:38 PM PST 24
Peak memory 256604 kb
Host smart-ba8869d7-5006-45cb-9b6e-c4bc8d3189f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19051
07128 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_alert_accum.1905107128
Directory /workspace/30.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/30.alert_handler_esc_intr_timeout.1468439728
Short name T685
Test name
Test status
Simulation time 1666926255 ps
CPU time 54.26 seconds
Started Feb 07 01:11:12 PM PST 24
Finished Feb 07 01:12:07 PM PST 24
Peak memory 254752 kb
Host smart-464fa8a6-e2ae-40c0-ab4d-ad098c154d23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14684
39728 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_intr_timeout.1468439728
Directory /workspace/30.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_lpg.2794676513
Short name T727
Test name
Test status
Simulation time 41162642229 ps
CPU time 1567.9 seconds
Started Feb 07 01:11:18 PM PST 24
Finished Feb 07 01:37:27 PM PST 24
Peak memory 288604 kb
Host smart-a770b064-f3bc-45b9-ae78-0e5939fadd3a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794676513 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg.2794676513
Directory /workspace/30.alert_handler_lpg/latest

Test location /workspace/coverage/default/30.alert_handler_lpg_stub_clk.2146203010
Short name T466
Test name
Test status
Simulation time 12314321325 ps
CPU time 712.06 seconds
Started Feb 07 01:11:18 PM PST 24
Finished Feb 07 01:23:10 PM PST 24
Peak memory 273104 kb
Host smart-020fc492-ac5c-44a7-a263-17992a588e5d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146203010 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg_stub_clk.2146203010
Directory /workspace/30.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/30.alert_handler_ping_timeout.889075764
Short name T52
Test name
Test status
Simulation time 34499609264 ps
CPU time 289.39 seconds
Started Feb 07 01:11:07 PM PST 24
Finished Feb 07 01:15:58 PM PST 24
Peak memory 253784 kb
Host smart-0f510d43-c17d-4bed-9900-c2b4879db3c7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889075764 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_ping_timeout.889075764
Directory /workspace/30.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_random_alerts.2817789405
Short name T710
Test name
Test status
Simulation time 274918085 ps
CPU time 23.98 seconds
Started Feb 07 01:11:11 PM PST 24
Finished Feb 07 01:11:37 PM PST 24
Peak memory 255064 kb
Host smart-5f4f5801-28f5-492c-a093-691f33b62ed2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28177
89405 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_alerts.2817789405
Directory /workspace/30.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/30.alert_handler_random_classes.993661759
Short name T40
Test name
Test status
Simulation time 3353669828 ps
CPU time 23.43 seconds
Started Feb 07 01:11:12 PM PST 24
Finished Feb 07 01:11:36 PM PST 24
Peak memory 248616 kb
Host smart-b72366e2-fedf-4550-9d52-f3cb80da5e31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99366
1759 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_classes.993661759
Directory /workspace/30.alert_handler_random_classes/latest

Test location /workspace/coverage/default/30.alert_handler_sig_int_fail.4216761803
Short name T571
Test name
Test status
Simulation time 326195874 ps
CPU time 35.88 seconds
Started Feb 07 01:11:11 PM PST 24
Finished Feb 07 01:11:48 PM PST 24
Peak memory 246856 kb
Host smart-65e2f698-8190-49eb-a4af-e61d10954d4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42167
61803 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_sig_int_fail.4216761803
Directory /workspace/30.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/30.alert_handler_smoke.3525948914
Short name T251
Test name
Test status
Simulation time 418617872 ps
CPU time 27.26 seconds
Started Feb 07 01:11:15 PM PST 24
Finished Feb 07 01:11:42 PM PST 24
Peak memory 248448 kb
Host smart-e2bc82b5-5210-417f-8235-a4fab2195d1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35259
48914 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_smoke.3525948914
Directory /workspace/30.alert_handler_smoke/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all_with_rand_reset.3730231600
Short name T626
Test name
Test status
Simulation time 271981571165 ps
CPU time 3147.06 seconds
Started Feb 07 01:11:23 PM PST 24
Finished Feb 07 02:03:53 PM PST 24
Peak memory 287072 kb
Host smart-7a16b4ac-ce95-4280-9313-00a6c3c9cc6a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730231600 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.alert_handler_stress_all_with_rand_reset.3730231600
Directory /workspace/30.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.alert_handler_entropy.1209614939
Short name T670
Test name
Test status
Simulation time 47834175082 ps
CPU time 1006.91 seconds
Started Feb 07 01:11:21 PM PST 24
Finished Feb 07 01:28:09 PM PST 24
Peak memory 272636 kb
Host smart-a69e8f09-e594-4f33-9e14-7877f05f4a38
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209614939 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_entropy.1209614939
Directory /workspace/31.alert_handler_entropy/latest

Test location /workspace/coverage/default/31.alert_handler_esc_alert_accum.2295810957
Short name T406
Test name
Test status
Simulation time 3015520313 ps
CPU time 87.79 seconds
Started Feb 07 01:11:19 PM PST 24
Finished Feb 07 01:12:47 PM PST 24
Peak memory 256064 kb
Host smart-361f569e-ddf9-44a9-8f90-8e14ddfb55d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22958
10957 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_alert_accum.2295810957
Directory /workspace/31.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/31.alert_handler_esc_intr_timeout.2242267946
Short name T673
Test name
Test status
Simulation time 3036409629 ps
CPU time 18.88 seconds
Started Feb 07 01:11:19 PM PST 24
Finished Feb 07 01:11:38 PM PST 24
Peak memory 254136 kb
Host smart-6b25ec03-dfac-41d0-9f35-f020f006d178
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22422
67946 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_intr_timeout.2242267946
Directory /workspace/31.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_lpg.996014919
Short name T343
Test name
Test status
Simulation time 81126932821 ps
CPU time 2181.54 seconds
Started Feb 07 01:11:21 PM PST 24
Finished Feb 07 01:47:44 PM PST 24
Peak memory 272744 kb
Host smart-034f7f86-ab72-4b1a-9e02-74f42e958344
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996014919 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg.996014919
Directory /workspace/31.alert_handler_lpg/latest

Test location /workspace/coverage/default/31.alert_handler_lpg_stub_clk.1462415415
Short name T103
Test name
Test status
Simulation time 36307047241 ps
CPU time 1010.09 seconds
Started Feb 07 01:11:21 PM PST 24
Finished Feb 07 01:28:12 PM PST 24
Peak memory 283064 kb
Host smart-5df2a0dc-437a-45bc-a536-ffc02c5cf8e0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462415415 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg_stub_clk.1462415415
Directory /workspace/31.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/31.alert_handler_random_alerts.3249327525
Short name T487
Test name
Test status
Simulation time 68975485 ps
CPU time 5.49 seconds
Started Feb 07 01:11:20 PM PST 24
Finished Feb 07 01:11:26 PM PST 24
Peak memory 240196 kb
Host smart-9f8fd032-6ac6-4877-90a3-7e7385d3e29f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32493
27525 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_alerts.3249327525
Directory /workspace/31.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/31.alert_handler_random_classes.2323863577
Short name T701
Test name
Test status
Simulation time 400336691 ps
CPU time 12.2 seconds
Started Feb 07 01:11:22 PM PST 24
Finished Feb 07 01:11:35 PM PST 24
Peak memory 246744 kb
Host smart-0f26fb5a-32a5-43d4-87f5-1b0a4a3d56c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23238
63577 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_classes.2323863577
Directory /workspace/31.alert_handler_random_classes/latest

Test location /workspace/coverage/default/31.alert_handler_sig_int_fail.2608651623
Short name T486
Test name
Test status
Simulation time 2517774620 ps
CPU time 32.2 seconds
Started Feb 07 01:11:20 PM PST 24
Finished Feb 07 01:11:53 PM PST 24
Peak memory 255356 kb
Host smart-bbdaba64-6ae9-465b-8911-28be7013e2a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26086
51623 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_sig_int_fail.2608651623
Directory /workspace/31.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/31.alert_handler_smoke.2152687747
Short name T358
Test name
Test status
Simulation time 1632842529 ps
CPU time 38.45 seconds
Started Feb 07 01:11:20 PM PST 24
Finished Feb 07 01:11:59 PM PST 24
Peak memory 248440 kb
Host smart-ca495987-3b86-4e7f-ba46-d7bcac63fd95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21526
87747 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_smoke.2152687747
Directory /workspace/31.alert_handler_smoke/latest

Test location /workspace/coverage/default/32.alert_handler_entropy.3212415227
Short name T591
Test name
Test status
Simulation time 179153307876 ps
CPU time 1951.96 seconds
Started Feb 07 01:11:23 PM PST 24
Finished Feb 07 01:43:57 PM PST 24
Peak memory 282436 kb
Host smart-3613538a-b1e7-4dab-8783-b34288761575
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212415227 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_entropy.3212415227
Directory /workspace/32.alert_handler_entropy/latest

Test location /workspace/coverage/default/32.alert_handler_esc_alert_accum.3259670960
Short name T475
Test name
Test status
Simulation time 523242812 ps
CPU time 48.32 seconds
Started Feb 07 01:11:23 PM PST 24
Finished Feb 07 01:12:14 PM PST 24
Peak memory 255728 kb
Host smart-d185a53c-494a-4f63-80f2-d15cbe9f44dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32596
70960 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_alert_accum.3259670960
Directory /workspace/32.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/32.alert_handler_esc_intr_timeout.1640841582
Short name T566
Test name
Test status
Simulation time 201476296 ps
CPU time 15.64 seconds
Started Feb 07 01:11:21 PM PST 24
Finished Feb 07 01:11:37 PM PST 24
Peak memory 254896 kb
Host smart-051266a8-497c-4be8-8ec9-b6d12ab74c90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16408
41582 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_intr_timeout.1640841582
Directory /workspace/32.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_lpg.3702937835
Short name T300
Test name
Test status
Simulation time 18998801858 ps
CPU time 852.44 seconds
Started Feb 07 01:11:23 PM PST 24
Finished Feb 07 01:25:37 PM PST 24
Peak memory 273132 kb
Host smart-92119622-582d-406f-acf6-7514dc46d2de
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702937835 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg.3702937835
Directory /workspace/32.alert_handler_lpg/latest

Test location /workspace/coverage/default/32.alert_handler_lpg_stub_clk.2608094702
Short name T698
Test name
Test status
Simulation time 26842498574 ps
CPU time 728.38 seconds
Started Feb 07 01:11:43 PM PST 24
Finished Feb 07 01:23:52 PM PST 24
Peak memory 273128 kb
Host smart-48b89f1f-ffef-4371-a884-0fae3dee51c9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608094702 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg_stub_clk.2608094702
Directory /workspace/32.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/32.alert_handler_random_alerts.130009383
Short name T635
Test name
Test status
Simulation time 913021820 ps
CPU time 18.41 seconds
Started Feb 07 01:11:23 PM PST 24
Finished Feb 07 01:11:43 PM PST 24
Peak memory 248404 kb
Host smart-38c37e4b-2b8f-4cb0-8b7e-7e2b1df9fa89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13000
9383 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_alerts.130009383
Directory /workspace/32.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/32.alert_handler_random_classes.1519509540
Short name T116
Test name
Test status
Simulation time 329773846 ps
CPU time 21.6 seconds
Started Feb 07 01:11:21 PM PST 24
Finished Feb 07 01:11:43 PM PST 24
Peak memory 253556 kb
Host smart-6af906e7-df47-4a03-8d8a-006f770dc5b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15195
09540 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_classes.1519509540
Directory /workspace/32.alert_handler_random_classes/latest

Test location /workspace/coverage/default/32.alert_handler_sig_int_fail.2785155671
Short name T289
Test name
Test status
Simulation time 1116802739 ps
CPU time 28.77 seconds
Started Feb 07 01:11:24 PM PST 24
Finished Feb 07 01:11:54 PM PST 24
Peak memory 246596 kb
Host smart-91800808-bcc1-490b-9f7d-77831a78ac2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27851
55671 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_sig_int_fail.2785155671
Directory /workspace/32.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/32.alert_handler_smoke.1276759465
Short name T367
Test name
Test status
Simulation time 7559386151 ps
CPU time 48.91 seconds
Started Feb 07 01:11:21 PM PST 24
Finished Feb 07 01:12:11 PM PST 24
Peak memory 256720 kb
Host smart-272ad9b8-9592-45fe-ac3a-d5b2b3d6ee23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12767
59465 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_smoke.1276759465
Directory /workspace/32.alert_handler_smoke/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all.1008706841
Short name T532
Test name
Test status
Simulation time 85907221160 ps
CPU time 2986.19 seconds
Started Feb 07 01:11:40 PM PST 24
Finished Feb 07 02:01:27 PM PST 24
Peak memory 305440 kb
Host smart-5d87c3b1-16d3-4fcd-8546-4b5b798700bd
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008706841 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_ha
ndler_stress_all.1008706841
Directory /workspace/32.alert_handler_stress_all/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all_with_rand_reset.3793501571
Short name T98
Test name
Test status
Simulation time 64291524945 ps
CPU time 1722.02 seconds
Started Feb 07 01:11:38 PM PST 24
Finished Feb 07 01:40:21 PM PST 24
Peak memory 305844 kb
Host smart-ea1aff00-8511-40cf-93bb-88b84ca65e77
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793501571 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 32.alert_handler_stress_all_with_rand_reset.3793501571
Directory /workspace/32.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.alert_handler_entropy.4135378532
Short name T379
Test name
Test status
Simulation time 39408039338 ps
CPU time 1305.76 seconds
Started Feb 07 01:11:40 PM PST 24
Finished Feb 07 01:33:27 PM PST 24
Peak memory 272812 kb
Host smart-0128573f-12ae-447a-9abe-45f906a69e8a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135378532 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_entropy.4135378532
Directory /workspace/33.alert_handler_entropy/latest

Test location /workspace/coverage/default/33.alert_handler_esc_alert_accum.755806128
Short name T535
Test name
Test status
Simulation time 4970627093 ps
CPU time 194.15 seconds
Started Feb 07 01:11:39 PM PST 24
Finished Feb 07 01:14:54 PM PST 24
Peak memory 255808 kb
Host smart-432d8f24-4256-4998-9427-47995f5c8249
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75580
6128 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_alert_accum.755806128
Directory /workspace/33.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/33.alert_handler_esc_intr_timeout.2931045160
Short name T102
Test name
Test status
Simulation time 1226432806 ps
CPU time 16.93 seconds
Started Feb 07 01:11:40 PM PST 24
Finished Feb 07 01:11:57 PM PST 24
Peak memory 252872 kb
Host smart-743e716a-c44d-41df-9d90-7d30a30affd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29310
45160 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_intr_timeout.2931045160
Directory /workspace/33.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_lpg.2971856717
Short name T337
Test name
Test status
Simulation time 28202783663 ps
CPU time 1624.61 seconds
Started Feb 07 01:11:40 PM PST 24
Finished Feb 07 01:38:45 PM PST 24
Peak memory 273140 kb
Host smart-880c3e78-8abb-4d7e-b1ec-aaefeb284b1f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971856717 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg.2971856717
Directory /workspace/33.alert_handler_lpg/latest

Test location /workspace/coverage/default/33.alert_handler_lpg_stub_clk.983309476
Short name T645
Test name
Test status
Simulation time 47953094596 ps
CPU time 2646.67 seconds
Started Feb 07 01:11:42 PM PST 24
Finished Feb 07 01:55:49 PM PST 24
Peak memory 288572 kb
Host smart-9df5305e-79ba-445c-b64a-bfad8194da41
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983309476 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg_stub_clk.983309476
Directory /workspace/33.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/33.alert_handler_ping_timeout.3989745579
Short name T312
Test name
Test status
Simulation time 10831594179 ps
CPU time 445.99 seconds
Started Feb 07 01:11:42 PM PST 24
Finished Feb 07 01:19:09 PM PST 24
Peak memory 247352 kb
Host smart-6be90a30-1c0b-4567-838d-63be53ee75fc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989745579 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_ping_timeout.3989745579
Directory /workspace/33.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_random_alerts.2751454809
Short name T642
Test name
Test status
Simulation time 1725637710 ps
CPU time 56.29 seconds
Started Feb 07 01:11:38 PM PST 24
Finished Feb 07 01:12:35 PM PST 24
Peak memory 254432 kb
Host smart-13a06210-4e18-4bba-9295-038805d44057
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27514
54809 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_alerts.2751454809
Directory /workspace/33.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/33.alert_handler_random_classes.750609690
Short name T58
Test name
Test status
Simulation time 1468123095 ps
CPU time 36.87 seconds
Started Feb 07 01:11:38 PM PST 24
Finished Feb 07 01:12:16 PM PST 24
Peak memory 254832 kb
Host smart-e4f9ca87-1c09-4929-887e-eaca9931ce47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75060
9690 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_classes.750609690
Directory /workspace/33.alert_handler_random_classes/latest

Test location /workspace/coverage/default/33.alert_handler_sig_int_fail.3274756732
Short name T398
Test name
Test status
Simulation time 143310143 ps
CPU time 10.34 seconds
Started Feb 07 01:11:41 PM PST 24
Finished Feb 07 01:11:51 PM PST 24
Peak memory 251040 kb
Host smart-867ef635-4017-4211-9b22-6de385f182ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32747
56732 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_sig_int_fail.3274756732
Directory /workspace/33.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/33.alert_handler_smoke.3729964513
Short name T433
Test name
Test status
Simulation time 76997096 ps
CPU time 9.13 seconds
Started Feb 07 01:11:38 PM PST 24
Finished Feb 07 01:11:48 PM PST 24
Peak memory 248536 kb
Host smart-75fea4bd-cd53-40a5-8f5e-70e5e4a6a1d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37299
64513 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_smoke.3729964513
Directory /workspace/33.alert_handler_smoke/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all.985216822
Short name T561
Test name
Test status
Simulation time 3652076673 ps
CPU time 127.84 seconds
Started Feb 07 01:11:39 PM PST 24
Finished Feb 07 01:13:47 PM PST 24
Peak memory 256748 kb
Host smart-e94f29b6-045a-438e-8d05-6b0e382fc622
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985216822 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_han
dler_stress_all.985216822
Directory /workspace/33.alert_handler_stress_all/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all_with_rand_reset.3769019808
Short name T554
Test name
Test status
Simulation time 46510217678 ps
CPU time 2599.99 seconds
Started Feb 07 01:11:41 PM PST 24
Finished Feb 07 01:55:02 PM PST 24
Peak memory 289368 kb
Host smart-b5aa36a7-fd47-46da-8e79-4f7fe9ed7acf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769019808 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 33.alert_handler_stress_all_with_rand_reset.3769019808
Directory /workspace/33.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.alert_handler_entropy.2879525522
Short name T542
Test name
Test status
Simulation time 17094647867 ps
CPU time 627.57 seconds
Started Feb 07 01:11:39 PM PST 24
Finished Feb 07 01:22:07 PM PST 24
Peak memory 264504 kb
Host smart-f46697e3-eaf6-44f0-a4fe-581093eb7a37
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2879525522 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_entropy.2879525522
Directory /workspace/34.alert_handler_entropy/latest

Test location /workspace/coverage/default/34.alert_handler_esc_alert_accum.444355148
Short name T448
Test name
Test status
Simulation time 384773270 ps
CPU time 10.43 seconds
Started Feb 07 01:11:39 PM PST 24
Finished Feb 07 01:11:51 PM PST 24
Peak memory 253368 kb
Host smart-d0051099-922c-41ec-a2f4-e3292c2310e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44435
5148 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_alert_accum.444355148
Directory /workspace/34.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/34.alert_handler_esc_intr_timeout.463061402
Short name T525
Test name
Test status
Simulation time 1698395748 ps
CPU time 25.45 seconds
Started Feb 07 01:11:40 PM PST 24
Finished Feb 07 01:12:06 PM PST 24
Peak memory 254544 kb
Host smart-0959e828-05d5-4b04-8878-63b3e60425ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46306
1402 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_intr_timeout.463061402
Directory /workspace/34.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_lpg.851705472
Short name T618
Test name
Test status
Simulation time 89457711440 ps
CPU time 2592.09 seconds
Started Feb 07 01:12:00 PM PST 24
Finished Feb 07 01:55:13 PM PST 24
Peak memory 281284 kb
Host smart-c3d75e96-0073-46b5-a14c-b5bdf430021d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851705472 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg.851705472
Directory /workspace/34.alert_handler_lpg/latest

Test location /workspace/coverage/default/34.alert_handler_lpg_stub_clk.3766439947
Short name T341
Test name
Test status
Simulation time 22402630812 ps
CPU time 1399.36 seconds
Started Feb 07 01:12:04 PM PST 24
Finished Feb 07 01:35:24 PM PST 24
Peak memory 273140 kb
Host smart-45d1fa9d-4941-47ce-8dac-97b1f9641294
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766439947 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg_stub_clk.3766439947
Directory /workspace/34.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/34.alert_handler_ping_timeout.3088048261
Short name T715
Test name
Test status
Simulation time 10761148138 ps
CPU time 441.67 seconds
Started Feb 07 01:12:01 PM PST 24
Finished Feb 07 01:19:23 PM PST 24
Peak memory 247340 kb
Host smart-cb7e68f5-8c1e-48b0-8eb2-1a63bf9c823e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088048261 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_ping_timeout.3088048261
Directory /workspace/34.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_random_alerts.638477660
Short name T136
Test name
Test status
Simulation time 970598625 ps
CPU time 35.92 seconds
Started Feb 07 01:11:38 PM PST 24
Finished Feb 07 01:12:14 PM PST 24
Peak memory 248456 kb
Host smart-7f947d5f-4b1e-450c-8643-b1cad7d6db3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63847
7660 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_alerts.638477660
Directory /workspace/34.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/34.alert_handler_random_classes.4068695163
Short name T518
Test name
Test status
Simulation time 950212920 ps
CPU time 33.5 seconds
Started Feb 07 01:11:39 PM PST 24
Finished Feb 07 01:12:13 PM PST 24
Peak memory 248028 kb
Host smart-d9589e4b-88bb-4254-8672-ffda22d67b4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40686
95163 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_classes.4068695163
Directory /workspace/34.alert_handler_random_classes/latest

Test location /workspace/coverage/default/34.alert_handler_sig_int_fail.2209864323
Short name T134
Test name
Test status
Simulation time 1545082741 ps
CPU time 31.01 seconds
Started Feb 07 01:11:41 PM PST 24
Finished Feb 07 01:12:12 PM PST 24
Peak memory 246712 kb
Host smart-3ab6171e-c3ac-4bbc-a71a-d4add8c96399
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22098
64323 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_sig_int_fail.2209864323
Directory /workspace/34.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/34.alert_handler_smoke.2944108870
Short name T19
Test name
Test status
Simulation time 821956775 ps
CPU time 44.29 seconds
Started Feb 07 01:11:39 PM PST 24
Finished Feb 07 01:12:24 PM PST 24
Peak memory 248452 kb
Host smart-c6fce2d8-5b0c-4df3-8f22-9b3ea9106971
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29441
08870 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_smoke.2944108870
Directory /workspace/34.alert_handler_smoke/latest

Test location /workspace/coverage/default/35.alert_handler_entropy.28995708
Short name T604
Test name
Test status
Simulation time 13132907764 ps
CPU time 961.56 seconds
Started Feb 07 01:12:02 PM PST 24
Finished Feb 07 01:28:05 PM PST 24
Peak memory 282388 kb
Host smart-e4eb41bc-2849-45e3-b14d-f535dd0dbcd2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28995708 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_entropy.28995708
Directory /workspace/35.alert_handler_entropy/latest

Test location /workspace/coverage/default/35.alert_handler_esc_alert_accum.1390743856
Short name T375
Test name
Test status
Simulation time 3650253795 ps
CPU time 149.34 seconds
Started Feb 07 01:12:00 PM PST 24
Finished Feb 07 01:14:30 PM PST 24
Peak memory 250844 kb
Host smart-293f1a8e-1a58-43b3-bbc3-9ffb655f4670
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13907
43856 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_alert_accum.1390743856
Directory /workspace/35.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/35.alert_handler_esc_intr_timeout.507658432
Short name T686
Test name
Test status
Simulation time 460826084 ps
CPU time 31.78 seconds
Started Feb 07 01:12:02 PM PST 24
Finished Feb 07 01:12:34 PM PST 24
Peak memory 254424 kb
Host smart-2f56bc19-3a42-4421-a0b6-09224b4031a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50765
8432 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_intr_timeout.507658432
Directory /workspace/35.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_lpg.144481266
Short name T232
Test name
Test status
Simulation time 21086375112 ps
CPU time 1128.11 seconds
Started Feb 07 01:12:01 PM PST 24
Finished Feb 07 01:30:51 PM PST 24
Peak memory 264932 kb
Host smart-be65a92b-feb3-4ddb-9740-86fdf0311d17
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144481266 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg.144481266
Directory /workspace/35.alert_handler_lpg/latest

Test location /workspace/coverage/default/35.alert_handler_lpg_stub_clk.1600039241
Short name T644
Test name
Test status
Simulation time 26857001933 ps
CPU time 888.06 seconds
Started Feb 07 01:12:01 PM PST 24
Finished Feb 07 01:26:50 PM PST 24
Peak memory 272048 kb
Host smart-4211ccb7-e24e-4c8c-b490-fd8d964060a1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600039241 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg_stub_clk.1600039241
Directory /workspace/35.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/35.alert_handler_ping_timeout.1207074229
Short name T314
Test name
Test status
Simulation time 14698243805 ps
CPU time 282.52 seconds
Started Feb 07 01:12:04 PM PST 24
Finished Feb 07 01:16:47 PM PST 24
Peak memory 247364 kb
Host smart-fc927bc7-923e-444b-bed1-ced9d909798e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207074229 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_ping_timeout.1207074229
Directory /workspace/35.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_random_alerts.50457334
Short name T48
Test name
Test status
Simulation time 969816107 ps
CPU time 36.18 seconds
Started Feb 07 01:12:00 PM PST 24
Finished Feb 07 01:12:37 PM PST 24
Peak memory 248600 kb
Host smart-492dcdb8-3ec2-4602-94cd-a4eb34f13358
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50457
334 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_alerts.50457334
Directory /workspace/35.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/35.alert_handler_random_classes.945534891
Short name T614
Test name
Test status
Simulation time 270127409 ps
CPU time 29.58 seconds
Started Feb 07 01:12:00 PM PST 24
Finished Feb 07 01:12:31 PM PST 24
Peak memory 246564 kb
Host smart-c406b6b7-946f-4f3e-aae2-7068289af003
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94553
4891 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_classes.945534891
Directory /workspace/35.alert_handler_random_classes/latest

Test location /workspace/coverage/default/35.alert_handler_smoke.3798706784
Short name T639
Test name
Test status
Simulation time 124478302 ps
CPU time 7.75 seconds
Started Feb 07 01:11:59 PM PST 24
Finished Feb 07 01:12:07 PM PST 24
Peak memory 240336 kb
Host smart-d0d36824-78dc-4a03-8b35-ee46a4a8c16a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37987
06784 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_smoke.3798706784
Directory /workspace/35.alert_handler_smoke/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all_with_rand_reset.1323178064
Short name T702
Test name
Test status
Simulation time 48277434955 ps
CPU time 796.15 seconds
Started Feb 07 01:12:03 PM PST 24
Finished Feb 07 01:25:20 PM PST 24
Peak memory 269536 kb
Host smart-ec1f61e2-3d8b-4190-92be-cdb74f890b12
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323178064 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 35.alert_handler_stress_all_with_rand_reset.1323178064
Directory /workspace/35.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.alert_handler_entropy.2208000200
Short name T668
Test name
Test status
Simulation time 11827739735 ps
CPU time 1109.96 seconds
Started Feb 07 01:12:05 PM PST 24
Finished Feb 07 01:30:36 PM PST 24
Peak memory 272620 kb
Host smart-2c43de4b-c9aa-4fa6-a176-9522fd9a516e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208000200 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_entropy.2208000200
Directory /workspace/36.alert_handler_entropy/latest

Test location /workspace/coverage/default/36.alert_handler_esc_alert_accum.2075624838
Short name T697
Test name
Test status
Simulation time 3686730481 ps
CPU time 190.28 seconds
Started Feb 07 01:12:05 PM PST 24
Finished Feb 07 01:15:17 PM PST 24
Peak memory 256376 kb
Host smart-6b2bb2b8-e884-459e-86e5-fcde8bac196d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20756
24838 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_alert_accum.2075624838
Directory /workspace/36.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/36.alert_handler_esc_intr_timeout.693414492
Short name T695
Test name
Test status
Simulation time 459057263 ps
CPU time 28.15 seconds
Started Feb 07 01:12:06 PM PST 24
Finished Feb 07 01:12:34 PM PST 24
Peak memory 253444 kb
Host smart-aebefe23-cd7b-4453-9925-387de5135885
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69341
4492 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_intr_timeout.693414492
Directory /workspace/36.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_lpg.2174671517
Short name T331
Test name
Test status
Simulation time 176823778583 ps
CPU time 2522.83 seconds
Started Feb 07 01:12:06 PM PST 24
Finished Feb 07 01:54:10 PM PST 24
Peak memory 282088 kb
Host smart-3fac949e-7e5d-49d4-a626-c87706a2d450
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174671517 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg.2174671517
Directory /workspace/36.alert_handler_lpg/latest

Test location /workspace/coverage/default/36.alert_handler_lpg_stub_clk.2424560123
Short name T690
Test name
Test status
Simulation time 36353949906 ps
CPU time 1405.66 seconds
Started Feb 07 01:12:06 PM PST 24
Finished Feb 07 01:35:33 PM PST 24
Peak memory 288756 kb
Host smart-e4a43ce0-cc72-4d75-92a3-a96242fdedf4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424560123 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg_stub_clk.2424560123
Directory /workspace/36.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/36.alert_handler_ping_timeout.2021121547
Short name T527
Test name
Test status
Simulation time 2559152088 ps
CPU time 103.12 seconds
Started Feb 07 01:12:07 PM PST 24
Finished Feb 07 01:13:51 PM PST 24
Peak memory 247400 kb
Host smart-0f22585d-d28c-4c82-ab24-109c44cf56d0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021121547 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_ping_timeout.2021121547
Directory /workspace/36.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_random_alerts.921462961
Short name T453
Test name
Test status
Simulation time 478693196 ps
CPU time 37.01 seconds
Started Feb 07 01:12:05 PM PST 24
Finished Feb 07 01:12:43 PM PST 24
Peak memory 248368 kb
Host smart-aac1508f-1001-4fe0-b952-d2a6e7caedba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92146
2961 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_alerts.921462961
Directory /workspace/36.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/36.alert_handler_random_classes.3429170564
Short name T50
Test name
Test status
Simulation time 360068082 ps
CPU time 27.52 seconds
Started Feb 07 01:12:06 PM PST 24
Finished Feb 07 01:12:34 PM PST 24
Peak memory 255236 kb
Host smart-ad222cc0-0330-491f-ae1e-538fbbcf11bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34291
70564 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_classes.3429170564
Directory /workspace/36.alert_handler_random_classes/latest

Test location /workspace/coverage/default/36.alert_handler_sig_int_fail.274894553
Short name T543
Test name
Test status
Simulation time 878681978 ps
CPU time 35.14 seconds
Started Feb 07 01:12:03 PM PST 24
Finished Feb 07 01:12:39 PM PST 24
Peak memory 254692 kb
Host smart-4e58714e-6fd7-424f-be64-c80ab8bfa7bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27489
4553 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_sig_int_fail.274894553
Directory /workspace/36.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/36.alert_handler_smoke.1658676401
Short name T721
Test name
Test status
Simulation time 677685988 ps
CPU time 42.95 seconds
Started Feb 07 01:12:04 PM PST 24
Finished Feb 07 01:12:48 PM PST 24
Peak memory 256624 kb
Host smart-b106a020-8dd4-46c0-b2b3-6f3294202e97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16586
76401 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_smoke.1658676401
Directory /workspace/36.alert_handler_smoke/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all.1342740272
Short name T95
Test name
Test status
Simulation time 2577552911 ps
CPU time 25.92 seconds
Started Feb 07 01:12:05 PM PST 24
Finished Feb 07 01:12:32 PM PST 24
Peak memory 248512 kb
Host smart-9d0bb592-336f-45fd-94c1-d66aa40fd1dd
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342740272 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_ha
ndler_stress_all.1342740272
Directory /workspace/36.alert_handler_stress_all/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all_with_rand_reset.3452618728
Short name T277
Test name
Test status
Simulation time 71313556703 ps
CPU time 4515.02 seconds
Started Feb 07 01:12:04 PM PST 24
Finished Feb 07 02:27:20 PM PST 24
Peak memory 322152 kb
Host smart-6f17c131-c6a1-4fae-a86c-f76e65d9cbd8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452618728 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 36.alert_handler_stress_all_with_rand_reset.3452618728
Directory /workspace/36.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.alert_handler_entropy.1929042932
Short name T553
Test name
Test status
Simulation time 39528839847 ps
CPU time 1112.11 seconds
Started Feb 07 01:12:06 PM PST 24
Finished Feb 07 01:30:39 PM PST 24
Peak memory 289308 kb
Host smart-f425d0a5-76b0-4e0d-b39e-88f05b637d0b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929042932 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_entropy.1929042932
Directory /workspace/37.alert_handler_entropy/latest

Test location /workspace/coverage/default/37.alert_handler_esc_alert_accum.1616496218
Short name T59
Test name
Test status
Simulation time 2993799304 ps
CPU time 164.29 seconds
Started Feb 07 01:12:06 PM PST 24
Finished Feb 07 01:14:51 PM PST 24
Peak memory 256148 kb
Host smart-33e22f5e-c70d-418c-8488-046e4a59bfd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16164
96218 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_alert_accum.1616496218
Directory /workspace/37.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/37.alert_handler_esc_intr_timeout.2554583016
Short name T135
Test name
Test status
Simulation time 1023042822 ps
CPU time 25.39 seconds
Started Feb 07 01:12:03 PM PST 24
Finished Feb 07 01:12:29 PM PST 24
Peak memory 255308 kb
Host smart-4e08f8fe-0b08-4a84-abe4-a71dd414c167
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25545
83016 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_intr_timeout.2554583016
Directory /workspace/37.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_lpg.3247443251
Short name T330
Test name
Test status
Simulation time 26360008134 ps
CPU time 1428.41 seconds
Started Feb 07 01:12:04 PM PST 24
Finished Feb 07 01:35:54 PM PST 24
Peak memory 289084 kb
Host smart-006f1503-76b8-4e11-a779-12b4b8ebc673
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247443251 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg.3247443251
Directory /workspace/37.alert_handler_lpg/latest

Test location /workspace/coverage/default/37.alert_handler_lpg_stub_clk.2559981510
Short name T519
Test name
Test status
Simulation time 57931261829 ps
CPU time 620.43 seconds
Started Feb 07 01:12:07 PM PST 24
Finished Feb 07 01:22:28 PM PST 24
Peak memory 272612 kb
Host smart-bcfd4d31-1993-4f00-abd7-a4ea7fd2c096
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559981510 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg_stub_clk.2559981510
Directory /workspace/37.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/37.alert_handler_ping_timeout.2152592770
Short name T10
Test name
Test status
Simulation time 8304249904 ps
CPU time 359.82 seconds
Started Feb 07 01:12:08 PM PST 24
Finished Feb 07 01:18:08 PM PST 24
Peak memory 246548 kb
Host smart-6ce0d499-ad67-4464-baa4-f3422d7d6fda
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152592770 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_ping_timeout.2152592770
Directory /workspace/37.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_random_alerts.58016485
Short name T625
Test name
Test status
Simulation time 26689177 ps
CPU time 4.72 seconds
Started Feb 07 01:12:05 PM PST 24
Finished Feb 07 01:12:11 PM PST 24
Peak memory 248444 kb
Host smart-cd974775-c936-412e-afa8-c97ae43e5ab8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58016
485 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_alerts.58016485
Directory /workspace/37.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/37.alert_handler_random_classes.3348339930
Short name T49
Test name
Test status
Simulation time 1760971424 ps
CPU time 57.37 seconds
Started Feb 07 01:12:05 PM PST 24
Finished Feb 07 01:13:03 PM PST 24
Peak memory 254020 kb
Host smart-6fdee98d-b66a-4311-81b8-30bc03803c6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33483
39930 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_classes.3348339930
Directory /workspace/37.alert_handler_random_classes/latest

Test location /workspace/coverage/default/37.alert_handler_sig_int_fail.3570674524
Short name T35
Test name
Test status
Simulation time 1469983671 ps
CPU time 45.31 seconds
Started Feb 07 01:12:05 PM PST 24
Finished Feb 07 01:12:51 PM PST 24
Peak memory 254728 kb
Host smart-9a46adc2-c82c-4426-9409-8f70a185c2b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35706
74524 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_sig_int_fail.3570674524
Directory /workspace/37.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/37.alert_handler_smoke.1978790506
Short name T137
Test name
Test status
Simulation time 737231454 ps
CPU time 22.13 seconds
Started Feb 07 01:12:06 PM PST 24
Finished Feb 07 01:12:29 PM PST 24
Peak memory 256608 kb
Host smart-32999294-cd95-4f3d-a8c7-8d1c1911dfe2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19787
90506 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_smoke.1978790506
Directory /workspace/37.alert_handler_smoke/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all.1786533764
Short name T290
Test name
Test status
Simulation time 56635231335 ps
CPU time 1394.7 seconds
Started Feb 07 01:12:06 PM PST 24
Finished Feb 07 01:35:21 PM PST 24
Peak memory 289496 kb
Host smart-df4e720a-4144-4c2d-82f5-ce5094f0d187
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786533764 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_ha
ndler_stress_all.1786533764
Directory /workspace/37.alert_handler_stress_all/latest

Test location /workspace/coverage/default/38.alert_handler_entropy.2298600326
Short name T422
Test name
Test status
Simulation time 86835513651 ps
CPU time 2777.07 seconds
Started Feb 07 01:12:33 PM PST 24
Finished Feb 07 01:58:51 PM PST 24
Peak memory 289152 kb
Host smart-16840bd9-1cd0-4587-a6fc-c7d2b09be9ca
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298600326 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_entropy.2298600326
Directory /workspace/38.alert_handler_entropy/latest

Test location /workspace/coverage/default/38.alert_handler_esc_alert_accum.4274639857
Short name T539
Test name
Test status
Simulation time 1497411064 ps
CPU time 48.69 seconds
Started Feb 07 01:12:33 PM PST 24
Finished Feb 07 01:13:22 PM PST 24
Peak memory 247860 kb
Host smart-7189e7ef-ef42-4c1c-8a54-a19a13dddd08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42746
39857 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_alert_accum.4274639857
Directory /workspace/38.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/38.alert_handler_esc_intr_timeout.3429778563
Short name T46
Test name
Test status
Simulation time 226734892 ps
CPU time 5.47 seconds
Started Feb 07 01:12:06 PM PST 24
Finished Feb 07 01:12:12 PM PST 24
Peak memory 238324 kb
Host smart-2f7f2b4e-7f7a-4b01-98c4-f004181a5e84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34297
78563 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_intr_timeout.3429778563
Directory /workspace/38.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_lpg.2037727514
Short name T342
Test name
Test status
Simulation time 27130241827 ps
CPU time 1805.33 seconds
Started Feb 07 01:12:24 PM PST 24
Finished Feb 07 01:42:30 PM PST 24
Peak memory 273136 kb
Host smart-6583e7e7-657f-403c-aac9-48a92da48cc2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037727514 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg.2037727514
Directory /workspace/38.alert_handler_lpg/latest

Test location /workspace/coverage/default/38.alert_handler_lpg_stub_clk.4042900819
Short name T372
Test name
Test status
Simulation time 27831129498 ps
CPU time 1868.55 seconds
Started Feb 07 01:12:33 PM PST 24
Finished Feb 07 01:43:42 PM PST 24
Peak memory 272488 kb
Host smart-2c16ace1-1556-4d91-98a8-3ba6cfeb6bb6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042900819 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg_stub_clk.4042900819
Directory /workspace/38.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/38.alert_handler_ping_timeout.3586213993
Short name T296
Test name
Test status
Simulation time 8608672544 ps
CPU time 361.78 seconds
Started Feb 07 01:12:23 PM PST 24
Finished Feb 07 01:18:25 PM PST 24
Peak memory 246444 kb
Host smart-c4517d75-cbfb-4404-ba52-fd709f7b1796
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586213993 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_ping_timeout.3586213993
Directory /workspace/38.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_random_alerts.3234489735
Short name T394
Test name
Test status
Simulation time 457666441 ps
CPU time 19.62 seconds
Started Feb 07 01:12:07 PM PST 24
Finished Feb 07 01:12:27 PM PST 24
Peak memory 248404 kb
Host smart-59f58c54-8330-4ee7-8426-0402d93bd610
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32344
89735 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_alerts.3234489735
Directory /workspace/38.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/38.alert_handler_random_classes.4079566522
Short name T409
Test name
Test status
Simulation time 10449730584 ps
CPU time 44.37 seconds
Started Feb 07 01:12:05 PM PST 24
Finished Feb 07 01:12:50 PM PST 24
Peak memory 254180 kb
Host smart-8c6b2eec-1376-4c95-84c8-c82311e9bbfb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40795
66522 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_classes.4079566522
Directory /workspace/38.alert_handler_random_classes/latest

Test location /workspace/coverage/default/38.alert_handler_sig_int_fail.517856705
Short name T649
Test name
Test status
Simulation time 1845984786 ps
CPU time 19.32 seconds
Started Feb 07 01:12:31 PM PST 24
Finished Feb 07 01:12:51 PM PST 24
Peak memory 254628 kb
Host smart-bff26aa0-086b-4e39-b170-4c8164b50382
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51785
6705 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_sig_int_fail.517856705
Directory /workspace/38.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/38.alert_handler_smoke.3618358616
Short name T365
Test name
Test status
Simulation time 832370605 ps
CPU time 59.41 seconds
Started Feb 07 01:12:08 PM PST 24
Finished Feb 07 01:13:08 PM PST 24
Peak memory 247836 kb
Host smart-9d3ba00f-b2cb-4228-9d3c-309634fb592f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36183
58616 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_smoke.3618358616
Directory /workspace/38.alert_handler_smoke/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all.356698430
Short name T408
Test name
Test status
Simulation time 9446665368 ps
CPU time 149.62 seconds
Started Feb 07 01:12:37 PM PST 24
Finished Feb 07 01:15:07 PM PST 24
Peak memory 255968 kb
Host smart-f97d2214-3074-423e-b43b-649400cd1539
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356698430 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_han
dler_stress_all.356698430
Directory /workspace/38.alert_handler_stress_all/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all_with_rand_reset.1402187572
Short name T643
Test name
Test status
Simulation time 84559750951 ps
CPU time 2255.41 seconds
Started Feb 07 01:12:25 PM PST 24
Finished Feb 07 01:50:02 PM PST 24
Peak memory 315604 kb
Host smart-d3f07f92-6ff1-40df-9575-d42d673a832a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402187572 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.alert_handler_stress_all_with_rand_reset.1402187572
Directory /workspace/38.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.alert_handler_entropy.2391468329
Short name T41
Test name
Test status
Simulation time 43425748124 ps
CPU time 787.18 seconds
Started Feb 07 01:12:30 PM PST 24
Finished Feb 07 01:25:37 PM PST 24
Peak memory 273044 kb
Host smart-e45c061e-6499-48af-9b64-2867d3ecdd8d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2391468329 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_entropy.2391468329
Directory /workspace/39.alert_handler_entropy/latest

Test location /workspace/coverage/default/39.alert_handler_esc_alert_accum.1848299586
Short name T371
Test name
Test status
Simulation time 6033539214 ps
CPU time 76.13 seconds
Started Feb 07 01:12:25 PM PST 24
Finished Feb 07 01:13:42 PM PST 24
Peak memory 255972 kb
Host smart-0665fd02-b2cb-46f1-848b-10046954773f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18482
99586 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_alert_accum.1848299586
Directory /workspace/39.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/39.alert_handler_esc_intr_timeout.1670960309
Short name T96
Test name
Test status
Simulation time 1620500347 ps
CPU time 18.39 seconds
Started Feb 07 01:12:30 PM PST 24
Finished Feb 07 01:12:49 PM PST 24
Peak memory 254676 kb
Host smart-4d870142-9594-453f-85ca-922f1a552351
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16709
60309 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_intr_timeout.1670960309
Directory /workspace/39.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_lpg.2566613408
Short name T563
Test name
Test status
Simulation time 9617488427 ps
CPU time 842.64 seconds
Started Feb 07 01:12:24 PM PST 24
Finished Feb 07 01:26:27 PM PST 24
Peak memory 282108 kb
Host smart-3b3dee30-6c83-4627-a5c2-964973eeec69
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566613408 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg.2566613408
Directory /workspace/39.alert_handler_lpg/latest

Test location /workspace/coverage/default/39.alert_handler_lpg_stub_clk.1232762726
Short name T233
Test name
Test status
Simulation time 25041218296 ps
CPU time 1511.29 seconds
Started Feb 07 01:12:24 PM PST 24
Finished Feb 07 01:37:36 PM PST 24
Peak memory 272428 kb
Host smart-c8488db4-af47-4c9e-bd89-be7f6563f4c9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232762726 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg_stub_clk.1232762726
Directory /workspace/39.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/39.alert_handler_ping_timeout.112797831
Short name T714
Test name
Test status
Simulation time 5736819300 ps
CPU time 244.49 seconds
Started Feb 07 01:12:31 PM PST 24
Finished Feb 07 01:16:36 PM PST 24
Peak memory 246444 kb
Host smart-be3deff5-7c44-4be8-aee1-f93d0e924b48
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112797831 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_ping_timeout.112797831
Directory /workspace/39.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_random_alerts.2714844948
Short name T386
Test name
Test status
Simulation time 1782560949 ps
CPU time 31.39 seconds
Started Feb 07 01:12:30 PM PST 24
Finished Feb 07 01:13:02 PM PST 24
Peak memory 255236 kb
Host smart-4bc1c7d5-8d7c-4073-bc8c-0369d27dcb9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27148
44948 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_alerts.2714844948
Directory /workspace/39.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/39.alert_handler_random_classes.2574784275
Short name T598
Test name
Test status
Simulation time 4496734917 ps
CPU time 75.74 seconds
Started Feb 07 01:12:25 PM PST 24
Finished Feb 07 01:13:41 PM PST 24
Peak memory 256060 kb
Host smart-9709c89a-67dd-4d51-89b5-868ae090e325
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25747
84275 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_classes.2574784275
Directory /workspace/39.alert_handler_random_classes/latest

Test location /workspace/coverage/default/39.alert_handler_sig_int_fail.1580488646
Short name T89
Test name
Test status
Simulation time 278029029 ps
CPU time 29.92 seconds
Started Feb 07 01:12:26 PM PST 24
Finished Feb 07 01:12:56 PM PST 24
Peak memory 246552 kb
Host smart-3fb03e77-6526-405b-89b2-89b01da0a653
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15804
88646 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_sig_int_fail.1580488646
Directory /workspace/39.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/39.alert_handler_smoke.1761511459
Short name T481
Test name
Test status
Simulation time 946624877 ps
CPU time 28.8 seconds
Started Feb 07 01:12:23 PM PST 24
Finished Feb 07 01:12:52 PM PST 24
Peak memory 248440 kb
Host smart-1bc9eae5-3ed7-4786-b44b-a779a88e77e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17615
11459 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_smoke.1761511459
Directory /workspace/39.alert_handler_smoke/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all.1490056273
Short name T495
Test name
Test status
Simulation time 71419325374 ps
CPU time 3758.57 seconds
Started Feb 07 01:12:31 PM PST 24
Finished Feb 07 02:15:11 PM PST 24
Peak memory 297492 kb
Host smart-c3509e2b-4543-41ca-b3ca-bd781c494b0f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490056273 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_ha
ndler_stress_all.1490056273
Directory /workspace/39.alert_handler_stress_all/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all_with_rand_reset.954941901
Short name T491
Test name
Test status
Simulation time 29155061113 ps
CPU time 869.58 seconds
Started Feb 07 01:12:24 PM PST 24
Finished Feb 07 01:26:54 PM PST 24
Peak memory 272840 kb
Host smart-0a8394d3-4df3-46be-a772-2e1ffd530030
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954941901 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 39.alert_handler_stress_all_with_rand_reset.954941901
Directory /workspace/39.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.alert_handler_alert_accum_saturation.3870488723
Short name T218
Test name
Test status
Simulation time 92536324 ps
CPU time 3.8 seconds
Started Feb 07 01:08:59 PM PST 24
Finished Feb 07 01:09:03 PM PST 24
Peak memory 248692 kb
Host smart-ea9f5a1d-0329-442d-a92d-d00de6f05a35
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3870488723 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_alert_accum_saturation.3870488723
Directory /workspace/4.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/4.alert_handler_entropy.1649187191
Short name T5
Test name
Test status
Simulation time 23320400496 ps
CPU time 1303.31 seconds
Started Feb 07 01:08:59 PM PST 24
Finished Feb 07 01:30:44 PM PST 24
Peak memory 271268 kb
Host smart-845edabc-fb76-4b78-9d3f-7826e9b7bea6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1649187191 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy.1649187191
Directory /workspace/4.alert_handler_entropy/latest

Test location /workspace/coverage/default/4.alert_handler_entropy_stress.1875423598
Short name T669
Test name
Test status
Simulation time 484915200 ps
CPU time 22.44 seconds
Started Feb 07 01:08:59 PM PST 24
Finished Feb 07 01:09:23 PM PST 24
Peak memory 240216 kb
Host smart-6c47d75b-d453-4a61-8348-110c7a187d2c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1875423598 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy_stress.1875423598
Directory /workspace/4.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/4.alert_handler_esc_alert_accum.2964456072
Short name T570
Test name
Test status
Simulation time 13847513000 ps
CPU time 162.95 seconds
Started Feb 07 01:08:59 PM PST 24
Finished Feb 07 01:11:43 PM PST 24
Peak memory 250572 kb
Host smart-27d06260-bace-4c6d-987a-274081e81964
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29644
56072 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_alert_accum.2964456072
Directory /workspace/4.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/4.alert_handler_esc_intr_timeout.2113284870
Short name T671
Test name
Test status
Simulation time 131682704 ps
CPU time 12.5 seconds
Started Feb 07 01:08:59 PM PST 24
Finished Feb 07 01:09:12 PM PST 24
Peak memory 254924 kb
Host smart-278b2946-9fb4-446f-a88c-1b7e68dd2b3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21132
84870 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_intr_timeout.2113284870
Directory /workspace/4.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_lpg.3189872596
Short name T546
Test name
Test status
Simulation time 28138048036 ps
CPU time 584.56 seconds
Started Feb 07 01:09:07 PM PST 24
Finished Feb 07 01:18:53 PM PST 24
Peak memory 264936 kb
Host smart-b2e638ff-46df-4641-8003-fd007390cd65
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189872596 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg.3189872596
Directory /workspace/4.alert_handler_lpg/latest

Test location /workspace/coverage/default/4.alert_handler_lpg_stub_clk.4189882124
Short name T577
Test name
Test status
Simulation time 23282752522 ps
CPU time 1299.9 seconds
Started Feb 07 01:09:01 PM PST 24
Finished Feb 07 01:30:44 PM PST 24
Peak memory 264948 kb
Host smart-5cda92f2-db0c-4d7d-8b2a-a462b7122937
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189882124 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg_stub_clk.4189882124
Directory /workspace/4.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/4.alert_handler_ping_timeout.2849971427
Short name T611
Test name
Test status
Simulation time 11426037944 ps
CPU time 451.15 seconds
Started Feb 07 01:09:04 PM PST 24
Finished Feb 07 01:16:36 PM PST 24
Peak memory 247428 kb
Host smart-6375fd7a-6a5b-4e3a-b742-3ff62ca09743
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849971427 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_ping_timeout.2849971427
Directory /workspace/4.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_random_alerts.1293184642
Short name T691
Test name
Test status
Simulation time 787276929 ps
CPU time 14.07 seconds
Started Feb 07 01:09:00 PM PST 24
Finished Feb 07 01:09:15 PM PST 24
Peak memory 248388 kb
Host smart-9bd14ef2-15e9-48b1-96ab-a594edd4ad63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12931
84642 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_alerts.1293184642
Directory /workspace/4.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/4.alert_handler_random_classes.22161053
Short name T602
Test name
Test status
Simulation time 2210474657 ps
CPU time 34.94 seconds
Started Feb 07 01:08:59 PM PST 24
Finished Feb 07 01:09:35 PM PST 24
Peak memory 246884 kb
Host smart-73cbbe4c-7744-43f2-9133-0ec53b5053bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22161
053 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_classes.22161053
Directory /workspace/4.alert_handler_random_classes/latest

Test location /workspace/coverage/default/4.alert_handler_sec_cm.1979901291
Short name T12
Test name
Test status
Simulation time 1527860477 ps
CPU time 22.38 seconds
Started Feb 07 01:09:02 PM PST 24
Finished Feb 07 01:09:26 PM PST 24
Peak memory 268796 kb
Host smart-cd412c34-1c4b-4a26-8b46-ac542d12562a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1979901291 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sec_cm.1979901291
Directory /workspace/4.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/4.alert_handler_sig_int_fail.1913831455
Short name T693
Test name
Test status
Simulation time 144652279 ps
CPU time 9.19 seconds
Started Feb 07 01:09:00 PM PST 24
Finished Feb 07 01:09:12 PM PST 24
Peak memory 246648 kb
Host smart-db916f52-7437-49c4-ab32-8168a01ada79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19138
31455 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sig_int_fail.1913831455
Directory /workspace/4.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/4.alert_handler_smoke.4272781846
Short name T442
Test name
Test status
Simulation time 241571655 ps
CPU time 14.9 seconds
Started Feb 07 01:08:58 PM PST 24
Finished Feb 07 01:09:13 PM PST 24
Peak memory 248564 kb
Host smart-0b82edc8-2e36-456b-b560-83aa19d2970f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42727
81846 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_smoke.4272781846
Directory /workspace/4.alert_handler_smoke/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all.3180529375
Short name T402
Test name
Test status
Simulation time 8591612150 ps
CPU time 247.17 seconds
Started Feb 07 01:09:00 PM PST 24
Finished Feb 07 01:13:08 PM PST 24
Peak memory 256760 kb
Host smart-e7730bb0-2c15-44d8-9d6d-d06b1463f81d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180529375 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_han
dler_stress_all.3180529375
Directory /workspace/4.alert_handler_stress_all/latest

Test location /workspace/coverage/default/40.alert_handler_entropy.1952509869
Short name T415
Test name
Test status
Simulation time 32373763863 ps
CPU time 1385.14 seconds
Started Feb 07 01:12:41 PM PST 24
Finished Feb 07 01:35:47 PM PST 24
Peak memory 289360 kb
Host smart-ca81381a-6347-4d79-a591-a36b23ca599c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952509869 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_entropy.1952509869
Directory /workspace/40.alert_handler_entropy/latest

Test location /workspace/coverage/default/40.alert_handler_esc_alert_accum.2346591127
Short name T359
Test name
Test status
Simulation time 75313613 ps
CPU time 6.83 seconds
Started Feb 07 01:12:24 PM PST 24
Finished Feb 07 01:12:32 PM PST 24
Peak memory 250168 kb
Host smart-58aa915b-0899-4d59-b95c-7cc6b9243a69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23465
91127 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_alert_accum.2346591127
Directory /workspace/40.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/40.alert_handler_esc_intr_timeout.1162145542
Short name T34
Test name
Test status
Simulation time 1111430483 ps
CPU time 19.88 seconds
Started Feb 07 01:12:33 PM PST 24
Finished Feb 07 01:12:53 PM PST 24
Peak memory 253544 kb
Host smart-60883bfa-683b-4b56-b278-a67291ed4732
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11621
45542 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_intr_timeout.1162145542
Directory /workspace/40.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_lpg_stub_clk.1663646149
Short name T509
Test name
Test status
Simulation time 9937413031 ps
CPU time 938.98 seconds
Started Feb 07 01:12:46 PM PST 24
Finished Feb 07 01:28:26 PM PST 24
Peak memory 272100 kb
Host smart-dc3d3d6a-279d-4152-a9be-e3b69103f4b1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663646149 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg_stub_clk.1663646149
Directory /workspace/40.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/40.alert_handler_ping_timeout.1076800495
Short name T323
Test name
Test status
Simulation time 133949940592 ps
CPU time 534.02 seconds
Started Feb 07 01:12:40 PM PST 24
Finished Feb 07 01:21:35 PM PST 24
Peak memory 247404 kb
Host smart-68b442f7-9678-448b-953d-d09bfb38b6ac
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076800495 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_ping_timeout.1076800495
Directory /workspace/40.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_random_alerts.3874316735
Short name T488
Test name
Test status
Simulation time 604218606 ps
CPU time 38.16 seconds
Started Feb 07 01:12:34 PM PST 24
Finished Feb 07 01:13:13 PM PST 24
Peak memory 255280 kb
Host smart-c8700205-826f-4861-9227-e545a2710da4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38743
16735 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_alerts.3874316735
Directory /workspace/40.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/40.alert_handler_random_classes.3139252391
Short name T594
Test name
Test status
Simulation time 1886038738 ps
CPU time 61.07 seconds
Started Feb 07 01:12:31 PM PST 24
Finished Feb 07 01:13:33 PM PST 24
Peak memory 247876 kb
Host smart-69959264-daf8-42b5-b1cf-0a1f0744726a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31392
52391 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_classes.3139252391
Directory /workspace/40.alert_handler_random_classes/latest

Test location /workspace/coverage/default/40.alert_handler_sig_int_fail.3329697541
Short name T623
Test name
Test status
Simulation time 197134254 ps
CPU time 18.77 seconds
Started Feb 07 01:12:26 PM PST 24
Finished Feb 07 01:12:46 PM PST 24
Peak memory 254076 kb
Host smart-53ee846c-3414-418f-821f-c46d5bf5ac12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33296
97541 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_sig_int_fail.3329697541
Directory /workspace/40.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/40.alert_handler_smoke.2639067204
Short name T363
Test name
Test status
Simulation time 28225814 ps
CPU time 5.07 seconds
Started Feb 07 01:12:25 PM PST 24
Finished Feb 07 01:12:30 PM PST 24
Peak memory 248428 kb
Host smart-1f1f0537-c74d-451d-8670-af2fba0f8e07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26390
67204 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_smoke.2639067204
Directory /workspace/40.alert_handler_smoke/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all.2483959248
Short name T139
Test name
Test status
Simulation time 15122545540 ps
CPU time 1471.62 seconds
Started Feb 07 01:12:41 PM PST 24
Finished Feb 07 01:37:14 PM PST 24
Peak memory 288712 kb
Host smart-6e89e353-88ba-47ed-af0f-c1bb614cf7d3
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483959248 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_ha
ndler_stress_all.2483959248
Directory /workspace/40.alert_handler_stress_all/latest

Test location /workspace/coverage/default/41.alert_handler_entropy.4032480827
Short name T502
Test name
Test status
Simulation time 22128011692 ps
CPU time 1285.57 seconds
Started Feb 07 01:13:26 PM PST 24
Finished Feb 07 01:34:54 PM PST 24
Peak memory 272412 kb
Host smart-2dc41cae-8aa5-4237-8fd4-d240e6b01490
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032480827 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_entropy.4032480827
Directory /workspace/41.alert_handler_entropy/latest

Test location /workspace/coverage/default/41.alert_handler_esc_alert_accum.133863047
Short name T381
Test name
Test status
Simulation time 1120871381 ps
CPU time 68.32 seconds
Started Feb 07 01:13:28 PM PST 24
Finished Feb 07 01:14:40 PM PST 24
Peak memory 256000 kb
Host smart-def2b845-4376-48d4-9e5d-2ad025b1fda3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13386
3047 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_alert_accum.133863047
Directory /workspace/41.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/41.alert_handler_esc_intr_timeout.3199403839
Short name T86
Test name
Test status
Simulation time 386162341 ps
CPU time 38.12 seconds
Started Feb 07 01:12:38 PM PST 24
Finished Feb 07 01:13:17 PM PST 24
Peak memory 248004 kb
Host smart-fd9c2379-2d01-4af3-a695-9a8cd112a643
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31994
03839 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_intr_timeout.3199403839
Directory /workspace/41.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_lpg.2383599961
Short name T340
Test name
Test status
Simulation time 9896138881 ps
CPU time 855.31 seconds
Started Feb 07 01:13:29 PM PST 24
Finished Feb 07 01:27:49 PM PST 24
Peak memory 272620 kb
Host smart-f35cc5a4-fe54-4733-9c4b-787b50cf9cfe
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383599961 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg.2383599961
Directory /workspace/41.alert_handler_lpg/latest

Test location /workspace/coverage/default/41.alert_handler_lpg_stub_clk.674308623
Short name T550
Test name
Test status
Simulation time 30628599075 ps
CPU time 1350.9 seconds
Started Feb 07 01:13:25 PM PST 24
Finished Feb 07 01:36:00 PM PST 24
Peak memory 288928 kb
Host smart-246dfab3-4338-4991-ad4b-bffe39e8b4e7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674308623 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg_stub_clk.674308623
Directory /workspace/41.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/41.alert_handler_ping_timeout.2743390960
Short name T658
Test name
Test status
Simulation time 40061404137 ps
CPU time 175.24 seconds
Started Feb 07 01:13:22 PM PST 24
Finished Feb 07 01:16:23 PM PST 24
Peak memory 247044 kb
Host smart-5f09c073-ee69-4585-b2ac-233f51e3a3c8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743390960 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_ping_timeout.2743390960
Directory /workspace/41.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_random_alerts.4046123481
Short name T572
Test name
Test status
Simulation time 2769723371 ps
CPU time 23.61 seconds
Started Feb 07 01:12:43 PM PST 24
Finished Feb 07 01:13:07 PM PST 24
Peak memory 248564 kb
Host smart-3dd97b07-242b-412b-b17a-498888478ed3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40461
23481 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_alerts.4046123481
Directory /workspace/41.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/41.alert_handler_random_classes.3501003354
Short name T600
Test name
Test status
Simulation time 1023202312 ps
CPU time 59.59 seconds
Started Feb 07 01:12:39 PM PST 24
Finished Feb 07 01:13:39 PM PST 24
Peak memory 254704 kb
Host smart-c7bc70c4-f7be-44ff-935c-2fb3fe4671dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35010
03354 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_classes.3501003354
Directory /workspace/41.alert_handler_random_classes/latest

Test location /workspace/coverage/default/41.alert_handler_smoke.2168756870
Short name T574
Test name
Test status
Simulation time 428068945 ps
CPU time 11.96 seconds
Started Feb 07 01:12:42 PM PST 24
Finished Feb 07 01:12:54 PM PST 24
Peak memory 248428 kb
Host smart-10c6a536-4376-49e8-9bab-e2fc980119b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21687
56870 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_smoke.2168756870
Directory /workspace/41.alert_handler_smoke/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all.1219218307
Short name T545
Test name
Test status
Simulation time 194966825741 ps
CPU time 2356.96 seconds
Started Feb 07 01:13:29 PM PST 24
Finished Feb 07 01:52:51 PM PST 24
Peak memory 288116 kb
Host smart-c3d9ccaa-6120-4501-b2f6-35901b33d175
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219218307 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_ha
ndler_stress_all.1219218307
Directory /workspace/41.alert_handler_stress_all/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all_with_rand_reset.1353907573
Short name T62
Test name
Test status
Simulation time 74922295748 ps
CPU time 4674.64 seconds
Started Feb 07 01:13:26 PM PST 24
Finished Feb 07 02:31:24 PM PST 24
Peak memory 289576 kb
Host smart-d801aecf-467d-483a-82cd-690f51f127d3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353907573 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 41.alert_handler_stress_all_with_rand_reset.1353907573
Directory /workspace/41.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.alert_handler_entropy.3141440562
Short name T428
Test name
Test status
Simulation time 50088985565 ps
CPU time 1249.42 seconds
Started Feb 07 01:13:29 PM PST 24
Finished Feb 07 01:34:23 PM PST 24
Peak memory 283352 kb
Host smart-99761a0b-5793-4c59-a1c8-a530bf2eab39
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141440562 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_entropy.3141440562
Directory /workspace/42.alert_handler_entropy/latest

Test location /workspace/coverage/default/42.alert_handler_esc_alert_accum.4024448843
Short name T431
Test name
Test status
Simulation time 3908097056 ps
CPU time 248.57 seconds
Started Feb 07 01:13:29 PM PST 24
Finished Feb 07 01:17:42 PM PST 24
Peak memory 255888 kb
Host smart-2a09b5c6-525c-4310-8849-fac6da088ffe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40244
48843 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_alert_accum.4024448843
Directory /workspace/42.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/42.alert_handler_esc_intr_timeout.527636310
Short name T376
Test name
Test status
Simulation time 3057219003 ps
CPU time 58.89 seconds
Started Feb 07 01:13:23 PM PST 24
Finished Feb 07 01:14:27 PM PST 24
Peak memory 254396 kb
Host smart-ae8c58fb-1ab8-483a-9698-84b44128a0ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52763
6310 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_intr_timeout.527636310
Directory /workspace/42.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_lpg.3637152412
Short name T680
Test name
Test status
Simulation time 22418496192 ps
CPU time 1429.1 seconds
Started Feb 07 01:13:31 PM PST 24
Finished Feb 07 01:37:24 PM PST 24
Peak memory 272772 kb
Host smart-24119d08-9394-4bc7-b2bd-e66b930670a4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637152412 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg.3637152412
Directory /workspace/42.alert_handler_lpg/latest

Test location /workspace/coverage/default/42.alert_handler_lpg_stub_clk.214198742
Short name T524
Test name
Test status
Simulation time 115334262141 ps
CPU time 1143.21 seconds
Started Feb 07 01:13:31 PM PST 24
Finished Feb 07 01:32:38 PM PST 24
Peak memory 287888 kb
Host smart-9d15dcc4-bb67-4211-a55b-e723612e410f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214198742 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg_stub_clk.214198742
Directory /workspace/42.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/42.alert_handler_ping_timeout.2965374613
Short name T322
Test name
Test status
Simulation time 6706048458 ps
CPU time 289.01 seconds
Started Feb 07 01:13:31 PM PST 24
Finished Feb 07 01:18:23 PM PST 24
Peak memory 246560 kb
Host smart-0d1cc75f-5c8f-4808-9504-c8d8ba8d9962
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965374613 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_ping_timeout.2965374613
Directory /workspace/42.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_random_alerts.1557554526
Short name T609
Test name
Test status
Simulation time 685305649 ps
CPU time 23.01 seconds
Started Feb 07 01:13:29 PM PST 24
Finished Feb 07 01:13:57 PM PST 24
Peak memory 248448 kb
Host smart-530a0134-b926-45f6-a310-bb105ee9fbba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15575
54526 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_alerts.1557554526
Directory /workspace/42.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/42.alert_handler_random_classes.4196844464
Short name T421
Test name
Test status
Simulation time 120365017 ps
CPU time 8.82 seconds
Started Feb 07 01:13:23 PM PST 24
Finished Feb 07 01:13:37 PM PST 24
Peak memory 251420 kb
Host smart-7fc121fc-7de8-47db-bee4-a77a02ce9943
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41968
44464 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_classes.4196844464
Directory /workspace/42.alert_handler_random_classes/latest

Test location /workspace/coverage/default/42.alert_handler_sig_int_fail.347943470
Short name T722
Test name
Test status
Simulation time 106346052 ps
CPU time 12.53 seconds
Started Feb 07 01:13:23 PM PST 24
Finished Feb 07 01:13:41 PM PST 24
Peak memory 253984 kb
Host smart-d0ba2c1e-719e-4eb4-be81-a0aa1e7b7767
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34794
3470 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_sig_int_fail.347943470
Directory /workspace/42.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/42.alert_handler_smoke.931939796
Short name T603
Test name
Test status
Simulation time 918826332 ps
CPU time 58.08 seconds
Started Feb 07 01:13:31 PM PST 24
Finished Feb 07 01:14:32 PM PST 24
Peak memory 248500 kb
Host smart-5a4a4bd2-6d10-4afc-becb-93574b6de312
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93193
9796 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_smoke.931939796
Directory /workspace/42.alert_handler_smoke/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all.2645344315
Short name T396
Test name
Test status
Simulation time 83035872175 ps
CPU time 2527.51 seconds
Started Feb 07 01:13:30 PM PST 24
Finished Feb 07 01:55:42 PM PST 24
Peak memory 288692 kb
Host smart-0ca340ca-5b99-4779-89fd-eadb1c0f3248
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645344315 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_ha
ndler_stress_all.2645344315
Directory /workspace/42.alert_handler_stress_all/latest

Test location /workspace/coverage/default/43.alert_handler_entropy.3768571705
Short name T640
Test name
Test status
Simulation time 11778608024 ps
CPU time 1156.91 seconds
Started Feb 07 01:13:43 PM PST 24
Finished Feb 07 01:33:01 PM PST 24
Peak memory 284452 kb
Host smart-dfc3c304-c945-492f-90de-1e5344e8cec5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768571705 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_entropy.3768571705
Directory /workspace/43.alert_handler_entropy/latest

Test location /workspace/coverage/default/43.alert_handler_esc_alert_accum.1787983435
Short name T302
Test name
Test status
Simulation time 963814695 ps
CPU time 53.95 seconds
Started Feb 07 01:13:44 PM PST 24
Finished Feb 07 01:14:39 PM PST 24
Peak memory 255248 kb
Host smart-4659876e-b2f2-4a1f-83cb-4570898a1452
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17879
83435 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_alert_accum.1787983435
Directory /workspace/43.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/43.alert_handler_esc_intr_timeout.580837603
Short name T450
Test name
Test status
Simulation time 664442164 ps
CPU time 22.04 seconds
Started Feb 07 01:13:43 PM PST 24
Finished Feb 07 01:14:06 PM PST 24
Peak memory 254884 kb
Host smart-320dfa18-4b94-4e4d-be1e-019b55090b39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58083
7603 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_intr_timeout.580837603
Directory /workspace/43.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_lpg.2129694233
Short name T126
Test name
Test status
Simulation time 244990782701 ps
CPU time 2167.45 seconds
Started Feb 07 01:13:42 PM PST 24
Finished Feb 07 01:49:50 PM PST 24
Peak memory 285836 kb
Host smart-b36310af-15fb-4e38-b374-7d37e36a1f2b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129694233 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg.2129694233
Directory /workspace/43.alert_handler_lpg/latest

Test location /workspace/coverage/default/43.alert_handler_lpg_stub_clk.2493556697
Short name T404
Test name
Test status
Simulation time 17036993367 ps
CPU time 1177.46 seconds
Started Feb 07 01:13:43 PM PST 24
Finished Feb 07 01:33:22 PM PST 24
Peak memory 264912 kb
Host smart-105f80b7-402f-40f2-a998-ae9cfcc7d21e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493556697 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg_stub_clk.2493556697
Directory /workspace/43.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/43.alert_handler_ping_timeout.1681908246
Short name T325
Test name
Test status
Simulation time 7051653874 ps
CPU time 76.36 seconds
Started Feb 07 01:13:42 PM PST 24
Finished Feb 07 01:14:59 PM PST 24
Peak memory 247420 kb
Host smart-93ca5434-85a0-449e-a483-efc1ece696a2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1681908246 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_ping_timeout.1681908246
Directory /workspace/43.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_random_alerts.211829356
Short name T694
Test name
Test status
Simulation time 19236129 ps
CPU time 3.75 seconds
Started Feb 07 01:13:42 PM PST 24
Finished Feb 07 01:13:47 PM PST 24
Peak memory 240220 kb
Host smart-05c352c1-2386-40c0-bf0e-4af44d16bdc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21182
9356 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_alerts.211829356
Directory /workspace/43.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/43.alert_handler_sig_int_fail.859837152
Short name T512
Test name
Test status
Simulation time 83496555 ps
CPU time 3.95 seconds
Started Feb 07 01:13:44 PM PST 24
Finished Feb 07 01:13:48 PM PST 24
Peak memory 240220 kb
Host smart-74a1049f-00e1-44a5-910f-9e65d6397312
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85983
7152 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_sig_int_fail.859837152
Directory /workspace/43.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/43.alert_handler_smoke.2906822425
Short name T420
Test name
Test status
Simulation time 1539383642 ps
CPU time 24.57 seconds
Started Feb 07 01:13:28 PM PST 24
Finished Feb 07 01:13:56 PM PST 24
Peak memory 248380 kb
Host smart-b9f3b7cf-e7c6-4461-92ce-a87f0a642e2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29068
22425 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_smoke.2906822425
Directory /workspace/43.alert_handler_smoke/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all.2071486059
Short name T75
Test name
Test status
Simulation time 51734994503 ps
CPU time 2960.36 seconds
Started Feb 07 01:13:43 PM PST 24
Finished Feb 07 02:03:04 PM PST 24
Peak memory 288580 kb
Host smart-2d158a1b-40b1-40fd-aff2-1385129dd83a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071486059 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_ha
ndler_stress_all.2071486059
Directory /workspace/43.alert_handler_stress_all/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all_with_rand_reset.4288235173
Short name T256
Test name
Test status
Simulation time 136692407650 ps
CPU time 2705.75 seconds
Started Feb 07 01:13:44 PM PST 24
Finished Feb 07 01:58:50 PM PST 24
Peak memory 322276 kb
Host smart-8f5efb32-afa6-4292-9429-944869d07d52
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288235173 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 43.alert_handler_stress_all_with_rand_reset.4288235173
Directory /workspace/43.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.alert_handler_entropy.1050853494
Short name T624
Test name
Test status
Simulation time 78523218473 ps
CPU time 1395.74 seconds
Started Feb 07 01:13:43 PM PST 24
Finished Feb 07 01:37:00 PM PST 24
Peak memory 272688 kb
Host smart-c4de9beb-a6b4-4f19-bfb3-e8a513ce25e6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050853494 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_entropy.1050853494
Directory /workspace/44.alert_handler_entropy/latest

Test location /workspace/coverage/default/44.alert_handler_esc_alert_accum.1668941405
Short name T576
Test name
Test status
Simulation time 15180684673 ps
CPU time 144.19 seconds
Started Feb 07 01:13:45 PM PST 24
Finished Feb 07 01:16:09 PM PST 24
Peak memory 255880 kb
Host smart-da2b28f2-7d77-4624-b0db-9525e7a4881c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16689
41405 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_alert_accum.1668941405
Directory /workspace/44.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/44.alert_handler_esc_intr_timeout.1502223309
Short name T521
Test name
Test status
Simulation time 4276306258 ps
CPU time 39.86 seconds
Started Feb 07 01:13:42 PM PST 24
Finished Feb 07 01:14:22 PM PST 24
Peak memory 254440 kb
Host smart-d0e057f2-9b78-444b-a0f8-5215556df0ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15022
23309 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_intr_timeout.1502223309
Directory /workspace/44.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_lpg.903187211
Short name T336
Test name
Test status
Simulation time 60806870445 ps
CPU time 1281.22 seconds
Started Feb 07 01:13:42 PM PST 24
Finished Feb 07 01:35:04 PM PST 24
Peak memory 285980 kb
Host smart-6e2eb8b1-615a-4c78-a3f9-1e79e8c635af
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903187211 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg.903187211
Directory /workspace/44.alert_handler_lpg/latest

Test location /workspace/coverage/default/44.alert_handler_lpg_stub_clk.3542606508
Short name T663
Test name
Test status
Simulation time 11942729406 ps
CPU time 749.65 seconds
Started Feb 07 01:13:42 PM PST 24
Finished Feb 07 01:26:12 PM PST 24
Peak memory 272104 kb
Host smart-885fd589-2d5e-4c9b-94ea-203072d41841
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3542606508 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg_stub_clk.3542606508
Directory /workspace/44.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/44.alert_handler_ping_timeout.4209680309
Short name T676
Test name
Test status
Simulation time 10432259472 ps
CPU time 228.16 seconds
Started Feb 07 01:13:43 PM PST 24
Finished Feb 07 01:17:32 PM PST 24
Peak memory 248364 kb
Host smart-daa6fd6c-9fdd-4e85-b9f8-d0a5512c0757
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209680309 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_ping_timeout.4209680309
Directory /workspace/44.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_random_alerts.2910859810
Short name T661
Test name
Test status
Simulation time 371888146 ps
CPU time 10.01 seconds
Started Feb 07 01:13:44 PM PST 24
Finished Feb 07 01:13:55 PM PST 24
Peak memory 248412 kb
Host smart-bdff85dc-cd55-44ae-9675-5e646d37257b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29108
59810 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_alerts.2910859810
Directory /workspace/44.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/44.alert_handler_random_classes.2089515698
Short name T575
Test name
Test status
Simulation time 3105078797 ps
CPU time 53.72 seconds
Started Feb 07 01:13:43 PM PST 24
Finished Feb 07 01:14:38 PM PST 24
Peak memory 255012 kb
Host smart-e886b67e-73bd-46c5-9353-49134112cc10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20895
15698 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_classes.2089515698
Directory /workspace/44.alert_handler_random_classes/latest

Test location /workspace/coverage/default/44.alert_handler_sig_int_fail.748145656
Short name T111
Test name
Test status
Simulation time 288330290 ps
CPU time 18.43 seconds
Started Feb 07 01:13:44 PM PST 24
Finished Feb 07 01:14:03 PM PST 24
Peak memory 246672 kb
Host smart-013e3be6-04ee-4508-be4a-412f9aa87d5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74814
5656 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_sig_int_fail.748145656
Directory /workspace/44.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/44.alert_handler_smoke.4028659916
Short name T483
Test name
Test status
Simulation time 331797716 ps
CPU time 7.39 seconds
Started Feb 07 01:13:43 PM PST 24
Finished Feb 07 01:13:51 PM PST 24
Peak memory 240208 kb
Host smart-d47ca2ef-93d2-44a0-900e-329644d0aa7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40286
59916 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_smoke.4028659916
Directory /workspace/44.alert_handler_smoke/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all.3654322074
Short name T38
Test name
Test status
Simulation time 18094103189 ps
CPU time 1547.08 seconds
Started Feb 07 01:14:00 PM PST 24
Finished Feb 07 01:39:48 PM PST 24
Peak memory 298280 kb
Host smart-0a3a6a82-6339-4132-8d57-b503e5444aa9
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654322074 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_ha
ndler_stress_all.3654322074
Directory /workspace/44.alert_handler_stress_all/latest

Test location /workspace/coverage/default/45.alert_handler_entropy.1723852000
Short name T432
Test name
Test status
Simulation time 13512896406 ps
CPU time 1103.45 seconds
Started Feb 07 01:13:59 PM PST 24
Finished Feb 07 01:32:23 PM PST 24
Peak memory 281364 kb
Host smart-38cff661-0cea-477c-8bd9-13ef4fd41363
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1723852000 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_entropy.1723852000
Directory /workspace/45.alert_handler_entropy/latest

Test location /workspace/coverage/default/45.alert_handler_esc_alert_accum.1049489293
Short name T382
Test name
Test status
Simulation time 4078521910 ps
CPU time 95.33 seconds
Started Feb 07 01:13:59 PM PST 24
Finished Feb 07 01:15:35 PM PST 24
Peak memory 249524 kb
Host smart-6e9045c3-b741-46d5-b90d-387d31605fa6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10494
89293 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_alert_accum.1049489293
Directory /workspace/45.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/45.alert_handler_esc_intr_timeout.3245304720
Short name T534
Test name
Test status
Simulation time 711920293 ps
CPU time 42.87 seconds
Started Feb 07 01:14:03 PM PST 24
Finished Feb 07 01:14:46 PM PST 24
Peak memory 254744 kb
Host smart-b06cc19f-1bf6-4390-bb7d-121a7c2c6307
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32453
04720 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_intr_timeout.3245304720
Directory /workspace/45.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_lpg.83040060
Short name T346
Test name
Test status
Simulation time 82203423374 ps
CPU time 1312.74 seconds
Started Feb 07 01:14:01 PM PST 24
Finished Feb 07 01:35:55 PM PST 24
Peak memory 264916 kb
Host smart-8199fec6-7cd2-49fc-99d3-52569c91169b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83040060 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg.83040060
Directory /workspace/45.alert_handler_lpg/latest

Test location /workspace/coverage/default/45.alert_handler_lpg_stub_clk.3520860943
Short name T114
Test name
Test status
Simulation time 51951466403 ps
CPU time 1110.06 seconds
Started Feb 07 01:14:00 PM PST 24
Finished Feb 07 01:32:31 PM PST 24
Peak memory 272600 kb
Host smart-1c8d7cd4-8739-42c1-bcd5-7435bd9b3793
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3520860943 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg_stub_clk.3520860943
Directory /workspace/45.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/45.alert_handler_ping_timeout.2423380252
Short name T321
Test name
Test status
Simulation time 5133085193 ps
CPU time 111.77 seconds
Started Feb 07 01:13:59 PM PST 24
Finished Feb 07 01:15:52 PM PST 24
Peak memory 247408 kb
Host smart-158f8073-af70-4e33-90b8-da3632affa1f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423380252 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_ping_timeout.2423380252
Directory /workspace/45.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_random_classes.229795071
Short name T712
Test name
Test status
Simulation time 260655167 ps
CPU time 19.59 seconds
Started Feb 07 01:14:03 PM PST 24
Finished Feb 07 01:14:23 PM PST 24
Peak memory 255204 kb
Host smart-68adac4b-e0e2-40b1-9334-44fe480d48a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22979
5071 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_classes.229795071
Directory /workspace/45.alert_handler_random_classes/latest

Test location /workspace/coverage/default/45.alert_handler_sig_int_fail.3849500160
Short name T267
Test name
Test status
Simulation time 3097377697 ps
CPU time 57.26 seconds
Started Feb 07 01:13:59 PM PST 24
Finished Feb 07 01:14:57 PM PST 24
Peak memory 248676 kb
Host smart-cbda9e6d-ca4b-4c09-a2ed-cf81d255e9d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38495
00160 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_sig_int_fail.3849500160
Directory /workspace/45.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/45.alert_handler_smoke.2923152878
Short name T565
Test name
Test status
Simulation time 417964238 ps
CPU time 10.91 seconds
Started Feb 07 01:13:59 PM PST 24
Finished Feb 07 01:14:11 PM PST 24
Peak memory 248452 kb
Host smart-94c4cd4f-e255-4dfa-90b8-bb927e41baa4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29231
52878 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_smoke.2923152878
Directory /workspace/45.alert_handler_smoke/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all.954365273
Short name T269
Test name
Test status
Simulation time 95476700210 ps
CPU time 2953.29 seconds
Started Feb 07 01:14:03 PM PST 24
Finished Feb 07 02:03:17 PM PST 24
Peak memory 299448 kb
Host smart-158e449f-e731-42b3-a7a8-d7dd4f861ced
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954365273 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_han
dler_stress_all.954365273
Directory /workspace/45.alert_handler_stress_all/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all_with_rand_reset.2945907717
Short name T729
Test name
Test status
Simulation time 50467797003 ps
CPU time 2400.45 seconds
Started Feb 07 01:13:58 PM PST 24
Finished Feb 07 01:54:00 PM PST 24
Peak memory 305516 kb
Host smart-b1f1d793-863a-47f3-8b27-81769791d5fa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945907717 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 45.alert_handler_stress_all_with_rand_reset.2945907717
Directory /workspace/45.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.alert_handler_entropy.4278350621
Short name T15
Test name
Test status
Simulation time 113023961917 ps
CPU time 1603.31 seconds
Started Feb 07 01:14:03 PM PST 24
Finished Feb 07 01:40:47 PM PST 24
Peak memory 273124 kb
Host smart-0645e98d-9309-45c1-9b35-ddf8a5384c9a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278350621 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_entropy.4278350621
Directory /workspace/46.alert_handler_entropy/latest

Test location /workspace/coverage/default/46.alert_handler_esc_alert_accum.2031588165
Short name T501
Test name
Test status
Simulation time 22554381159 ps
CPU time 165.52 seconds
Started Feb 07 01:14:02 PM PST 24
Finished Feb 07 01:16:48 PM PST 24
Peak memory 255884 kb
Host smart-41594a94-1d8c-4c5a-a12a-a0cc53c1a8ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20315
88165 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_alert_accum.2031588165
Directory /workspace/46.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/46.alert_handler_esc_intr_timeout.2608236261
Short name T586
Test name
Test status
Simulation time 129364074 ps
CPU time 8.39 seconds
Started Feb 07 01:13:58 PM PST 24
Finished Feb 07 01:14:07 PM PST 24
Peak memory 250844 kb
Host smart-55d97593-4276-4d70-9e61-45ef3040a28d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26082
36261 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_intr_timeout.2608236261
Directory /workspace/46.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_lpg.2394371706
Short name T595
Test name
Test status
Simulation time 45937478845 ps
CPU time 692.05 seconds
Started Feb 07 01:14:03 PM PST 24
Finished Feb 07 01:25:36 PM PST 24
Peak memory 273084 kb
Host smart-c26d8a13-8b28-4c37-97e4-188cf5494192
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394371706 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg.2394371706
Directory /workspace/46.alert_handler_lpg/latest

Test location /workspace/coverage/default/46.alert_handler_lpg_stub_clk.2837541570
Short name T6
Test name
Test status
Simulation time 214934435450 ps
CPU time 3028.88 seconds
Started Feb 07 01:13:58 PM PST 24
Finished Feb 07 02:04:28 PM PST 24
Peak memory 289004 kb
Host smart-dbd7de09-9809-4106-8161-f864b68d4fc2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837541570 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg_stub_clk.2837541570
Directory /workspace/46.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/46.alert_handler_ping_timeout.1592532506
Short name T327
Test name
Test status
Simulation time 22449452241 ps
CPU time 468.4 seconds
Started Feb 07 01:14:00 PM PST 24
Finished Feb 07 01:21:49 PM PST 24
Peak memory 247332 kb
Host smart-e0db85ec-591e-4f10-96a5-5fec049fbc78
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592532506 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_ping_timeout.1592532506
Directory /workspace/46.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_random_alerts.2878029090
Short name T436
Test name
Test status
Simulation time 16479058726 ps
CPU time 60.4 seconds
Started Feb 07 01:14:02 PM PST 24
Finished Feb 07 01:15:03 PM PST 24
Peak memory 248504 kb
Host smart-8667253b-11e2-475a-abeb-112373ac8ac8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28780
29090 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_alerts.2878029090
Directory /workspace/46.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/46.alert_handler_random_classes.4161121381
Short name T388
Test name
Test status
Simulation time 2024709724 ps
CPU time 29.73 seconds
Started Feb 07 01:13:59 PM PST 24
Finished Feb 07 01:14:30 PM PST 24
Peak memory 247060 kb
Host smart-851e4378-af99-42f6-a7df-d0072b81e2a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41611
21381 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_classes.4161121381
Directory /workspace/46.alert_handler_random_classes/latest

Test location /workspace/coverage/default/46.alert_handler_sig_int_fail.27271685
Short name T107
Test name
Test status
Simulation time 586881010 ps
CPU time 39.69 seconds
Started Feb 07 01:14:02 PM PST 24
Finished Feb 07 01:14:42 PM PST 24
Peak memory 255088 kb
Host smart-ef442727-6677-420d-bb91-e8234c0d1fdf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27271
685 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_sig_int_fail.27271685
Directory /workspace/46.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/46.alert_handler_smoke.1626248197
Short name T55
Test name
Test status
Simulation time 540146004 ps
CPU time 33.63 seconds
Started Feb 07 01:14:01 PM PST 24
Finished Feb 07 01:14:36 PM PST 24
Peak memory 248328 kb
Host smart-71292878-e547-4383-b6be-7462892fb684
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16262
48197 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_smoke.1626248197
Directory /workspace/46.alert_handler_smoke/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all.2441829470
Short name T559
Test name
Test status
Simulation time 6882970916 ps
CPU time 154.92 seconds
Started Feb 07 01:13:58 PM PST 24
Finished Feb 07 01:16:34 PM PST 24
Peak memory 256756 kb
Host smart-b02430c8-6988-4ffb-82b0-7d9ee20d5a8c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441829470 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_ha
ndler_stress_all.2441829470
Directory /workspace/46.alert_handler_stress_all/latest

Test location /workspace/coverage/default/47.alert_handler_entropy.2375980770
Short name T617
Test name
Test status
Simulation time 188127542825 ps
CPU time 1517 seconds
Started Feb 07 01:14:14 PM PST 24
Finished Feb 07 01:39:32 PM PST 24
Peak memory 272572 kb
Host smart-b710552d-d54b-41da-b532-1e721b5b416e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375980770 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_entropy.2375980770
Directory /workspace/47.alert_handler_entropy/latest

Test location /workspace/coverage/default/47.alert_handler_esc_alert_accum.3587357461
Short name T464
Test name
Test status
Simulation time 979311189 ps
CPU time 100.95 seconds
Started Feb 07 01:14:16 PM PST 24
Finished Feb 07 01:15:58 PM PST 24
Peak memory 250580 kb
Host smart-435f2499-4f6d-42ce-b5f9-16d9671416b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35873
57461 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_alert_accum.3587357461
Directory /workspace/47.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/47.alert_handler_esc_intr_timeout.2378918953
Short name T275
Test name
Test status
Simulation time 5020966269 ps
CPU time 30.02 seconds
Started Feb 07 01:14:13 PM PST 24
Finished Feb 07 01:14:44 PM PST 24
Peak memory 246920 kb
Host smart-bdf5070d-4e1e-4c24-9f78-9fc9e9912701
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23789
18953 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_intr_timeout.2378918953
Directory /workspace/47.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_lpg.365716549
Short name T82
Test name
Test status
Simulation time 17148620554 ps
CPU time 1400.35 seconds
Started Feb 07 01:14:14 PM PST 24
Finished Feb 07 01:37:35 PM PST 24
Peak memory 286060 kb
Host smart-f194fa70-296b-46f5-85c4-07ed746ea01e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365716549 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg.365716549
Directory /workspace/47.alert_handler_lpg/latest

Test location /workspace/coverage/default/47.alert_handler_lpg_stub_clk.1247635116
Short name T547
Test name
Test status
Simulation time 35437333958 ps
CPU time 1894.18 seconds
Started Feb 07 01:14:22 PM PST 24
Finished Feb 07 01:45:57 PM PST 24
Peak memory 281512 kb
Host smart-6621d2fe-33f0-49a7-bae5-9de910645179
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1247635116 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg_stub_clk.1247635116
Directory /workspace/47.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/47.alert_handler_ping_timeout.2411304619
Short name T706
Test name
Test status
Simulation time 2630052237 ps
CPU time 111.35 seconds
Started Feb 07 01:14:18 PM PST 24
Finished Feb 07 01:16:10 PM PST 24
Peak memory 247088 kb
Host smart-f899f2ae-fab2-46c6-86c5-1a7efe088d69
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411304619 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_ping_timeout.2411304619
Directory /workspace/47.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_random_alerts.2792540314
Short name T558
Test name
Test status
Simulation time 495789305 ps
CPU time 7.19 seconds
Started Feb 07 01:14:18 PM PST 24
Finished Feb 07 01:14:26 PM PST 24
Peak memory 240320 kb
Host smart-2fec5d94-8d3d-4f62-b731-c067868d4316
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27925
40314 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_alerts.2792540314
Directory /workspace/47.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/47.alert_handler_random_classes.2440833929
Short name T656
Test name
Test status
Simulation time 913239370 ps
CPU time 15.52 seconds
Started Feb 07 01:14:17 PM PST 24
Finished Feb 07 01:14:34 PM PST 24
Peak memory 254068 kb
Host smart-ff94832b-c3a2-456e-8c2c-9dc431a8fce2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24408
33929 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_classes.2440833929
Directory /workspace/47.alert_handler_random_classes/latest

Test location /workspace/coverage/default/47.alert_handler_sig_int_fail.2179104552
Short name T268
Test name
Test status
Simulation time 32885881 ps
CPU time 4.8 seconds
Started Feb 07 01:14:13 PM PST 24
Finished Feb 07 01:14:19 PM PST 24
Peak memory 240120 kb
Host smart-214172eb-9846-400f-a948-91adb4ddafbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21791
04552 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_sig_int_fail.2179104552
Directory /workspace/47.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/47.alert_handler_smoke.1400746777
Short name T138
Test name
Test status
Simulation time 240558004 ps
CPU time 14.7 seconds
Started Feb 07 01:14:00 PM PST 24
Finished Feb 07 01:14:15 PM PST 24
Peak memory 256608 kb
Host smart-a3f3101f-05e9-444b-812c-c673680ae88b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14007
46777 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_smoke.1400746777
Directory /workspace/47.alert_handler_smoke/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all.1621617749
Short name T124
Test name
Test status
Simulation time 160832442912 ps
CPU time 1126.92 seconds
Started Feb 07 01:14:21 PM PST 24
Finished Feb 07 01:33:09 PM PST 24
Peak memory 284888 kb
Host smart-acda0423-cb5c-4b21-b9da-e5cb3a060bdd
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621617749 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_ha
ndler_stress_all.1621617749
Directory /workspace/47.alert_handler_stress_all/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all_with_rand_reset.2552528573
Short name T119
Test name
Test status
Simulation time 1206336080821 ps
CPU time 4542.02 seconds
Started Feb 07 01:14:16 PM PST 24
Finished Feb 07 02:29:59 PM PST 24
Peak memory 297812 kb
Host smart-d127644e-755e-4ee7-8572-e7ddcf733732
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552528573 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 47.alert_handler_stress_all_with_rand_reset.2552528573
Directory /workspace/47.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.alert_handler_entropy.127849774
Short name T234
Test name
Test status
Simulation time 41821419209 ps
CPU time 1476.84 seconds
Started Feb 07 01:14:19 PM PST 24
Finished Feb 07 01:38:56 PM PST 24
Peak memory 273008 kb
Host smart-0d8bd0ae-d68c-41f4-9e5b-934ca56ddb5c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127849774 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_entropy.127849774
Directory /workspace/48.alert_handler_entropy/latest

Test location /workspace/coverage/default/48.alert_handler_esc_alert_accum.1570680983
Short name T653
Test name
Test status
Simulation time 954465294 ps
CPU time 73.69 seconds
Started Feb 07 01:14:17 PM PST 24
Finished Feb 07 01:15:32 PM PST 24
Peak memory 255620 kb
Host smart-204c2bd2-b36e-4a1c-b00e-cd266edc641e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15706
80983 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_alert_accum.1570680983
Directory /workspace/48.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/48.alert_handler_esc_intr_timeout.691499490
Short name T434
Test name
Test status
Simulation time 320520736 ps
CPU time 17.12 seconds
Started Feb 07 01:14:18 PM PST 24
Finished Feb 07 01:14:36 PM PST 24
Peak memory 254172 kb
Host smart-07e61322-49b0-4886-a647-7d3a831ef5e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69149
9490 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_intr_timeout.691499490
Directory /workspace/48.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_lpg.4156339254
Short name T304
Test name
Test status
Simulation time 193559114847 ps
CPU time 1982.61 seconds
Started Feb 07 01:14:16 PM PST 24
Finished Feb 07 01:47:20 PM PST 24
Peak memory 273300 kb
Host smart-ace73c28-0af3-45cb-8a03-82537667ff96
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156339254 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg.4156339254
Directory /workspace/48.alert_handler_lpg/latest

Test location /workspace/coverage/default/48.alert_handler_lpg_stub_clk.2823067197
Short name T500
Test name
Test status
Simulation time 14771227360 ps
CPU time 1169.57 seconds
Started Feb 07 01:14:19 PM PST 24
Finished Feb 07 01:33:49 PM PST 24
Peak memory 281292 kb
Host smart-978e3288-ae12-44b6-8ab2-0075dac54be7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823067197 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg_stub_clk.2823067197
Directory /workspace/48.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/48.alert_handler_ping_timeout.1674651608
Short name T718
Test name
Test status
Simulation time 10923450675 ps
CPU time 266.08 seconds
Started Feb 07 01:14:22 PM PST 24
Finished Feb 07 01:18:48 PM PST 24
Peak memory 246984 kb
Host smart-ef2ffbf4-75c6-4f68-8089-04b887a01354
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1674651608 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_ping_timeout.1674651608
Directory /workspace/48.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_random_alerts.3176066891
Short name T297
Test name
Test status
Simulation time 4302858568 ps
CPU time 41.11 seconds
Started Feb 07 01:14:14 PM PST 24
Finished Feb 07 01:14:56 PM PST 24
Peak memory 248532 kb
Host smart-eb8da903-5de9-45cf-88cf-68e496235a9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31760
66891 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_alerts.3176066891
Directory /workspace/48.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/48.alert_handler_random_classes.2784311170
Short name T64
Test name
Test status
Simulation time 7258619070 ps
CPU time 58.08 seconds
Started Feb 07 01:14:16 PM PST 24
Finished Feb 07 01:15:15 PM PST 24
Peak memory 255436 kb
Host smart-85f17dbd-a4e3-4afc-93fe-536d5410998d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27843
11170 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_classes.2784311170
Directory /workspace/48.alert_handler_random_classes/latest

Test location /workspace/coverage/default/48.alert_handler_sig_int_fail.2877224531
Short name T610
Test name
Test status
Simulation time 371073932 ps
CPU time 25.36 seconds
Started Feb 07 01:14:21 PM PST 24
Finished Feb 07 01:14:47 PM PST 24
Peak memory 254420 kb
Host smart-03892770-964c-49bc-b1d4-acdd088ea579
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28772
24531 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_sig_int_fail.2877224531
Directory /workspace/48.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/48.alert_handler_smoke.4081302823
Short name T478
Test name
Test status
Simulation time 53826148 ps
CPU time 5.88 seconds
Started Feb 07 01:14:18 PM PST 24
Finished Feb 07 01:14:25 PM PST 24
Peak memory 256664 kb
Host smart-a0adfbf1-f1f2-414a-8316-d173ae5a37e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40813
02823 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_smoke.4081302823
Directory /workspace/48.alert_handler_smoke/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all.2597754569
Short name T459
Test name
Test status
Simulation time 60017694731 ps
CPU time 225.97 seconds
Started Feb 07 01:14:16 PM PST 24
Finished Feb 07 01:18:03 PM PST 24
Peak memory 256712 kb
Host smart-d287b052-95f7-49b8-85b8-ab290870ed49
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597754569 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_ha
ndler_stress_all.2597754569
Directory /workspace/48.alert_handler_stress_all/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all_with_rand_reset.719798622
Short name T287
Test name
Test status
Simulation time 250418037070 ps
CPU time 3886.82 seconds
Started Feb 07 01:14:21 PM PST 24
Finished Feb 07 02:19:09 PM PST 24
Peak memory 297780 kb
Host smart-1901c2a4-18e3-474c-a4bb-622bcb08b7d1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719798622 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 48.alert_handler_stress_all_with_rand_reset.719798622
Directory /workspace/48.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.alert_handler_entropy.2658759089
Short name T2
Test name
Test status
Simulation time 139455008867 ps
CPU time 2482.26 seconds
Started Feb 07 01:14:27 PM PST 24
Finished Feb 07 01:55:50 PM PST 24
Peak memory 283692 kb
Host smart-f1d3f806-913a-4450-bc01-399072163764
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658759089 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_entropy.2658759089
Directory /workspace/49.alert_handler_entropy/latest

Test location /workspace/coverage/default/49.alert_handler_esc_alert_accum.1159675792
Short name T476
Test name
Test status
Simulation time 103955318 ps
CPU time 7.25 seconds
Started Feb 07 01:14:25 PM PST 24
Finished Feb 07 01:14:33 PM PST 24
Peak memory 253328 kb
Host smart-fc4635e7-3c52-4bbf-8e57-75abd25a3d28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11596
75792 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_alert_accum.1159675792
Directory /workspace/49.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/49.alert_handler_esc_intr_timeout.506595010
Short name T703
Test name
Test status
Simulation time 537980439 ps
CPU time 32.93 seconds
Started Feb 07 01:14:24 PM PST 24
Finished Feb 07 01:14:58 PM PST 24
Peak memory 254056 kb
Host smart-4d459866-400f-4562-adc9-14c9dee10c2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50659
5010 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_intr_timeout.506595010
Directory /workspace/49.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_lpg.2825697729
Short name T17
Test name
Test status
Simulation time 32504082592 ps
CPU time 753.66 seconds
Started Feb 07 01:14:28 PM PST 24
Finished Feb 07 01:27:02 PM PST 24
Peak memory 272800 kb
Host smart-ac3a0896-d734-41a1-8291-f7dd5d89ee23
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825697729 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg.2825697729
Directory /workspace/49.alert_handler_lpg/latest

Test location /workspace/coverage/default/49.alert_handler_lpg_stub_clk.3074530121
Short name T384
Test name
Test status
Simulation time 191642659442 ps
CPU time 2793.76 seconds
Started Feb 07 01:14:24 PM PST 24
Finished Feb 07 02:00:58 PM PST 24
Peak memory 288692 kb
Host smart-de77a6dd-b09c-4f22-a180-10ae04e654cd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3074530121 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg_stub_clk.3074530121
Directory /workspace/49.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/49.alert_handler_ping_timeout.3842253468
Short name T324
Test name
Test status
Simulation time 30151520833 ps
CPU time 625.98 seconds
Started Feb 07 01:14:28 PM PST 24
Finished Feb 07 01:24:55 PM PST 24
Peak memory 247432 kb
Host smart-79eb9604-bacd-4e95-8265-b02dc223d3de
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842253468 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_ping_timeout.3842253468
Directory /workspace/49.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_random_alerts.572560743
Short name T454
Test name
Test status
Simulation time 197266372 ps
CPU time 13.74 seconds
Started Feb 07 01:14:18 PM PST 24
Finished Feb 07 01:14:33 PM PST 24
Peak memory 248408 kb
Host smart-b0bd96c5-54dc-458c-a4b5-7105d1f83d82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57256
0743 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_alerts.572560743
Directory /workspace/49.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/49.alert_handler_random_classes.1568693768
Short name T67
Test name
Test status
Simulation time 185967094 ps
CPU time 22.65 seconds
Started Feb 07 01:14:24 PM PST 24
Finished Feb 07 01:14:47 PM PST 24
Peak memory 254844 kb
Host smart-1c2ad3a4-5a1b-4ab6-b91f-313c3ba274cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15686
93768 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_classes.1568693768
Directory /workspace/49.alert_handler_random_classes/latest

Test location /workspace/coverage/default/49.alert_handler_sig_int_fail.3539954749
Short name T736
Test name
Test status
Simulation time 1465033542 ps
CPU time 50.82 seconds
Started Feb 07 01:14:23 PM PST 24
Finished Feb 07 01:15:15 PM PST 24
Peak memory 254560 kb
Host smart-66de24e6-0f2d-46c5-b99b-c42e00d5f5f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35399
54749 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_sig_int_fail.3539954749
Directory /workspace/49.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/49.alert_handler_smoke.46615244
Short name T692
Test name
Test status
Simulation time 1387364409 ps
CPU time 26.25 seconds
Started Feb 07 01:14:19 PM PST 24
Finished Feb 07 01:14:46 PM PST 24
Peak memory 248500 kb
Host smart-0b1b213a-e786-4e90-8e05-34f09e19cf28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46615
244 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_smoke.46615244
Directory /workspace/49.alert_handler_smoke/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all.3008991405
Short name T499
Test name
Test status
Simulation time 163484643967 ps
CPU time 2577.17 seconds
Started Feb 07 01:14:28 PM PST 24
Finished Feb 07 01:57:26 PM PST 24
Peak memory 280972 kb
Host smart-b9b909f2-306b-4855-9ac5-23aac10aaef0
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008991405 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_ha
ndler_stress_all.3008991405
Directory /workspace/49.alert_handler_stress_all/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all_with_rand_reset.87296159
Short name T549
Test name
Test status
Simulation time 77867996130 ps
CPU time 1796.85 seconds
Started Feb 07 01:14:26 PM PST 24
Finished Feb 07 01:44:24 PM PST 24
Peak memory 297800 kb
Host smart-d7514ea0-5c30-4c91-9f4b-44ce9bb5a61b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87296159 -assert nopostproc +UVM_TESTNAME=alert_
handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 49.alert_handler_stress_all_with_rand_reset.87296159
Directory /workspace/49.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.alert_handler_alert_accum_saturation.2126622627
Short name T220
Test name
Test status
Simulation time 75693768 ps
CPU time 3.59 seconds
Started Feb 07 01:09:05 PM PST 24
Finished Feb 07 01:09:09 PM PST 24
Peak memory 248632 kb
Host smart-f5bf7129-eddd-4183-8f9a-20e9a84d7a91
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2126622627 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_alert_accum_saturation.2126622627
Directory /workspace/5.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/5.alert_handler_entropy.3277340897
Short name T522
Test name
Test status
Simulation time 8940915329 ps
CPU time 676.07 seconds
Started Feb 07 01:09:04 PM PST 24
Finished Feb 07 01:20:21 PM PST 24
Peak memory 264940 kb
Host smart-f6559360-0b9a-4915-8d12-d4125e6ee4a3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277340897 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy.3277340897
Directory /workspace/5.alert_handler_entropy/latest

Test location /workspace/coverage/default/5.alert_handler_entropy_stress.840332
Short name T498
Test name
Test status
Simulation time 301882781 ps
CPU time 14.89 seconds
Started Feb 07 01:09:00 PM PST 24
Finished Feb 07 01:09:15 PM PST 24
Peak memory 240188 kb
Host smart-2abd88cb-f356-4e0a-a5be-5b12692a015f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=840332 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy_stress.840332
Directory /workspace/5.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/5.alert_handler_esc_alert_accum.1050824656
Short name T628
Test name
Test status
Simulation time 5474105169 ps
CPU time 102.07 seconds
Started Feb 07 01:09:00 PM PST 24
Finished Feb 07 01:10:43 PM PST 24
Peak memory 256048 kb
Host smart-f5f6da0b-6cf6-4e16-b62c-6a59c07f39d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10508
24656 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_alert_accum.1050824656
Directory /workspace/5.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/5.alert_handler_esc_intr_timeout.1187891937
Short name T99
Test name
Test status
Simulation time 738476867 ps
CPU time 13.22 seconds
Started Feb 07 01:09:00 PM PST 24
Finished Feb 07 01:09:14 PM PST 24
Peak memory 252408 kb
Host smart-40856654-522d-496c-b084-11fd65b30f31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11878
91937 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_intr_timeout.1187891937
Directory /workspace/5.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_lpg.2057005907
Short name T552
Test name
Test status
Simulation time 122960156100 ps
CPU time 1999.13 seconds
Started Feb 07 01:09:01 PM PST 24
Finished Feb 07 01:42:22 PM PST 24
Peak memory 289160 kb
Host smart-bf38b319-68cd-49ab-a5cb-f881335223b4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057005907 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg.2057005907
Directory /workspace/5.alert_handler_lpg/latest

Test location /workspace/coverage/default/5.alert_handler_lpg_stub_clk.4022645688
Short name T689
Test name
Test status
Simulation time 78837166561 ps
CPU time 1300.88 seconds
Started Feb 07 01:09:02 PM PST 24
Finished Feb 07 01:30:45 PM PST 24
Peak memory 272540 kb
Host smart-8a375d53-aacc-48ab-be19-0db3718bf859
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022645688 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg_stub_clk.4022645688
Directory /workspace/5.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/5.alert_handler_ping_timeout.1831204259
Short name T93
Test name
Test status
Simulation time 2988794722 ps
CPU time 127.97 seconds
Started Feb 07 01:09:04 PM PST 24
Finished Feb 07 01:11:13 PM PST 24
Peak memory 248512 kb
Host smart-4f900b2d-f8f9-4f47-af25-10e9ebd76d0a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831204259 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_ping_timeout.1831204259
Directory /workspace/5.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_random_alerts.3818859827
Short name T413
Test name
Test status
Simulation time 83804304 ps
CPU time 10.35 seconds
Started Feb 07 01:09:00 PM PST 24
Finished Feb 07 01:09:11 PM PST 24
Peak memory 256640 kb
Host smart-809051ea-c037-4b7b-b392-450dce0fafab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38188
59827 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_alerts.3818859827
Directory /workspace/5.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/5.alert_handler_random_classes.512361766
Short name T737
Test name
Test status
Simulation time 670014501 ps
CPU time 20 seconds
Started Feb 07 01:09:04 PM PST 24
Finished Feb 07 01:09:25 PM PST 24
Peak memory 246664 kb
Host smart-93094a38-86ad-46a3-b4fa-feeed92dd049
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51236
1766 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_classes.512361766
Directory /workspace/5.alert_handler_random_classes/latest

Test location /workspace/coverage/default/5.alert_handler_sig_int_fail.503568616
Short name T648
Test name
Test status
Simulation time 182817625 ps
CPU time 12.83 seconds
Started Feb 07 01:09:02 PM PST 24
Finished Feb 07 01:09:16 PM PST 24
Peak memory 252036 kb
Host smart-a7d973b0-b513-4562-8b9b-ed8ea483e9b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50356
8616 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_sig_int_fail.503568616
Directory /workspace/5.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/5.alert_handler_smoke.728968573
Short name T425
Test name
Test status
Simulation time 845594695 ps
CPU time 44.2 seconds
Started Feb 07 01:09:02 PM PST 24
Finished Feb 07 01:09:48 PM PST 24
Peak memory 248544 kb
Host smart-d2742700-ba75-456b-ab71-f37587e4ff92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72896
8573 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_smoke.728968573
Directory /workspace/5.alert_handler_smoke/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all.2972943316
Short name T705
Test name
Test status
Simulation time 340266817217 ps
CPU time 1336.72 seconds
Started Feb 07 01:09:02 PM PST 24
Finished Feb 07 01:31:20 PM PST 24
Peak memory 288724 kb
Host smart-440de14a-c5e4-4dbb-a3ca-27a87df18de9
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972943316 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_han
dler_stress_all.2972943316
Directory /workspace/5.alert_handler_stress_all/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all_with_rand_reset.42175249
Short name T529
Test name
Test status
Simulation time 12931875953 ps
CPU time 870.57 seconds
Started Feb 07 01:09:02 PM PST 24
Finished Feb 07 01:23:34 PM PST 24
Peak memory 272604 kb
Host smart-ccf4e123-785a-432d-9be8-4325b5fa3951
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42175249 -assert nopostproc +UVM_TESTNAME=alert_
handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 5.alert_handler_stress_all_with_rand_reset.42175249
Directory /workspace/5.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.alert_handler_alert_accum_saturation.206491524
Short name T216
Test name
Test status
Simulation time 13492008 ps
CPU time 2.52 seconds
Started Feb 07 01:09:02 PM PST 24
Finished Feb 07 01:09:06 PM PST 24
Peak memory 248636 kb
Host smart-8942fcd7-e8b9-4db4-b914-e93436c9145c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=206491524 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_alert_accum_saturation.206491524
Directory /workspace/6.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/6.alert_handler_entropy.2545742306
Short name T508
Test name
Test status
Simulation time 31347398487 ps
CPU time 2101.54 seconds
Started Feb 07 01:09:02 PM PST 24
Finished Feb 07 01:44:05 PM PST 24
Peak memory 288484 kb
Host smart-a85a132e-e6aa-400a-8bbb-9fdb2daf8635
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545742306 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy.2545742306
Directory /workspace/6.alert_handler_entropy/latest

Test location /workspace/coverage/default/6.alert_handler_entropy_stress.3695736880
Short name T590
Test name
Test status
Simulation time 145497761 ps
CPU time 9.5 seconds
Started Feb 07 01:09:05 PM PST 24
Finished Feb 07 01:09:15 PM PST 24
Peak memory 240216 kb
Host smart-e5f9e666-1630-4c59-af77-be40110d4650
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3695736880 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy_stress.3695736880
Directory /workspace/6.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/6.alert_handler_esc_alert_accum.3332826119
Short name T573
Test name
Test status
Simulation time 6756676423 ps
CPU time 131.04 seconds
Started Feb 07 01:09:01 PM PST 24
Finished Feb 07 01:11:15 PM PST 24
Peak memory 255996 kb
Host smart-b3907d65-fe42-4911-8f2f-ff9e4a1f68f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33328
26119 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_alert_accum.3332826119
Directory /workspace/6.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/6.alert_handler_esc_intr_timeout.1332547451
Short name T117
Test name
Test status
Simulation time 2395356686 ps
CPU time 34.05 seconds
Started Feb 07 01:09:05 PM PST 24
Finished Feb 07 01:09:39 PM PST 24
Peak memory 246728 kb
Host smart-45737ce2-4ffe-476b-910b-b64680de65f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13325
47451 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_intr_timeout.1332547451
Directory /workspace/6.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_lpg.1006019083
Short name T339
Test name
Test status
Simulation time 295672415440 ps
CPU time 2064.4 seconds
Started Feb 07 01:09:01 PM PST 24
Finished Feb 07 01:43:27 PM PST 24
Peak memory 273092 kb
Host smart-22d49554-b11e-4c57-9816-1f8169397019
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006019083 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg.1006019083
Directory /workspace/6.alert_handler_lpg/latest

Test location /workspace/coverage/default/6.alert_handler_lpg_stub_clk.1659284517
Short name T536
Test name
Test status
Simulation time 285135882193 ps
CPU time 2010.6 seconds
Started Feb 07 01:09:02 PM PST 24
Finished Feb 07 01:42:35 PM PST 24
Peak memory 273056 kb
Host smart-8de7abac-f3d3-4690-8b03-231b3a8758b0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659284517 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg_stub_clk.1659284517
Directory /workspace/6.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/6.alert_handler_ping_timeout.2995065022
Short name T87
Test name
Test status
Simulation time 137688309395 ps
CPU time 342.38 seconds
Started Feb 07 01:09:05 PM PST 24
Finished Feb 07 01:14:48 PM PST 24
Peak memory 247304 kb
Host smart-b20f0a56-b666-4d03-9fdb-b2557464a8d7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995065022 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_ping_timeout.2995065022
Directory /workspace/6.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_random_alerts.4242739623
Short name T477
Test name
Test status
Simulation time 777021654 ps
CPU time 13.19 seconds
Started Feb 07 01:09:03 PM PST 24
Finished Feb 07 01:09:17 PM PST 24
Peak memory 248404 kb
Host smart-3f55d1cf-1081-4b43-8f93-576bd7508875
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42427
39623 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_alerts.4242739623
Directory /workspace/6.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/6.alert_handler_random_classes.1246587604
Short name T71
Test name
Test status
Simulation time 426192952 ps
CPU time 25.94 seconds
Started Feb 07 01:09:02 PM PST 24
Finished Feb 07 01:09:30 PM PST 24
Peak memory 254516 kb
Host smart-efb66cf3-49a9-4564-8797-d2666ac7b42f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12465
87604 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_classes.1246587604
Directory /workspace/6.alert_handler_random_classes/latest

Test location /workspace/coverage/default/6.alert_handler_sig_int_fail.2875177658
Short name T112
Test name
Test status
Simulation time 2130359446 ps
CPU time 44.23 seconds
Started Feb 07 01:09:05 PM PST 24
Finished Feb 07 01:09:50 PM PST 24
Peak memory 253436 kb
Host smart-4c1f072e-e943-4bfa-b61d-0dc8349c4f42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28751
77658 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_sig_int_fail.2875177658
Directory /workspace/6.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/6.alert_handler_smoke.3008513070
Short name T430
Test name
Test status
Simulation time 622260825 ps
CPU time 9.54 seconds
Started Feb 07 01:09:03 PM PST 24
Finished Feb 07 01:09:14 PM PST 24
Peak memory 248432 kb
Host smart-292064ce-842a-4eb1-b02e-ae2170b9da67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30085
13070 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_smoke.3008513070
Directory /workspace/6.alert_handler_smoke/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all.4017582203
Short name T72
Test name
Test status
Simulation time 28239240218 ps
CPU time 1794.29 seconds
Started Feb 07 01:09:01 PM PST 24
Finished Feb 07 01:38:58 PM PST 24
Peak memory 282096 kb
Host smart-5624ced5-bcf7-4a64-9465-21db5042bec7
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017582203 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_han
dler_stress_all.4017582203
Directory /workspace/6.alert_handler_stress_all/latest

Test location /workspace/coverage/default/7.alert_handler_alert_accum_saturation.4060878381
Short name T224
Test name
Test status
Simulation time 114063517 ps
CPU time 2.51 seconds
Started Feb 07 01:09:00 PM PST 24
Finished Feb 07 01:09:04 PM PST 24
Peak memory 248644 kb
Host smart-591df75b-4b18-4de6-9885-6505eb571a96
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4060878381 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_alert_accum_saturation.4060878381
Directory /workspace/7.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/7.alert_handler_entropy.3582229975
Short name T123
Test name
Test status
Simulation time 120653804952 ps
CPU time 3501.54 seconds
Started Feb 07 01:09:04 PM PST 24
Finished Feb 07 02:07:27 PM PST 24
Peak memory 289020 kb
Host smart-1ed68d5e-7024-49fe-a1eb-79a5ec23dee8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582229975 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy.3582229975
Directory /workspace/7.alert_handler_entropy/latest

Test location /workspace/coverage/default/7.alert_handler_entropy_stress.3780609678
Short name T373
Test name
Test status
Simulation time 505724040 ps
CPU time 23.95 seconds
Started Feb 07 01:09:08 PM PST 24
Finished Feb 07 01:09:33 PM PST 24
Peak memory 240208 kb
Host smart-5c61ed0c-0d8e-4599-9462-ef5d5243174c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3780609678 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy_stress.3780609678
Directory /workspace/7.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/7.alert_handler_esc_alert_accum.1437832025
Short name T724
Test name
Test status
Simulation time 3319014829 ps
CPU time 153.37 seconds
Started Feb 07 01:09:11 PM PST 24
Finished Feb 07 01:11:46 PM PST 24
Peak memory 256144 kb
Host smart-3d14a25b-b31f-42e6-b1f6-715d1edfa969
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14378
32025 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_alert_accum.1437832025
Directory /workspace/7.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/7.alert_handler_esc_intr_timeout.2401802807
Short name T541
Test name
Test status
Simulation time 402838570 ps
CPU time 25.73 seconds
Started Feb 07 01:09:06 PM PST 24
Finished Feb 07 01:09:32 PM PST 24
Peak memory 256052 kb
Host smart-bc825ebd-e9a7-4cb6-b0f1-82446752170d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24018
02807 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_intr_timeout.2401802807
Directory /workspace/7.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_lpg.4258864584
Short name T344
Test name
Test status
Simulation time 32183009798 ps
CPU time 608.27 seconds
Started Feb 07 01:10:09 PM PST 24
Finished Feb 07 01:20:18 PM PST 24
Peak memory 271548 kb
Host smart-b6f2e88e-c9e1-4880-9d1c-94c2139e49b4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258864584 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg.4258864584
Directory /workspace/7.alert_handler_lpg/latest

Test location /workspace/coverage/default/7.alert_handler_lpg_stub_clk.2568222716
Short name T683
Test name
Test status
Simulation time 77636071819 ps
CPU time 2282.58 seconds
Started Feb 07 01:09:03 PM PST 24
Finished Feb 07 01:47:07 PM PST 24
Peak memory 284016 kb
Host smart-1e6fd47e-cbce-4c65-badb-fae8e934eae9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568222716 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg_stub_clk.2568222716
Directory /workspace/7.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/7.alert_handler_ping_timeout.3305117619
Short name T315
Test name
Test status
Simulation time 41364054058 ps
CPU time 181.17 seconds
Started Feb 07 01:09:05 PM PST 24
Finished Feb 07 01:12:07 PM PST 24
Peak memory 246272 kb
Host smart-275015e2-80f9-4fa2-af17-b9bfd5b0f4a1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305117619 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_ping_timeout.3305117619
Directory /workspace/7.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_random_alerts.1995118132
Short name T494
Test name
Test status
Simulation time 15631323756 ps
CPU time 56 seconds
Started Feb 07 01:09:03 PM PST 24
Finished Feb 07 01:10:00 PM PST 24
Peak memory 248540 kb
Host smart-8e6f1fa1-dbd9-4cc2-be69-9e77db686c47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19951
18132 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_alerts.1995118132
Directory /workspace/7.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/7.alert_handler_random_classes.1647980860
Short name T399
Test name
Test status
Simulation time 2580575072 ps
CPU time 30.48 seconds
Started Feb 07 01:09:04 PM PST 24
Finished Feb 07 01:09:35 PM PST 24
Peak memory 253632 kb
Host smart-ca248378-d026-4e86-a670-97fd322c0fd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16479
80860 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_classes.1647980860
Directory /workspace/7.alert_handler_random_classes/latest

Test location /workspace/coverage/default/7.alert_handler_sig_int_fail.2165528194
Short name T79
Test name
Test status
Simulation time 446587014 ps
CPU time 17.28 seconds
Started Feb 07 01:09:07 PM PST 24
Finished Feb 07 01:09:25 PM PST 24
Peak memory 248444 kb
Host smart-f536ef90-9524-4046-b39d-44b4c28712a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21655
28194 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_sig_int_fail.2165528194
Directory /workspace/7.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/7.alert_handler_smoke.1376147636
Short name T630
Test name
Test status
Simulation time 1074854015 ps
CPU time 17.43 seconds
Started Feb 07 01:09:05 PM PST 24
Finished Feb 07 01:09:23 PM PST 24
Peak memory 248440 kb
Host smart-8ed2c659-fd0b-46bf-9697-4c0c61759fe7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13761
47636 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_smoke.1376147636
Directory /workspace/7.alert_handler_smoke/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all.1195263344
Short name T263
Test name
Test status
Simulation time 178809088218 ps
CPU time 2748.74 seconds
Started Feb 07 01:09:06 PM PST 24
Finished Feb 07 01:54:56 PM PST 24
Peak memory 300172 kb
Host smart-94e6bad6-c53d-4402-9687-030d3ffe0159
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195263344 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_han
dler_stress_all.1195263344
Directory /workspace/7.alert_handler_stress_all/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all_with_rand_reset.2730584724
Short name T262
Test name
Test status
Simulation time 461970553972 ps
CPU time 8426.63 seconds
Started Feb 07 01:09:04 PM PST 24
Finished Feb 07 03:29:32 PM PST 24
Peak memory 337840 kb
Host smart-24691043-806b-493c-8944-a59b9770c02e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730584724 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.alert_handler_stress_all_with_rand_reset.2730584724
Directory /workspace/7.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.alert_handler_alert_accum_saturation.903770107
Short name T219
Test name
Test status
Simulation time 90693804 ps
CPU time 3.92 seconds
Started Feb 07 01:09:21 PM PST 24
Finished Feb 07 01:09:31 PM PST 24
Peak memory 248592 kb
Host smart-1151d3b0-6ed3-42b4-a06c-7fcf48b9fad8
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=903770107 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_alert_accum_saturation.903770107
Directory /workspace/8.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/8.alert_handler_entropy.2937749224
Short name T414
Test name
Test status
Simulation time 11194626876 ps
CPU time 1230.37 seconds
Started Feb 07 01:09:22 PM PST 24
Finished Feb 07 01:29:58 PM PST 24
Peak memory 288992 kb
Host smart-28b5b2da-1070-4e82-b531-d1b4b6566a27
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937749224 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy.2937749224
Directory /workspace/8.alert_handler_entropy/latest

Test location /workspace/coverage/default/8.alert_handler_entropy_stress.949632460
Short name T634
Test name
Test status
Simulation time 706175475 ps
CPU time 11.14 seconds
Started Feb 07 01:09:16 PM PST 24
Finished Feb 07 01:09:32 PM PST 24
Peak memory 252156 kb
Host smart-5b6c5870-7eee-4321-89b4-ec0b10989f09
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=949632460 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy_stress.949632460
Directory /workspace/8.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/8.alert_handler_esc_alert_accum.297494811
Short name T516
Test name
Test status
Simulation time 9594876175 ps
CPU time 272.79 seconds
Started Feb 07 01:09:14 PM PST 24
Finished Feb 07 01:13:54 PM PST 24
Peak memory 256676 kb
Host smart-ac8a00ec-9086-4e42-8671-510943b32d1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29749
4811 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_alert_accum.297494811
Directory /workspace/8.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/8.alert_handler_esc_intr_timeout.808733048
Short name T646
Test name
Test status
Simulation time 612454221 ps
CPU time 16.74 seconds
Started Feb 07 01:09:12 PM PST 24
Finished Feb 07 01:09:33 PM PST 24
Peak memory 254092 kb
Host smart-43aa8208-b768-4a11-b9a2-bc8a125faa67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80873
3048 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_intr_timeout.808733048
Directory /workspace/8.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_lpg_stub_clk.784630721
Short name T231
Test name
Test status
Simulation time 41180538392 ps
CPU time 974.49 seconds
Started Feb 07 01:09:22 PM PST 24
Finished Feb 07 01:25:42 PM PST 24
Peak memory 272336 kb
Host smart-5697b6b0-85eb-49e0-b223-b45506e85b3f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784630721 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg_stub_clk.784630721
Directory /workspace/8.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/8.alert_handler_ping_timeout.1777149343
Short name T328
Test name
Test status
Simulation time 8539513033 ps
CPU time 367.06 seconds
Started Feb 07 01:09:13 PM PST 24
Finished Feb 07 01:15:28 PM PST 24
Peak memory 247288 kb
Host smart-efe0efac-2e2e-42b7-a9d2-77b5c59ae731
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777149343 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_ping_timeout.1777149343
Directory /workspace/8.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_random_alerts.890221517
Short name T412
Test name
Test status
Simulation time 137178930 ps
CPU time 10.04 seconds
Started Feb 07 01:09:14 PM PST 24
Finished Feb 07 01:09:31 PM PST 24
Peak memory 253188 kb
Host smart-e9ab8305-a262-49f1-b7f3-0d80ab744e20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89022
1517 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_alerts.890221517
Directory /workspace/8.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/8.alert_handler_random_classes.3521235430
Short name T684
Test name
Test status
Simulation time 4493101027 ps
CPU time 55.4 seconds
Started Feb 07 01:09:18 PM PST 24
Finished Feb 07 01:10:18 PM PST 24
Peak memory 254652 kb
Host smart-a4fa14a5-d8b2-4d6c-a169-a37470414e37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35212
35430 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_classes.3521235430
Directory /workspace/8.alert_handler_random_classes/latest

Test location /workspace/coverage/default/8.alert_handler_sig_int_fail.3965197673
Short name T92
Test name
Test status
Simulation time 377177531 ps
CPU time 13.02 seconds
Started Feb 07 01:09:21 PM PST 24
Finished Feb 07 01:09:40 PM PST 24
Peak memory 254580 kb
Host smart-8fb9c004-a7b1-4cb5-b05d-1cd01a150e06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39651
97673 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_sig_int_fail.3965197673
Directory /workspace/8.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/8.alert_handler_smoke.1500613360
Short name T424
Test name
Test status
Simulation time 198544487 ps
CPU time 7.72 seconds
Started Feb 07 01:09:04 PM PST 24
Finished Feb 07 01:09:12 PM PST 24
Peak memory 248520 kb
Host smart-593a51ad-73fe-47e3-a427-abe703a95c3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15006
13360 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_smoke.1500613360
Directory /workspace/8.alert_handler_smoke/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all.904795121
Short name T520
Test name
Test status
Simulation time 37787553033 ps
CPU time 321.79 seconds
Started Feb 07 01:09:21 PM PST 24
Finished Feb 07 01:14:49 PM PST 24
Peak memory 256692 kb
Host smart-97d4b91d-aea8-4885-9f9b-0bbb7cce7c7a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904795121 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_hand
ler_stress_all.904795121
Directory /workspace/8.alert_handler_stress_all/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all_with_rand_reset.95439445
Short name T282
Test name
Test status
Simulation time 184085299112 ps
CPU time 2408.15 seconds
Started Feb 07 01:09:16 PM PST 24
Finished Feb 07 01:49:30 PM PST 24
Peak memory 289152 kb
Host smart-e89c21be-bfce-49e5-bb6e-bb8ec6d0b1f8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95439445 -assert nopostproc +UVM_TESTNAME=alert_
handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 8.alert_handler_stress_all_with_rand_reset.95439445
Directory /workspace/8.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.alert_handler_alert_accum_saturation.1155946784
Short name T225
Test name
Test status
Simulation time 72972258 ps
CPU time 3.53 seconds
Started Feb 07 01:09:15 PM PST 24
Finished Feb 07 01:09:25 PM PST 24
Peak memory 248636 kb
Host smart-cd1a479a-e874-4127-8355-959f604937a6
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1155946784 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_alert_accum_saturation.1155946784
Directory /workspace/9.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/9.alert_handler_entropy.3039552333
Short name T654
Test name
Test status
Simulation time 7812025377 ps
CPU time 844.37 seconds
Started Feb 07 01:09:19 PM PST 24
Finished Feb 07 01:23:27 PM PST 24
Peak memory 272092 kb
Host smart-4a97668f-5024-4aff-9824-f10295ec07a0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039552333 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy.3039552333
Directory /workspace/9.alert_handler_entropy/latest

Test location /workspace/coverage/default/9.alert_handler_entropy_stress.3529697941
Short name T369
Test name
Test status
Simulation time 721629497 ps
CPU time 25.11 seconds
Started Feb 07 01:09:21 PM PST 24
Finished Feb 07 01:09:52 PM PST 24
Peak memory 240152 kb
Host smart-f1fbc507-4633-4d06-8034-27634d0f92ac
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3529697941 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy_stress.3529697941
Directory /workspace/9.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/9.alert_handler_esc_alert_accum.3912502461
Short name T731
Test name
Test status
Simulation time 1718556343 ps
CPU time 143.36 seconds
Started Feb 07 01:09:20 PM PST 24
Finished Feb 07 01:11:46 PM PST 24
Peak memory 250496 kb
Host smart-825bb0ea-05d4-47e3-9568-db929a2dba9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39125
02461 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_alert_accum.3912502461
Directory /workspace/9.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/9.alert_handler_esc_intr_timeout.2229644050
Short name T515
Test name
Test status
Simulation time 9190769300 ps
CPU time 66.17 seconds
Started Feb 07 01:09:20 PM PST 24
Finished Feb 07 01:10:29 PM PST 24
Peak memory 254912 kb
Host smart-df3cd904-acea-424e-b3ee-aef957cd558d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22296
44050 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_intr_timeout.2229644050
Directory /workspace/9.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_lpg_stub_clk.2562618493
Short name T564
Test name
Test status
Simulation time 9469709000 ps
CPU time 984.69 seconds
Started Feb 07 01:09:23 PM PST 24
Finished Feb 07 01:25:52 PM PST 24
Peak memory 272080 kb
Host smart-d3cdc9bf-d8b8-4420-bd8a-c0379a066856
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562618493 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg_stub_clk.2562618493
Directory /workspace/9.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/9.alert_handler_random_alerts.263472453
Short name T716
Test name
Test status
Simulation time 47813031 ps
CPU time 6.23 seconds
Started Feb 07 01:09:22 PM PST 24
Finished Feb 07 01:09:33 PM PST 24
Peak memory 248384 kb
Host smart-247ab508-cf4a-41dd-b96a-23cfd820ff73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26347
2453 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_alerts.263472453
Directory /workspace/9.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/9.alert_handler_random_classes.3507947551
Short name T620
Test name
Test status
Simulation time 834543283 ps
CPU time 56.97 seconds
Started Feb 07 01:09:18 PM PST 24
Finished Feb 07 01:10:19 PM PST 24
Peak memory 254784 kb
Host smart-8ff8e816-e092-4111-9e6c-967da7664d22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35079
47551 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_classes.3507947551
Directory /workspace/9.alert_handler_random_classes/latest

Test location /workspace/coverage/default/9.alert_handler_sig_int_fail.61120626
Short name T514
Test name
Test status
Simulation time 925605530 ps
CPU time 52.71 seconds
Started Feb 07 01:09:20 PM PST 24
Finished Feb 07 01:10:15 PM PST 24
Peak memory 247840 kb
Host smart-eae537ef-95a5-4e68-8d96-60078cc95a52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61120
626 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_sig_int_fail.61120626
Directory /workspace/9.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/9.alert_handler_smoke.4265866344
Short name T22
Test name
Test status
Simulation time 1867015204 ps
CPU time 56.08 seconds
Started Feb 07 01:09:23 PM PST 24
Finished Feb 07 01:10:24 PM PST 24
Peak memory 248396 kb
Host smart-90c6816c-6b1e-46da-bb73-f918ed67f051
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42658
66344 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_smoke.4265866344
Directory /workspace/9.alert_handler_smoke/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all_with_rand_reset.2148379337
Short name T132
Test name
Test status
Simulation time 227983457918 ps
CPU time 3528.33 seconds
Started Feb 07 01:09:23 PM PST 24
Finished Feb 07 02:08:16 PM PST 24
Peak memory 305352 kb
Host smart-624dca05-8620-4dd8-822b-6048b41c4e55
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148379337 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 9.alert_handler_stress_all_with_rand_reset.2148379337
Directory /workspace/9.alert_handler_stress_all_with_rand_reset/latest
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