Unified Coverage Report :: Module :: alert_handler_accu

Module : alert_handler_accu

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[1].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[2].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[3].u_accu	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_classes[0].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[1].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[2].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[3].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

Line Coverage for Module : alert_handler_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Module : alert_handler_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T101,T199,T211
1	1	Covered	T2,T3,T4

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T5

---

Assert Coverage for Module : alert_handler_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	2147483647	12567	0	0
DisabledNoTrigBkwd_A	2147483647	797528	0	0
DisabledNoTrigFwd_A	2147483647	1397973027	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	12567	0	0
T15	59702	0	0	0
T23	604716	0	0	0
T44	319436	0	0	0
T58	90920	0	0	0
T73	9333	0	0	0
T79	27061	0	0	0
T80	8058	0	0	0
T86	116567	0	0	0
T87	22172	0	0	0
T88	609460	0	0	0
T101	1276	565	0	0
T102	208353	0	0	0
T119	37768	0	0	0
T120	164141	0	0	0
T199	3080	858	0	0
T200	233467	0	0	0
T201	441560	0	0	0
T202	3503	0	0	0
T211	0	954	0	0
T212	3012	773	0	0
T213	0	575	0	0
T214	0	311	0	0
T215	0	1633	0	0
T216	0	741	0	0
T217	0	699	0	0
T218	0	316	0	0
T219	0	308	0	0
T220	0	731	0	0
T221	0	474	0	0
T222	0	180	0	0
T223	0	241	0	0
T224	0	811	0	0
T225	0	724	0	0
T226	0	262	0	0
T227	0	360	0	0
T228	0	1051	0	0
T229	69353	0	0	0
T230	80182	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	797528	0	0
T2	394221	4619	0	0
T3	52416	0	0	0
T4	1252908	6146	0	0
T5	926920	3284	0	0
T6	981820	4214	0	0
T7	229680	0	0	0
T8	198656	0	0	0
T9	139876	15	0	0
T10	1006432	0	0	0
T18	799230	5	0	0
T19	0	312	0	0
T20	0	3097	0	0
T24	0	2476	0	0
T27	0	3	0	0
T31	0	267	0	0
T32	0	45	0	0
T33	0	4	0	0
T34	0	1	0	0
T35	0	53	0	0
T36	0	228	0	0
T37	0	2039	0	0
T38	439516	3	0	0
T39	0	1	0	0
T40	172971	0	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1397973027	0	0
T1	68736	68408	0	0
T2	525628	431562	0	0
T3	69888	12769	0	0
T4	1252908	671681	0	0
T5	926920	509357	0	0
T6	981820	629652	0	0
T7	229680	150946	0	0
T8	198656	71694	0	0
T9	139876	102228	0	0
T10	1006432	980040	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T101,T213,T214
1	1	Covered	T2,T3,T4

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T6

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	619359372	5182	0	0
DisabledNoTrigBkwd_A	619359372	234356	0	0
DisabledNoTrigFwd_A	619359372	326191360	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	619359372	5182	0	0
T15	59702	0	0	0
T23	604716	0	0	0
T58	90920	0	0	0
T73	9333	0	0	0
T79	27061	0	0	0
T80	8058	0	0	0
T101	1276	565	0	0
T102	208353	0	0	0
T119	37768	0	0	0
T213	0	575	0	0
T214	0	311	0	0
T215	0	1633	0	0
T217	0	699	0	0
T219	0	308	0	0
T220	0	731	0	0
T227	0	360	0	0
T229	69353	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	619359372	234356	0	0
T2	131407	4496	0	0
T3	17472	0	0	0
T4	313227	14	0	0
T5	231730	0	0	0
T6	245455	3539	0	0
T7	57420	0	0	0
T8	49664	0	0	0
T9	34969	0	0	0
T10	251608	0	0	0
T18	0	1	0	0
T19	0	81	0	0
T20	0	1441	0	0
T31	0	24	0	0
T32	0	45	0	0
T33	0	4	0	0
T34	0	1	0	0
T38	109879	0	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	619359372	326191360	0	0
T1	17184	17102	0	0
T2	131407	47228	0	0
T3	17472	3411	0	0
T4	313227	311514	0	0
T5	231730	231723	0	0
T6	245455	119514	0	0
T7	57420	8961	0	0
T8	49664	16023	0	0
T9	34969	34918	0	0
T10	251608	246084	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T199,T216,T221
1	1	Covered	T2,T3,T4

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T5

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	619359372	2884	0	0
DisabledNoTrigBkwd_A	619359372	186586	0	0
DisabledNoTrigFwd_A	619359372	355709857	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	619359372	2884	0	0
T44	319436	0	0	0
T86	116567	0	0	0
T87	22172	0	0	0
T88	609460	0	0	0
T120	164141	0	0	0
T199	3080	858	0	0
T200	233467	0	0	0
T201	441560	0	0	0
T202	3503	0	0	0
T216	0	741	0	0
T221	0	474	0	0
T224	0	811	0	0
T230	80182	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	619359372	186586	0	0
T2	131407	55	0	0
T3	17472	0	0	0
T4	313227	5113	0	0
T5	231730	1574	0	0
T6	245455	357	0	0
T7	57420	0	0	0
T8	49664	0	0	0
T9	34969	0	0	0
T10	251608	0	0	0
T18	0	2	0	0
T19	0	142	0	0
T20	0	1649	0	0
T31	0	20	0	0
T35	0	32	0	0
T37	0	4	0	0
T38	109879	0	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	619359372	355709857	0	0
T1	17184	17102	0	0
T2	131407	126402	0	0
T3	17472	2357	0	0
T4	313227	15297	0	0
T5	231730	16700	0	0
T6	245455	202679	0	0
T7	57420	57342	0	0
T8	49664	49614	0	0
T9	34969	31802	0	0
T10	251608	236371	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T5
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T5

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T212,T218,T222
1	1	Covered	T2,T3,T5

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T5,T9

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	619359372	2582	0	0
DisabledNoTrigBkwd_A	619359372	172722	0	0
DisabledNoTrigFwd_A	619359372	375137010	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	619359372	2582	0	0
T29	46457	0	0	0
T48	156574	0	0	0
T212	3012	773	0	0
T213	3945	0	0	0
T218	0	316	0	0
T222	0	180	0	0
T226	0	262	0	0
T228	0	1051	0	0
T231	407932	0	0	0
T232	306157	0	0	0
T233	11493	0	0	0
T234	113439	0	0	0
T235	22903	0	0	0
T236	451468	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	619359372	172722	0	0
T2	131407	68	0	0
T3	17472	0	0	0
T4	313227	0	0	0
T5	231730	2	0	0
T6	245455	0	0	0
T7	57420	0	0	0
T8	49664	0	0	0
T9	34969	15	0	0
T10	251608	0	0	0
T18	0	1	0	0
T20	0	3	0	0
T24	0	2476	0	0
T31	0	223	0	0
T35	0	2	0	0
T36	0	228	0	0
T38	109879	3	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	619359372	375137010	0	0
T1	17184	17102	0	0
T2	131407	126544	0	0
T3	17472	4632	0	0
T4	313227	313221	0	0
T5	231730	231213	0	0
T6	245455	159959	0	0
T7	57420	27301	0	0
T8	49664	3021	0	0
T9	34969	590	0	0
T10	251608	251523	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Covered	T2,T3,T4
1	1	Covered	T3,T4,T5

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T211,T223,T225
1	1	Covered	T3,T4,T5

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T3,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	619359372	1919	0	0
DisabledNoTrigBkwd_A	619359372	203864	0	0
DisabledNoTrigFwd_A	619359372	340934800	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	619359372	1919	0	0
T47	514434	0	0	0
T211	2036	954	0	0
T223	0	241	0	0
T225	0	724	0	0
T237	561556	0	0	0
T238	13147	0	0	0
T239	33620	0	0	0
T240	60436	0	0	0
T241	33214	0	0	0
T242	267423	0	0	0
T243	165725	0	0	0
T244	108428	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	619359372	203864	0	0
T4	313227	1019	0	0
T5	231730	1708	0	0
T6	245455	318	0	0
T7	57420	0	0	0
T8	49664	0	0	0
T9	34969	0	0	0
T10	251608	0	0	0
T18	799230	1	0	0
T19	0	89	0	0
T20	0	4	0	0
T27	0	3	0	0
T35	0	19	0	0
T37	0	2035	0	0
T38	109879	0	0	0
T39	0	1	0	0
T40	172971	0	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	619359372	340934800	0	0
T1	17184	17102	0	0
T2	131407	131388	0	0
T3	17472	2369	0	0
T4	313227	31649	0	0
T5	231730	29721	0	0
T6	245455	147500	0	0
T7	57420	57342	0	0
T8	49664	3036	0	0
T9	34969	34918	0	0
T10	251608	246062	0	0