Unified Coverage Report :: Module :: alert_handler_esc_timer

Module : alert_handler_esc_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.30	100.00	91.49		70.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[2].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[3].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[1].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00

---

Module Instance : tb.dut.gen_classes[0].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[2].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[3].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[1].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.26	100.00	95.56	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	80	1	1	100.00
ALWAYS	129	89	89	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
ALWAYS	300	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
80	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
137	1	1
139	1	1
143	1	1
144	1	1
146	1	1
147	1	1
148	1	1
149	1	1
152	1	1
153	1	1
154	1	1
			MISSING_ELSE
164	1	1
166	1	1
167	1	1
168	1	1
169	1	1
170	1	1
173	1	1
174	1	1
176	1	1
177	1	1
182	1	1
183	1	1
184	1	1
185	1	1
186	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
195	1	1
			MISSING_ELSE
199	1	1
200	1	1
201	1	1
202	1	1
203	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
212	1	1
			MISSING_ELSE
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
229	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
			MISSING_ELSE
253	1	1
254	1	1
255	1	1
256	1	1
			MISSING_ELSE
263	1	1
264	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
287	4	4
290	4	4
300	3	3

---

Cond Coverage for Module : alert_handler_esc_timer

	Total	Covered	Percent
Conditions	47	43	91.49
Logical	47	43	91.49
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

 LINE       146
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T4
1	0	1	Not Covered
1	1	0	Covered	T14
1	1	1	Covered	T2,T4,T5

 LINE       152
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T4
1	0	1	Covered	T4,T5,T6
1	1	0	Covered	T2,T3,T4
1	1	1	Covered	T3,T6,T7

 LINE       166
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T3,T6,T7
0	1	Covered	T6,T7,T8
1	0	Covered	T15,T16,T17

 LINE       166
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T6,T7
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T15,T16,T17

 LINE       166
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T6,T7
1	0	Not Covered
1	1	Covered	T6,T7,T8

 LINE       186
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T2,T4,T5

 LINE       203
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T2,T5,T6

 LINE       220
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T6,T18,T19

 LINE       237
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T4,T6,T20

 LINE       278
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13

 LINE       290
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T4,T5

 LINE       290
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T4,T5

 LINE       290
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T4,T5

 LINE       290
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T4,T5

---

FSM Coverage for Module : alert_handler_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	20	14	70.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	279	Covered	T11,T12,T13
IdleSt	176	Covered	T1,T2,T3
Phase0St	147	Covered	T2,T4,T5
Phase1St	193	Covered	T2,T4,T5
Phase2St	210	Covered	T2,T4,T5
Phase3St	228	Covered	T2,T4,T5
TerminalSt	244	Covered	T2,T4,T5
TimeoutSt	154	Covered	T3,T6,T7

transitions	Line No.	Covered	Tests
IdleSt->FsmErrorSt	279	Covered	T11,T12,T13
IdleSt->Phase0St	147	Covered	T2,T4,T5
IdleSt->TimeoutSt	154	Covered	T3,T6,T7
Phase0St->FsmErrorSt	279	Not Covered
Phase0St->IdleSt	189	Covered	T21,T22,T17
Phase0St->Phase1St	193	Covered	T2,T4,T5
Phase1St->FsmErrorSt	279	Not Covered
Phase1St->IdleSt	206	Covered	T21,T23,T17
Phase1St->Phase2St	210	Covered	T2,T4,T5
Phase2St->FsmErrorSt	279	Not Covered
Phase2St->IdleSt	224	Covered	T24,T25,T26
Phase2St->Phase3St	228	Covered	T2,T4,T5
Phase3St->FsmErrorSt	279	Not Covered
Phase3St->IdleSt	240	Covered	T27,T17,T28
Phase3St->TerminalSt	244	Covered	T2,T4,T5
TerminalSt->FsmErrorSt	279	Not Covered
TerminalSt->IdleSt	256	Covered	T2,T4,T5
TimeoutSt->FsmErrorSt	279	Not Covered
TimeoutSt->IdleSt	176	Covered	T3,T6,T7
TimeoutSt->Phase0St	167	Covered	T6,T7,T21

---

Branch Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	139	22	22	100.00
IF	278	2	2	100.00
IF	300	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	139	case (state_q)
-2-:	146	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	152	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	166	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	173	if (timeout_en_i)
-6-:	188	if (clr_i)
-7-:	192	if (cnt_ge)
-8-:	205	if (clr_i)
-9-:	209	if (cnt_ge)
-10-:	223	if (clr_i)
-11-:	227	if (cnt_ge)
-12-:	239	if (clr_i)
-13-:	243	if (cnt_ge)
-14-:	255	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T5
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T6,T7
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T6,T7,T21
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T3,T6,T7
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T3,T6,T7
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T21,T22,T17
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T4,T5
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T4,T5
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T21,T23,T17
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T4,T5
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T4,T5
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T24,T25,T26
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T2,T4,T5
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T4,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T27,T17,T28
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T2,T4,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T4,T5
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T2,T4,T5
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T4,T5
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	278	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	300	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	2147483647	1065	0	0
CheckAccumTrig0_A	2147483647	2114	0	0
CheckAccumTrig1_A	2147483647	80	0	0
CheckClr_A	2147483647	954	0	0
CheckEn_A	2147483647	1070595652	0	0
CheckPhase0_A	2147483647	2321	0	0
CheckPhase1_A	2147483647	2276	0	0
CheckPhase2_A	2147483647	2235	0	0
CheckPhase3_A	2147483647	2191	0	0
CheckTimeout0_A	2147483647	3750	0	0
CheckTimeoutSt1_A	2147483647	394313	0	0
CheckTimeoutSt2_A	2147483647	3494	0	0
CheckTimeoutStTrig_A	2147483647	173	0	0
ErrorStAllEscAsserted_A	2147483647	5751	0	0
ErrorStIsTerminal_A	2147483647	4791	0	0
u_state_regs_A	2147483647	2147483647	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1065	0	0
T11	208276	142	0	0
T12	76388	138	0	0
T13	0	236	0	0
T24	620120	0	0	0
T29	0	276	0	0
T30	0	273	0	0
T31	285112	0	0	0
T32	172096	0	0	0
T33	126508	0	0	0
T34	78264	0	0	0
T35	449356	0	0	0
T36	705144	0	0	0
T37	1721268	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2114	0	0
T2	394221	5	0	0
T3	52416	0	0	0
T4	1252908	6	0	0
T5	926920	4	0	0
T6	981820	4	0	0
T7	229680	0	0	0
T8	198656	0	0	0
T9	139876	5	0	0
T10	1006432	0	0	0
T18	799230	4	0	0
T19	0	3	0	0
T20	0	4	0	0
T24	0	1	0	0
T27	0	1	0	0
T31	0	3	0	0
T32	0	1	0	0
T33	0	1	0	0
T34	0	1	0	0
T35	0	4	0	0
T36	0	1	0	0
T37	0	3	0	0
T38	439516	1	0	0
T39	0	1	0	0
T40	172971	0	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	80	0	0
T15	59702	1	0	0
T16	114869	2	0	0
T17	70160	2	0	0
T22	299661	0	0	0
T25	134817	0	0	0
T28	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	156574	1	0	0
T49	301296	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T52	0	2	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	0	2	0	0
T57	0	1	0	0
T58	90920	0	0	0
T59	1375824	0	0	0
T60	275732	0	0	0
T61	56878	0	0	0
T62	52204	0	0	0
T63	925118	0	0	0
T64	42943	0	0	0
T65	31764	0	0	0
T66	106443	0	0	0
T67	28134	0	0	0
T68	149945	0	0	0
T69	20698	0	0	0
T70	41434	0	0	0
T71	11642	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	954	0	0
T2	131407	1	0	0
T3	17472	0	0	0
T4	626454	2	0	0
T5	926920	2	0	0
T6	981820	1	0	0
T7	229680	1	0	0
T8	198656	0	0	0
T9	139876	0	0	0
T10	1006432	0	0	0
T17	0	4	0	0
T18	2397690	0	0	0
T19	287950	0	0	0
T21	0	8	0	0
T22	0	2	0	0
T23	0	1	0	0
T24	0	2	0	0
T25	0	12	0	0
T27	0	1	0	0
T34	0	1	0	0
T35	0	2	0	0
T37	0	1	0	0
T38	439516	0	0	0
T40	518913	0	0	0
T58	0	6	0	0
T72	0	3	0	0
T73	0	1	0	0
T74	0	4	0	0
T75	0	1	0	0
T76	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1070595652	0	0
T1	68736	68404	0	0
T2	525628	385157	0	0
T3	69888	12769	0	0
T4	1252908	374683	0	0
T5	926920	503807	0	0
T6	981820	603860	0	0
T7	229680	150944	0	0
T8	198656	71693	0	0
T9	139876	102225	0	0
T10	1006432	980036	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2321	0	0
T2	394221	5	0	0
T3	52416	0	0	0
T4	1252908	6	0	0
T5	926920	4	0	0
T6	981820	7	0	0
T7	229680	1	0	0
T8	198656	1	0	0
T9	139876	5	0	0
T10	1006432	0	0	0
T18	799230	4	0	0
T19	0	3	0	0
T20	0	4	0	0
T31	0	3	0	0
T32	0	1	0	0
T33	0	1	0	0
T34	0	1	0	0
T35	0	4	0	0
T37	0	3	0	0
T38	439516	1	0	0
T40	172971	0	0	0
T72	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2276	0	0
T2	394221	5	0	0
T3	52416	0	0	0
T4	1252908	6	0	0
T5	926920	4	0	0
T6	981820	7	0	0
T7	229680	1	0	0
T8	198656	1	0	0
T9	139876	5	0	0
T10	1006432	0	0	0
T18	799230	4	0	0
T19	0	3	0	0
T20	0	4	0	0
T31	0	3	0	0
T32	0	1	0	0
T33	0	1	0	0
T34	0	1	0	0
T35	0	4	0	0
T37	0	3	0	0
T38	439516	1	0	0
T40	172971	0	0	0
T72	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2235	0	0
T2	394221	5	0	0
T3	52416	0	0	0
T4	1252908	6	0	0
T5	926920	4	0	0
T6	981820	7	0	0
T7	229680	1	0	0
T8	198656	1	0	0
T9	139876	5	0	0
T10	1006432	0	0	0
T18	799230	4	0	0
T19	0	3	0	0
T20	0	4	0	0
T31	0	3	0	0
T32	0	1	0	0
T33	0	1	0	0
T34	0	1	0	0
T35	0	4	0	0
T37	0	3	0	0
T38	439516	1	0	0
T40	172971	0	0	0
T72	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2191	0	0
T2	394221	5	0	0
T3	52416	0	0	0
T4	1252908	6	0	0
T5	926920	4	0	0
T6	981820	7	0	0
T7	229680	1	0	0
T8	198656	1	0	0
T9	139876	5	0	0
T10	1006432	0	0	0
T18	799230	4	0	0
T19	0	3	0	0
T20	0	4	0	0
T31	0	3	0	0
T32	0	1	0	0
T33	0	1	0	0
T34	0	1	0	0
T35	0	4	0	0
T37	0	3	0	0
T38	439516	1	0	0
T40	172971	0	0	0
T72	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3750	0	0
T3	69888	13	0	0
T4	1252908	0	0	0
T5	926920	0	0	0
T6	981820	20	0	0
T7	229680	6	0	0
T8	198656	9	0	0
T9	139876	0	0	0
T10	1006432	0	0	0
T17	0	10	0	0
T18	3196920	0	0	0
T20	0	2	0	0
T21	0	21	0	0
T23	0	3	0	0
T33	0	1	0	0
T38	439516	0	0	0
T58	0	5	0	0
T59	0	5	0	0
T72	0	2	0	0
T74	0	2	0	0
T77	0	2	0	0
T78	0	7	0	0
T79	0	1	0	0
T80	0	3	0	0
T81	0	2	0	0
T82	0	2	0	0
T83	0	1	0	0
T84	0	2	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	394313	0	0
T3	69888	597	0	0
T4	1252908	0	0	0
T5	926920	0	0	0
T6	981820	1421	0	0
T7	229680	937	0	0
T8	198656	2181	0	0
T9	139876	0	0	0
T10	1006432	0	0	0
T17	0	3555	0	0
T18	3196920	0	0	0
T20	0	76	0	0
T21	0	4034	0	0
T23	0	64	0	0
T33	0	21	0	0
T38	439516	0	0	0
T58	0	2691	0	0
T59	0	365	0	0
T72	0	677	0	0
T74	0	169	0	0
T77	0	61	0	0
T78	0	393	0	0
T79	0	92	0	0
T80	0	237	0	0
T81	0	109	0	0
T82	0	103	0	0
T83	0	87	0	0
T84	0	385	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3494	0	0
T3	69888	13	0	0
T4	1252908	0	0	0
T5	926920	0	0	0
T6	981820	17	0	0
T7	229680	5	0	0
T8	198656	8	0	0
T9	139876	0	0	0
T10	1006432	0	0	0
T17	0	6	0	0
T18	3196920	0	0	0
T20	0	2	0	0
T21	0	17	0	0
T23	0	3	0	0
T33	0	1	0	0
T38	439516	0	0	0
T58	0	3	0	0
T59	0	139	0	0
T72	0	1	0	0
T74	0	2	0	0
T77	0	1	0	0
T78	0	7	0	0
T79	0	1	0	0
T80	0	3	0	0
T81	0	2	0	0
T82	0	2	0	0
T83	0	1	0	0
T84	0	2	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	173	0	0
T6	490910	3	0	0
T7	114840	1	0	0
T8	148992	1	0	0
T9	104907	0	0	0
T10	754824	0	0	0
T13	33821	0	0	0
T17	0	5	0	0
T18	2397690	0	0	0
T19	431925	0	0	0
T20	2383860	0	0	0
T21	279740	4	0	0
T23	604716	0	0	0
T28	0	2	0	0
T38	329637	0	0	0
T40	518913	0	0	0
T44	0	3	0	0
T46	0	2	0	0
T58	0	3	0	0
T78	107529	0	0	0
T84	0	3	0	0
T85	0	1	0	0
T86	0	1	0	0
T87	0	2	0	0
T88	0	2	0	0
T89	0	2	0	0
T90	0	3	0	0
T91	0	1	0	0
T92	0	1	0	0
T93	0	1	0	0
T94	0	1	0	0
T95	0	1	0	0
T96	82586	0	0	0
T97	6250	0	0	0
T98	94744	0	0	0
T99	118400	0	0	0
T100	15734	0	0	0
T101	1276	0	0	0
T102	208353	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5751	0	0
T11	208276	703	0	0
T12	76388	725	0	0
T13	0	1453	0	0
T24	620120	0	0	0
T29	0	1422	0	0
T30	0	1448	0	0
T31	285112	0	0	0
T32	172096	0	0	0
T33	126508	0	0	0
T34	78264	0	0	0
T35	449356	0	0	0
T36	705144	0	0	0
T37	1721268	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4791	0	0
T11	208276	583	0	0
T12	76388	605	0	0
T13	0	1213	0	0
T24	620120	0	0	0
T29	0	1182	0	0
T30	0	1208	0	0
T31	285112	0	0	0
T32	172096	0	0	0
T33	126508	0	0	0
T34	78264	0	0	0
T35	449356	0	0	0
T36	705144	0	0	0
T37	1721268	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	68736	68408	0	0
T2	525628	525552	0	0
T3	69888	69576	0	0
T4	1252908	1252884	0	0
T5	926920	926892	0	0
T6	981820	981700	0	0
T7	229680	229368	0	0
T8	198656	198456	0	0
T9	139876	139672	0	0
T10	1006432	1006092	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	80	1	1	100.00
ALWAYS	129	89	89	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
ALWAYS	300	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
80	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
137	1	1
139	1	1
143	1	1
144	1	1
146	1	1
147	1	1
148	1	1
149	1	1
152	1	1
153	1	1
154	1	1
			MISSING_ELSE
164	1	1
166	1	1
167	1	1
168	1	1
169	1	1
170	1	1
173	1	1
174	1	1
176	1	1
177	1	1
182	1	1
183	1	1
184	1	1
185	1	1
186	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
195	1	1
			MISSING_ELSE
199	1	1
200	1	1
201	1	1
202	1	1
203	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
212	1	1
			MISSING_ELSE
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
229	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
			MISSING_ELSE
253	1	1
254	1	1
255	1	1
256	1	1
			MISSING_ELSE
263	1	1
264	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
287	4	4
290	4	4
300	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

 LINE       146
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T3,T4
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T2,T4,T6

 LINE       152
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T4
1	0	1	Covered	T6,T10,T18
1	1	0	Covered	T3,T4,T6
1	1	1	Covered	T3,T6,T7

 LINE       166
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T3,T6,T7
0	1	Covered	T21,T58,T17
1	0	Covered	T15,T16,T17

 LINE       166
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T3,T6,T7
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T15,T16,T17

 LINE       166
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T6,T7
1	0	Not Covered
1	1	Covered	T21,T58,T17

 LINE       186
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T4,T6,T18
1	Covered	T2,T4,T24

 LINE       203
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T4,T6
1	Covered	T18,T33,T34

 LINE       220
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T4,T6
1	Covered	T6,T19,T20

 LINE       237
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T4,T6
1	Covered	T4,T6,T24

 LINE       278
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13

 LINE       290
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T4,T6

 LINE       290
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T6,T18

 LINE       290
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T4,T6

 LINE       290
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T4,T6

---

FSM Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	279	Covered	T11,T12,T13
IdleSt	176	Covered	T1,T2,T3
Phase0St	147	Covered	T2,T4,T6
Phase1St	193	Covered	T2,T4,T6
Phase2St	210	Covered	T2,T4,T6
Phase3St	228	Covered	T2,T4,T6
TerminalSt	244	Covered	T2,T4,T6
TimeoutSt	154	Covered	T3,T6,T7

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	279	Covered	T11,T12,T13
IdleSt->Phase0St	147	Covered	T2,T4,T6
IdleSt->TimeoutSt	154	Covered	T3,T6,T7
Phase0St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	189	Covered	T17,T25,T45
Phase0St->Phase1St	193	Covered	T2,T4,T6
Phase1St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	206	Covered	T23,T17,T85
Phase1St->Phase2St	210	Covered	T2,T4,T6
Phase2St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	224	Covered	T24,T25,T103
Phase2St->Phase3St	228	Covered	T2,T4,T6
Phase3St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	240	Covered	T27,T17,T104
Phase3St->TerminalSt	244	Covered	T2,T4,T6
TerminalSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	256	Covered	T2,T4,T6
TimeoutSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	176	Covered	T3,T6,T7
TimeoutSt->Phase0St	167	Covered	T21,T15,T58

---

Branch Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	139	22	22	100.00
IF	278	2	2	100.00
IF	300	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	139	case (state_q)
-2-:	146	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	152	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	166	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	173	if (timeout_en_i)
-6-:	188	if (clr_i)
-7-:	192	if (cnt_ge)
-8-:	205	if (clr_i)
-9-:	209	if (cnt_ge)
-10-:	223	if (clr_i)
-11-:	227	if (cnt_ge)
-12-:	239	if (clr_i)
-13-:	243	if (cnt_ge)
-14-:	255	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T6
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T6,T7
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T21,T15,T58
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T3,T6,T7
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T3,T6,T7
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T17,T25,T45
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T4,T6
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T4,T6
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T23,T17,T85
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T4,T6
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T4,T6
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T24,T25,T103
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T2,T4,T6
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T4,T6
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T27,T17,T104
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T2,T4,T6
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T4,T6
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T2,T4,T34
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T4,T6
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	278	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	300	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	619359372	224	0	0
CheckAccumTrig0_A	619359372	781	0	0
CheckAccumTrig1_A	619359372	34	0	0
CheckClr_A	619359372	360	0	0
CheckEn_A	619175232	230479022	0	0
CheckPhase0_A	619359372	841	0	0
CheckPhase1_A	619359372	821	0	0
CheckPhase2_A	619359372	807	0	0
CheckPhase3_A	619359372	793	0	0
CheckTimeout0_A	619359372	1236	0	0
CheckTimeoutSt1_A	619359372	132576	0	0
CheckTimeoutSt2_A	619359372	1157	0	0
CheckTimeoutStTrig_A	619359372	44	0	0
ErrorStAllEscAsserted_A	619359372	1406	0	0
ErrorStIsTerminal_A	619359372	1166	0	0
u_state_regs_A	619359372	619190096	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	619359372	224	0	0
T11	52069	25	0	0
T12	19097	23	0	0
T13	0	54	0	0
T24	155030	0	0	0
T29	0	69	0	0
T30	0	53	0	0
T31	71278	0	0	0
T32	43024	0	0	0
T33	31627	0	0	0
T34	19566	0	0	0
T35	112339	0	0	0
T36	176286	0	0	0
T37	430317	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	619359372	781	0	0
T2	131407	3	0	0
T3	17472	0	0	0
T4	313227	3	0	0
T5	231730	0	0	0
T6	245455	2	0	0
T7	57420	0	0	0
T8	49664	0	0	0
T9	34969	0	0	0
T10	251608	0	0	0
T18	0	1	0	0
T19	0	1	0	0
T20	0	1	0	0
T31	0	1	0	0
T32	0	1	0	0
T33	0	1	0	0
T34	0	1	0	0
T38	109879	0	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	619359372	34	0	0
T15	59702	1	0	0
T16	114869	2	0	0
T17	35080	1	0	0
T22	299661	0	0	0
T28	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T58	90920	0	0	0
T59	687912	0	0	0
T60	137866	0	0	0
T61	28439	0	0	0
T62	26102	0	0	0
T63	462559	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	619359372	360	0	0
T2	131407	1	0	0
T3	17472	0	0	0
T4	313227	2	0	0
T5	231730	0	0	0
T6	245455	0	0	0
T7	57420	0	0	0
T8	49664	0	0	0
T9	34969	0	0	0
T10	251608	0	0	0
T21	0	2	0	0
T23	0	1	0	0
T24	0	2	0	0
T27	0	1	0	0
T34	0	1	0	0
T38	109879	0	0	0
T58	0	6	0	0
T72	0	2	0	0
T73	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	619175232	230479022	0	0
T1	17184	17101	0	0
T2	131407	1208	0	0
T3	17472	3411	0	0
T4	313227	14516	0	0
T5	231730	231723	0	0
T6	245455	119513	0	0
T7	57420	8961	0	0
T8	49664	16023	0	0
T9	34969	34917	0	0
T10	251608	246083	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	619359372	841	0	0
T2	131407	3	0	0
T3	17472	0	0	0
T4	313227	3	0	0
T5	231730	0	0	0
T6	245455	2	0	0
T7	57420	0	0	0
T8	49664	0	0	0
T9	34969	0	0	0
T10	251608	0	0	0
T18	0	1	0	0
T19	0	1	0	0
T20	0	1	0	0
T31	0	1	0	0
T32	0	1	0	0
T33	0	1	0	0
T34	0	1	0	0
T38	109879	0	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	619359372	821	0	0
T2	131407	3	0	0
T3	17472	0	0	0
T4	313227	3	0	0
T5	231730	0	0	0
T6	245455	2	0	0
T7	57420	0	0	0
T8	49664	0	0	0
T9	34969	0	0	0
T10	251608	0	0	0
T18	0	1	0	0
T19	0	1	0	0
T20	0	1	0	0
T31	0	1	0	0
T32	0	1	0	0
T33	0	1	0	0
T34	0	1	0	0
T38	109879	0	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	619359372	807	0	0
T2	131407	3	0	0
T3	17472	0	0	0
T4	313227	3	0	0
T5	231730	0	0	0
T6	245455	2	0	0
T7	57420	0	0	0
T8	49664	0	0	0
T9	34969	0	0	0
T10	251608	0	0	0
T18	0	1	0	0
T19	0	1	0	0
T20	0	1	0	0
T31	0	1	0	0
T32	0	1	0	0
T33	0	1	0	0
T34	0	1	0	0
T38	109879	0	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	619359372	793	0	0
T2	131407	3	0	0
T3	17472	0	0	0
T4	313227	3	0	0
T5	231730	0	0	0
T6	245455	2	0	0
T7	57420	0	0	0
T8	49664	0	0	0
T9	34969	0	0	0
T10	251608	0	0	0
T18	0	1	0	0
T19	0	1	0	0
T20	0	1	0	0
T31	0	1	0	0
T32	0	1	0	0
T33	0	1	0	0
T34	0	1	0	0
T38	109879	0	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	619359372	1236	0	0
T3	17472	4	0	0
T4	313227	0	0	0
T5	231730	0	0	0
T6	245455	1	0	0
T7	57420	4	0	0
T8	49664	2	0	0
T9	34969	0	0	0
T10	251608	0	0	0
T18	799230	0	0	0
T20	0	2	0	0
T21	0	5	0	0
T33	0	1	0	0
T38	109879	0	0	0
T72	0	1	0	0
T79	0	1	0	0
T80	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	619359372	132576	0	0
T3	17472	191	0	0
T4	313227	0	0	0
T5	231730	0	0	0
T6	245455	92	0	0
T7	57420	747	0	0
T8	49664	416	0	0
T9	34969	0	0	0
T10	251608	0	0	0
T18	799230	0	0	0
T20	0	76	0	0
T21	0	876	0	0
T33	0	21	0	0
T38	109879	0	0	0
T72	0	82	0	0
T79	0	92	0	0
T80	0	72	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	619359372	1157	0	0
T3	17472	4	0	0
T4	313227	0	0	0
T5	231730	0	0	0
T6	245455	1	0	0
T7	57420	4	0	0
T8	49664	2	0	0
T9	34969	0	0	0
T10	251608	0	0	0
T18	799230	0	0	0
T20	0	2	0	0
T21	0	3	0	0
T33	0	1	0	0
T38	109879	0	0	0
T72	0	1	0	0
T79	0	1	0	0
T80	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	619359372	44	0	0
T13	33821	0	0	0
T17	0	3	0	0
T21	279740	2	0	0
T23	604716	0	0	0
T46	0	2	0	0
T58	0	1	0	0
T78	107529	0	0	0
T84	0	1	0	0
T85	0	1	0	0
T86	0	1	0	0
T87	0	1	0	0
T88	0	1	0	0
T89	0	1	0	0
T97	6250	0	0	0
T98	94744	0	0	0
T99	118400	0	0	0
T100	15734	0	0	0
T101	1276	0	0	0
T102	208353	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	619359372	1406	0	0
T11	52069	175	0	0
T12	19097	180	0	0
T13	0	345	0	0
T24	155030	0	0	0
T29	0	365	0	0
T30	0	341	0	0
T31	71278	0	0	0
T32	43024	0	0	0
T33	31627	0	0	0
T34	19566	0	0	0
T35	112339	0	0	0
T36	176286	0	0	0
T37	430317	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	619359372	1166	0	0
T11	52069	145	0	0
T12	19097	150	0	0
T13	0	285	0	0
T24	155030	0	0	0
T29	0	305	0	0
T30	0	281	0	0
T31	71278	0	0	0
T32	43024	0	0	0
T33	31627	0	0	0
T34	19566	0	0	0
T35	112339	0	0	0
T36	176286	0	0	0
T37	430317	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	619359372	619190096	0	0
T1	17184	17102	0	0
T2	131407	131388	0	0
T3	17472	17394	0	0
T4	313227	313221	0	0
T5	231730	231723	0	0
T6	245455	245425	0	0
T7	57420	57342	0	0
T8	49664	49614	0	0
T9	34969	34918	0	0
T10	251608	251523	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	80	1	1	100.00
ALWAYS	129	89	89	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
ALWAYS	300	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
80	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
137	1	1
139	1	1
143	1	1
144	1	1
146	1	1
147	1	1
148	1	1
149	1	1
152	1	1
153	1	1
154	1	1
			MISSING_ELSE
164	1	1
166	1	1
167	1	1
168	1	1
169	1	1
170	1	1
173	1	1
174	1	1
176	1	1
177	1	1
182	1	1
183	1	1
184	1	1
185	1	1
186	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
195	1	1
			MISSING_ELSE
199	1	1
200	1	1
201	1	1
202	1	1
203	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
212	1	1
			MISSING_ELSE
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
229	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
			MISSING_ELSE
253	1	1
254	1	1
255	1	1
256	1	1
			MISSING_ELSE
263	1	1
264	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
287	4	4
290	4	4
300	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T3,T5
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T5

 LINE       146
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T3,T5
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T2,T5,T9

 LINE       152
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T6
1	0	1	Covered	T6,T9,T31
1	1	0	Covered	T4,T6,T7
1	1	1	Covered	T3,T6,T7

 LINE       166
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T3,T6,T7
0	1	Covered	T6,T7,T17
1	0	Covered	T17,T45,T103

 LINE       166
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T3,T6,T7
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T17,T45,T103

 LINE       166
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T6,T7
1	0	Not Covered
1	1	Covered	T6,T7,T17

 LINE       186
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T2,T38,T18

 LINE       203
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T6,T38
1	Covered	T5,T6,T7

 LINE       220
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T5,T6
1	Covered	T6,T35,T72

 LINE       237
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T5,T6
1	Covered	T31,T39,T59

 LINE       278
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13

 LINE       290
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T6,T18

 LINE       290
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T5,T9,T38

 LINE       290
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T7,T38,T18

 LINE       290
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T5,T6

---

FSM Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	279	Covered	T11,T12,T13
IdleSt	176	Covered	T1,T2,T3
Phase0St	147	Covered	T2,T5,T6
Phase1St	193	Covered	T2,T5,T6
Phase2St	210	Covered	T2,T5,T6
Phase3St	228	Covered	T2,T5,T6
TerminalSt	244	Covered	T2,T5,T6
TimeoutSt	154	Covered	T3,T6,T7

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	279	Covered	T11,T12,T13
IdleSt->Phase0St	147	Covered	T2,T5,T9
IdleSt->TimeoutSt	154	Covered	T3,T6,T7
Phase0St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	189	Covered	T17,T105,T106
Phase0St->Phase1St	193	Covered	T2,T5,T6
Phase1St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	206	Covered	T21,T107,T108
Phase1St->Phase2St	210	Covered	T2,T5,T6
Phase2St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	224	Covered	T25,T26,T109
Phase2St->Phase3St	228	Covered	T2,T5,T6
Phase3St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	240	Covered	T28,T110,T111
Phase3St->TerminalSt	244	Covered	T2,T5,T6
TerminalSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	256	Covered	T2,T5,T6
TimeoutSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	176	Covered	T3,T6,T7
TimeoutSt->Phase0St	167	Covered	T6,T7,T17

---

Branch Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	139	22	22	100.00
IF	278	2	2	100.00
IF	300	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	139	case (state_q)
-2-:	146	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	152	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	166	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	173	if (timeout_en_i)
-6-:	188	if (clr_i)
-7-:	192	if (cnt_ge)
-8-:	205	if (clr_i)
-9-:	209	if (cnt_ge)
-10-:	223	if (clr_i)
-11-:	227	if (cnt_ge)
-12-:	239	if (clr_i)
-13-:	243	if (cnt_ge)
-14-:	255	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T5,T9
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T6,T7
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T6,T7,T17
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T3,T6,T7
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T3,T6,T7
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T17,T105,T106
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T5,T6
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T5,T6
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T21,T107,T108
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T5,T6
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T5,T6
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T25,T26,T109
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T2,T5,T6
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T5,T6
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T28,T110,T106
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T2,T5,T6
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T5,T6
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T5,T6,T7
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T5,T6
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	278	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	300	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	619359372	266	0	0
CheckAccumTrig0_A	619359372	446	0	0
CheckAccumTrig1_A	619359372	16	0	0
CheckClr_A	619359372	190	0	0
CheckEn_A	619175232	286782615	0	0
CheckPhase0_A	619359372	498	0	0
CheckPhase1_A	619359372	491	0	0
CheckPhase2_A	619359372	481	0	0
CheckPhase3_A	619359372	473	0	0
CheckTimeout0_A	619359372	1248	0	0
CheckTimeoutSt1_A	619359372	123795	0	0
CheckTimeoutSt2_A	619359372	1189	0	0
CheckTimeoutStTrig_A	619359372	41	0	0
ErrorStAllEscAsserted_A	619359372	1425	0	0
ErrorStIsTerminal_A	619359372	1185	0	0
u_state_regs_A	619359372	619190096	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	619359372	266	0	0
T11	52069	36	0	0
T12	19097	36	0	0
T13	0	65	0	0
T24	155030	0	0	0
T29	0	59	0	0
T30	0	70	0	0
T31	71278	0	0	0
T32	43024	0	0	0
T33	31627	0	0	0
T34	19566	0	0	0
T35	112339	0	0	0
T36	176286	0	0	0
T37	430317	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	619359372	446	0	0
T2	131407	1	0	0
T3	17472	0	0	0
T4	313227	0	0	0
T5	231730	1	0	0
T6	245455	0	0	0
T7	57420	0	0	0
T8	49664	0	0	0
T9	34969	5	0	0
T10	251608	0	0	0
T18	0	1	0	0
T20	0	1	0	0
T24	0	1	0	0
T31	0	1	0	0
T35	0	1	0	0
T36	0	1	0	0
T38	109879	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	619359372	16	0	0
T17	35080	1	0	0
T25	134817	0	0	0
T45	0	1	0	0
T56	0	1	0	0
T59	687912	0	0	0
T60	137866	0	0	0
T61	28439	0	0	0
T62	26102	0	0	0
T63	462559	0	0	0
T81	19910	0	0	0
T103	0	1	0	0
T106	0	1	0	0
T108	0	2	0	0
T112	0	1	0	0
T113	0	1	0	0
T114	0	1	0	0
T115	0	1	0	0
T116	5098	0	0	0
T117	903480	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	619359372	190	0	0
T5	231730	1	0	0
T6	245455	1	0	0
T7	57420	1	0	0
T8	49664	0	0	0
T9	34969	4	0	0
T10	251608	0	0	0
T17	0	3	0	0
T18	799230	0	0	0
T19	143975	0	0	0
T21	0	1	0	0
T25	0	4	0	0
T35	0	1	0	0
T38	109879	0	0	0
T40	172971	0	0	0
T59	0	2	0	0
T72	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	619175232	286782615	0	0
T1	17184	17101	0	0
T2	131407	126160	0	0
T3	17472	4632	0	0
T4	313227	313221	0	0
T5	231730	231213	0	0
T6	245455	159959	0	0
T7	57420	27301	0	0
T8	49664	3021	0	0
T9	34969	590	0	0
T10	251608	251522	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	619359372	498	0	0
T2	131407	1	0	0
T3	17472	0	0	0
T4	313227	0	0	0
T5	231730	1	0	0
T6	245455	2	0	0
T7	57420	1	0	0
T8	49664	0	0	0
T9	34969	5	0	0
T10	251608	0	0	0
T18	0	1	0	0
T20	0	1	0	0
T31	0	1	0	0
T35	0	1	0	0
T38	109879	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	619359372	491	0	0
T2	131407	1	0	0
T3	17472	0	0	0
T4	313227	0	0	0
T5	231730	1	0	0
T6	245455	2	0	0
T7	57420	1	0	0
T8	49664	0	0	0
T9	34969	5	0	0
T10	251608	0	0	0
T18	0	1	0	0
T20	0	1	0	0
T31	0	1	0	0
T35	0	1	0	0
T38	109879	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	619359372	481	0	0
T2	131407	1	0	0
T3	17472	0	0	0
T4	313227	0	0	0
T5	231730	1	0	0
T6	245455	2	0	0
T7	57420	1	0	0
T8	49664	0	0	0
T9	34969	5	0	0
T10	251608	0	0	0
T18	0	1	0	0
T20	0	1	0	0
T31	0	1	0	0
T35	0	1	0	0
T38	109879	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	619359372	473	0	0
T2	131407	1	0	0
T3	17472	0	0	0
T4	313227	0	0	0
T5	231730	1	0	0
T6	245455	2	0	0
T7	57420	1	0	0
T8	49664	0	0	0
T9	34969	5	0	0
T10	251608	0	0	0
T18	0	1	0	0
T20	0	1	0	0
T31	0	1	0	0
T35	0	1	0	0
T38	109879	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	619359372	1248	0	0
T3	17472	3	0	0
T4	313227	0	0	0
T5	231730	0	0	0
T6	245455	13	0	0
T7	57420	2	0	0
T8	49664	4	0	0
T9	34969	0	0	0
T10	251608	0	0	0
T17	0	5	0	0
T18	799230	0	0	0
T21	0	10	0	0
T23	0	1	0	0
T38	109879	0	0	0
T59	0	1	0	0
T78	0	7	0	0
T80	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	619359372	123795	0	0
T3	17472	123	0	0
T4	313227	0	0	0
T5	231730	0	0	0
T6	245455	888	0	0
T7	57420	190	0	0
T8	49664	1137	0	0
T9	34969	0	0	0
T10	251608	0	0	0
T17	0	1662	0	0
T18	799230	0	0	0
T21	0	1836	0	0
T23	0	29	0	0
T38	109879	0	0	0
T59	0	71	0	0
T78	0	393	0	0
T80	0	93	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	619359372	1189	0	0
T3	17472	3	0	0
T4	313227	0	0	0
T5	231730	0	0	0
T6	245455	11	0	0
T7	57420	1	0	0
T8	49664	4	0	0
T9	34969	0	0	0
T10	251608	0	0	0
T17	0	3	0	0
T18	799230	0	0	0
T21	0	10	0	0
T23	0	1	0	0
T38	109879	0	0	0
T59	0	1	0	0
T78	0	7	0	0
T80	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	619359372	41	0	0
T6	245455	2	0	0
T7	57420	1	0	0
T8	49664	0	0	0
T9	34969	0	0	0
T10	251608	0	0	0
T17	0	1	0	0
T18	799230	0	0	0
T19	143975	0	0	0
T20	794620	0	0	0
T38	109879	0	0	0
T40	172971	0	0	0
T44	0	1	0	0
T84	0	2	0	0
T90	0	1	0	0
T92	0	1	0	0
T93	0	1	0	0
T94	0	1	0	0
T95	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	619359372	1425	0	0
T11	52069	161	0	0
T12	19097	177	0	0
T13	0	372	0	0
T24	155030	0	0	0
T29	0	340	0	0
T30	0	375	0	0
T31	71278	0	0	0
T32	43024	0	0	0
T33	31627	0	0	0
T34	19566	0	0	0
T35	112339	0	0	0
T36	176286	0	0	0
T37	430317	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	619359372	1185	0	0
T11	52069	131	0	0
T12	19097	147	0	0
T13	0	312	0	0
T24	155030	0	0	0
T29	0	280	0	0
T30	0	315	0	0
T31	71278	0	0	0
T32	43024	0	0	0
T33	31627	0	0	0
T34	19566	0	0	0
T35	112339	0	0	0
T36	176286	0	0	0
T37	430317	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	619359372	619190096	0	0
T1	17184	17102	0	0
T2	131407	131388	0	0
T3	17472	17394	0	0
T4	313227	313221	0	0
T5	231730	231723	0	0
T6	245455	245425	0	0
T7	57420	57342	0	0
T8	49664	49614	0	0
T9	34969	34918	0	0
T10	251608	251523	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	80	1	1	100.00
ALWAYS	129	89	89	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
ALWAYS	300	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
80	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
137	1	1
139	1	1
143	1	1
144	1	1
146	1	1
147	1	1
148	1	1
149	1	1
152	1	1
153	1	1
154	1	1
			MISSING_ELSE
164	1	1
166	1	1
167	1	1
168	1	1
169	1	1
170	1	1
173	1	1
174	1	1
176	1	1
177	1	1
182	1	1
183	1	1
184	1	1
185	1	1
186	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
195	1	1
			MISSING_ELSE
199	1	1
200	1	1
201	1	1
202	1	1
203	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
212	1	1
			MISSING_ELSE
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
229	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
			MISSING_ELSE
253	1	1
254	1	1
255	1	1
256	1	1
			MISSING_ELSE
263	1	1
264	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
287	4	4
290	4	4
300	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T3,T4,T5
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T4,T5

 LINE       146
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T3,T4,T5
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T4,T5,T6

 LINE       152
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T4,T6
1	0	1	Covered	T5,T6,T19
1	1	0	Covered	T2,T6,T7
1	1	1	Covered	T3,T6,T8

 LINE       166
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T3,T6,T8
0	1	Covered	T8,T72,T77
1	0	Covered	T17,T59,T118

 LINE       166
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T3,T6,T8
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T17,T59,T118

 LINE       166
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T6,T8
1	0	Not Covered
1	1	Covered	T8,T72,T77

 LINE       186
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T5,T6,T18
1	Covered	T4,T8,T19

 LINE       203
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T4,T5,T8
1	Covered	T6,T18,T20

 LINE       220
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T4,T6,T8
1	Covered	T5,T39,T27

 LINE       237
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T72,T119,T58

 LINE       278
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13

 LINE       290
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T5,T19,T20

 LINE       290
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T5,T18,T19

 LINE       290
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T6,T18,T20

 LINE       290
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T4,T5,T8

---

FSM Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	279	Covered	T11,T12,T13
IdleSt	176	Covered	T1,T2,T3
Phase0St	147	Covered	T4,T5,T6
Phase1St	193	Covered	T4,T5,T6
Phase2St	210	Covered	T4,T5,T6
Phase3St	228	Covered	T4,T5,T6
TerminalSt	244	Covered	T4,T5,T6
TimeoutSt	154	Covered	T3,T6,T8

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	279	Covered	T11,T12,T13
IdleSt->Phase0St	147	Covered	T4,T5,T6
IdleSt->TimeoutSt	154	Covered	T3,T6,T8
Phase0St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	189	Covered	T120,T121,T122
Phase0St->Phase1St	193	Covered	T4,T5,T6
Phase1St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	206	Covered	T103,T95,T106
Phase1St->Phase2St	210	Covered	T4,T5,T6
Phase2St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	224	Covered	T47,T123,T124
Phase2St->Phase3St	228	Covered	T4,T5,T6
Phase3St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	240	Covered	T125,T126,T121
Phase3St->TerminalSt	244	Covered	T4,T5,T6
TerminalSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	256	Covered	T4,T6,T21
TimeoutSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	176	Covered	T3,T6,T8
TimeoutSt->Phase0St	167	Covered	T8,T72,T77

---

Branch Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	139	22	22	100.00
IF	278	2	2	100.00
IF	300	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	139	case (state_q)
-2-:	146	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	152	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	166	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	173	if (timeout_en_i)
-6-:	188	if (clr_i)
-7-:	192	if (cnt_ge)
-8-:	205	if (clr_i)
-9-:	209	if (cnt_ge)
-10-:	223	if (clr_i)
-11-:	227	if (cnt_ge)
-12-:	239	if (clr_i)
-13-:	243	if (cnt_ge)
-14-:	255	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T6,T8
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T8,T72,T77
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T3,T6,T8
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T3,T6,T8
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T120,T121,T122
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T4,T5,T6
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T4,T5,T6
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T103,T95,T106
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T4,T5,T6
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T4,T5,T6
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T47,T123,T124
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T4,T5,T6
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T4,T5,T6
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T125,T126,T121
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T4,T5,T6
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T4,T5,T6
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T4,T23,T58
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T4,T5,T6
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	278	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	300	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	619359372	262	0	0
CheckAccumTrig0_A	619359372	452	0	0
CheckAccumTrig1_A	619359372	16	0	0
CheckClr_A	619359372	199	0	0
CheckEn_A	619175232	257103423	0	0
CheckPhase0_A	619359372	502	0	0
CheckPhase1_A	619359372	494	0	0
CheckPhase2_A	619359372	489	0	0
CheckPhase3_A	619359372	477	0	0
CheckTimeout0_A	619359372	891	0	0
CheckTimeoutSt1_A	619359372	88856	0	0
CheckTimeoutSt2_A	619359372	834	0	0
CheckTimeoutStTrig_A	619359372	41	0	0
ErrorStAllEscAsserted_A	619359372	1453	0	0
ErrorStIsTerminal_A	619359372	1213	0	0
u_state_regs_A	619359372	619190096	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	619359372	262	0	0
T11	52069	39	0	0
T12	19097	32	0	0
T13	0	57	0	0
T24	155030	0	0	0
T29	0	70	0	0
T30	0	64	0	0
T31	71278	0	0	0
T32	43024	0	0	0
T33	31627	0	0	0
T34	19566	0	0	0
T35	112339	0	0	0
T36	176286	0	0	0
T37	430317	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	619359372	452	0	0
T4	313227	2	0	0
T5	231730	1	0	0
T6	245455	1	0	0
T7	57420	0	0	0
T8	49664	0	0	0
T9	34969	0	0	0
T10	251608	0	0	0
T18	799230	1	0	0
T19	0	1	0	0
T20	0	1	0	0
T27	0	1	0	0
T35	0	1	0	0
T37	0	1	0	0
T38	109879	0	0	0
T39	0	1	0	0
T40	172971	0	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	619359372	16	0	0
T17	35080	1	0	0
T25	134817	0	0	0
T59	687912	1	0	0
T60	137866	0	0	0
T61	28439	0	0	0
T62	26102	0	0	0
T63	462559	0	0	0
T81	19910	0	0	0
T95	0	1	0	0
T114	0	1	0	0
T116	5098	0	0	0
T117	903480	0	0	0
T118	0	1	0	0
T127	0	1	0	0
T128	0	1	0	0
T129	0	1	0	0
T130	0	2	0	0
T131	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	619359372	199	0	0
T4	313227	1	0	0
T5	231730	0	0	0
T6	245455	0	0	0
T7	57420	0	0	0
T8	49664	0	0	0
T9	34969	0	0	0
T10	251608	0	0	0
T17	0	1	0	0
T18	799230	0	0	0
T23	0	3	0	0
T25	0	1	0	0
T38	109879	0	0	0
T40	172971	0	0	0
T43	0	1	0	0
T58	0	3	0	0
T59	0	1	0	0
T82	0	5	0	0
T117	0	1	0	0
T132	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	619175232	257103423	0	0
T1	17184	17101	0	0
T2	131407	131387	0	0
T3	17472	2369	0	0
T4	313227	31649	0	0
T5	231730	24171	0	0
T6	245455	147500	0	0
T7	57420	57341	0	0
T8	49664	3036	0	0
T9	34969	34917	0	0
T10	251608	246061	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	619359372	502	0	0
T4	313227	2	0	0
T5	231730	1	0	0
T6	245455	1	0	0
T7	57420	0	0	0
T8	49664	1	0	0
T9	34969	0	0	0
T10	251608	0	0	0
T18	799230	1	0	0
T19	0	1	0	0
T20	0	1	0	0
T35	0	1	0	0
T37	0	1	0	0
T38	109879	0	0	0
T40	172971	0	0	0
T72	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	619359372	494	0	0
T4	313227	2	0	0
T5	231730	1	0	0
T6	245455	1	0	0
T7	57420	0	0	0
T8	49664	1	0	0
T9	34969	0	0	0
T10	251608	0	0	0
T18	799230	1	0	0
T19	0	1	0	0
T20	0	1	0	0
T35	0	1	0	0
T37	0	1	0	0
T38	109879	0	0	0
T40	172971	0	0	0
T72	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	619359372	489	0	0
T4	313227	2	0	0
T5	231730	1	0	0
T6	245455	1	0	0
T7	57420	0	0	0
T8	49664	1	0	0
T9	34969	0	0	0
T10	251608	0	0	0
T18	799230	1	0	0
T19	0	1	0	0
T20	0	1	0	0
T35	0	1	0	0
T37	0	1	0	0
T38	109879	0	0	0
T40	172971	0	0	0
T72	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	619359372	477	0	0
T4	313227	2	0	0
T5	231730	1	0	0
T6	245455	1	0	0
T7	57420	0	0	0
T8	49664	1	0	0
T9	34969	0	0	0
T10	251608	0	0	0
T18	799230	1	0	0
T19	0	1	0	0
T20	0	1	0	0
T35	0	1	0	0
T37	0	1	0	0
T38	109879	0	0	0
T40	172971	0	0	0
T72	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	619359372	891	0	0
T3	17472	2	0	0
T4	313227	0	0	0
T5	231730	0	0	0
T6	245455	4	0	0
T7	57420	0	0	0
T8	49664	3	0	0
T9	34969	0	0	0
T10	251608	0	0	0
T17	0	2	0	0
T18	799230	0	0	0
T21	0	4	0	0
T23	0	2	0	0
T38	109879	0	0	0
T58	0	5	0	0
T72	0	1	0	0
T77	0	2	0	0
T80	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	619359372	88856	0	0
T3	17472	89	0	0
T4	313227	0	0	0
T5	231730	0	0	0
T6	245455	288	0	0
T7	57420	0	0	0
T8	49664	628	0	0
T9	34969	0	0	0
T10	251608	0	0	0
T17	0	20	0	0
T18	799230	0	0	0
T21	0	985	0	0
T23	0	35	0	0
T38	109879	0	0	0
T58	0	2691	0	0
T72	0	595	0	0
T77	0	61	0	0
T80	0	72	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	619359372	834	0	0
T3	17472	2	0	0
T4	313227	0	0	0
T5	231730	0	0	0
T6	245455	4	0	0
T7	57420	0	0	0
T8	49664	2	0	0
T9	34969	0	0	0
T10	251608	0	0	0
T17	0	1	0	0
T18	799230	0	0	0
T21	0	3	0	0
T23	0	2	0	0
T38	109879	0	0	0
T58	0	3	0	0
T59	0	134	0	0
T77	0	1	0	0
T80	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	619359372	41	0	0
T8	49664	1	0	0
T9	34969	0	0	0
T10	251608	0	0	0
T11	52069	0	0	0
T18	799230	0	0	0
T19	143975	0	0	0
T20	794620	0	0	0
T21	0	1	0	0
T28	0	1	0	0
T38	109879	0	0	0
T40	172971	0	0	0
T43	0	1	0	0
T44	0	1	0	0
T58	0	2	0	0
T59	0	1	0	0
T72	0	1	0	0
T77	0	1	0	0
T96	82586	0	0	0
T133	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	619359372	1453	0	0
T11	52069	191	0	0
T12	19097	181	0	0
T13	0	353	0	0
T24	155030	0	0	0
T29	0	378	0	0
T30	0	350	0	0
T31	71278	0	0	0
T32	43024	0	0	0
T33	31627	0	0	0
T34	19566	0	0	0
T35	112339	0	0	0
T36	176286	0	0	0
T37	430317	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	619359372	1213	0	0
T11	52069	161	0	0
T12	19097	151	0	0
T13	0	293	0	0
T24	155030	0	0	0
T29	0	318	0	0
T30	0	290	0	0
T31	71278	0	0	0
T32	43024	0	0	0
T33	31627	0	0	0
T34	19566	0	0	0
T35	112339	0	0	0
T36	176286	0	0	0
T37	430317	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	619359372	619190096	0	0
T1	17184	17102	0	0
T2	131407	131388	0	0
T3	17472	17394	0	0
T4	313227	313221	0	0
T5	231730	231723	0	0
T6	245455	245425	0	0
T7	57420	57342	0	0
T8	49664	49614	0	0
T9	34969	34918	0	0
T10	251608	251523	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	80	1	1	100.00
ALWAYS	129	89	89	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
ALWAYS	300	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
80	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
137	1	1
139	1	1
143	1	1
144	1	1
146	1	1
147	1	1
148	1	1
149	1	1
152	1	1
153	1	1
154	1	1
			MISSING_ELSE
164	1	1
166	1	1
167	1	1
168	1	1
169	1	1
170	1	1
173	1	1
174	1	1
176	1	1
177	1	1
182	1	1
183	1	1
184	1	1
185	1	1
186	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
195	1	1
			MISSING_ELSE
199	1	1
200	1	1
201	1	1
202	1	1
203	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
212	1	1
			MISSING_ELSE
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
229	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
			MISSING_ELSE
253	1	1
254	1	1
255	1	1
256	1	1
			MISSING_ELSE
263	1	1
264	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
287	4	4
290	4	4
300	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

 LINE       146
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T3,T4
1	0	1	Excluded		VC_COV_UNR
1	1	0	Covered	T14
1	1	1	Covered	T2,T4,T5

 LINE       152
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T4
1	0	1	Covered	T4,T5,T6
1	1	0	Covered	T3,T6,T7
1	1	1	Covered	T3,T6,T21

 LINE       166
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T3,T6,T21
0	1	Covered	T6,T21,T17
1	0	Covered	T48,T49,T50

 LINE       166
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T3,T6,T21
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T48,T49,T50

 LINE       166
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T6,T21
1	0	Not Covered
1	1	Covered	T6,T21,T17

 LINE       186
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T5,T6
1	Covered	T4,T5,T99

 LINE       203
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T5,T6

 LINE       220
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T18,T31,T35

 LINE       237
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T6,T20,T35

 LINE       278
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13

 LINE       290
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T4,T5,T6

 LINE       290
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T4,T5

 LINE       290
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T4,T5

 LINE       290
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T5,T18

---

FSM Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	279	Covered	T11,T12,T13
IdleSt	176	Covered	T1,T2,T3
Phase0St	147	Covered	T2,T4,T5
Phase1St	193	Covered	T2,T4,T5
Phase2St	210	Covered	T2,T4,T5
Phase3St	228	Covered	T2,T4,T5
TerminalSt	244	Covered	T2,T4,T5
TimeoutSt	154	Covered	T3,T6,T21

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	279	Covered	T11,T12,T13
IdleSt->Phase0St	147	Covered	T2,T4,T5
IdleSt->TimeoutSt	154	Covered	T3,T6,T21
Phase0St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	189	Covered	T21,T22,T74
Phase0St->Phase1St	193	Covered	T2,T4,T5
Phase1St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	206	Covered	T74,T76,T110
Phase1St->Phase2St	210	Covered	T2,T4,T5
Phase2St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	224	Covered	T25,T93,T107
Phase2St->Phase3St	228	Covered	T2,T4,T5
Phase3St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	240	Covered	T28,T109,T106
Phase3St->TerminalSt	244	Covered	T2,T4,T5
TerminalSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	256	Covered	T2,T5,T6
TimeoutSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	176	Covered	T3,T6,T21
TimeoutSt->Phase0St	167	Covered	T6,T21,T17

---

Branch Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	139	22	22	100.00
IF	278	2	2	100.00
IF	300	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	139	case (state_q)
-2-:	146	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	152	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	166	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	173	if (timeout_en_i)
-6-:	188	if (clr_i)
-7-:	192	if (cnt_ge)
-8-:	205	if (clr_i)
-9-:	209	if (cnt_ge)
-10-:	223	if (clr_i)
-11-:	227	if (cnt_ge)
-12-:	239	if (clr_i)
-13-:	243	if (cnt_ge)
-14-:	255	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T5
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T6,T21
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T6,T21,T17
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T3,T6,T21
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T3,T6,T21
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T21,T22,T74
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T4,T5
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T4,T5
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T74,T76,T110
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T4,T5
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T4,T5
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T25,T93,T107
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T2,T4,T5
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T4,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T28,T109,T106
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T2,T4,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T4,T5
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T5,T35,T37
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T4,T5
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	278	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	300	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	619359372	313	0	0
CheckAccumTrig0_A	619359372	435	0	0
CheckAccumTrig1_A	619359372	14	0	0
CheckClr_A	619359372	205	0	0
CheckEn_A	619175232	296230592	0	0
CheckPhase0_A	619359372	480	0	0
CheckPhase1_A	619359372	470	0	0
CheckPhase2_A	619359372	458	0	0
CheckPhase3_A	619359372	448	0	0
CheckTimeout0_A	619359372	375	0	0
CheckTimeoutSt1_A	619359372	49086	0	0
CheckTimeoutSt2_A	619359372	314	0	0
CheckTimeoutStTrig_A	619359372	47	0	0
ErrorStAllEscAsserted_A	619359372	1467	0	0
ErrorStIsTerminal_A	619359372	1227	0	0
u_state_regs_A	619359372	619190096	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	619359372	313	0	0
T11	52069	42	0	0
T12	19097	47	0	0
T13	0	60	0	0
T24	155030	0	0	0
T29	0	78	0	0
T30	0	86	0	0
T31	71278	0	0	0
T32	43024	0	0	0
T33	31627	0	0	0
T34	19566	0	0	0
T35	112339	0	0	0
T36	176286	0	0	0
T37	430317	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	619359372	435	0	0
T2	131407	1	0	0
T3	17472	0	0	0
T4	313227	1	0	0
T5	231730	2	0	0
T6	245455	1	0	0
T7	57420	0	0	0
T8	49664	0	0	0
T9	34969	0	0	0
T10	251608	0	0	0
T18	0	1	0	0
T19	0	1	0	0
T20	0	1	0	0
T31	0	1	0	0
T35	0	2	0	0
T37	0	2	0	0
T38	109879	0	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	619359372	14	0	0
T48	156574	1	0	0
T49	301296	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T52	0	2	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T64	42943	0	0	0
T65	31764	0	0	0
T66	106443	0	0	0
T67	28134	0	0	0
T68	149945	0	0	0
T69	20698	0	0	0
T70	41434	0	0	0
T71	11642	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	619359372	205	0	0
T5	231730	1	0	0
T6	245455	0	0	0
T7	57420	0	0	0
T8	49664	0	0	0
T9	34969	0	0	0
T10	251608	0	0	0
T17	0	1	0	0
T18	799230	0	0	0
T19	143975	0	0	0
T21	0	5	0	0
T22	0	2	0	0
T25	0	8	0	0
T35	0	1	0	0
T37	0	1	0	0
T38	109879	0	0	0
T40	172971	0	0	0
T74	0	4	0	0
T75	0	1	0	0
T76	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	619175232	296230592	0	0
T1	17184	17101	0	0
T2	131407	126402	0	0
T3	17472	2357	0	0
T4	313227	15297	0	0
T5	231730	16700	0	0
T6	245455	176888	0	0
T7	57420	57341	0	0
T8	49664	49613	0	0
T9	34969	31801	0	0
T10	251608	236370	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	619359372	480	0	0
T2	131407	1	0	0
T3	17472	0	0	0
T4	313227	1	0	0
T5	231730	2	0	0
T6	245455	2	0	0
T7	57420	0	0	0
T8	49664	0	0	0
T9	34969	0	0	0
T10	251608	0	0	0
T18	0	1	0	0
T19	0	1	0	0
T20	0	1	0	0
T31	0	1	0	0
T35	0	2	0	0
T37	0	2	0	0
T38	109879	0	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	619359372	470	0	0
T2	131407	1	0	0
T3	17472	0	0	0
T4	313227	1	0	0
T5	231730	2	0	0
T6	245455	2	0	0
T7	57420	0	0	0
T8	49664	0	0	0
T9	34969	0	0	0
T10	251608	0	0	0
T18	0	1	0	0
T19	0	1	0	0
T20	0	1	0	0
T31	0	1	0	0
T35	0	2	0	0
T37	0	2	0	0
T38	109879	0	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	619359372	458	0	0
T2	131407	1	0	0
T3	17472	0	0	0
T4	313227	1	0	0
T5	231730	2	0	0
T6	245455	2	0	0
T7	57420	0	0	0
T8	49664	0	0	0
T9	34969	0	0	0
T10	251608	0	0	0
T18	0	1	0	0
T19	0	1	0	0
T20	0	1	0	0
T31	0	1	0	0
T35	0	2	0	0
T37	0	2	0	0
T38	109879	0	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	619359372	448	0	0
T2	131407	1	0	0
T3	17472	0	0	0
T4	313227	1	0	0
T5	231730	2	0	0
T6	245455	2	0	0
T7	57420	0	0	0
T8	49664	0	0	0
T9	34969	0	0	0
T10	251608	0	0	0
T18	0	1	0	0
T19	0	1	0	0
T20	0	1	0	0
T31	0	1	0	0
T35	0	2	0	0
T37	0	2	0	0
T38	109879	0	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	619359372	375	0	0
T3	17472	4	0	0
T4	313227	0	0	0
T5	231730	0	0	0
T6	245455	2	0	0
T7	57420	0	0	0
T8	49664	0	0	0
T9	34969	0	0	0
T10	251608	0	0	0
T17	0	3	0	0
T18	799230	0	0	0
T21	0	2	0	0
T38	109879	0	0	0
T59	0	4	0	0
T74	0	2	0	0
T81	0	2	0	0
T82	0	2	0	0
T83	0	1	0	0
T84	0	2	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	619359372	49086	0	0
T3	17472	194	0	0
T4	313227	0	0	0
T5	231730	0	0	0
T6	245455	153	0	0
T7	57420	0	0	0
T8	49664	0	0	0
T9	34969	0	0	0
T10	251608	0	0	0
T17	0	1873	0	0
T18	799230	0	0	0
T21	0	337	0	0
T38	109879	0	0	0
T59	0	294	0	0
T74	0	169	0	0
T81	0	109	0	0
T82	0	103	0	0
T83	0	87	0	0
T84	0	385	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	619359372	314	0	0
T3	17472	4	0	0
T4	313227	0	0	0
T5	231730	0	0	0
T6	245455	1	0	0
T7	57420	0	0	0
T8	49664	0	0	0
T9	34969	0	0	0
T10	251608	0	0	0
T17	0	2	0	0
T18	799230	0	0	0
T21	0	1	0	0
T38	109879	0	0	0
T59	0	4	0	0
T74	0	2	0	0
T81	0	2	0	0
T82	0	2	0	0
T83	0	1	0	0
T84	0	2	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	619359372	47	0	0
T6	245455	1	0	0
T7	57420	0	0	0
T8	49664	0	0	0
T9	34969	0	0	0
T10	251608	0	0	0
T17	0	1	0	0
T18	799230	0	0	0
T19	143975	0	0	0
T20	794620	0	0	0
T21	0	1	0	0
T28	0	1	0	0
T38	109879	0	0	0
T40	172971	0	0	0
T44	0	1	0	0
T87	0	1	0	0
T88	0	1	0	0
T89	0	1	0	0
T90	0	2	0	0
T91	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	619359372	1467	0	0
T11	52069	176	0	0
T12	19097	187	0	0
T13	0	383	0	0
T24	155030	0	0	0
T29	0	339	0	0
T30	0	382	0	0
T31	71278	0	0	0
T32	43024	0	0	0
T33	31627	0	0	0
T34	19566	0	0	0
T35	112339	0	0	0
T36	176286	0	0	0
T37	430317	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	619359372	1227	0	0
T11	52069	146	0	0
T12	19097	157	0	0
T13	0	323	0	0
T24	155030	0	0	0
T29	0	279	0	0
T30	0	322	0	0
T31	71278	0	0	0
T32	43024	0	0	0
T33	31627	0	0	0
T34	19566	0	0	0
T35	112339	0	0	0
T36	176286	0	0	0
T37	430317	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	619359372	619190096	0	0
T1	17184	17102	0	0
T2	131407	131388	0	0
T3	17472	17394	0	0
T4	313227	313221	0	0
T5	231730	231723	0	0
T6	245455	245425	0	0
T7	57420	57342	0	0
T8	49664	49614	0	0
T9	34969	34918	0	0
T10	251608	251523	0	0