Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
esc_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	8	0	8	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	76900	1			T5	3		T7	14		T26	491
class_i[0x1]	58350	1			T5	1		T49	7		T16	3523
class_i[0x2]	54045	1			T20	18		T5	2		T7	18
class_i[0x3]	58309	1			T7	2796		T49	18		T69	39

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Summary for Variable esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	60896	1			T20	5		T5	3		T7	735
alert[0x1]	61528	1			T20	2		T5	2		T7	700
alert[0x2]	64536	1			T20	11		T5	1		T7	681
alert[0x3]	60644	1			T7	712		T49	15		T26	142

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Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

esc_integrity_fail

247327

1

T20

18

T7

2828

T49

30

esc_ping_fail

277

1

T5

6

T8

7

T9

8

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Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	esc_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	alert[0x0]	60811	1			T20	5		T7	735		T49	4
esc_integrity_fail	alert[0x1]	61463	1			T20	2		T7	700		T49	6
esc_integrity_fail	alert[0x2]	64471	1			T20	11		T7	681		T49	5
esc_integrity_fail	alert[0x3]	60582	1			T7	712		T49	15		T26	142
esc_ping_fail	alert[0x0]	85	1			T5	3		T8	2		T9	2
esc_ping_fail	alert[0x1]	65	1			T5	2		T8	1		T289	2
esc_ping_fail	alert[0x2]	65	1			T5	1		T8	4		T9	3
esc_ping_fail	alert[0x3]	62	1			T9	3		T289	1		T94	1

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Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	class_i[0x0]	76845	1			T7	14		T26	491		T27	642
esc_integrity_fail	class_i[0x1]	58273	1			T49	7		T16	3523		T51	1
esc_integrity_fail	class_i[0x2]	53951	1			T20	18		T7	18		T49	5
esc_integrity_fail	class_i[0x3]	58258	1			T7	2796		T49	18		T69	39
esc_ping_fail	class_i[0x0]	55	1			T5	3		T8	7		T289	7
esc_ping_fail	class_i[0x1]	77	1			T5	1		T9	1		T93	2
esc_ping_fail	class_i[0x2]	94	1			T5	2		T9	6		T94	2
esc_ping_fail	class_i[0x3]	51	1			T9	1		T290	3		T311	1