Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_edn_req.u_prim_packer_fifo.DataOStableWhenPending_A	0	0	662815529	0	0	626
tb.dut.u_edn_req.u_prim_packer_fifo.ValidOPairedWithReadyI_A	0	0	662815529	0	0	0

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.AckPKnownO_A	0	0	662815529	662627033	0	0
tb.dut.CheckAccuCntDw	0	0	626	626	0	0
tb.dut.CheckEscCntDw	0	0	626	626	0	0
tb.dut.CheckNAlerts	0	0	626	626	0	0
tb.dut.CheckNClasses	0	0	626	626	0	0
tb.dut.CheckNEscSev	0	0	626	626	0	0
tb.dut.CrashdumpKnownO_A	0	0	662815529	662627033	0	0
tb.dut.EdnKnownO_A	0	0	662815529	662627033	0	0
tb.dut.EscPKnownO_A	0	0	662815529	662627033	0	0
tb.dut.FpvSecCmPingTimerCnterCheck_A	0	0	662815529	90	0	0
tb.dut.FpvSecCmPingTimerDoubleLfsrCheck_A	0	0	662815529	90	0	0
tb.dut.FpvSecCmPingTimerEscCnterCheck_A	0	0	662815529	90	0	0
tb.dut.FpvSecCmPingTimerFsmCheck_A	0	0	662815529	90	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	662815529	90	0	0
tb.dut.IrqAKnownO_A	0	0	662815529	662627033	0	0
tb.dut.IrqBKnownO_A	0	0	662815529	662627033	0	0
tb.dut.IrqCKnownO_A	0	0	662815529	662627033	0	0
tb.dut.IrqDKnownO_A	0	0	662815529	662627033	0	0
tb.dut.TlAReadyKnownO_A	0	0	662815529	662627033	0	0
tb.dut.TlDValidKnownO_A	0	0	662815529	662627033	0	0
tb.dut.alert_handler_csr_assert.TlulOOBAddrErr_A	0	0	688496290	3110495	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_0_rd_A	0	0	688496290	10223	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_10_rd_A	0	0	688496290	11878	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_11_rd_A	0	0	688496290	12186	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_12_rd_A	0	0	688496290	11562	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_13_rd_A	0	0	688496290	10312	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_14_rd_A	0	0	688496290	11758	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_15_rd_A	0	0	688496290	11496	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_16_rd_A	0	0	688496290	10914	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_17_rd_A	0	0	688496290	10908	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_18_rd_A	0	0	688496290	10770	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_19_rd_A	0	0	688496290	12632	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_1_rd_A	0	0	688496290	11391	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_20_rd_A	0	0	688496290	12012	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_21_rd_A	0	0	688496290	11309	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_22_rd_A	0	0	688496290	11514	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_23_rd_A	0	0	688496290	10203	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_24_rd_A	0	0	688496290	11678	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_25_rd_A	0	0	688496290	10365	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_26_rd_A	0	0	688496290	10395	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_27_rd_A	0	0	688496290	11557	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_28_rd_A	0	0	688496290	11901	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_29_rd_A	0	0	688496290	12150	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_2_rd_A	0	0	688496290	10234	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_30_rd_A	0	0	688496290	10994	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_31_rd_A	0	0	688496290	10443	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_32_rd_A	0	0	688496290	11374	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_33_rd_A	0	0	688496290	10185	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_34_rd_A	0	0	688496290	11391	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_35_rd_A	0	0	688496290	12080	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_36_rd_A	0	0	688496290	11688	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_37_rd_A	0	0	688496290	11669	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_38_rd_A	0	0	688496290	13368	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_39_rd_A	0	0	688496290	11683	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_3_rd_A	0	0	688496290	11484	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_40_rd_A	0	0	688496290	13344	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_41_rd_A	0	0	688496290	10227	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_42_rd_A	0	0	688496290	11280	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_43_rd_A	0	0	688496290	10247	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_44_rd_A	0	0	688496290	12130	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_45_rd_A	0	0	688496290	10728	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_46_rd_A	0	0	688496290	13877	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_47_rd_A	0	0	688496290	10797	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_48_rd_A	0	0	688496290	11039	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_49_rd_A	0	0	688496290	11084	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_4_rd_A	0	0	688496290	11073	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_50_rd_A	0	0	688496290	11063	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_51_rd_A	0	0	688496290	11123	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_52_rd_A	0	0	688496290	11015	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_53_rd_A	0	0	688496290	12264	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_54_rd_A	0	0	688496290	11002	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_55_rd_A	0	0	688496290	10809	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_56_rd_A	0	0	688496290	11763	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_57_rd_A	0	0	688496290	11030	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_58_rd_A	0	0	688496290	11216	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_59_rd_A	0	0	688496290	12241	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_5_rd_A	0	0	688496290	10520	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_60_rd_A	0	0	688496290	13060	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_61_rd_A	0	0	688496290	13357	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_62_rd_A	0	0	688496290	10352	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_63_rd_A	0	0	688496290	13300	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_64_rd_A	0	0	688496290	10717	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_6_rd_A	0	0	688496290	11006	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_7_rd_A	0	0	688496290	11421	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_8_rd_A	0	0	688496290	11408	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_9_rd_A	0	0	688496290	11284	0	0
tb.dut.alert_handler_csr_assert.classa_regwen_rd_A	0	0	688496290	12274	0	0
tb.dut.alert_handler_csr_assert.classb_regwen_rd_A	0	0	688496290	9989	0	0
tb.dut.alert_handler_csr_assert.classc_regwen_rd_A	0	0	688496290	11668	0	0
tb.dut.alert_handler_csr_assert.classd_regwen_rd_A	0	0	688496290	11512	0	0
tb.dut.alert_handler_csr_assert.intr_enable_rd_A	0	0	688496290	20229	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_0_rd_A	0	0	688496290	10975	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_1_rd_A	0	0	688496290	10548	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_2_rd_A	0	0	688496290	11202	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_3_rd_A	0	0	688496290	11601	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_4_rd_A	0	0	688496290	10654	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_5_rd_A	0	0	688496290	12504	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_6_rd_A	0	0	688496290	11425	0	0
tb.dut.alert_handler_csr_assert.ping_timer_regwen_rd_A	0	0	688496290	12831	0	0
tb.dut.gen_classes[0].FpvSecCmAccuCnterCheck_A	0	0	662815529	90	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerCnterCheck_A	0	0	662815529	90	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerFsmCheck_A	0	0	662815529	90	0	0
tb.dut.gen_classes[0].u_accu.CountSaturateStable_A	0	0	662815529	508	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigBkwd_A	0	0	662815529	207912	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigFwd_A	0	0	662815529	362968503	0	0
tb.dut.gen_classes[0].u_esc_timer.AccuFailToFsmError_A	0	0	662815529	343	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig0_A	0	0	662815529	852	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig1_A	0	0	662815529	54	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckClr_A	0	0	662815529	441	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckEn_A	0	0	662568162	254670184	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase0_A	0	0	662815529	950	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase1_A	0	0	662815529	924	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase2_A	0	0	662815529	905	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase3_A	0	0	662815529	876	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeout0_A	0	0	662815529	707	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt1_A	0	0	662815529	90895	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt2_A	0	0	662815529	574	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutStTrig_A	0	0	662815529	78	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStAllEscAsserted_A	0	0	662815529	1664	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStIsTerminal_A	0	0	662815529	1394	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs.AssertConnected_A	0	0	626	626	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs_A	0	0	662815529	662627033	0	0
tb.dut.gen_classes[1].FpvSecCmAccuCnterCheck_A	0	0	662815529	90	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerCnterCheck_A	0	0	662815529	90	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerFsmCheck_A	0	0	662815529	90	0	0
tb.dut.gen_classes[1].u_accu.CountSaturateStable_A	0	0	662815529	4650	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigBkwd_A	0	0	662815529	169024	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigFwd_A	0	0	662815529	388031252	0	0
tb.dut.gen_classes[1].u_esc_timer.AccuFailToFsmError_A	0	0	662815529	282	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig0_A	0	0	662815529	484	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig1_A	0	0	662815529	31	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckClr_A	0	0	662815529	216	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckEn_A	0	0	662568162	291731051	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase0_A	0	0	662815529	575	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase1_A	0	0	662815529	560	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase2_A	0	0	662815529	553	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase3_A	0	0	662815529	546	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeout0_A	0	0	662815529	679	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt1_A	0	0	662815529	92068	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt2_A	0	0	662815529	579	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutStTrig_A	0	0	662815529	68	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStAllEscAsserted_A	0	0	662815529	1581	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStIsTerminal_A	0	0	662815529	1311	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs.AssertConnected_A	0	0	626	626	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs_A	0	0	662815529	662627033	0	0
tb.dut.gen_classes[2].FpvSecCmAccuCnterCheck_A	0	0	662815529	90	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerCnterCheck_A	0	0	662815529	90	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerFsmCheck_A	0	0	662815529	90	0	0
tb.dut.gen_classes[2].u_accu.CountSaturateStable_A	0	0	662815529	5449	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigBkwd_A	0	0	662815529	183002	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigFwd_A	0	0	662815529	370122959	0	0
tb.dut.gen_classes[2].u_esc_timer.AccuFailToFsmError_A	0	0	662815529	339	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig0_A	0	0	662815529	487	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig1_A	0	0	662815529	29	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckClr_A	0	0	662815529	201	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckEn_A	0	0	662568162	291288264	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase0_A	0	0	662815529	558	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase1_A	0	0	662815529	550	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase2_A	0	0	662815529	544	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase3_A	0	0	662815529	539	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeout0_A	0	0	662815529	759	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt1_A	0	0	662815529	97251	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt2_A	0	0	662815529	675	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutStTrig_A	0	0	662815529	53	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStAllEscAsserted_A	0	0	662815529	1623	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStIsTerminal_A	0	0	662815529	1353	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs.AssertConnected_A	0	0	626	626	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs_A	0	0	662815529	662627033	0	0
tb.dut.gen_classes[3].FpvSecCmAccuCnterCheck_A	0	0	662815529	90	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerCnterCheck_A	0	0	662815529	90	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerFsmCheck_A	0	0	662815529	90	0	0
tb.dut.gen_classes[3].u_accu.CountSaturateStable_A	0	0	662815529	3265	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigBkwd_A	0	0	662815529	178373	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigFwd_A	0	0	662815529	415234297	0	0
tb.dut.gen_classes[3].u_esc_timer.AccuFailToFsmError_A	0	0	662815529	298	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig0_A	0	0	662815529	459	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig1_A	0	0	662815529	26	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckClr_A	0	0	662815529	201	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckEn_A	0	0	662568162	324501606	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase0_A	0	0	662815529	549	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase1_A	0	0	662815529	542	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase2_A	0	0	662815529	528	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase3_A	0	0	662815529	517	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeout0_A	0	0	662815529	889	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt1_A	0	0	662815529	106252	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt2_A	0	0	662815529	791	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutStTrig_A	0	0	662815529	72	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStAllEscAsserted_A	0	0	662815529	1622	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStIsTerminal_A	0	0	662815529	1352	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs.AssertConnected_A	0	0	626	626	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs_A	0	0	662815529	662627033	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	688496290	133671158	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	688496290	687783414	0	0
tb.dut.tlul_assert_device.aReadyKnown_A	0	0	688496290	687783414	0	0
tb.dut.tlul_assert_device.dKnown_A	0	0	688496290	188213844	0	0
tb.dut.tlul_assert_device.dKnown_AKnownEnable	0	0	688496290	687783414	0	0
tb.dut.tlul_assert_device.dReadyKnown_A	0	0	688496290	687783414	0	0
tb.dut.tlul_assert_device.gen_assert_final[0].noOutstandingReqsAtEndOfSim_A	0	0	831	831	0	0
tb.dut.tlul_assert_device.gen_assert_final[100].noOutstandingReqsAtEndOfSim_A	0	0	831	831	0	0
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