Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.15	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	40	1	39	97.50

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
intr_timeout_cnt_cp	10	0	10	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	40	1	39	97.50	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	78	1			T23	1		T26	1		T27	1
class_index[0x1]	68	1			T24	2		T55	2		T81	2
class_index[0x2]	53	1			T23	1		T27	2		T52	1
class_index[0x3]	72	1			T23	1		T32	1		T27	2

---

Summary for Variable intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for intr_timeout_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
intr_timeout_cnt[0]	108	1			T32	1		T27	3		T69	2
intr_timeout_cnt[1]	64	1			T23	3		T26	1		T27	1
intr_timeout_cnt[2]	26	1			T27	1		T24	1		T86	1
intr_timeout_cnt[3]	14	1			T81	1		T85	1		T249	1
intr_timeout_cnt[4]	15	1			T52	1		T78	1		T81	2
intr_timeout_cnt[5]	16	1			T69	1		T42	1		T86	1
intr_timeout_cnt[6]	6	1			T24	1		T231	1		T268	1
intr_timeout_cnt[7]	6	1			T260	1		T122	1		T269	1
intr_timeout_cnt[8]	6	1			T52	1		T24	1		T30	1
intr_timeout_cnt[9]	10	1			T24	2		T55	1		T81	1

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	1	39	97.50	1

Automatically Generated Cross Bins for class_cnt_cross

Uncovered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	NUMBER	STATUS
[class_index[0x2]]	[intr_timeout_cnt[6]]	0	1	1

Covered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	intr_timeout_cnt[0]	42	1			T27	1		T80	1		T45	1
class_index[0x0]	intr_timeout_cnt[1]	10	1			T23	1		T26	1		T79	2
class_index[0x0]	intr_timeout_cnt[2]	8	1			T86	1		T270	1		T259	1
class_index[0x0]	intr_timeout_cnt[3]	2	1			T233	1		T271	1		-	-
class_index[0x0]	intr_timeout_cnt[4]	5	1			T78	1		T81	1		T260	1
class_index[0x0]	intr_timeout_cnt[5]	5	1			T69	1		T272	1		T249	1
class_index[0x0]	intr_timeout_cnt[6]	1	1			T231	1		-	-		-	-
class_index[0x0]	intr_timeout_cnt[7]	2	1			T269	1		T273	1		-	-
class_index[0x0]	intr_timeout_cnt[8]	2	1			T24	1		T274	1		-	-
class_index[0x0]	intr_timeout_cnt[9]	1	1			T24	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[0]	25	1			T24	1		T82	1		T44	1
class_index[0x1]	intr_timeout_cnt[1]	17	1			T55	2		T81	1		T44	1
class_index[0x1]	intr_timeout_cnt[2]	5	1			T97	1		T122	1		T249	1
class_index[0x1]	intr_timeout_cnt[3]	3	1			T85	1		T275	1		T116	1
class_index[0x1]	intr_timeout_cnt[4]	3	1			T233	1		T25	1		T274	1
class_index[0x1]	intr_timeout_cnt[5]	6	1			T42	1		T276	1		T277	2
class_index[0x1]	intr_timeout_cnt[6]	4	1			T24	1		T268	1		T278	1
class_index[0x1]	intr_timeout_cnt[7]	1	1			T260	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[8]	1	1			T241	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[9]	3	1			T81	1		T260	1		T279	1
class_index[0x2]	intr_timeout_cnt[0]	18	1			T69	1		T280	1		T281	1
class_index[0x2]	intr_timeout_cnt[1]	15	1			T23	1		T27	1		T262	1
class_index[0x2]	intr_timeout_cnt[2]	5	1			T27	1		T269	1		T249	1
class_index[0x2]	intr_timeout_cnt[3]	3	1			T81	1		T233	1		T282	1
class_index[0x2]	intr_timeout_cnt[4]	4	1			T52	1		T40	1		T97	1
class_index[0x2]	intr_timeout_cnt[5]	2	1			T86	1		T283	1		-	-
class_index[0x2]	intr_timeout_cnt[7]	2	1			T122	1		T277	1		-	-
class_index[0x2]	intr_timeout_cnt[8]	1	1			T30	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[9]	3	1			T24	1		T40	1		T249	1
class_index[0x3]	intr_timeout_cnt[0]	23	1			T32	1		T27	2		T69	1
class_index[0x3]	intr_timeout_cnt[1]	22	1			T23	1		T35	1		T81	1
class_index[0x3]	intr_timeout_cnt[2]	8	1			T24	1		T261	1		T259	3
class_index[0x3]	intr_timeout_cnt[3]	6	1			T249	1		T284	1		T116	1
class_index[0x3]	intr_timeout_cnt[4]	3	1			T81	1		T276	1		T274	1
class_index[0x3]	intr_timeout_cnt[5]	3	1			T120	1		T268	1		T274	1
class_index[0x3]	intr_timeout_cnt[6]	1	1			T285	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[7]	1	1			T283	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[8]	2	1			T52	1		T286	1		-	-
class_index[0x3]	intr_timeout_cnt[9]	3	1			T55	1		T269	1		T243	1