Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	346421	1			T1	1533		T2	332		T3	169
all_values[1]	346421	1			T1	1533		T2	332		T3	169
all_values[2]	346421	1			T1	1533		T2	332		T3	169
all_values[3]	346421	1			T1	1533		T2	332		T3	169

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

688902

1

T1

3048

T2

620

T3

325

auto[1]

696782

1

T1

3084

T2

708

T3

351

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

840886

1

T1

3095

T2

896

T3

344

auto[1]

544798

1

T1

3037

T2

432

T3

332

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	100133	1			T1	355		T2	87		T3	38
all_values[0]	auto[0]	auto[1]	71913	1			T1	355		T2	60		T3	37
all_values[0]	auto[1]	auto[0]	102124	1			T1	412		T2	104		T3	47
all_values[0]	auto[1]	auto[1]	72251	1			T1	411		T2	81		T3	47
all_values[1]	auto[0]	auto[0]	106635	1			T1	407		T2	119		T3	40
all_values[1]	auto[0]	auto[1]	66053	1			T1	377		T2	49		T3	37
all_values[1]	auto[1]	auto[0]	107492	1			T1	383		T2	114		T3	47
all_values[1]	auto[1]	auto[1]	66241	1			T1	366		T2	50		T3	45
all_values[2]	auto[0]	auto[0]	104575	1			T1	387		T2	113		T3	49
all_values[2]	auto[0]	auto[1]	67368	1			T1	381		T2	44		T3	48
all_values[2]	auto[1]	auto[0]	106268	1			T1	384		T2	126		T3	36
all_values[2]	auto[1]	auto[1]	68210	1			T1	381		T2	49		T3	36
all_values[3]	auto[0]	auto[0]	105976	1			T1	393		T2	101		T3	39
all_values[3]	auto[0]	auto[1]	66249	1			T1	393		T2	47		T3	37
all_values[3]	auto[1]	auto[0]	107683	1			T1	374		T2	132		T3	48
all_values[3]	auto[1]	auto[1]	66513	1			T1	373		T2	52		T3	45