Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	4	0	4	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	346421	1			T1	1533		T2	332		T3	169
all_pins[1]	346421	1			T1	1533		T2	332		T3	169
all_pins[2]	346421	1			T1	1533		T2	332		T3	169
all_pins[3]	346421	1			T1	1533		T2	332		T3	169

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1112469	1			T1	4601		T2	1096		T3	503
values[0x1]	273215	1			T1	1531		T2	232		T3	173
transitions[0x0=>0x1]	183223	1			T1	950		T2	154		T3	108
transitions[0x1=>0x0]	183471	1			T1	950		T2	155		T3	109

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	274170	1			T1	1122		T2	251		T3	122
all_pins[0]	values[0x1]	72251	1			T1	411		T2	81		T3	47
all_pins[0]	transitions[0x0=>0x1]	71574	1			T1	411		T2	80		T3	46
all_pins[0]	transitions[0x1=>0x0]	66084	1			T1	373		T2	52		T3	45
all_pins[1]	values[0x0]	280180	1			T1	1167		T2	282		T3	124
all_pins[1]	values[0x1]	66241	1			T1	366		T2	50		T3	45
all_pins[1]	transitions[0x0=>0x1]	36698	1			T1	162		T2	22		T3	20
all_pins[1]	transitions[0x1=>0x0]	42708	1			T1	207		T2	53		T3	22
all_pins[2]	values[0x0]	278211	1			T1	1152		T2	283		T3	133
all_pins[2]	values[0x1]	68210	1			T1	381		T2	49		T3	36
all_pins[2]	transitions[0x0=>0x1]	38365	1			T1	202		T2	24		T3	17
all_pins[2]	transitions[0x1=>0x0]	36396	1			T1	187		T2	25		T3	26
all_pins[3]	values[0x0]	279908	1			T1	1160		T2	280		T3	124
all_pins[3]	values[0x1]	66513	1			T1	373		T2	52		T3	45
all_pins[3]	transitions[0x0=>0x1]	36586	1			T1	175		T2	28		T3	25
all_pins[3]	transitions[0x1=>0x0]	38283	1			T1	183		T2	25		T3	16