Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
accum_cnt_cp	6	0	6	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	24	0	24	100.00	100	1	1	0

Summary for Variable accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for accum_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
accum_cnt_2000	75913	1			T1	533		T7	252		T6	296
accum_cnt_1000	207308	1			T1	543		T2	122		T3	37
accum_cnt_100	24531	1			T1	27		T2	50		T3	27
accum_cnt_50	81146	1			T1	1152		T2	56		T3	17
accum_cnt_10	177334	1			T1	27		T2	40		T3	168
accum_cnt_0	420621	1			T1	2294		T2	516		T3	87

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Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	255641	1			T1	1144		T2	196		T3	84
class_index[0x1]	255641	1			T1	1144		T2	196		T3	84
class_index[0x2]	255641	1			T1	1144		T2	196		T3	84
class_index[0x3]	255641	1			T1	1144		T2	196		T3	84

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Summary for Cross class_cnt_cross

Samples crossed: class_index_cp accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for class_cnt_cross

Bins

class_index_cp	accum_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	accum_cnt_2000	16276	1			T7	1		T17	69		T37	265
class_index[0x0]	accum_cnt_1000	54017	1			T2	59		T4	942		T7	687
class_index[0x0]	accum_cnt_100	6774	1			T2	33		T4	155		T7	32
class_index[0x0]	accum_cnt_50	25000	1			T1	1133		T2	42		T4	102
class_index[0x0]	accum_cnt_10	46919	1			T1	7		T2	38		T3	82
class_index[0x0]	accum_cnt_0	96518	1			T1	4		T2	24		T3	2
class_index[0x1]	accum_cnt_2000	19148	1			T16	64		T70	311		T35	493
class_index[0x1]	accum_cnt_1000	49862	1			T2	63		T3	37		T4	911
class_index[0x1]	accum_cnt_100	6378	1			T2	17		T3	27		T4	149
class_index[0x1]	accum_cnt_50	21979	1			T2	14		T3	17		T4	140
class_index[0x1]	accum_cnt_10	44640	1			T1	3		T2	2		T3	2
class_index[0x1]	accum_cnt_0	105689	1			T1	1141		T2	100		T3	1
class_index[0x2]	accum_cnt_2000	24276	1			T1	533		T7	251		T6	296
class_index[0x2]	accum_cnt_1000	56817	1			T1	543		T28	885		T7	203
class_index[0x2]	accum_cnt_100	5732	1			T1	27		T28	70		T7	17
class_index[0x2]	accum_cnt_50	16379	1			T1	19		T28	47		T7	12
class_index[0x2]	accum_cnt_10	36700	1			T1	14		T18	7		T20	3
class_index[0x2]	accum_cnt_0	108463	1			T1	8		T2	196		T3	84
class_index[0x3]	accum_cnt_2000	16213	1			T69	377		T37	149		T81	236
class_index[0x3]	accum_cnt_1000	46612	1			T4	931		T26	4		T6	1078
class_index[0x3]	accum_cnt_100	5647	1			T4	140		T26	108		T6	92
class_index[0x3]	accum_cnt_50	17788	1			T18	2		T4	120		T49	6
class_index[0x3]	accum_cnt_10	49075	1			T1	3		T3	84		T18	5
class_index[0x3]	accum_cnt_0	109951	1			T1	1141		T2	196		T19	13