Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	71	0	71	100.00
Crosses	138	0	138	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
alert_index_cp	65	0	65	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	130	0	130	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for alert_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	7383	1			T16	10		T8	2		T35	112
alert[0x1]	3804	1			T7	395		T16	169		T8	1
alert[0x2]	4120	1			T51	4		T78	1		T289	1
alert[0x3]	1946	1			T5	1		T27	3		T8	1
alert[0x4]	5202	1			T16	27		T8	1		T9	1
alert[0x5]	3547	1			T5	1		T7	12		T16	49
alert[0x6]	6743	1			T290	1		T55	2		T83	43
alert[0x7]	5261	1			T7	23		T16	10		T9	1
alert[0x8]	7254	1			T123	1		T69	276		T9	2
alert[0x9]	3727	1			T7	21		T69	130		T9	1
alert[0xa]	1436	1			T7	3		T51	6		T35	74
alert[0xb]	4007	1			T5	1		T7	119		T16	70
alert[0xc]	12711	1			T7	17		T16	4579		T8	1
alert[0xd]	5087	1			T7	1		T27	25		T35	297
alert[0xe]	4562	1			T7	7		T49	1		T27	1
alert[0xf]	5278	1			T7	102		T16	21		T81	3
alert[0x10]	4862	1			T8	1		T69	48		T9	3
alert[0x11]	5057	1			T7	250		T16	28		T69	254
alert[0x12]	6951	1			T7	39		T51	1		T35	31
alert[0x13]	6008	1			T5	1		T27	1		T69	17
alert[0x14]	6525	1			T35	124		T24	3		T80	11
alert[0x15]	7473	1			T7	801		T69	186		T35	164
alert[0x16]	6396	1			T7	42		T6	1		T16	814
alert[0x17]	9861	1			T7	15		T9	2		T289	1
alert[0x18]	8799	1			T16	26		T35	2063		T24	95
alert[0x19]	5841	1			T16	149		T57	1		T260	3
alert[0x1a]	3484	1			T7	9		T16	9		T8	1
alert[0x1b]	5463	1			T16	83		T51	74		T69	9
alert[0x1c]	4473	1			T69	1		T35	117		T81	99
alert[0x1d]	4955	1			T7	97		T16	15		T35	45
alert[0x1e]	13391	1			T7	30		T16	5853		T27	1
alert[0x1f]	7220	1			T4	1		T27	1		T24	15
alert[0x20]	3213	1			T9	1		T290	1		T81	215
alert[0x21]	15108	1			T7	16		T16	1		T24	106
alert[0x22]	11935	1			T9	1		T88	1		T55	2
alert[0x23]	4482	1			T16	76		T78	1		T35	6
alert[0x24]	3091	1			T7	191		T24	2		T93	1
alert[0x25]	2232	1			T5	1		T16	34		T9	1
alert[0x26]	2810	1			T7	128		T16	14		T27	18
alert[0x27]	8361	1			T16	749		T69	162		T9	1
alert[0x28]	5435	1			T5	2		T7	136		T16	67
alert[0x29]	9337	1			T16	28		T8	1		T69	164
alert[0x2a]	2571	1			T7	20		T6	1		T35	378
alert[0x2b]	4111	1			T7	51		T16	152		T69	154
alert[0x2c]	6943	1			T16	2		T106	1		T123	1
alert[0x2d]	6965	1			T5	1		T7	439		T49	2
alert[0x2e]	3457	1			T69	157		T35	120		T24	7
alert[0x2f]	4919	1			T16	96		T69	257		T78	1
alert[0x30]	18004	1			T7	44		T51	3		T106	1
alert[0x31]	1721	1			T16	124		T69	10		T35	116
alert[0x32]	2818	1			T7	38		T16	42		T69	25
alert[0x33]	6298	1			T16	5		T78	7		T35	23
alert[0x34]	1912	1			T49	3		T24	245		T81	12
alert[0x35]	10945	1			T7	6		T51	1		T8	1
alert[0x36]	8139	1			T7	15		T49	8		T69	64
alert[0x37]	4050	1			T7	20		T9	1		T35	531
alert[0x38]	5596	1			T5	1		T16	119		T24	106
alert[0x39]	1436	1			T5	1		T16	59		T27	6
alert[0x3a]	2471	1			T5	2		T7	58		T16	117
alert[0x3b]	3753	1			T16	14		T51	3		T8	1
alert[0x3c]	4110	1			T7	378		T27	2		T8	1
alert[0x3d]	5874	1			T49	1		T51	5		T24	153
alert[0x3e]	5683	1			T5	1		T69	8		T81	311
alert[0x3f]	4055	1			T16	173		T69	47		T78	3
alert[0x40]	6264	1			T16	152		T55	55		T81	1892

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	93940	1			T8	3		T69	6568		T9	3
class_i[0x1]	57599	1			T4	1		T16	14524		T51	101
class_i[0x2]	82420	1			T5	1		T7	3523		T49	15
class_i[0x3]	142967	1			T5	12		T27	14		T8	1

---

Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

alert_integrity_fail

376282

1

T7

3523

T49

15

T16

14524

alert_ping_fail

644

1

T4

1

T5

13

T6

2

---

Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	0	130	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	alert_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	alert[0x0]	7376	1			T16	10		T35	112		T24	77
alert_integrity_fail	alert[0x1]	3795	1			T7	395		T16	169		T35	13
alert_integrity_fail	alert[0x2]	4111	1			T51	4		T78	1		T83	12
alert_integrity_fail	alert[0x3]	1934	1			T27	3		T78	1		T35	42
alert_integrity_fail	alert[0x4]	5189	1			T16	27		T35	2999		T24	18
alert_integrity_fail	alert[0x5]	3538	1			T7	12		T16	49		T69	294
alert_integrity_fail	alert[0x6]	6732	1			T55	2		T83	43		T84	131
alert_integrity_fail	alert[0x7]	5247	1			T7	23		T16	10		T81	19
alert_integrity_fail	alert[0x8]	7239	1			T69	276		T24	17		T55	1
alert_integrity_fail	alert[0x9]	3722	1			T7	21		T69	130		T35	187
alert_integrity_fail	alert[0xa]	1423	1			T7	3		T51	6		T35	74
alert_integrity_fail	alert[0xb]	3994	1			T7	119		T16	70		T51	4
alert_integrity_fail	alert[0xc]	12699	1			T7	17		T16	4579		T24	3
alert_integrity_fail	alert[0xd]	5081	1			T7	1		T27	25		T35	297
alert_integrity_fail	alert[0xe]	4556	1			T7	7		T49	1		T27	1
alert_integrity_fail	alert[0xf]	5266	1			T7	102		T16	21		T81	3
alert_integrity_fail	alert[0x10]	4848	1			T69	48		T35	310		T24	28
alert_integrity_fail	alert[0x11]	5043	1			T7	250		T16	28		T69	254
alert_integrity_fail	alert[0x12]	6945	1			T7	39		T51	1		T35	31
alert_integrity_fail	alert[0x13]	5995	1			T27	1		T69	17		T84	1870
alert_integrity_fail	alert[0x14]	6508	1			T35	124		T24	3		T80	11
alert_integrity_fail	alert[0x15]	7463	1			T7	801		T69	186		T35	164
alert_integrity_fail	alert[0x16]	6376	1			T7	42		T16	814		T78	1
alert_integrity_fail	alert[0x17]	9840	1			T7	15		T80	1		T81	38
alert_integrity_fail	alert[0x18]	8794	1			T16	26		T35	2063		T24	95
alert_integrity_fail	alert[0x19]	5837	1			T16	149		T57	1		T260	3
alert_integrity_fail	alert[0x1a]	3477	1			T7	9		T16	9		T24	26
alert_integrity_fail	alert[0x1b]	5454	1			T16	83		T51	74		T69	9
alert_integrity_fail	alert[0x1c]	4465	1			T69	1		T35	117		T81	99
alert_integrity_fail	alert[0x1d]	4948	1			T7	97		T16	15		T35	45
alert_integrity_fail	alert[0x1e]	13380	1			T7	30		T16	5853		T27	1
alert_integrity_fail	alert[0x1f]	7207	1			T27	1		T24	15		T83	262
alert_integrity_fail	alert[0x20]	3202	1			T81	215		T42	8		T83	5
alert_integrity_fail	alert[0x21]	15102	1			T7	16		T16	1		T24	106
alert_integrity_fail	alert[0x22]	11922	1			T55	2		T83	7		T57	14
alert_integrity_fail	alert[0x23]	4474	1			T16	76		T78	1		T35	6
alert_integrity_fail	alert[0x24]	3084	1			T7	191		T24	2		T81	267
alert_integrity_fail	alert[0x25]	2221	1			T16	34		T35	210		T81	17
alert_integrity_fail	alert[0x26]	2800	1			T7	128		T16	14		T27	18
alert_integrity_fail	alert[0x27]	8349	1			T16	749		T69	162		T42	68
alert_integrity_fail	alert[0x28]	5419	1			T7	136		T16	67		T69	7
alert_integrity_fail	alert[0x29]	9327	1			T16	28		T69	164		T35	4488
alert_integrity_fail	alert[0x2a]	2561	1			T7	20		T35	378		T81	38
alert_integrity_fail	alert[0x2b]	4101	1			T7	51		T16	152		T69	154
alert_integrity_fail	alert[0x2c]	6932	1			T16	2		T35	426		T24	365
alert_integrity_fail	alert[0x2d]	6953	1			T7	439		T49	2		T16	588
alert_integrity_fail	alert[0x2e]	3447	1			T69	157		T35	120		T24	7
alert_integrity_fail	alert[0x2f]	4897	1			T16	96		T69	257		T78	1
alert_integrity_fail	alert[0x30]	17996	1			T7	44		T51	3		T69	2755
alert_integrity_fail	alert[0x31]	1713	1			T16	124		T69	10		T35	116
alert_integrity_fail	alert[0x32]	2806	1			T7	38		T16	42		T69	25
alert_integrity_fail	alert[0x33]	6292	1			T16	5		T78	7		T35	23
alert_integrity_fail	alert[0x34]	1906	1			T49	3		T24	245		T81	12
alert_integrity_fail	alert[0x35]	10938	1			T7	6		T51	1		T42	1
alert_integrity_fail	alert[0x36]	8131	1			T7	15		T49	8		T69	64
alert_integrity_fail	alert[0x37]	4039	1			T7	20		T35	531		T83	3
alert_integrity_fail	alert[0x38]	5590	1			T16	119		T24	106		T84	9
alert_integrity_fail	alert[0x39]	1429	1			T16	59		T27	6		T69	21
alert_integrity_fail	alert[0x3a]	2462	1			T7	58		T16	117		T83	38
alert_integrity_fail	alert[0x3b]	3743	1			T16	14		T51	3		T35	89
alert_integrity_fail	alert[0x3c]	4103	1			T7	378		T27	2		T35	14
alert_integrity_fail	alert[0x3d]	5868	1			T49	1		T51	5		T24	153
alert_integrity_fail	alert[0x3e]	5679	1			T69	8		T81	311		T83	215
alert_integrity_fail	alert[0x3f]	4052	1			T16	173		T69	47		T78	3
alert_integrity_fail	alert[0x40]	6262	1			T16	152		T55	55		T81	1892
alert_ping_fail	alert[0x0]	7	1			T8	2		T291	1		T292	1
alert_ping_fail	alert[0x1]	9	1			T8	1		T9	1		T293	2
alert_ping_fail	alert[0x2]	9	1			T289	1		T94	1		T294	1
alert_ping_fail	alert[0x3]	12	1			T5	1		T8	1		T289	1
alert_ping_fail	alert[0x4]	13	1			T8	1		T9	1		T94	1
alert_ping_fail	alert[0x5]	9	1			T5	1		T8	1		T291	1
alert_ping_fail	alert[0x6]	11	1			T290	1		T295	2		T296	1
alert_ping_fail	alert[0x7]	14	1			T9	1		T291	1		T297	1
alert_ping_fail	alert[0x8]	15	1			T123	1		T9	2		T290	1
alert_ping_fail	alert[0x9]	5	1			T9	1		T289	1		T48	1
alert_ping_fail	alert[0xa]	13	1			T48	1		T102	1		T298	1
alert_ping_fail	alert[0xb]	13	1			T5	1		T48	2		T102	1
alert_ping_fail	alert[0xc]	12	1			T8	1		T9	1		T289	1
alert_ping_fail	alert[0xd]	6	1			T94	1		T299	1		T292	1
alert_ping_fail	alert[0xe]	6	1			T8	1		T225	1		T300	1
alert_ping_fail	alert[0xf]	12	1			T291	2		T301	1		T300	1
alert_ping_fail	alert[0x10]	14	1			T8	1		T9	3		T289	1
alert_ping_fail	alert[0x11]	14	1			T289	1		T293	1		T291	1
alert_ping_fail	alert[0x12]	6	1			T292	1		T302	1		T303	1
alert_ping_fail	alert[0x13]	13	1			T5	1		T88	1		T299	1
alert_ping_fail	alert[0x14]	17	1			T304	1		T294	1		T305	1
alert_ping_fail	alert[0x15]	10	1			T293	1		T306	1		T295	2
alert_ping_fail	alert[0x16]	20	1			T6	1		T106	1		T9	2
alert_ping_fail	alert[0x17]	21	1			T9	2		T289	1		T94	1
alert_ping_fail	alert[0x18]	5	1			T48	1		T304	1		T307	1
alert_ping_fail	alert[0x19]	4	1			T308	1		T309	1		T310	1
alert_ping_fail	alert[0x1a]	7	1			T8	1		T304	2		T295	1
alert_ping_fail	alert[0x1b]	9	1			T289	1		T291	1		T294	1
alert_ping_fail	alert[0x1c]	8	1			T225	1		T300	2		T296	1
alert_ping_fail	alert[0x1d]	7	1			T289	1		T93	1		T311	2
alert_ping_fail	alert[0x1e]	11	1			T8	1		T93	1		T299	1
alert_ping_fail	alert[0x1f]	13	1			T4	1		T94	1		T48	1
alert_ping_fail	alert[0x20]	11	1			T9	1		T290	1		T301	1
alert_ping_fail	alert[0x21]	6	1			T225	1		T295	1		T312	2
alert_ping_fail	alert[0x22]	13	1			T9	1		T88	1		T291	1
alert_ping_fail	alert[0x23]	8	1			T290	1		T289	1		T291	1
alert_ping_fail	alert[0x24]	7	1			T93	1		T48	1		T311	1
alert_ping_fail	alert[0x25]	11	1			T5	1		T9	1		T294	1
alert_ping_fail	alert[0x26]	10	1			T291	1		T306	1		T300	2
alert_ping_fail	alert[0x27]	12	1			T9	1		T299	1		T291	1
alert_ping_fail	alert[0x28]	16	1			T5	2		T93	1		T291	1
alert_ping_fail	alert[0x29]	10	1			T8	1		T93	2		T48	1
alert_ping_fail	alert[0x2a]	10	1			T6	1		T290	1		T294	1
alert_ping_fail	alert[0x2b]	10	1			T299	1		T102	1		T292	1
alert_ping_fail	alert[0x2c]	11	1			T106	1		T123	1		T301	1
alert_ping_fail	alert[0x2d]	12	1			T5	1		T9	1		T293	1
alert_ping_fail	alert[0x2e]	10	1			T295	1		T313	1		T314	1
alert_ping_fail	alert[0x2f]	22	1			T94	1		T291	2		T292	1
alert_ping_fail	alert[0x30]	8	1			T106	1		T293	1		T291	1
alert_ping_fail	alert[0x31]	8	1			T299	1		T301	1		T313	1
alert_ping_fail	alert[0x32]	12	1			T93	1		T311	1		T225	1
alert_ping_fail	alert[0x33]	6	1			T315	1		T300	1		T310	1
alert_ping_fail	alert[0x34]	6	1			T301	1		T315	1		T308	1
alert_ping_fail	alert[0x35]	7	1			T8	1		T293	1		T301	1
alert_ping_fail	alert[0x36]	8	1			T9	1		T300	1		T316	1
alert_ping_fail	alert[0x37]	11	1			T9	1		T294	1		T301	1
alert_ping_fail	alert[0x38]	6	1			T5	1		T295	1		T317	1
alert_ping_fail	alert[0x39]	7	1			T5	1		T9	1		T306	1
alert_ping_fail	alert[0x3a]	9	1			T5	2		T8	1		T299	1
alert_ping_fail	alert[0x3b]	10	1			T8	1		T289	1		T301	1
alert_ping_fail	alert[0x3c]	7	1			T8	1		T315	1		T296	1
alert_ping_fail	alert[0x3d]	6	1			T225	2		T296	1		T318	1
alert_ping_fail	alert[0x3e]	4	1			T5	1		T308	1		T309	1
alert_ping_fail	alert[0x3f]	3	1			T291	1		T319	1		T310	1
alert_ping_fail	alert[0x40]	2	1			T292	1		T320	1		-	-

---

Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	class_i[0x0]	93806	1			T69	6568		T78	4		T35	186
alert_integrity_fail	class_i[0x1]	57420	1			T16	14524		T51	101		T27	18
alert_integrity_fail	class_i[0x2]	82251	1			T7	3523		T49	15		T27	29
alert_integrity_fail	class_i[0x3]	142805	1			T27	14		T35	17257		T24	585
alert_ping_fail	class_i[0x0]	134	1			T8	3		T9	3		T93	4
alert_ping_fail	class_i[0x1]	179	1			T4	1		T106	3		T8	4
alert_ping_fail	class_i[0x2]	169	1			T5	1		T6	2		T8	8
alert_ping_fail	class_i[0x3]	162	1			T5	12		T8	1		T123	2