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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.66 99.99 98.69 100.00 100.00 100.00 99.38 99.56


Total test records in report: 831
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html
T773 /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.1899193221 Feb 21 12:43:46 PM PST 24 Feb 21 12:43:59 PM PST 24 128385810 ps
T142 /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.33410899 Feb 21 12:43:31 PM PST 24 Feb 21 12:48:38 PM PST 24 54179942287 ps
T143 /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.2361949843 Feb 21 12:43:45 PM PST 24 Feb 21 12:51:15 PM PST 24 24006414596 ps
T774 /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.3598062809 Feb 21 12:43:26 PM PST 24 Feb 21 12:43:47 PM PST 24 325877951 ps
T775 /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.1565771908 Feb 21 12:43:43 PM PST 24 Feb 21 12:43:57 PM PST 24 323501918 ps
T776 /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.2252650464 Feb 21 12:43:42 PM PST 24 Feb 21 12:43:46 PM PST 24 11192224 ps
T777 /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.2632800215 Feb 21 12:43:47 PM PST 24 Feb 21 12:43:57 PM PST 24 57426154 ps
T778 /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.2632340019 Feb 21 12:43:55 PM PST 24 Feb 21 12:44:08 PM PST 24 153043941 ps
T779 /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.2883795263 Feb 21 12:43:25 PM PST 24 Feb 21 12:43:31 PM PST 24 37362412 ps
T780 /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.4130299030 Feb 21 12:43:56 PM PST 24 Feb 21 12:44:00 PM PST 24 83835308 ps
T781 /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.1664697524 Feb 21 12:43:54 PM PST 24 Feb 21 12:43:57 PM PST 24 10177047 ps
T782 /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.3153550297 Feb 21 12:43:44 PM PST 24 Feb 21 12:43:49 PM PST 24 10151987 ps
T783 /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.3401232910 Feb 21 12:43:51 PM PST 24 Feb 21 12:43:55 PM PST 24 9322178 ps
T154 /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.2131161184 Feb 21 12:43:54 PM PST 24 Feb 21 12:48:49 PM PST 24 20408869956 ps
T784 /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.1561329233 Feb 21 12:43:47 PM PST 24 Feb 21 12:43:52 PM PST 24 20580012 ps
T157 /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.2675213807 Feb 21 12:43:57 PM PST 24 Feb 21 12:51:35 PM PST 24 7249457664 ps
T785 /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.1730067179 Feb 21 12:43:51 PM PST 24 Feb 21 12:43:56 PM PST 24 11430374 ps
T786 /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.466170982 Feb 21 12:43:40 PM PST 24 Feb 21 12:43:44 PM PST 24 28056244 ps
T787 /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.811203271 Feb 21 12:43:35 PM PST 24 Feb 21 12:43:49 PM PST 24 409353812 ps
T788 /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.3733303794 Feb 21 12:43:33 PM PST 24 Feb 21 12:43:38 PM PST 24 99941246 ps
T789 /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.4008403134 Feb 21 12:43:17 PM PST 24 Feb 21 12:43:19 PM PST 24 11801211 ps
T790 /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.1484486602 Feb 21 12:43:32 PM PST 24 Feb 21 12:43:35 PM PST 24 34226563 ps
T153 /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.3065015216 Feb 21 12:43:43 PM PST 24 Feb 21 12:46:58 PM PST 24 3403401516 ps
T791 /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.1836498473 Feb 21 12:43:44 PM PST 24 Feb 21 12:43:48 PM PST 24 6628570 ps
T158 /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.3657725173 Feb 21 12:43:48 PM PST 24 Feb 21 12:51:50 PM PST 24 90660348615 ps
T150 /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.689146563 Feb 21 12:43:35 PM PST 24 Feb 21 12:47:22 PM PST 24 1698638082 ps
T792 /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.1896767903 Feb 21 12:43:37 PM PST 24 Feb 21 12:43:59 PM PST 24 3128823071 ps
T793 /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.4070858339 Feb 21 12:43:39 PM PST 24 Feb 21 12:43:41 PM PST 24 16697349 ps
T169 /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.451299820 Feb 21 12:43:27 PM PST 24 Feb 21 12:43:30 PM PST 24 61854220 ps
T794 /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.2189868774 Feb 21 12:43:15 PM PST 24 Feb 21 12:44:58 PM PST 24 829416337 ps
T795 /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.2829282310 Feb 21 12:43:47 PM PST 24 Feb 21 12:43:54 PM PST 24 8883286 ps
T796 /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.2295859397 Feb 21 12:43:16 PM PST 24 Feb 21 12:43:19 PM PST 24 10249484 ps
T797 /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.4057216212 Feb 21 12:43:51 PM PST 24 Feb 21 12:44:03 PM PST 24 113066147 ps
T798 /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.3321395627 Feb 21 12:43:44 PM PST 24 Feb 21 12:43:49 PM PST 24 64054886 ps
T799 /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.2157200879 Feb 21 12:43:37 PM PST 24 Feb 21 12:44:27 PM PST 24 2616583663 ps
T800 /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.751424888 Feb 21 12:43:43 PM PST 24 Feb 21 12:44:08 PM PST 24 353581672 ps
T801 /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.3600560426 Feb 21 12:43:46 PM PST 24 Feb 21 12:43:58 PM PST 24 55626213 ps
T802 /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.1916368146 Feb 21 12:43:43 PM PST 24 Feb 21 12:43:58 PM PST 24 199277003 ps
T803 /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.718218338 Feb 21 12:43:45 PM PST 24 Feb 21 12:43:55 PM PST 24 113601388 ps
T804 /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.342307869 Feb 21 12:43:49 PM PST 24 Feb 21 12:43:54 PM PST 24 24396200 ps
T805 /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.2035438344 Feb 21 12:43:44 PM PST 24 Feb 21 12:43:48 PM PST 24 7702989 ps
T806 /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.2565921896 Feb 21 12:43:45 PM PST 24 Feb 21 12:44:12 PM PST 24 1435579700 ps
T807 /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.833094992 Feb 21 12:43:57 PM PST 24 Feb 21 12:44:12 PM PST 24 189851088 ps
T808 /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.960481068 Feb 21 12:43:49 PM PST 24 Feb 21 12:46:33 PM PST 24 1097024217 ps
T354 /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.1811526326 Feb 21 12:43:23 PM PST 24 Feb 21 12:53:29 PM PST 24 87827807599 ps
T809 /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.1707157025 Feb 21 12:43:31 PM PST 24 Feb 21 12:43:42 PM PST 24 68952004 ps
T355 /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.1910575248 Feb 21 12:43:20 PM PST 24 Feb 21 12:52:32 PM PST 24 18830031207 ps
T810 /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.2320673080 Feb 21 12:43:47 PM PST 24 Feb 21 12:43:57 PM PST 24 254988880 ps
T811 /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.4190002354 Feb 21 12:43:43 PM PST 24 Feb 21 12:43:47 PM PST 24 12295642 ps
T812 /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.1335666134 Feb 21 12:43:59 PM PST 24 Feb 21 12:44:01 PM PST 24 7515752 ps
T171 /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.4120624180 Feb 21 12:43:31 PM PST 24 Feb 21 12:43:35 PM PST 24 188371364 ps
T148 /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.525172687 Feb 21 12:43:18 PM PST 24 Feb 21 12:59:45 PM PST 24 24677641314 ps
T813 /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.3822651244 Feb 21 12:43:33 PM PST 24 Feb 21 12:43:46 PM PST 24 164454079 ps
T181 /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.1622773401 Feb 21 12:43:41 PM PST 24 Feb 21 12:43:44 PM PST 24 120906009 ps
T814 /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.3650050173 Feb 21 12:43:53 PM PST 24 Feb 21 12:44:01 PM PST 24 34647537 ps
T815 /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.3890548003 Feb 21 12:43:43 PM PST 24 Feb 21 12:43:46 PM PST 24 10177254 ps
T816 /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.1326897946 Feb 21 12:43:57 PM PST 24 Feb 21 12:44:01 PM PST 24 55938100 ps
T149 /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.1744708683 Feb 21 12:43:41 PM PST 24 Feb 21 12:51:52 PM PST 24 14817449366 ps
T817 /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.2299960005 Feb 21 12:43:47 PM PST 24 Feb 21 12:44:27 PM PST 24 5386749020 ps
T818 /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.3070303883 Feb 21 12:43:37 PM PST 24 Feb 21 12:50:41 PM PST 24 28456138122 ps
T819 /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.752694494 Feb 21 12:43:53 PM PST 24 Feb 21 12:44:01 PM PST 24 52336124 ps
T820 /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.2242433483 Feb 21 12:43:44 PM PST 24 Feb 21 12:43:48 PM PST 24 43410382 ps
T821 /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.1092911349 Feb 21 12:43:52 PM PST 24 Feb 21 12:46:16 PM PST 24 4032307882 ps
T176 /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.1395383436 Feb 21 12:43:54 PM PST 24 Feb 21 12:43:58 PM PST 24 57727010 ps
T822 /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.2624047503 Feb 21 12:43:48 PM PST 24 Feb 21 12:44:01 PM PST 24 208013023 ps
T823 /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.2846809931 Feb 21 12:43:49 PM PST 24 Feb 21 12:43:55 PM PST 24 19269508 ps
T824 /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.3651407157 Feb 21 12:43:32 PM PST 24 Feb 21 12:52:38 PM PST 24 16745644279 ps
T152 /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.3697484556 Feb 21 12:43:45 PM PST 24 Feb 21 12:59:50 PM PST 24 24674870425 ps
T182 /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.3559384335 Feb 21 12:43:16 PM PST 24 Feb 21 12:43:58 PM PST 24 611903195 ps
T825 /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.1211049774 Feb 21 12:43:52 PM PST 24 Feb 21 12:43:56 PM PST 24 11933928 ps
T826 /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.1135928585 Feb 21 12:43:27 PM PST 24 Feb 21 12:43:34 PM PST 24 74406409 ps
T827 /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.3799059727 Feb 21 12:43:28 PM PST 24 Feb 21 12:43:29 PM PST 24 80891334 ps
T172 /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.962099221 Feb 21 12:44:01 PM PST 24 Feb 21 12:44:06 PM PST 24 702298454 ps
T828 /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.4264916929 Feb 21 12:43:35 PM PST 24 Feb 21 12:43:37 PM PST 24 18936539 ps
T829 /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.71934345 Feb 21 12:43:28 PM PST 24 Feb 21 12:43:30 PM PST 24 19445106 ps
T170 /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.1832160999 Feb 21 12:43:32 PM PST 24 Feb 21 12:43:35 PM PST 24 38686572 ps
T830 /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.2970413762 Feb 21 12:43:49 PM PST 24 Feb 21 12:44:01 PM PST 24 426063108 ps
T831 /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.1683748877 Feb 21 12:43:39 PM PST 24 Feb 21 12:44:15 PM PST 24 522743842 ps
T159 /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.99789365 Feb 21 12:43:56 PM PST 24 Feb 21 01:00:23 PM PST 24 46558515032 ps
T155 /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.1373474580 Feb 21 12:43:40 PM PST 24 Feb 21 12:46:46 PM PST 24 6499179838 ps
T156 /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.3659168530 Feb 21 12:43:45 PM PST 24 Feb 21 12:51:30 PM PST 24 7744921691 ps

Test location /workspace/coverage/default/32.alert_handler_lpg_stub_clk.3278418037
Short name T1
Test name
Test status
Simulation time 46848929239 ps
CPU time 1269.65 seconds
Started Feb 21 03:56:13 PM PST 24
Finished Feb 21 04:17:24 PM PST 24
Peak memory 283980 kb
Host smart-8303a4f7-eb98-4090-9ecf-8ffa5290e0cf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278418037 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg_stub_clk.3278418037
Directory /workspace/32.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all_with_rand_reset.327867973
Short name T26
Test name
Test status
Simulation time 19275417910 ps
CPU time 1102.77 seconds
Started Feb 21 03:56:08 PM PST 24
Finished Feb 21 04:14:32 PM PST 24
Peak memory 270592 kb
Host smart-298ceb7e-a3d0-47f0-aa91-3d6d2fe97191
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327867973 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 28.alert_handler_stress_all_with_rand_reset.327867973
Directory /workspace/28.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all.1527623916
Short name T35
Test name
Test status
Simulation time 601106993014 ps
CPU time 2995.02 seconds
Started Feb 21 03:56:32 PM PST 24
Finished Feb 21 04:46:28 PM PST 24
Peak memory 288556 kb
Host smart-8375e8b7-bb7c-40a3-84d2-b6c2f28e0565
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527623916 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_ha
ndler_stress_all.1527623916
Directory /workspace/34.alert_handler_stress_all/latest

Test location /workspace/coverage/default/0.alert_handler_sec_cm.971051876
Short name T11
Test name
Test status
Simulation time 490729922 ps
CPU time 25.49 seconds
Started Feb 21 03:53:42 PM PST 24
Finished Feb 21 03:54:08 PM PST 24
Peak memory 269232 kb
Host smart-6219cce4-0681-4d9f-9296-1f7f95380a4c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=971051876 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sec_cm.971051876
Directory /workspace/0.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all.372690948
Short name T28
Test name
Test status
Simulation time 17772171004 ps
CPU time 1056.84 seconds
Started Feb 21 03:54:05 PM PST 24
Finished Feb 21 04:11:42 PM PST 24
Peak memory 281912 kb
Host smart-8b74bea6-7ca3-4320-9a32-216ed116f57c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372690948 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_hand
ler_stress_all.372690948
Directory /workspace/6.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.1606829214
Short name T160
Test name
Test status
Simulation time 4397145971 ps
CPU time 68.39 seconds
Started Feb 21 12:43:51 PM PST 24
Finished Feb 21 12:45:03 PM PST 24
Peak memory 239176 kb
Host smart-12119968-005f-49c6-8b03-5712140e5a38
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1606829214 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_intg_err.1606829214
Directory /workspace/3.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all_with_rand_reset.4252192960
Short name T24
Test name
Test status
Simulation time 148897130039 ps
CPU time 4008.94 seconds
Started Feb 21 03:57:03 PM PST 24
Finished Feb 21 05:03:53 PM PST 24
Peak memory 304828 kb
Host smart-601f2d05-2547-410b-a30a-b42ddd5a1fa5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252192960 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.alert_handler_stress_all_with_rand_reset.4252192960
Directory /workspace/39.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.alert_handler_entropy.2251134551
Short name T7
Test name
Test status
Simulation time 30108902512 ps
CPU time 1578.19 seconds
Started Feb 21 03:54:43 PM PST 24
Finished Feb 21 04:21:03 PM PST 24
Peak memory 272872 kb
Host smart-1f4d7e71-8d72-415a-8591-18c1f66f4d2f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251134551 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy.2251134551
Directory /workspace/12.alert_handler_entropy/latest

Test location /workspace/coverage/default/5.alert_handler_lpg.3806921166
Short name T6
Test name
Test status
Simulation time 15055138795 ps
CPU time 1201.63 seconds
Started Feb 21 03:53:59 PM PST 24
Finished Feb 21 04:14:01 PM PST 24
Peak memory 285188 kb
Host smart-30651225-5f4b-4399-9e10-bf81c1d94b5e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806921166 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg.3806921166
Directory /workspace/5.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.2810663756
Short name T126
Test name
Test status
Simulation time 9945881700 ps
CPU time 326.72 seconds
Started Feb 21 12:43:33 PM PST 24
Finished Feb 21 12:49:01 PM PST 24
Peak memory 265168 kb
Host smart-3319e4a6-423d-46e7-a591-1e99449df501
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2810663756 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shadow_reg_erro
rs.2810663756
Directory /workspace/5.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.2315198311
Short name T128
Test name
Test status
Simulation time 16977117795 ps
CPU time 524.19 seconds
Started Feb 21 12:43:45 PM PST 24
Finished Feb 21 12:52:33 PM PST 24
Peak memory 264976 kb
Host smart-4bcfe058-96b2-45d9-8c6f-2df278c31109
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315198311 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 10.alert_handler_shadow_reg_errors_with_csr_rw.2315198311
Directory /workspace/10.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all.2423132871
Short name T581
Test name
Test status
Simulation time 70612938312 ps
CPU time 1545.08 seconds
Started Feb 21 03:56:04 PM PST 24
Finished Feb 21 04:21:49 PM PST 24
Peak memory 304900 kb
Host smart-c8b1950e-1cca-4864-963f-bec7eed17ecd
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423132871 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_ha
ndler_stress_all.2423132871
Directory /workspace/29.alert_handler_stress_all/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all.100002709
Short name T27
Test name
Test status
Simulation time 13772018397 ps
CPU time 756.57 seconds
Started Feb 21 03:57:03 PM PST 24
Finished Feb 21 04:09:40 PM PST 24
Peak memory 265716 kb
Host smart-40bfc684-b834-4c30-add1-1c4a6b0442f7
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100002709 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_han
dler_stress_all.100002709
Directory /workspace/37.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.2865825008
Short name T136
Test name
Test status
Simulation time 17661054088 ps
CPU time 329.94 seconds
Started Feb 21 12:43:51 PM PST 24
Finished Feb 21 12:49:24 PM PST 24
Peak memory 272772 kb
Host smart-6698d008-52eb-432a-921f-8ec82b092a49
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2865825008 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shadow_reg_erro
rs.2865825008
Directory /workspace/6.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all_with_rand_reset.3450155818
Short name T84
Test name
Test status
Simulation time 32986076584 ps
CPU time 3052.43 seconds
Started Feb 21 03:54:49 PM PST 24
Finished Feb 21 04:45:42 PM PST 24
Peak memory 322196 kb
Host smart-1de00cff-70e6-4bdc-b120-f3dcadaaccec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450155818 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 14.alert_handler_stress_all_with_rand_reset.3450155818
Directory /workspace/14.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.alert_handler_ping_timeout.4105539517
Short name T5
Test name
Test status
Simulation time 23640342510 ps
CPU time 368.37 seconds
Started Feb 21 03:57:03 PM PST 24
Finished Feb 21 04:03:12 PM PST 24
Peak memory 247164 kb
Host smart-1e169543-0fb1-47cb-9790-5961ee7d6ebb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105539517 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_ping_timeout.4105539517
Directory /workspace/37.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_lpg.1956773937
Short name T297
Test name
Test status
Simulation time 220763841064 ps
CPU time 2306.27 seconds
Started Feb 21 03:56:38 PM PST 24
Finished Feb 21 04:35:05 PM PST 24
Peak memory 281272 kb
Host smart-0cf0702b-45f8-455a-9c9f-006ec512e222
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956773937 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg.1956773937
Directory /workspace/34.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.1692471822
Short name T124
Test name
Test status
Simulation time 24711002865 ps
CPU time 812.58 seconds
Started Feb 21 12:43:31 PM PST 24
Finished Feb 21 12:57:05 PM PST 24
Peak memory 270604 kb
Host smart-688f76a7-9385-40fe-a84f-fdf8ddee56a1
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692471822 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.alert_handler_shadow_reg_errors_with_csr_rw.1692471822
Directory /workspace/4.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.1765122369
Short name T341
Test name
Test status
Simulation time 8435692 ps
CPU time 1.45 seconds
Started Feb 21 12:43:51 PM PST 24
Finished Feb 21 12:43:56 PM PST 24
Peak memory 236220 kb
Host smart-52328b1b-814f-4478-9201-e29ce619129e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1765122369 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.alert_handler_intr_test.1765122369
Directory /workspace/41.alert_handler_intr_test/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all_with_rand_reset.3100094335
Short name T81
Test name
Test status
Simulation time 80779675272 ps
CPU time 7620 seconds
Started Feb 21 03:55:38 PM PST 24
Finished Feb 21 06:02:39 PM PST 24
Peak memory 370964 kb
Host smart-c5ce2aa2-9b9a-4be2-915c-1e2a3b65ef1b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100094335 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 23.alert_handler_stress_all_with_rand_reset.3100094335
Directory /workspace/23.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.alert_handler_lpg.3351784416
Short name T321
Test name
Test status
Simulation time 40226216205 ps
CPU time 2016.98 seconds
Started Feb 21 03:56:49 PM PST 24
Finished Feb 21 04:30:27 PM PST 24
Peak memory 282112 kb
Host smart-c4f2fdd5-37a5-4e8d-8e9f-3eb38fe11ab4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351784416 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg.3351784416
Directory /workspace/36.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.551179572
Short name T144
Test name
Test status
Simulation time 3909464949 ps
CPU time 283.67 seconds
Started Feb 21 12:43:48 PM PST 24
Finished Feb 21 12:48:36 PM PST 24
Peak memory 264976 kb
Host smart-2523998a-98cb-4718-8042-339441e3ba61
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=551179572 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shadow_reg_erro
rs.551179572
Directory /workspace/15.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/23.alert_handler_ping_timeout.3395960197
Short name T8
Test name
Test status
Simulation time 15053638027 ps
CPU time 314.1 seconds
Started Feb 21 03:55:48 PM PST 24
Finished Feb 21 04:01:03 PM PST 24
Peak memory 255860 kb
Host smart-8e3adf21-4ceb-4914-9fd6-282a187200c5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395960197 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_ping_timeout.3395960197
Directory /workspace/23.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.99789365
Short name T159
Test name
Test status
Simulation time 46558515032 ps
CPU time 986.23 seconds
Started Feb 21 12:43:56 PM PST 24
Finished Feb 21 01:00:23 PM PST 24
Peak memory 265300 kb
Host smart-7d5a539c-3b35-40fb-8560-7c6ceebdca69
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99789365 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_
TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -
cm_name 14.alert_handler_shadow_reg_errors_with_csr_rw.99789365
Directory /workspace/14.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/41.alert_handler_lpg.3384397588
Short name T257
Test name
Test status
Simulation time 167421754612 ps
CPU time 2151.01 seconds
Started Feb 21 03:57:13 PM PST 24
Finished Feb 21 04:33:04 PM PST 24
Peak memory 281296 kb
Host smart-d70564d2-b1e8-444a-a655-fe6412a11181
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384397588 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg.3384397588
Directory /workspace/41.alert_handler_lpg/latest

Test location /workspace/coverage/default/0.alert_handler_ping_timeout.2815851531
Short name T310
Test name
Test status
Simulation time 29669423151 ps
CPU time 621.23 seconds
Started Feb 21 03:53:44 PM PST 24
Finished Feb 21 04:04:08 PM PST 24
Peak memory 246984 kb
Host smart-7268bf30-050e-4120-a052-0e979e5a6003
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815851531 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_ping_timeout.2815851531
Directory /workspace/0.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.1517002893
Short name T131
Test name
Test status
Simulation time 14217467526 ps
CPU time 323.57 seconds
Started Feb 21 12:43:41 PM PST 24
Finished Feb 21 12:49:06 PM PST 24
Peak memory 265076 kb
Host smart-440df3a4-b545-4afd-8fdd-f47e40a6214e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1517002893 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shadow_reg_erro
rs.1517002893
Directory /workspace/9.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all_with_rand_reset.2127120688
Short name T69
Test name
Test status
Simulation time 43150363741 ps
CPU time 2417.68 seconds
Started Feb 21 03:54:44 PM PST 24
Finished Feb 21 04:35:04 PM PST 24
Peak memory 305784 kb
Host smart-4b1f0cab-eff8-45e3-ad0e-fc9340fb2276
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127120688 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.alert_handler_stress_all_with_rand_reset.2127120688
Directory /workspace/13.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.alert_handler_ping_timeout.1654808690
Short name T9
Test name
Test status
Simulation time 54130947254 ps
CPU time 541.01 seconds
Started Feb 21 03:53:48 PM PST 24
Finished Feb 21 04:02:51 PM PST 24
Peak memory 247208 kb
Host smart-358f486f-a7cf-4502-9a50-fe038ef83a74
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654808690 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_ping_timeout.1654808690
Directory /workspace/2.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_lpg.393180599
Short name T106
Test name
Test status
Simulation time 77583172623 ps
CPU time 2634.06 seconds
Started Feb 21 03:54:52 PM PST 24
Finished Feb 21 04:38:47 PM PST 24
Peak memory 288936 kb
Host smart-537fa9fa-5164-4cca-bf22-23065f1a4462
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393180599 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg.393180599
Directory /workspace/16.alert_handler_lpg/latest

Test location /workspace/coverage/default/26.alert_handler_lpg_stub_clk.1834601104
Short name T242
Test name
Test status
Simulation time 49633219432 ps
CPU time 2570.39 seconds
Started Feb 21 03:56:02 PM PST 24
Finished Feb 21 04:38:53 PM PST 24
Peak memory 288804 kb
Host smart-4f5bafb1-d92e-40d6-8290-d4485fbffdbd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834601104 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg_stub_clk.1834601104
Directory /workspace/26.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.3657725173
Short name T158
Test name
Test status
Simulation time 90660348615 ps
CPU time 476.79 seconds
Started Feb 21 12:43:48 PM PST 24
Finished Feb 21 12:51:50 PM PST 24
Peak memory 265072 kb
Host smart-a271d42a-a4ad-4b9b-908d-10fe0be1258a
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657725173 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.alert_handler_shadow_reg_errors_with_csr_rw.3657725173
Directory /workspace/7.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all.649487953
Short name T260
Test name
Test status
Simulation time 10883353102 ps
CPU time 602.5 seconds
Started Feb 21 03:53:39 PM PST 24
Finished Feb 21 04:03:42 PM PST 24
Peak memory 256524 kb
Host smart-7c9f00f2-2627-405b-90eb-098e1c3fa8fe
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649487953 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_hand
ler_stress_all.649487953
Directory /workspace/1.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.3516528270
Short name T137
Test name
Test status
Simulation time 15263459690 ps
CPU time 955.52 seconds
Started Feb 21 12:43:50 PM PST 24
Finished Feb 21 12:59:49 PM PST 24
Peak memory 265128 kb
Host smart-50348dfe-5afa-4783-b457-1626c8c3c827
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516528270 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 18.alert_handler_shadow_reg_errors_with_csr_rw.3516528270
Directory /workspace/18.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/0.alert_handler_lpg.2209207362
Short name T328
Test name
Test status
Simulation time 254637463231 ps
CPU time 1807.41 seconds
Started Feb 21 03:53:41 PM PST 24
Finished Feb 21 04:23:49 PM PST 24
Peak memory 271860 kb
Host smart-5d582ffa-249e-4a4b-abda-6991920e9a85
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2209207362 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg.2209207362
Directory /workspace/0.alert_handler_lpg/latest

Test location /workspace/coverage/default/28.alert_handler_ping_timeout.2684489617
Short name T669
Test name
Test status
Simulation time 19769123571 ps
CPU time 431.64 seconds
Started Feb 21 03:56:12 PM PST 24
Finished Feb 21 04:03:24 PM PST 24
Peak memory 246044 kb
Host smart-f1e7066e-83c1-48d4-b7f9-4aa52df4ddee
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2684489617 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_ping_timeout.2684489617
Directory /workspace/28.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all_with_rand_reset.1078523808
Short name T25
Test name
Test status
Simulation time 77504613304 ps
CPU time 3881.1 seconds
Started Feb 21 03:56:04 PM PST 24
Finished Feb 21 05:00:46 PM PST 24
Peak memory 337612 kb
Host smart-42ab62d0-d25d-4f98-9543-de5c96319fb2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078523808 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.alert_handler_stress_all_with_rand_reset.1078523808
Directory /workspace/30.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all.2227075099
Short name T249
Test name
Test status
Simulation time 168763626247 ps
CPU time 928.99 seconds
Started Feb 21 03:54:52 PM PST 24
Finished Feb 21 04:10:22 PM PST 24
Peak memory 264720 kb
Host smart-76d89bb2-2ac7-4f60-b5a1-091cbc72384c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227075099 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_ha
ndler_stress_all.2227075099
Directory /workspace/17.alert_handler_stress_all/latest

Test location /workspace/coverage/default/22.alert_handler_lpg.2727716510
Short name T265
Test name
Test status
Simulation time 14483604858 ps
CPU time 1194.78 seconds
Started Feb 21 03:55:20 PM PST 24
Finished Feb 21 04:15:16 PM PST 24
Peak memory 272516 kb
Host smart-f4c285f7-f6bc-4fe4-94cd-c1d1448afd27
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2727716510 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg.2727716510
Directory /workspace/22.alert_handler_lpg/latest

Test location /workspace/coverage/default/36.alert_handler_ping_timeout.1268720470
Short name T303
Test name
Test status
Simulation time 13642894896 ps
CPU time 547.91 seconds
Started Feb 21 03:56:49 PM PST 24
Finished Feb 21 04:05:58 PM PST 24
Peak memory 247216 kb
Host smart-930d258d-9635-426a-98ca-295743910670
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1268720470 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_ping_timeout.1268720470
Directory /workspace/36.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.3641288399
Short name T129
Test name
Test status
Simulation time 4997052471 ps
CPU time 573.1 seconds
Started Feb 21 12:43:28 PM PST 24
Finished Feb 21 12:53:02 PM PST 24
Peak memory 264880 kb
Host smart-b51bb43f-7ac7-4e2a-8034-33908a2f807a
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641288399 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.alert_handler_shadow_reg_errors_with_csr_rw.3641288399
Directory /workspace/6.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.2468105166
Short name T168
Test name
Test status
Simulation time 1079487069 ps
CPU time 37.64 seconds
Started Feb 21 12:43:32 PM PST 24
Finished Feb 21 12:44:10 PM PST 24
Peak memory 245092 kb
Host smart-5ed0d258-f135-43a6-ac93-4693749ad8a4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2468105166 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_intg_err.2468105166
Directory /workspace/5.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.2131161184
Short name T154
Test name
Test status
Simulation time 20408869956 ps
CPU time 292.99 seconds
Started Feb 21 12:43:54 PM PST 24
Finished Feb 21 12:48:49 PM PST 24
Peak memory 273180 kb
Host smart-644d0707-2233-4cb0-99a2-53fa8d2424b4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2131161184 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shadow_reg_err
ors.2131161184
Directory /workspace/16.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.1449415711
Short name T343
Test name
Test status
Simulation time 68348262 ps
CPU time 1.33 seconds
Started Feb 21 12:43:47 PM PST 24
Finished Feb 21 12:43:53 PM PST 24
Peak memory 235400 kb
Host smart-7c2601bc-74c2-4c34-87a8-fcbf7e7bf664
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1449415711 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_intr_test.1449415711
Directory /workspace/3.alert_handler_intr_test/latest

Test location /workspace/coverage/default/39.alert_handler_lpg.4085356640
Short name T636
Test name
Test status
Simulation time 65405315087 ps
CPU time 1914.39 seconds
Started Feb 21 03:57:03 PM PST 24
Finished Feb 21 04:28:58 PM PST 24
Peak memory 285236 kb
Host smart-9ad77e71-a322-4ccf-b890-ebbe5140318d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085356640 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg.4085356640
Directory /workspace/39.alert_handler_lpg/latest

Test location /workspace/coverage/default/9.alert_handler_sig_int_fail.2861450765
Short name T243
Test name
Test status
Simulation time 9766157374 ps
CPU time 44.28 seconds
Started Feb 21 03:54:35 PM PST 24
Finished Feb 21 03:55:20 PM PST 24
Peak memory 247340 kb
Host smart-075f856f-d021-4f41-8bbe-7132f67151a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28614
50765 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_sig_int_fail.2861450765
Directory /workspace/9.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.3981818918
Short name T167
Test name
Test status
Simulation time 59440828 ps
CPU time 3.68 seconds
Started Feb 21 12:43:47 PM PST 24
Finished Feb 21 12:43:55 PM PST 24
Peak memory 235332 kb
Host smart-078bb6aa-73cd-4702-982e-5f58002e6418
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3981818918 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_intg_err.3981818918
Directory /workspace/17.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/0.alert_handler_alert_accum_saturation.2255556888
Short name T206
Test name
Test status
Simulation time 116036461 ps
CPU time 3.24 seconds
Started Feb 21 03:53:38 PM PST 24
Finished Feb 21 03:53:42 PM PST 24
Peak memory 248348 kb
Host smart-87396b08-4679-4afc-b13b-5b0fdee5bb8a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2255556888 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_alert_accum_saturation.2255556888
Directory /workspace/0.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/10.alert_handler_alert_accum_saturation.4159116215
Short name T211
Test name
Test status
Simulation time 152876658 ps
CPU time 3.72 seconds
Started Feb 21 03:54:38 PM PST 24
Finished Feb 21 03:54:42 PM PST 24
Peak memory 248544 kb
Host smart-d913f892-e8b6-4876-8240-bbb0f863475a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4159116215 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_alert_accum_saturation.4159116215
Directory /workspace/10.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/12.alert_handler_alert_accum_saturation.2345264876
Short name T195
Test name
Test status
Simulation time 127612084 ps
CPU time 3.34 seconds
Started Feb 21 03:54:45 PM PST 24
Finished Feb 21 03:54:50 PM PST 24
Peak memory 248544 kb
Host smart-234319b6-79bd-422a-bb36-3ca2e66b40c0
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2345264876 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_alert_accum_saturation.2345264876
Directory /workspace/12.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/8.alert_handler_alert_accum_saturation.2792113089
Short name T202
Test name
Test status
Simulation time 20058455 ps
CPU time 2.88 seconds
Started Feb 21 03:54:19 PM PST 24
Finished Feb 21 03:54:22 PM PST 24
Peak memory 248564 kb
Host smart-40b6f82a-776c-422e-aff4-39099072b964
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2792113089 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_alert_accum_saturation.2792113089
Directory /workspace/8.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.4079683
Short name T125
Test name
Test status
Simulation time 5452392451 ps
CPU time 333.87 seconds
Started Feb 21 12:43:56 PM PST 24
Finished Feb 21 12:49:31 PM PST 24
Peak memory 270512 kb
Host smart-9ae83c33-fd0c-40e0-8149-ccc65f61ae49
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4079683 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shadow_reg_errors.4079683
Directory /workspace/12.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/21.alert_handler_lpg.184451795
Short name T324
Test name
Test status
Simulation time 187650376368 ps
CPU time 2552.74 seconds
Started Feb 21 03:55:31 PM PST 24
Finished Feb 21 04:38:04 PM PST 24
Peak memory 288576 kb
Host smart-a4ea6dcf-8625-4a4f-8491-5dff1466f2d8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184451795 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg.184451795
Directory /workspace/21.alert_handler_lpg/latest

Test location /workspace/coverage/default/24.alert_handler_random_classes.3623492098
Short name T252
Test name
Test status
Simulation time 4054372802 ps
CPU time 62.3 seconds
Started Feb 21 03:55:36 PM PST 24
Finished Feb 21 03:56:39 PM PST 24
Peak memory 246960 kb
Host smart-7cc69cea-7feb-49aa-aabd-8026d7f30ac8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36234
92098 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_classes.3623492098
Directory /workspace/24.alert_handler_random_classes/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all.1959446823
Short name T277
Test name
Test status
Simulation time 213089108199 ps
CPU time 3245.5 seconds
Started Feb 21 03:53:49 PM PST 24
Finished Feb 21 04:47:57 PM PST 24
Peak memory 301096 kb
Host smart-ec141b59-1f70-4baf-a703-6fe6d11f6686
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959446823 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_han
dler_stress_all.1959446823
Directory /workspace/3.alert_handler_stress_all/latest

Test location /workspace/coverage/default/30.alert_handler_sig_int_fail.3165356720
Short name T283
Test name
Test status
Simulation time 3764838099 ps
CPU time 45.11 seconds
Started Feb 21 03:56:13 PM PST 24
Finished Feb 21 03:56:59 PM PST 24
Peak memory 254748 kb
Host smart-5cb3f2ff-a156-4a88-9eac-a3ebe0b103ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31653
56720 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_sig_int_fail.3165356720
Directory /workspace/30.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all.1317665115
Short name T116
Test name
Test status
Simulation time 486442858175 ps
CPU time 3913.41 seconds
Started Feb 21 03:56:15 PM PST 24
Finished Feb 21 05:01:30 PM PST 24
Peak memory 300860 kb
Host smart-e71697d1-7065-4048-b055-1f208609b914
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317665115 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_ha
ndler_stress_all.1317665115
Directory /workspace/32.alert_handler_stress_all/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all.1131741873
Short name T245
Test name
Test status
Simulation time 61845662261 ps
CPU time 3275.02 seconds
Started Feb 21 03:56:30 PM PST 24
Finished Feb 21 04:51:06 PM PST 24
Peak memory 297748 kb
Host smart-f7581ddf-f889-4138-8f63-9da71128eb2b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131741873 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_ha
ndler_stress_all.1131741873
Directory /workspace/35.alert_handler_stress_all/latest

Test location /workspace/coverage/default/38.alert_handler_ping_timeout.1204399725
Short name T318
Test name
Test status
Simulation time 12428718962 ps
CPU time 468.26 seconds
Started Feb 21 03:57:02 PM PST 24
Finished Feb 21 04:04:51 PM PST 24
Peak memory 246968 kb
Host smart-0c57fdb7-df82-4e9a-a406-00b78c234b17
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204399725 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_ping_timeout.1204399725
Directory /workspace/38.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all.3380161128
Short name T120
Test name
Test status
Simulation time 16227873678 ps
CPU time 541.96 seconds
Started Feb 21 03:57:48 PM PST 24
Finished Feb 21 04:06:52 PM PST 24
Peak memory 256508 kb
Host smart-7b4c3d72-ce76-42f0-b209-3738a781df08
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380161128 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_ha
ndler_stress_all.3380161128
Directory /workspace/47.alert_handler_stress_all/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all.2567500517
Short name T97
Test name
Test status
Simulation time 14851379768 ps
CPU time 1426.94 seconds
Started Feb 21 03:57:22 PM PST 24
Finished Feb 21 04:21:09 PM PST 24
Peak memory 288528 kb
Host smart-8306736b-44fe-487c-a2c3-2cb5238fa3dd
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567500517 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_ha
ndler_stress_all.2567500517
Directory /workspace/43.alert_handler_stress_all/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all.1398779090
Short name T30
Test name
Test status
Simulation time 52849945911 ps
CPU time 2934.02 seconds
Started Feb 21 03:55:18 PM PST 24
Finished Feb 21 04:44:13 PM PST 24
Peak memory 302148 kb
Host smart-f0d4319b-8623-4dff-8e55-4ba78e2ae3dd
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398779090 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_ha
ndler_stress_all.1398779090
Directory /workspace/19.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.2140194570
Short name T132
Test name
Test status
Simulation time 7469391133 ps
CPU time 156.83 seconds
Started Feb 21 12:43:38 PM PST 24
Finished Feb 21 12:46:15 PM PST 24
Peak memory 265004 kb
Host smart-cd7a4a57-3a03-4a87-ad99-139f2f52aeaf
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2140194570 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shadow_reg_erro
rs.2140194570
Directory /workspace/2.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.3854246060
Short name T767
Test name
Test status
Simulation time 30931270 ps
CPU time 1.21 seconds
Started Feb 21 12:43:22 PM PST 24
Finished Feb 21 12:43:24 PM PST 24
Peak memory 234448 kb
Host smart-71ff491a-696f-4196-9938-2284b4f8dd78
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3854246060 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_intr_test.3854246060
Directory /workspace/0.alert_handler_intr_test/latest

Test location /workspace/coverage/default/11.alert_handler_ping_timeout.531196564
Short name T320
Test name
Test status
Simulation time 10182543637 ps
CPU time 219.09 seconds
Started Feb 21 03:54:47 PM PST 24
Finished Feb 21 03:58:27 PM PST 24
Peak memory 247128 kb
Host smart-f03fb690-6c3f-46a5-86e8-66030f86740c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531196564 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_ping_timeout.531196564
Directory /workspace/11.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_random_classes.3999622975
Short name T256
Test name
Test status
Simulation time 335403922 ps
CPU time 10.34 seconds
Started Feb 21 03:54:47 PM PST 24
Finished Feb 21 03:54:58 PM PST 24
Peak memory 248252 kb
Host smart-8a5bfeac-46fa-4efb-b4ad-0f80d1bd7535
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39996
22975 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_classes.3999622975
Directory /workspace/11.alert_handler_random_classes/latest

Test location /workspace/coverage/default/11.alert_handler_sig_int_fail.2436185863
Short name T269
Test name
Test status
Simulation time 621327639 ps
CPU time 45.32 seconds
Started Feb 21 03:54:45 PM PST 24
Finished Feb 21 03:55:31 PM PST 24
Peak memory 254556 kb
Host smart-fe775e56-fab4-407f-82e9-1e45cc0f9b57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24361
85863 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_sig_int_fail.2436185863
Directory /workspace/11.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/14.alert_handler_lpg.529403939
Short name T327
Test name
Test status
Simulation time 23477778273 ps
CPU time 1289.03 seconds
Started Feb 21 03:54:45 PM PST 24
Finished Feb 21 04:16:16 PM PST 24
Peak memory 272584 kb
Host smart-6eb2c515-6024-4472-913a-a0dd546687cc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=529403939 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg.529403939
Directory /workspace/14.alert_handler_lpg/latest

Test location /workspace/coverage/default/19.alert_handler_sig_int_fail.3203461869
Short name T20
Test name
Test status
Simulation time 68498706 ps
CPU time 8.54 seconds
Started Feb 21 03:55:57 PM PST 24
Finished Feb 21 03:56:05 PM PST 24
Peak memory 252332 kb
Host smart-fed8b497-b3a9-485f-8e24-43f2a41c4439
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32034
61869 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_sig_int_fail.3203461869
Directory /workspace/19.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all_with_rand_reset.3747174063
Short name T231
Test name
Test status
Simulation time 250762868462 ps
CPU time 1870.14 seconds
Started Feb 21 03:55:59 PM PST 24
Finished Feb 21 04:27:10 PM PST 24
Peak memory 281176 kb
Host smart-258eaa10-dcc6-44c0-878a-af521e5c20d3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747174063 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 25.alert_handler_stress_all_with_rand_reset.3747174063
Directory /workspace/25.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all_with_rand_reset.3584267048
Short name T233
Test name
Test status
Simulation time 76499544199 ps
CPU time 4298.39 seconds
Started Feb 21 03:56:08 PM PST 24
Finished Feb 21 05:07:48 PM PST 24
Peak memory 305096 kb
Host smart-9f8cdaaa-b611-41d7-8cf7-b875f8e18283
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584267048 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.alert_handler_stress_all_with_rand_reset.3584267048
Directory /workspace/27.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.alert_handler_sig_int_fail.1047255256
Short name T286
Test name
Test status
Simulation time 3106809114 ps
CPU time 42.73 seconds
Started Feb 21 03:56:06 PM PST 24
Finished Feb 21 03:56:51 PM PST 24
Peak memory 246820 kb
Host smart-1c191c00-201e-430c-86b5-8a9120af8086
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10472
55256 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_sig_int_fail.1047255256
Directory /workspace/28.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/3.alert_handler_lpg.2789314655
Short name T660
Test name
Test status
Simulation time 9434217975 ps
CPU time 742.84 seconds
Started Feb 21 03:53:47 PM PST 24
Finished Feb 21 04:06:12 PM PST 24
Peak memory 272340 kb
Host smart-c6b2e13f-8738-4b5b-a7aa-3669ba392ce0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789314655 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg.2789314655
Directory /workspace/3.alert_handler_lpg/latest

Test location /workspace/coverage/default/31.alert_handler_esc_alert_accum.93526206
Short name T18
Test name
Test status
Simulation time 130506965 ps
CPU time 12.78 seconds
Started Feb 21 03:56:10 PM PST 24
Finished Feb 21 03:56:24 PM PST 24
Peak memory 255220 kb
Host smart-11995298-8731-44ee-b722-6e24849f7f62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93526
206 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_alert_accum.93526206
Directory /workspace/31.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/49.alert_handler_sig_int_fail.3373841782
Short name T241
Test name
Test status
Simulation time 251399266 ps
CPU time 35.01 seconds
Started Feb 21 03:58:04 PM PST 24
Finished Feb 21 03:58:40 PM PST 24
Peak memory 246920 kb
Host smart-bee3efed-c1f5-4905-99b5-047c6b6c7713
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33738
41782 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_sig_int_fail.3373841782
Directory /workspace/49.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all.2179064478
Short name T285
Test name
Test status
Simulation time 53960258087 ps
CPU time 1626.44 seconds
Started Feb 21 03:54:36 PM PST 24
Finished Feb 21 04:21:43 PM PST 24
Peak memory 282740 kb
Host smart-28233cca-4102-47ea-baca-46a84dff0c2b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179064478 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_han
dler_stress_all.2179064478
Directory /workspace/9.alert_handler_stress_all/latest

Test location /workspace/coverage/default/0.alert_handler_entropy_stress.1595542540
Short name T230
Test name
Test status
Simulation time 360899852 ps
CPU time 12.38 seconds
Started Feb 21 03:53:37 PM PST 24
Finished Feb 21 03:53:49 PM PST 24
Peak memory 240048 kb
Host smart-93032aab-4b0b-4016-a8e2-2f5bde378e4d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1595542540 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy_stress.1595542540
Directory /workspace/0.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all.21080619
Short name T602
Test name
Test status
Simulation time 90236017257 ps
CPU time 1312.25 seconds
Started Feb 21 03:54:47 PM PST 24
Finished Feb 21 04:16:40 PM PST 24
Peak memory 288768 kb
Host smart-1e8ac263-d9b1-4d34-a21c-91d8d9548955
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21080619 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_hand
ler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_hand
ler_stress_all.21080619
Directory /workspace/11.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.4120624180
Short name T171
Test name
Test status
Simulation time 188371364 ps
CPU time 3.88 seconds
Started Feb 21 12:43:31 PM PST 24
Finished Feb 21 12:43:35 PM PST 24
Peak memory 236216 kb
Host smart-2acf4290-dd73-43f6-95ce-849b5cb1e4ac
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4120624180 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_intg_err.4120624180
Directory /workspace/0.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.3697484556
Short name T152
Test name
Test status
Simulation time 24674870425 ps
CPU time 959.97 seconds
Started Feb 21 12:43:45 PM PST 24
Finished Feb 21 12:59:50 PM PST 24
Peak memory 265092 kb
Host smart-cd231485-f373-4c22-9ffa-ba8a78fe7c0d
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697484556 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 15.alert_handler_shadow_reg_errors_with_csr_rw.3697484556
Directory /workspace/15.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.1832160999
Short name T170
Test name
Test status
Simulation time 38686572 ps
CPU time 2.46 seconds
Started Feb 21 12:43:32 PM PST 24
Finished Feb 21 12:43:35 PM PST 24
Peak memory 236240 kb
Host smart-1d5b0861-8913-4383-8e60-0b2ed5713b75
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1832160999 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_intg_err.1832160999
Directory /workspace/2.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.562680412
Short name T141
Test name
Test status
Simulation time 1996496954 ps
CPU time 202.54 seconds
Started Feb 21 12:43:18 PM PST 24
Finished Feb 21 12:46:41 PM PST 24
Peak memory 269940 kb
Host smart-3c50e896-deea-44ae-b252-f2cbbe9aa1c3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=562680412 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shadow_reg_error
s.562680412
Directory /workspace/0.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.1982665912
Short name T180
Test name
Test status
Simulation time 46115755 ps
CPU time 3.01 seconds
Started Feb 21 12:43:26 PM PST 24
Finished Feb 21 12:43:30 PM PST 24
Peak memory 236128 kb
Host smart-0845d302-1402-4944-9b4a-2e4766d40d6c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1982665912 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_intg_err.1982665912
Directory /workspace/1.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.4169145964
Short name T166
Test name
Test status
Simulation time 162324550 ps
CPU time 3.64 seconds
Started Feb 21 12:43:31 PM PST 24
Finished Feb 21 12:43:36 PM PST 24
Peak memory 236136 kb
Host smart-4d12f77c-04f9-4068-98a2-6afe38467672
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4169145964 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_intg_err.4169145964
Directory /workspace/10.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.2675213807
Short name T157
Test name
Test status
Simulation time 7249457664 ps
CPU time 457.33 seconds
Started Feb 21 12:43:57 PM PST 24
Finished Feb 21 12:51:35 PM PST 24
Peak memory 265112 kb
Host smart-955f380e-caf1-4114-b342-e6cd8a10ccbc
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675213807 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 13.alert_handler_shadow_reg_errors_with_csr_rw.2675213807
Directory /workspace/13.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.3954433969
Short name T175
Test name
Test status
Simulation time 7394817866 ps
CPU time 61.93 seconds
Started Feb 21 12:43:31 PM PST 24
Finished Feb 21 12:44:34 PM PST 24
Peak memory 239216 kb
Host smart-ede8fb8b-3fd4-4818-8ea1-0dd0e92ac200
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3954433969 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_intg_err.3954433969
Directory /workspace/13.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.729291300
Short name T162
Test name
Test status
Simulation time 62452703 ps
CPU time 2.42 seconds
Started Feb 21 12:43:39 PM PST 24
Finished Feb 21 12:43:42 PM PST 24
Peak memory 236192 kb
Host smart-ed3c0175-00e6-4719-8889-3b55887e9dc9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=729291300 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_intg_err.729291300
Directory /workspace/12.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.3790845967
Short name T174
Test name
Test status
Simulation time 155251432 ps
CPU time 25.79 seconds
Started Feb 21 12:43:56 PM PST 24
Finished Feb 21 12:44:23 PM PST 24
Peak memory 239428 kb
Host smart-bd5a0d55-ebc4-4ee0-9b1f-9ae25215ef7c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3790845967 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_intg_err.3790845967
Directory /workspace/14.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.1395383436
Short name T176
Test name
Test status
Simulation time 57727010 ps
CPU time 2.29 seconds
Started Feb 21 12:43:54 PM PST 24
Finished Feb 21 12:43:58 PM PST 24
Peak memory 236444 kb
Host smart-1975ecea-1369-4313-af55-f36b6fa07702
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1395383436 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_intg_err.1395383436
Directory /workspace/18.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.1074509520
Short name T173
Test name
Test status
Simulation time 2801925569 ps
CPU time 41.68 seconds
Started Feb 21 12:43:45 PM PST 24
Finished Feb 21 12:44:31 PM PST 24
Peak memory 236380 kb
Host smart-7b0722e7-72ff-4fc5-8156-fa72cfe7c6e7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1074509520 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_intg_err.1074509520
Directory /workspace/19.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.451299820
Short name T169
Test name
Test status
Simulation time 61854220 ps
CPU time 1.98 seconds
Started Feb 21 12:43:27 PM PST 24
Finished Feb 21 12:43:30 PM PST 24
Peak memory 235352 kb
Host smart-b0ef2f65-38f7-4b84-915d-fc3d4ea9356a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=451299820 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_intg_err.451299820
Directory /workspace/4.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.962099221
Short name T172
Test name
Test status
Simulation time 702298454 ps
CPU time 4.14 seconds
Started Feb 21 12:44:01 PM PST 24
Finished Feb 21 12:44:06 PM PST 24
Peak memory 236264 kb
Host smart-60e42dd7-37d9-4133-bc64-7d2e3c805ce4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=962099221 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_intg_err.962099221
Directory /workspace/6.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.3559384335
Short name T182
Test name
Test status
Simulation time 611903195 ps
CPU time 41.5 seconds
Started Feb 21 12:43:16 PM PST 24
Finished Feb 21 12:43:58 PM PST 24
Peak memory 239192 kb
Host smart-1145d7a5-47d0-48cb-86a0-d591b21d8c3c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3559384335 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_intg_err.3559384335
Directory /workspace/7.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.1622773401
Short name T181
Test name
Test status
Simulation time 120906009 ps
CPU time 2.43 seconds
Started Feb 21 12:43:41 PM PST 24
Finished Feb 21 12:43:44 PM PST 24
Peak memory 236528 kb
Host smart-9679ded9-0308-4b84-8a32-84c8d91f60d9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1622773401 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_intg_err.1622773401
Directory /workspace/8.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.741379774
Short name T359
Test name
Test status
Simulation time 25846725953 ps
CPU time 284.15 seconds
Started Feb 21 12:43:52 PM PST 24
Finished Feb 21 12:48:39 PM PST 24
Peak memory 239616 kb
Host smart-dd322fa4-b19e-4431-a6c9-0d9d9e02ed87
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=741379774 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_aliasing.741379774
Directory /workspace/0.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.432336399
Short name T360
Test name
Test status
Simulation time 842666693 ps
CPU time 97.85 seconds
Started Feb 21 12:43:39 PM PST 24
Finished Feb 21 12:45:18 PM PST 24
Peak memory 236140 kb
Host smart-cb537a96-1a5f-486a-8346-27a5846532b4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=432336399 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_bit_bash.432336399
Directory /workspace/0.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.2632800215
Short name T777
Test name
Test status
Simulation time 57426154 ps
CPU time 4.6 seconds
Started Feb 21 12:43:47 PM PST 24
Finished Feb 21 12:43:57 PM PST 24
Peak memory 240144 kb
Host smart-37a79cbc-619f-40bd-9873-f88e8da8bbda
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2632800215 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_hw_reset.2632800215
Directory /workspace/0.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.413484662
Short name T348
Test name
Test status
Simulation time 255030573 ps
CPU time 4.91 seconds
Started Feb 21 12:43:43 PM PST 24
Finished Feb 21 12:43:51 PM PST 24
Peak memory 237180 kb
Host smart-a5115ca7-2fb1-41d6-b577-4cc0dd2d08f5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413484662 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 0.alert_handler_csr_mem_rw_with_rand_reset.413484662
Directory /workspace/0.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.752694494
Short name T819
Test name
Test status
Simulation time 52336124 ps
CPU time 5.29 seconds
Started Feb 21 12:43:53 PM PST 24
Finished Feb 21 12:44:01 PM PST 24
Peak memory 240028 kb
Host smart-d780edf4-6566-4cd8-a28c-c52ea9716b5e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=752694494 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_rw.752694494
Directory /workspace/0.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.1938751772
Short name T190
Test name
Test status
Simulation time 102094031 ps
CPU time 11.82 seconds
Started Feb 21 12:43:44 PM PST 24
Finished Feb 21 12:43:59 PM PST 24
Peak memory 240156 kb
Host smart-f17ebf35-73b8-44e8-8f2c-0e72bd41eab7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1938751772 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_same_csr_out
standing.1938751772
Directory /workspace/0.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.1803483999
Short name T127
Test name
Test status
Simulation time 3803117965 ps
CPU time 260.36 seconds
Started Feb 21 12:43:51 PM PST 24
Finished Feb 21 12:48:14 PM PST 24
Peak memory 265080 kb
Host smart-ce527001-5ffa-485f-8819-1d55e0f49856
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803483999 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.alert_handler_shadow_reg_errors_with_csr_rw.1803483999
Directory /workspace/0.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.1716141801
Short name T712
Test name
Test status
Simulation time 587690672 ps
CPU time 12.39 seconds
Started Feb 21 12:43:41 PM PST 24
Finished Feb 21 12:43:54 PM PST 24
Peak memory 248408 kb
Host smart-c567b9ad-6604-494a-8678-565ce37a297f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1716141801 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_errors.1716141801
Directory /workspace/0.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.960481068
Short name T808
Test name
Test status
Simulation time 1097024217 ps
CPU time 160.07 seconds
Started Feb 21 12:43:49 PM PST 24
Finished Feb 21 12:46:33 PM PST 24
Peak memory 240164 kb
Host smart-11f4c2b3-96dd-4f61-adc4-a81b590b2534
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=960481068 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_aliasing.960481068
Directory /workspace/1.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.113566501
Short name T747
Test name
Test status
Simulation time 2944603965 ps
CPU time 178.96 seconds
Started Feb 21 12:43:27 PM PST 24
Finished Feb 21 12:46:27 PM PST 24
Peak memory 240216 kb
Host smart-36e49242-7520-4c7b-8c2f-818ce1977b0b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=113566501 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_bit_bash.113566501
Directory /workspace/1.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.2486198379
Short name T771
Test name
Test status
Simulation time 75391510 ps
CPU time 6.09 seconds
Started Feb 21 12:43:33 PM PST 24
Finished Feb 21 12:43:40 PM PST 24
Peak memory 240152 kb
Host smart-26563309-6e9a-4bdb-925f-dbf581dfda97
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2486198379 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_hw_reset.2486198379
Directory /workspace/1.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.718218338
Short name T803
Test name
Test status
Simulation time 113601388 ps
CPU time 7.95 seconds
Started Feb 21 12:43:45 PM PST 24
Finished Feb 21 12:43:55 PM PST 24
Peak memory 250504 kb
Host smart-c6a97e1c-a034-4e09-9cda-475edc085ade
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718218338 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 1.alert_handler_csr_mem_rw_with_rand_reset.718218338
Directory /workspace/1.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.1675283307
Short name T765
Test name
Test status
Simulation time 346626262 ps
CPU time 8.92 seconds
Started Feb 21 12:43:22 PM PST 24
Finished Feb 21 12:43:32 PM PST 24
Peak memory 236184 kb
Host smart-4fa2bbec-8821-4616-99ba-294fff2df9cc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1675283307 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_rw.1675283307
Directory /workspace/1.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.4008403134
Short name T789
Test name
Test status
Simulation time 11801211 ps
CPU time 1.21 seconds
Started Feb 21 12:43:17 PM PST 24
Finished Feb 21 12:43:19 PM PST 24
Peak memory 235312 kb
Host smart-b1fd88ba-85d6-427b-a742-c0e90cbcdbf4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4008403134 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_intr_test.4008403134
Directory /workspace/1.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.3598062809
Short name T774
Test name
Test status
Simulation time 325877951 ps
CPU time 20.09 seconds
Started Feb 21 12:43:26 PM PST 24
Finished Feb 21 12:43:47 PM PST 24
Peak memory 244304 kb
Host smart-6e86abe9-ea9c-4389-a758-8e4284918086
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3598062809 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_same_csr_out
standing.3598062809
Directory /workspace/1.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.3927739606
Short name T139
Test name
Test status
Simulation time 3998974103 ps
CPU time 257.12 seconds
Started Feb 21 12:43:16 PM PST 24
Finished Feb 21 12:47:34 PM PST 24
Peak memory 264984 kb
Host smart-fc036c98-4227-4117-b82b-8367a22c1674
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3927739606 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shadow_reg_erro
rs.3927739606
Directory /workspace/1.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.1910575248
Short name T355
Test name
Test status
Simulation time 18830031207 ps
CPU time 551.71 seconds
Started Feb 21 12:43:20 PM PST 24
Finished Feb 21 12:52:32 PM PST 24
Peak memory 265116 kb
Host smart-ec046389-6f9f-4639-a904-1b20f3b6f5ab
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910575248 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.alert_handler_shadow_reg_errors_with_csr_rw.1910575248
Directory /workspace/1.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.2182511592
Short name T725
Test name
Test status
Simulation time 86040264 ps
CPU time 4.21 seconds
Started Feb 21 12:43:37 PM PST 24
Finished Feb 21 12:43:42 PM PST 24
Peak memory 239656 kb
Host smart-549819eb-a500-4c99-80ff-4263172c868c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2182511592 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_errors.2182511592
Directory /workspace/1.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.1135928585
Short name T826
Test name
Test status
Simulation time 74406409 ps
CPU time 5.86 seconds
Started Feb 21 12:43:27 PM PST 24
Finished Feb 21 12:43:34 PM PST 24
Peak memory 238184 kb
Host smart-2c4572d4-c016-4f49-9b82-d0a4eabf4ba3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135928585 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 10.alert_handler_csr_mem_rw_with_rand_reset.1135928585
Directory /workspace/10.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.2320673080
Short name T810
Test name
Test status
Simulation time 254988880 ps
CPU time 5.39 seconds
Started Feb 21 12:43:47 PM PST 24
Finished Feb 21 12:43:57 PM PST 24
Peak memory 239984 kb
Host smart-4315fe38-5b77-47c5-9cbf-2945e951728a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2320673080 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_rw.2320673080
Directory /workspace/10.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.2776509003
Short name T755
Test name
Test status
Simulation time 10502591 ps
CPU time 1.55 seconds
Started Feb 21 12:43:44 PM PST 24
Finished Feb 21 12:43:47 PM PST 24
Peak memory 236236 kb
Host smart-28d5b1cd-2f86-41b3-81c4-5c5abbb35aef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2776509003 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_intr_test.2776509003
Directory /workspace/10.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.2299960005
Short name T817
Test name
Test status
Simulation time 5386749020 ps
CPU time 35.93 seconds
Started Feb 21 12:43:47 PM PST 24
Finished Feb 21 12:44:27 PM PST 24
Peak memory 248320 kb
Host smart-6456ee9c-2248-42fc-bdaf-70ea13bef43e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2299960005 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_same_csr_ou
tstanding.2299960005
Directory /workspace/10.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.3597645789
Short name T134
Test name
Test status
Simulation time 1977896515 ps
CPU time 129.33 seconds
Started Feb 21 12:43:40 PM PST 24
Finished Feb 21 12:45:50 PM PST 24
Peak memory 256848 kb
Host smart-52c21cbe-aeed-4863-9916-fcb7382839e7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3597645789 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shadow_reg_err
ors.3597645789
Directory /workspace/10.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.810765185
Short name T713
Test name
Test status
Simulation time 115606804 ps
CPU time 6.51 seconds
Started Feb 21 12:43:55 PM PST 24
Finished Feb 21 12:44:02 PM PST 24
Peak memory 247916 kb
Host smart-6c127495-f6f0-4d1d-be61-b246407da00e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=810765185 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_errors.810765185
Directory /workspace/10.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.133855948
Short name T353
Test name
Test status
Simulation time 60550972 ps
CPU time 8.99 seconds
Started Feb 21 12:43:39 PM PST 24
Finished Feb 21 12:43:49 PM PST 24
Peak memory 250568 kb
Host smart-e0920923-8abd-48b7-9b1b-aa85e1742356
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133855948 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 11.alert_handler_csr_mem_rw_with_rand_reset.133855948
Directory /workspace/11.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.3934275755
Short name T745
Test name
Test status
Simulation time 119226961 ps
CPU time 5.26 seconds
Started Feb 21 12:43:42 PM PST 24
Finished Feb 21 12:43:49 PM PST 24
Peak memory 236192 kb
Host smart-d07cda7c-d68b-43cd-860b-aade9c2f8010
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3934275755 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_rw.3934275755
Directory /workspace/11.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.1704676873
Short name T347
Test name
Test status
Simulation time 10888866 ps
CPU time 1.51 seconds
Started Feb 21 12:43:42 PM PST 24
Finished Feb 21 12:43:46 PM PST 24
Peak memory 235396 kb
Host smart-d157ad72-b36a-4f83-b770-3add8197914f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1704676873 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_intr_test.1704676873
Directory /workspace/11.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.2582124153
Short name T179
Test name
Test status
Simulation time 345791300 ps
CPU time 20.93 seconds
Started Feb 21 12:43:42 PM PST 24
Finished Feb 21 12:44:06 PM PST 24
Peak memory 244392 kb
Host smart-5732315c-c660-4a41-88b2-12ad370ea931
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2582124153 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_same_csr_ou
tstanding.2582124153
Directory /workspace/11.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.33410899
Short name T142
Test name
Test status
Simulation time 54179942287 ps
CPU time 305.93 seconds
Started Feb 21 12:43:31 PM PST 24
Finished Feb 21 12:48:38 PM PST 24
Peak memory 265040 kb
Host smart-b8657917-af39-4b2a-a553-f6bfca10bd37
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=33410899 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shadow_reg_error
s.33410899
Directory /workspace/11.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.705840747
Short name T146
Test name
Test status
Simulation time 32343318479 ps
CPU time 536.36 seconds
Started Feb 21 12:43:44 PM PST 24
Finished Feb 21 12:52:43 PM PST 24
Peak memory 268592 kb
Host smart-cb91f03f-47db-4b32-a843-41ec966a8e93
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705840747 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 11.alert_handler_shadow_reg_errors_with_csr_rw.705840747
Directory /workspace/11.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.3043983083
Short name T714
Test name
Test status
Simulation time 451731997 ps
CPU time 25.91 seconds
Started Feb 21 12:43:38 PM PST 24
Finished Feb 21 12:44:05 PM PST 24
Peak memory 248480 kb
Host smart-c8bb1dbd-b602-4289-8a08-30cdd46a3e94
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3043983083 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_errors.3043983083
Directory /workspace/11.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.1326897946
Short name T816
Test name
Test status
Simulation time 55938100 ps
CPU time 3.71 seconds
Started Feb 21 12:43:57 PM PST 24
Finished Feb 21 12:44:01 PM PST 24
Peak memory 236676 kb
Host smart-46788ce7-3c8f-4e0e-9b55-3a30272928a1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1326897946 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_intg_err.1326897946
Directory /workspace/11.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.2624047503
Short name T822
Test name
Test status
Simulation time 208013023 ps
CPU time 7.78 seconds
Started Feb 21 12:43:48 PM PST 24
Finished Feb 21 12:44:01 PM PST 24
Peak memory 243324 kb
Host smart-fedd29b1-2cd3-4651-8025-83b57e9e4603
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624047503 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 12.alert_handler_csr_mem_rw_with_rand_reset.2624047503
Directory /workspace/12.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.2283891331
Short name T350
Test name
Test status
Simulation time 611828178 ps
CPU time 8.49 seconds
Started Feb 21 12:43:54 PM PST 24
Finished Feb 21 12:44:04 PM PST 24
Peak memory 240340 kb
Host smart-786727a1-19be-4bfd-99ad-f60f4a92f9f9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2283891331 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_rw.2283891331
Directory /workspace/12.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.103688574
Short name T738
Test name
Test status
Simulation time 9690299 ps
CPU time 1.45 seconds
Started Feb 21 12:43:34 PM PST 24
Finished Feb 21 12:43:36 PM PST 24
Peak memory 236356 kb
Host smart-b3d33ee6-a24a-4eaa-b36d-dee7e23f7fef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=103688574 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_intr_test.103688574
Directory /workspace/12.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.727703339
Short name T731
Test name
Test status
Simulation time 357936806 ps
CPU time 21.56 seconds
Started Feb 21 12:43:42 PM PST 24
Finished Feb 21 12:44:05 PM PST 24
Peak memory 244372 kb
Host smart-6199b8dd-8836-459f-9e6a-1884195f1c32
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=727703339 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_same_csr_out
standing.727703339
Directory /workspace/12.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.3659168530
Short name T156
Test name
Test status
Simulation time 7744921691 ps
CPU time 461.39 seconds
Started Feb 21 12:43:45 PM PST 24
Finished Feb 21 12:51:30 PM PST 24
Peak memory 265088 kb
Host smart-c98f382c-f999-450f-b7d6-648cb9db2496
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659168530 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 12.alert_handler_shadow_reg_errors_with_csr_rw.3659168530
Directory /workspace/12.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.2565921896
Short name T806
Test name
Test status
Simulation time 1435579700 ps
CPU time 22.54 seconds
Started Feb 21 12:43:45 PM PST 24
Finished Feb 21 12:44:12 PM PST 24
Peak memory 248080 kb
Host smart-5f4661ed-4e44-4393-a56c-f1b699d20876
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2565921896 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_errors.2565921896
Directory /workspace/12.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.2357932896
Short name T763
Test name
Test status
Simulation time 152164733 ps
CPU time 11.09 seconds
Started Feb 21 12:43:23 PM PST 24
Finished Feb 21 12:43:37 PM PST 24
Peak memory 249436 kb
Host smart-f720eb5e-80ad-4e88-9de3-30135aab0473
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357932896 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 13.alert_handler_csr_mem_rw_with_rand_reset.2357932896
Directory /workspace/13.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.4130299030
Short name T780
Test name
Test status
Simulation time 83835308 ps
CPU time 3.24 seconds
Started Feb 21 12:43:56 PM PST 24
Finished Feb 21 12:44:00 PM PST 24
Peak memory 236472 kb
Host smart-c2f7afc2-3600-4a5e-9528-6283dbf1bdf8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4130299030 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_rw.4130299030
Directory /workspace/13.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.3890548003
Short name T815
Test name
Test status
Simulation time 10177254 ps
CPU time 1.25 seconds
Started Feb 21 12:43:43 PM PST 24
Finished Feb 21 12:43:46 PM PST 24
Peak memory 234416 kb
Host smart-38954b22-cf7e-415e-9f3a-ffada21556de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3890548003 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_intr_test.3890548003
Directory /workspace/13.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.1754833877
Short name T722
Test name
Test status
Simulation time 590832940 ps
CPU time 22.46 seconds
Started Feb 21 12:43:56 PM PST 24
Finished Feb 21 12:44:19 PM PST 24
Peak memory 243792 kb
Host smart-eb5ada60-89f4-4b53-8a88-978ca7df13ab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1754833877 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_same_csr_ou
tstanding.1754833877
Directory /workspace/13.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.3463967183
Short name T133
Test name
Test status
Simulation time 17983835020 ps
CPU time 333.07 seconds
Started Feb 21 12:44:01 PM PST 24
Finished Feb 21 12:49:35 PM PST 24
Peak memory 265112 kb
Host smart-1ba29542-e7f7-4f4a-82b3-c57e69224e6f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3463967183 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shadow_reg_err
ors.3463967183
Directory /workspace/13.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.1271549164
Short name T768
Test name
Test status
Simulation time 66027701 ps
CPU time 7.97 seconds
Started Feb 21 12:43:44 PM PST 24
Finished Feb 21 12:43:56 PM PST 24
Peak memory 248324 kb
Host smart-be969df7-3568-49f8-baf5-185b6bf9c615
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1271549164 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_errors.1271549164
Directory /workspace/13.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.2591609687
Short name T743
Test name
Test status
Simulation time 57629840 ps
CPU time 4.92 seconds
Started Feb 21 12:43:40 PM PST 24
Finished Feb 21 12:43:45 PM PST 24
Peak memory 240228 kb
Host smart-8ece06b2-6596-4edd-b14a-44565e2a5682
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591609687 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 14.alert_handler_csr_mem_rw_with_rand_reset.2591609687
Directory /workspace/14.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.1406577048
Short name T194
Test name
Test status
Simulation time 67147517 ps
CPU time 3.28 seconds
Started Feb 21 12:43:38 PM PST 24
Finished Feb 21 12:43:42 PM PST 24
Peak memory 236220 kb
Host smart-17c16cc1-aa66-4aba-a08f-8a9b0a3a491e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1406577048 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_rw.1406577048
Directory /workspace/14.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.418624514
Short name T752
Test name
Test status
Simulation time 11765764 ps
CPU time 1.35 seconds
Started Feb 21 12:43:43 PM PST 24
Finished Feb 21 12:43:46 PM PST 24
Peak memory 234504 kb
Host smart-bcfd1c6e-901e-48fa-921e-0f3e0ab92afc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=418624514 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_intr_test.418624514
Directory /workspace/14.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.1896767903
Short name T792
Test name
Test status
Simulation time 3128823071 ps
CPU time 20.75 seconds
Started Feb 21 12:43:37 PM PST 24
Finished Feb 21 12:43:59 PM PST 24
Peak memory 244320 kb
Host smart-cb4f5c07-67b7-45f3-b44f-ce7af11a955b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1896767903 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_same_csr_ou
tstanding.1896767903
Directory /workspace/14.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.2323556234
Short name T147
Test name
Test status
Simulation time 4817073479 ps
CPU time 92.98 seconds
Started Feb 21 12:43:43 PM PST 24
Finished Feb 21 12:45:19 PM PST 24
Peak memory 256524 kb
Host smart-52179175-05b3-43ca-a466-d6abada76f03
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2323556234 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shadow_reg_err
ors.2323556234
Directory /workspace/14.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.3848971255
Short name T718
Test name
Test status
Simulation time 421061011 ps
CPU time 7.97 seconds
Started Feb 21 12:43:43 PM PST 24
Finished Feb 21 12:43:54 PM PST 24
Peak memory 248204 kb
Host smart-af038cdc-c0d8-4e65-9c74-68a4a3d2006f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3848971255 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_errors.3848971255
Directory /workspace/14.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.1841359168
Short name T352
Test name
Test status
Simulation time 177883819 ps
CPU time 5.64 seconds
Started Feb 21 12:43:39 PM PST 24
Finished Feb 21 12:43:45 PM PST 24
Peak memory 248472 kb
Host smart-3c9f65f8-a261-4334-af97-8772ade00b7a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841359168 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 15.alert_handler_csr_mem_rw_with_rand_reset.1841359168
Directory /workspace/15.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.3650050173
Short name T814
Test name
Test status
Simulation time 34647537 ps
CPU time 5.74 seconds
Started Feb 21 12:43:53 PM PST 24
Finished Feb 21 12:44:01 PM PST 24
Peak memory 240328 kb
Host smart-6847e508-17c4-48f4-ba44-016e1aa49656
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3650050173 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_rw.3650050173
Directory /workspace/15.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.4070858339
Short name T793
Test name
Test status
Simulation time 16697349 ps
CPU time 1.34 seconds
Started Feb 21 12:43:39 PM PST 24
Finished Feb 21 12:43:41 PM PST 24
Peak memory 234576 kb
Host smart-b063c48e-cbdd-45a7-a867-67bb6d3d8cbe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4070858339 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_intr_test.4070858339
Directory /workspace/15.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.3894952323
Short name T715
Test name
Test status
Simulation time 2159381319 ps
CPU time 39.17 seconds
Started Feb 21 12:43:36 PM PST 24
Finished Feb 21 12:44:15 PM PST 24
Peak memory 248384 kb
Host smart-583e8cb1-206f-42b0-91f7-683f3fc46302
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3894952323 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_same_csr_ou
tstanding.3894952323
Directory /workspace/15.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.558664167
Short name T759
Test name
Test status
Simulation time 252234836 ps
CPU time 13.98 seconds
Started Feb 21 12:43:50 PM PST 24
Finished Feb 21 12:44:08 PM PST 24
Peak memory 248196 kb
Host smart-050d676b-9704-48c3-b68e-67d19e6d8810
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=558664167 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_errors.558664167
Directory /workspace/15.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.2157200879
Short name T799
Test name
Test status
Simulation time 2616583663 ps
CPU time 49.78 seconds
Started Feb 21 12:43:37 PM PST 24
Finished Feb 21 12:44:27 PM PST 24
Peak memory 239108 kb
Host smart-3030a84b-f57e-4c5a-81c2-0d6bf355ed5f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2157200879 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_intg_err.2157200879
Directory /workspace/15.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.1878038708
Short name T349
Test name
Test status
Simulation time 568550262 ps
CPU time 12.31 seconds
Started Feb 21 12:43:52 PM PST 24
Finished Feb 21 12:44:08 PM PST 24
Peak memory 250524 kb
Host smart-2a7deced-44ae-496e-8f6a-c22e6aeaa023
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878038708 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 16.alert_handler_csr_mem_rw_with_rand_reset.1878038708
Directory /workspace/16.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.3801382630
Short name T724
Test name
Test status
Simulation time 190182013 ps
CPU time 4.82 seconds
Started Feb 21 12:43:43 PM PST 24
Finished Feb 21 12:43:50 PM PST 24
Peak memory 236208 kb
Host smart-cce1e60f-ce32-4503-a9fa-698d44eb33f2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3801382630 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_rw.3801382630
Directory /workspace/16.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.2829282310
Short name T795
Test name
Test status
Simulation time 8883286 ps
CPU time 1.52 seconds
Started Feb 21 12:43:47 PM PST 24
Finished Feb 21 12:43:54 PM PST 24
Peak memory 236372 kb
Host smart-83afa602-883d-4053-a52c-b9bbc3a829b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2829282310 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_intr_test.2829282310
Directory /workspace/16.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.751424888
Short name T800
Test name
Test status
Simulation time 353581672 ps
CPU time 21.85 seconds
Started Feb 21 12:43:43 PM PST 24
Finished Feb 21 12:44:08 PM PST 24
Peak memory 244460 kb
Host smart-b3b5f0a7-316e-4c31-9e28-18547bceeb49
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=751424888 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_same_csr_out
standing.751424888
Directory /workspace/16.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.2361949843
Short name T143
Test name
Test status
Simulation time 24006414596 ps
CPU time 445.54 seconds
Started Feb 21 12:43:45 PM PST 24
Finished Feb 21 12:51:15 PM PST 24
Peak memory 265060 kb
Host smart-d8fcd6fc-88f1-47ce-b607-c5bfbfe56e8d
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361949843 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 16.alert_handler_shadow_reg_errors_with_csr_rw.2361949843
Directory /workspace/16.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.3296957975
Short name T735
Test name
Test status
Simulation time 76202349 ps
CPU time 5.43 seconds
Started Feb 21 12:43:40 PM PST 24
Finished Feb 21 12:43:46 PM PST 24
Peak memory 247980 kb
Host smart-02a5e944-7473-4a20-b1cb-c48a93946e17
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3296957975 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_errors.3296957975
Directory /workspace/16.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.1484486602
Short name T790
Test name
Test status
Simulation time 34226563 ps
CPU time 2.17 seconds
Started Feb 21 12:43:32 PM PST 24
Finished Feb 21 12:43:35 PM PST 24
Peak memory 236836 kb
Host smart-4f62f9cc-27a1-4631-9532-a8e880c0ecfe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1484486602 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_intg_err.1484486602
Directory /workspace/16.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.2430263563
Short name T178
Test name
Test status
Simulation time 65361818 ps
CPU time 4.79 seconds
Started Feb 21 12:43:42 PM PST 24
Finished Feb 21 12:43:49 PM PST 24
Peak memory 240892 kb
Host smart-bb2ea19a-652c-42c7-8aae-57b815433fd6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430263563 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 17.alert_handler_csr_mem_rw_with_rand_reset.2430263563
Directory /workspace/17.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.466170982
Short name T786
Test name
Test status
Simulation time 28056244 ps
CPU time 3.92 seconds
Started Feb 21 12:43:40 PM PST 24
Finished Feb 21 12:43:44 PM PST 24
Peak memory 240112 kb
Host smart-4cc5ab91-906a-409b-96bf-5c0bad98f1fa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=466170982 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_rw.466170982
Directory /workspace/17.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.4190002354
Short name T811
Test name
Test status
Simulation time 12295642 ps
CPU time 1.58 seconds
Started Feb 21 12:43:43 PM PST 24
Finished Feb 21 12:43:47 PM PST 24
Peak memory 236296 kb
Host smart-0981ca93-877c-4306-995a-3c3bf7c97e7d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4190002354 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_intr_test.4190002354
Directory /workspace/17.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.1683748877
Short name T831
Test name
Test status
Simulation time 522743842 ps
CPU time 36.18 seconds
Started Feb 21 12:43:39 PM PST 24
Finished Feb 21 12:44:15 PM PST 24
Peak memory 244480 kb
Host smart-c187287c-2618-4e82-b7eb-0b4de39495e3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1683748877 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_same_csr_ou
tstanding.1683748877
Directory /workspace/17.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.3194230019
Short name T130
Test name
Test status
Simulation time 4540740544 ps
CPU time 151.67 seconds
Started Feb 21 12:43:39 PM PST 24
Finished Feb 21 12:46:11 PM PST 24
Peak memory 256804 kb
Host smart-656cd6b9-5b46-4118-a89e-590e2ce20a55
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3194230019 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shadow_reg_err
ors.3194230019
Directory /workspace/17.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.3739120878
Short name T140
Test name
Test status
Simulation time 21517336791 ps
CPU time 554.15 seconds
Started Feb 21 12:43:41 PM PST 24
Finished Feb 21 12:52:55 PM PST 24
Peak memory 265276 kb
Host smart-6af5e288-5544-47d7-a417-eb74b62c4adb
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739120878 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 17.alert_handler_shadow_reg_errors_with_csr_rw.3739120878
Directory /workspace/17.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.811203271
Short name T787
Test name
Test status
Simulation time 409353812 ps
CPU time 13.73 seconds
Started Feb 21 12:43:35 PM PST 24
Finished Feb 21 12:43:49 PM PST 24
Peak memory 252296 kb
Host smart-51a4ef5b-adab-4806-9e25-364dae75333b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=811203271 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_errors.811203271
Directory /workspace/17.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.2632340019
Short name T778
Test name
Test status
Simulation time 153043941 ps
CPU time 11.32 seconds
Started Feb 21 12:43:55 PM PST 24
Finished Feb 21 12:44:08 PM PST 24
Peak memory 241684 kb
Host smart-d21a70d4-2277-4145-a387-a8cfcb23b682
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632340019 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 18.alert_handler_csr_mem_rw_with_rand_reset.2632340019
Directory /workspace/18.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.3367221686
Short name T769
Test name
Test status
Simulation time 60582617 ps
CPU time 4.61 seconds
Started Feb 21 12:43:45 PM PST 24
Finished Feb 21 12:43:54 PM PST 24
Peak memory 235276 kb
Host smart-fc9a5265-814d-4425-936b-a11b49123349
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3367221686 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_rw.3367221686
Directory /workspace/18.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.2199338906
Short name T164
Test name
Test status
Simulation time 24565024 ps
CPU time 1.51 seconds
Started Feb 21 12:43:50 PM PST 24
Finished Feb 21 12:43:55 PM PST 24
Peak memory 236372 kb
Host smart-6d6435b3-c8b6-463e-bd81-22e388c83ef6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2199338906 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_intr_test.2199338906
Directory /workspace/18.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.3442046763
Short name T742
Test name
Test status
Simulation time 1148125247 ps
CPU time 18.77 seconds
Started Feb 21 12:43:47 PM PST 24
Finished Feb 21 12:44:10 PM PST 24
Peak memory 244408 kb
Host smart-9a09fc28-b1d5-41bf-8ca2-83d0a46e5ba3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3442046763 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_same_csr_ou
tstanding.3442046763
Directory /workspace/18.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.1373474580
Short name T155
Test name
Test status
Simulation time 6499179838 ps
CPU time 184.83 seconds
Started Feb 21 12:43:40 PM PST 24
Finished Feb 21 12:46:46 PM PST 24
Peak memory 265104 kb
Host smart-b2e91af2-265d-4f7a-9599-91e72e6dc608
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1373474580 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shadow_reg_err
ors.1373474580
Directory /workspace/18.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.833094992
Short name T807
Test name
Test status
Simulation time 189851088 ps
CPU time 13.95 seconds
Started Feb 21 12:43:57 PM PST 24
Finished Feb 21 12:44:12 PM PST 24
Peak memory 248168 kb
Host smart-af9f612a-04da-4b63-99e6-4af3819f4fd7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=833094992 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_errors.833094992
Directory /workspace/18.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.2970413762
Short name T830
Test name
Test status
Simulation time 426063108 ps
CPU time 7.82 seconds
Started Feb 21 12:43:49 PM PST 24
Finished Feb 21 12:44:01 PM PST 24
Peak memory 237004 kb
Host smart-9beab27e-05c7-449f-a563-c82b5f08c8c0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970413762 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 19.alert_handler_csr_mem_rw_with_rand_reset.2970413762
Directory /workspace/19.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.470310964
Short name T192
Test name
Test status
Simulation time 20314471 ps
CPU time 3.04 seconds
Started Feb 21 12:43:36 PM PST 24
Finished Feb 21 12:43:39 PM PST 24
Peak memory 238984 kb
Host smart-4c0375b9-2733-4d85-b330-4f7b78e6f149
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=470310964 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_rw.470310964
Directory /workspace/19.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.1561329233
Short name T784
Test name
Test status
Simulation time 20580012 ps
CPU time 1.29 seconds
Started Feb 21 12:43:47 PM PST 24
Finished Feb 21 12:43:52 PM PST 24
Peak memory 235448 kb
Host smart-07a6ac99-3585-42dc-9a6e-c0ce5c7025e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1561329233 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_intr_test.1561329233
Directory /workspace/19.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.451375140
Short name T729
Test name
Test status
Simulation time 88143304 ps
CPU time 11.48 seconds
Started Feb 21 12:43:45 PM PST 24
Finished Feb 21 12:44:00 PM PST 24
Peak memory 244368 kb
Host smart-f1fe8b8f-34e8-4c8c-9133-6083bbc84252
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=451375140 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_same_csr_out
standing.451375140
Directory /workspace/19.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.1092911349
Short name T821
Test name
Test status
Simulation time 4032307882 ps
CPU time 141.05 seconds
Started Feb 21 12:43:52 PM PST 24
Finished Feb 21 12:46:16 PM PST 24
Peak memory 264924 kb
Host smart-cd5c0532-27fc-4877-bd1d-e3612faf7be3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1092911349 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shadow_reg_err
ors.1092911349
Directory /workspace/19.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.4256105278
Short name T145
Test name
Test status
Simulation time 23736821319 ps
CPU time 403.01 seconds
Started Feb 21 12:43:37 PM PST 24
Finished Feb 21 12:50:20 PM PST 24
Peak memory 264996 kb
Host smart-c581d755-b5ed-4aa3-a02f-4579f50d9799
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256105278 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 19.alert_handler_shadow_reg_errors_with_csr_rw.4256105278
Directory /workspace/19.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.3910362336
Short name T749
Test name
Test status
Simulation time 787011508 ps
CPU time 10.77 seconds
Started Feb 21 12:43:42 PM PST 24
Finished Feb 21 12:43:54 PM PST 24
Peak memory 248460 kb
Host smart-2ca1b093-b341-422b-9bcf-c8b40c282f5e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3910362336 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_errors.3910362336
Directory /workspace/19.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.6031263
Short name T732
Test name
Test status
Simulation time 2069672916 ps
CPU time 110.76 seconds
Started Feb 21 12:43:18 PM PST 24
Finished Feb 21 12:45:10 PM PST 24
Peak memory 240152 kb
Host smart-bfa5cf0a-5fd9-46fc-b1be-8554e635b299
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=6031263 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_aliasing.6031263
Directory /workspace/2.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.2189868774
Short name T794
Test name
Test status
Simulation time 829416337 ps
CPU time 101.61 seconds
Started Feb 21 12:43:15 PM PST 24
Finished Feb 21 12:44:58 PM PST 24
Peak memory 240112 kb
Host smart-c0dd0be8-06e6-45fa-b346-20838c04a189
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2189868774 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_bit_bash.2189868774
Directory /workspace/2.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.1330856697
Short name T737
Test name
Test status
Simulation time 53728572 ps
CPU time 4.99 seconds
Started Feb 21 12:43:13 PM PST 24
Finished Feb 21 12:43:19 PM PST 24
Peak memory 240104 kb
Host smart-8655a5bd-9b1f-4930-926b-d40c2f7aa786
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1330856697 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_hw_reset.1330856697
Directory /workspace/2.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.804535430
Short name T177
Test name
Test status
Simulation time 375530295 ps
CPU time 7.56 seconds
Started Feb 21 12:43:43 PM PST 24
Finished Feb 21 12:43:53 PM PST 24
Peak memory 240252 kb
Host smart-7a95c10a-1ae1-42b3-a1b9-91de6411a4d2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804535430 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 2.alert_handler_csr_mem_rw_with_rand_reset.804535430
Directory /workspace/2.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.3321395627
Short name T798
Test name
Test status
Simulation time 64054886 ps
CPU time 3.18 seconds
Started Feb 21 12:43:44 PM PST 24
Finished Feb 21 12:43:49 PM PST 24
Peak memory 236232 kb
Host smart-a2784e63-8b56-46a5-a153-d635894e849f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3321395627 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_rw.3321395627
Directory /workspace/2.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.4000664018
Short name T229
Test name
Test status
Simulation time 13898559 ps
CPU time 1.39 seconds
Started Feb 21 12:43:32 PM PST 24
Finished Feb 21 12:43:34 PM PST 24
Peak memory 235452 kb
Host smart-cc83a53d-f1cc-4e43-8735-86d8c4b09c41
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4000664018 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_intr_test.4000664018
Directory /workspace/2.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.1916368146
Short name T802
Test name
Test status
Simulation time 199277003 ps
CPU time 12.24 seconds
Started Feb 21 12:43:43 PM PST 24
Finished Feb 21 12:43:58 PM PST 24
Peak memory 244420 kb
Host smart-992ccb33-d4fb-4be0-b340-46e6b23e67c1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1916368146 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_same_csr_out
standing.1916368146
Directory /workspace/2.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.525172687
Short name T148
Test name
Test status
Simulation time 24677641314 ps
CPU time 985.67 seconds
Started Feb 21 12:43:18 PM PST 24
Finished Feb 21 12:59:45 PM PST 24
Peak memory 265116 kb
Host smart-7d64f1d8-0def-4a7a-a43a-4d195e70ec6a
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525172687 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.alert_handler_shadow_reg_errors_with_csr_rw.525172687
Directory /workspace/2.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.2362234062
Short name T741
Test name
Test status
Simulation time 590839660 ps
CPU time 9.05 seconds
Started Feb 21 12:43:30 PM PST 24
Finished Feb 21 12:43:40 PM PST 24
Peak memory 248188 kb
Host smart-b45058cd-ddd3-4fdc-a4cf-a1be6c096e4a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2362234062 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_errors.2362234062
Directory /workspace/2.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.4264916929
Short name T828
Test name
Test status
Simulation time 18936539 ps
CPU time 1.39 seconds
Started Feb 21 12:43:35 PM PST 24
Finished Feb 21 12:43:37 PM PST 24
Peak memory 235404 kb
Host smart-e1a4b333-7be4-490d-835e-53793a0d0d56
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4264916929 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.alert_handler_intr_test.4264916929
Directory /workspace/20.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.1664697524
Short name T781
Test name
Test status
Simulation time 10177047 ps
CPU time 1.61 seconds
Started Feb 21 12:43:54 PM PST 24
Finished Feb 21 12:43:57 PM PST 24
Peak memory 236296 kb
Host smart-078a92a9-aff6-4a92-8702-e2211f5640a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1664697524 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.alert_handler_intr_test.1664697524
Directory /workspace/21.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.1211049774
Short name T825
Test name
Test status
Simulation time 11933928 ps
CPU time 1.26 seconds
Started Feb 21 12:43:52 PM PST 24
Finished Feb 21 12:43:56 PM PST 24
Peak memory 236224 kb
Host smart-dc71aec2-0c19-4170-b6cd-d9763cdade90
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1211049774 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.alert_handler_intr_test.1211049774
Directory /workspace/22.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.3248066369
Short name T744
Test name
Test status
Simulation time 31017582 ps
CPU time 1.22 seconds
Started Feb 21 12:43:43 PM PST 24
Finished Feb 21 12:43:47 PM PST 24
Peak memory 235240 kb
Host smart-45e365dd-1a8b-47d1-bfd0-7fdc4f3a70f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3248066369 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.alert_handler_intr_test.3248066369
Directory /workspace/23.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.435176105
Short name T758
Test name
Test status
Simulation time 12651840 ps
CPU time 1.27 seconds
Started Feb 21 12:43:48 PM PST 24
Finished Feb 21 12:43:53 PM PST 24
Peak memory 236160 kb
Host smart-a7406dda-2053-4d91-be42-507c951c60d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=435176105 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.alert_handler_intr_test.435176105
Directory /workspace/24.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.3810930348
Short name T754
Test name
Test status
Simulation time 12136590 ps
CPU time 1.59 seconds
Started Feb 21 12:43:45 PM PST 24
Finished Feb 21 12:43:51 PM PST 24
Peak memory 235464 kb
Host smart-a6f48cb4-7a19-4c9c-a34d-01695eae5695
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3810930348 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.alert_handler_intr_test.3810930348
Directory /workspace/25.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.30201113
Short name T342
Test name
Test status
Simulation time 6309649 ps
CPU time 1.31 seconds
Started Feb 21 12:43:53 PM PST 24
Finished Feb 21 12:43:57 PM PST 24
Peak memory 235340 kb
Host smart-bf66185f-1162-480b-bfd4-0479b839a85c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=30201113 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.alert_handler_intr_test.30201113
Directory /workspace/26.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.3480338814
Short name T750
Test name
Test status
Simulation time 9870871 ps
CPU time 1.29 seconds
Started Feb 21 12:43:37 PM PST 24
Finished Feb 21 12:43:38 PM PST 24
Peak memory 236308 kb
Host smart-4c4541c7-24d1-489a-9fd1-f3b8b9954d63
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3480338814 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.alert_handler_intr_test.3480338814
Directory /workspace/27.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.2723706857
Short name T740
Test name
Test status
Simulation time 16827056 ps
CPU time 1.24 seconds
Started Feb 21 12:43:53 PM PST 24
Finished Feb 21 12:43:57 PM PST 24
Peak memory 236360 kb
Host smart-82e25a9c-703c-40dc-a3c5-ee8524ad697e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2723706857 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.alert_handler_intr_test.2723706857
Directory /workspace/28.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.2252650464
Short name T776
Test name
Test status
Simulation time 11192224 ps
CPU time 1.55 seconds
Started Feb 21 12:43:42 PM PST 24
Finished Feb 21 12:43:46 PM PST 24
Peak memory 235452 kb
Host smart-d055921a-3c1b-4ccd-a54f-38d0dd8ba9f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2252650464 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.alert_handler_intr_test.2252650464
Directory /workspace/29.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.647181505
Short name T193
Test name
Test status
Simulation time 2274714807 ps
CPU time 68.05 seconds
Started Feb 21 12:43:30 PM PST 24
Finished Feb 21 12:44:44 PM PST 24
Peak memory 236300 kb
Host smart-79e5d5b5-79a2-47e6-8b54-eaf4a8dacab2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=647181505 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_aliasing.647181505
Directory /workspace/3.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.3070303883
Short name T818
Test name
Test status
Simulation time 28456138122 ps
CPU time 423.29 seconds
Started Feb 21 12:43:37 PM PST 24
Finished Feb 21 12:50:41 PM PST 24
Peak memory 235356 kb
Host smart-bf153f52-1735-476d-8b0c-f0e95720a409
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3070303883 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_bit_bash.3070303883
Directory /workspace/3.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.396917062
Short name T720
Test name
Test status
Simulation time 54007255 ps
CPU time 5.04 seconds
Started Feb 21 12:43:37 PM PST 24
Finished Feb 21 12:43:42 PM PST 24
Peak memory 240128 kb
Host smart-21af7463-9b3e-474b-8561-378fc6b16258
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=396917062 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_hw_reset.396917062
Directory /workspace/3.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.1293167492
Short name T356
Test name
Test status
Simulation time 181718761 ps
CPU time 10.8 seconds
Started Feb 21 12:43:19 PM PST 24
Finished Feb 21 12:43:31 PM PST 24
Peak memory 250424 kb
Host smart-2f795682-c479-4582-ac85-71ee50af0c9c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293167492 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 3.alert_handler_csr_mem_rw_with_rand_reset.1293167492
Directory /workspace/3.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.2792684145
Short name T770
Test name
Test status
Simulation time 34377089 ps
CPU time 5.19 seconds
Started Feb 21 12:43:32 PM PST 24
Finished Feb 21 12:43:38 PM PST 24
Peak memory 236204 kb
Host smart-eff413a7-90a8-4873-a4d3-6938c48c6ef8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2792684145 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_rw.2792684145
Directory /workspace/3.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.2936060885
Short name T191
Test name
Test status
Simulation time 316280595 ps
CPU time 17.75 seconds
Started Feb 21 12:43:27 PM PST 24
Finished Feb 21 12:43:51 PM PST 24
Peak memory 243424 kb
Host smart-4454028a-2015-4e48-9f01-6bb99721aa94
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2936060885 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_same_csr_out
standing.2936060885
Directory /workspace/3.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.689146563
Short name T150
Test name
Test status
Simulation time 1698638082 ps
CPU time 226.37 seconds
Started Feb 21 12:43:35 PM PST 24
Finished Feb 21 12:47:22 PM PST 24
Peak memory 271640 kb
Host smart-fdf76157-cdd6-4921-ba6a-3377de7d383e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=689146563 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shadow_reg_error
s.689146563
Directory /workspace/3.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.1811526326
Short name T354
Test name
Test status
Simulation time 87827807599 ps
CPU time 605.54 seconds
Started Feb 21 12:43:23 PM PST 24
Finished Feb 21 12:53:29 PM PST 24
Peak memory 265016 kb
Host smart-ce9e84e7-51bb-4f56-aa3d-8db22e32fe85
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811526326 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.alert_handler_shadow_reg_errors_with_csr_rw.1811526326
Directory /workspace/3.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.1193375332
Short name T716
Test name
Test status
Simulation time 327194238 ps
CPU time 10.4 seconds
Started Feb 21 12:43:34 PM PST 24
Finished Feb 21 12:43:44 PM PST 24
Peak memory 248380 kb
Host smart-18641624-1bb6-442b-a8d5-38d23ad8121e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1193375332 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_errors.1193375332
Directory /workspace/3.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.2393850705
Short name T344
Test name
Test status
Simulation time 23265761 ps
CPU time 1.39 seconds
Started Feb 21 12:43:56 PM PST 24
Finished Feb 21 12:43:59 PM PST 24
Peak memory 235484 kb
Host smart-cf3e8c5f-b676-4a3e-9a82-4d644bea204d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2393850705 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.alert_handler_intr_test.2393850705
Directory /workspace/30.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.2456870146
Short name T163
Test name
Test status
Simulation time 16036798 ps
CPU time 1.3 seconds
Started Feb 21 12:43:38 PM PST 24
Finished Feb 21 12:43:40 PM PST 24
Peak memory 235396 kb
Host smart-453efc17-d5cb-445a-ba43-b1953a0f4dde
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2456870146 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.alert_handler_intr_test.2456870146
Directory /workspace/31.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.2901497442
Short name T346
Test name
Test status
Simulation time 8520644 ps
CPU time 1.47 seconds
Started Feb 21 12:43:53 PM PST 24
Finished Feb 21 12:43:57 PM PST 24
Peak memory 235416 kb
Host smart-a7a68430-4ba8-4e56-bf7b-fca16ef48e57
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2901497442 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.alert_handler_intr_test.2901497442
Directory /workspace/32.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.3154527205
Short name T165
Test name
Test status
Simulation time 22467242 ps
CPU time 1.91 seconds
Started Feb 21 12:43:45 PM PST 24
Finished Feb 21 12:43:51 PM PST 24
Peak memory 235452 kb
Host smart-c8ee19e0-57b9-4f83-855a-779e29263dc0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3154527205 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.alert_handler_intr_test.3154527205
Directory /workspace/33.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.2179213084
Short name T723
Test name
Test status
Simulation time 12416598 ps
CPU time 1.32 seconds
Started Feb 21 12:44:01 PM PST 24
Finished Feb 21 12:44:03 PM PST 24
Peak memory 236348 kb
Host smart-8fb10269-49e5-4f1f-a54e-8117c671ee8d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2179213084 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.alert_handler_intr_test.2179213084
Directory /workspace/34.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.342307869
Short name T804
Test name
Test status
Simulation time 24396200 ps
CPU time 1.18 seconds
Started Feb 21 12:43:49 PM PST 24
Finished Feb 21 12:43:54 PM PST 24
Peak memory 235284 kb
Host smart-35e3f952-f7d4-49fd-b818-da32ce652ab1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=342307869 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.alert_handler_intr_test.342307869
Directory /workspace/35.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.1340675909
Short name T345
Test name
Test status
Simulation time 11931865 ps
CPU time 1.34 seconds
Started Feb 21 12:43:49 PM PST 24
Finished Feb 21 12:43:55 PM PST 24
Peak memory 236372 kb
Host smart-6ab24d65-177c-4381-95ea-b6a06bf54680
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1340675909 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.alert_handler_intr_test.1340675909
Directory /workspace/36.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.2035438344
Short name T805
Test name
Test status
Simulation time 7702989 ps
CPU time 1.29 seconds
Started Feb 21 12:43:44 PM PST 24
Finished Feb 21 12:43:48 PM PST 24
Peak memory 236212 kb
Host smart-545cddff-8da7-4d46-9d02-e9817ec47200
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2035438344 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.alert_handler_intr_test.2035438344
Directory /workspace/37.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.3401232910
Short name T783
Test name
Test status
Simulation time 9322178 ps
CPU time 1.37 seconds
Started Feb 21 12:43:51 PM PST 24
Finished Feb 21 12:43:55 PM PST 24
Peak memory 236292 kb
Host smart-bb4bddd8-f602-4fc7-bcba-217699d917c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3401232910 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.alert_handler_intr_test.3401232910
Directory /workspace/38.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.1070808587
Short name T753
Test name
Test status
Simulation time 31887053 ps
CPU time 1.2 seconds
Started Feb 21 12:43:55 PM PST 24
Finished Feb 21 12:43:57 PM PST 24
Peak memory 236100 kb
Host smart-f3fcc8dc-7e81-4cc3-ba22-f06f25c660f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1070808587 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.alert_handler_intr_test.1070808587
Directory /workspace/39.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.1128376665
Short name T357
Test name
Test status
Simulation time 3773517095 ps
CPU time 245.06 seconds
Started Feb 21 12:43:23 PM PST 24
Finished Feb 21 12:47:28 PM PST 24
Peak memory 238076 kb
Host smart-25a200e7-374f-43f7-bf7f-aea4dfa3edfb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1128376665 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_aliasing.1128376665
Directory /workspace/4.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.1596893018
Short name T757
Test name
Test status
Simulation time 171003120352 ps
CPU time 455.15 seconds
Started Feb 21 12:43:20 PM PST 24
Finished Feb 21 12:50:56 PM PST 24
Peak memory 240252 kb
Host smart-78340f1d-e789-457e-ac5a-76165625bdae
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1596893018 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_bit_bash.1596893018
Directory /workspace/4.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.3733303794
Short name T788
Test name
Test status
Simulation time 99941246 ps
CPU time 4.66 seconds
Started Feb 21 12:43:33 PM PST 24
Finished Feb 21 12:43:38 PM PST 24
Peak memory 240136 kb
Host smart-1710df7a-c644-4945-91c6-f9333590ca8d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3733303794 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_hw_reset.3733303794
Directory /workspace/4.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.3960812807
Short name T358
Test name
Test status
Simulation time 148313888 ps
CPU time 6.56 seconds
Started Feb 21 12:43:43 PM PST 24
Finished Feb 21 12:43:51 PM PST 24
Peak memory 240116 kb
Host smart-3898fea1-fd73-40e5-9529-cf0ca7313327
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960812807 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 4.alert_handler_csr_mem_rw_with_rand_reset.3960812807
Directory /workspace/4.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.1801577606
Short name T764
Test name
Test status
Simulation time 72840200 ps
CPU time 3.41 seconds
Started Feb 21 12:43:19 PM PST 24
Finished Feb 21 12:43:23 PM PST 24
Peak memory 236184 kb
Host smart-a99a47bb-1d42-4602-a9b9-586fbf39beed
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1801577606 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_rw.1801577606
Directory /workspace/4.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.3799059727
Short name T827
Test name
Test status
Simulation time 80891334 ps
CPU time 1.34 seconds
Started Feb 21 12:43:28 PM PST 24
Finished Feb 21 12:43:29 PM PST 24
Peak memory 236320 kb
Host smart-fd1cdb0b-b911-4d9c-93dc-2fffa401dc73
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3799059727 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_intr_test.3799059727
Directory /workspace/4.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.521103607
Short name T721
Test name
Test status
Simulation time 814266444 ps
CPU time 21.7 seconds
Started Feb 21 12:43:27 PM PST 24
Finished Feb 21 12:43:49 PM PST 24
Peak memory 248248 kb
Host smart-aa111c3f-54cf-4dc9-a096-5b73dc34a97f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=521103607 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_same_csr_outs
tanding.521103607
Directory /workspace/4.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.2169811700
Short name T138
Test name
Test status
Simulation time 4591373165 ps
CPU time 161.75 seconds
Started Feb 21 12:43:46 PM PST 24
Finished Feb 21 12:46:32 PM PST 24
Peak memory 256872 kb
Host smart-bbaeaf20-7abb-4e72-a7c9-9ebc2c73f396
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2169811700 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shadow_reg_erro
rs.2169811700
Directory /workspace/4.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.4057216212
Short name T797
Test name
Test status
Simulation time 113066147 ps
CPU time 8.71 seconds
Started Feb 21 12:43:51 PM PST 24
Finished Feb 21 12:44:03 PM PST 24
Peak memory 247808 kb
Host smart-1471622f-92ad-4f08-b9b9-b90560eb1ac6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4057216212 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_errors.4057216212
Directory /workspace/4.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.3330429063
Short name T761
Test name
Test status
Simulation time 15690986 ps
CPU time 1.33 seconds
Started Feb 21 12:43:54 PM PST 24
Finished Feb 21 12:43:57 PM PST 24
Peak memory 235352 kb
Host smart-3407d9fa-4000-403f-a298-4e4c29a1ff3b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3330429063 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.alert_handler_intr_test.3330429063
Directory /workspace/40.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.3079271436
Short name T736
Test name
Test status
Simulation time 8800370 ps
CPU time 1.57 seconds
Started Feb 21 12:43:58 PM PST 24
Finished Feb 21 12:44:00 PM PST 24
Peak memory 236296 kb
Host smart-69be393b-eed9-4cac-87a7-0673356581c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3079271436 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.alert_handler_intr_test.3079271436
Directory /workspace/42.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.1087490291
Short name T726
Test name
Test status
Simulation time 8027773 ps
CPU time 1.47 seconds
Started Feb 21 12:43:46 PM PST 24
Finished Feb 21 12:43:51 PM PST 24
Peak memory 234516 kb
Host smart-214610fe-6b49-4807-953c-90fb26d92b02
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1087490291 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.alert_handler_intr_test.1087490291
Directory /workspace/43.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.1730067179
Short name T785
Test name
Test status
Simulation time 11430374 ps
CPU time 1.26 seconds
Started Feb 21 12:43:51 PM PST 24
Finished Feb 21 12:43:56 PM PST 24
Peak memory 235356 kb
Host smart-58e16902-557d-4c68-9a5d-60b760692bf3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1730067179 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.alert_handler_intr_test.1730067179
Directory /workspace/44.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.600609700
Short name T772
Test name
Test status
Simulation time 19338906 ps
CPU time 1.36 seconds
Started Feb 21 12:43:57 PM PST 24
Finished Feb 21 12:43:59 PM PST 24
Peak memory 236300 kb
Host smart-8f24facf-f998-46cb-bf54-bad0086e44ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=600609700 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.alert_handler_intr_test.600609700
Directory /workspace/45.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.2846809931
Short name T823
Test name
Test status
Simulation time 19269508 ps
CPU time 1.36 seconds
Started Feb 21 12:43:49 PM PST 24
Finished Feb 21 12:43:55 PM PST 24
Peak memory 236328 kb
Host smart-39fc6aba-488d-4e27-9763-3f17de039142
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2846809931 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.alert_handler_intr_test.2846809931
Directory /workspace/46.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.2242433483
Short name T820
Test name
Test status
Simulation time 43410382 ps
CPU time 1.39 seconds
Started Feb 21 12:43:44 PM PST 24
Finished Feb 21 12:43:48 PM PST 24
Peak memory 236352 kb
Host smart-714b1755-b00d-4bb5-b212-6740f24da164
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2242433483 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.alert_handler_intr_test.2242433483
Directory /workspace/47.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.1836498473
Short name T791
Test name
Test status
Simulation time 6628570 ps
CPU time 1.37 seconds
Started Feb 21 12:43:44 PM PST 24
Finished Feb 21 12:43:48 PM PST 24
Peak memory 234436 kb
Host smart-6e9c71e7-c536-46fc-a69e-1bc6a49d62c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1836498473 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.alert_handler_intr_test.1836498473
Directory /workspace/48.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.1335666134
Short name T812
Test name
Test status
Simulation time 7515752 ps
CPU time 1.43 seconds
Started Feb 21 12:43:59 PM PST 24
Finished Feb 21 12:44:01 PM PST 24
Peak memory 235464 kb
Host smart-b9cb820c-6cc0-4f1d-ba05-06cbb82399d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1335666134 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.alert_handler_intr_test.1335666134
Directory /workspace/49.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.316658297
Short name T728
Test name
Test status
Simulation time 121044624 ps
CPU time 4.99 seconds
Started Feb 21 12:43:41 PM PST 24
Finished Feb 21 12:43:46 PM PST 24
Peak memory 256484 kb
Host smart-72698cf6-8df6-479b-8a2a-53dd56a410fd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316658297 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 5.alert_handler_csr_mem_rw_with_rand_reset.316658297
Directory /workspace/5.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.2385965593
Short name T762
Test name
Test status
Simulation time 253326693 ps
CPU time 7.96 seconds
Started Feb 21 12:43:30 PM PST 24
Finished Feb 21 12:43:39 PM PST 24
Peak memory 240128 kb
Host smart-7d502a6f-a4de-4010-bbf6-979b9fe6b51b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2385965593 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_rw.2385965593
Directory /workspace/5.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.3153550297
Short name T782
Test name
Test status
Simulation time 10151987 ps
CPU time 1.58 seconds
Started Feb 21 12:43:44 PM PST 24
Finished Feb 21 12:43:49 PM PST 24
Peak memory 236348 kb
Host smart-11a16063-ae81-4924-8623-27122f7f5842
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3153550297 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_intr_test.3153550297
Directory /workspace/5.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.3678057249
Short name T717
Test name
Test status
Simulation time 2971385298 ps
CPU time 38.13 seconds
Started Feb 21 12:43:42 PM PST 24
Finished Feb 21 12:44:23 PM PST 24
Peak memory 244388 kb
Host smart-7243a514-4b47-49b1-9ee9-2327a9d6143f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3678057249 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_same_csr_out
standing.3678057249
Directory /workspace/5.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.3651407157
Short name T824
Test name
Test status
Simulation time 16745644279 ps
CPU time 545.35 seconds
Started Feb 21 12:43:32 PM PST 24
Finished Feb 21 12:52:38 PM PST 24
Peak memory 265164 kb
Host smart-130e7772-051d-4f7c-8f93-ec908ea48284
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651407157 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.alert_handler_shadow_reg_errors_with_csr_rw.3651407157
Directory /workspace/5.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.2171916168
Short name T739
Test name
Test status
Simulation time 1190885390 ps
CPU time 10.54 seconds
Started Feb 21 12:43:32 PM PST 24
Finished Feb 21 12:43:43 PM PST 24
Peak memory 248448 kb
Host smart-d0de2dda-48d9-4898-a144-a0bee940818e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2171916168 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_errors.2171916168
Directory /workspace/5.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.2883795263
Short name T779
Test name
Test status
Simulation time 37362412 ps
CPU time 5.07 seconds
Started Feb 21 12:43:25 PM PST 24
Finished Feb 21 12:43:31 PM PST 24
Peak memory 248404 kb
Host smart-784e0ef4-8ef2-4373-80e1-fd6feb23501b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883795263 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 6.alert_handler_csr_mem_rw_with_rand_reset.2883795263
Directory /workspace/6.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.1899193221
Short name T773
Test name
Test status
Simulation time 128385810 ps
CPU time 8.75 seconds
Started Feb 21 12:43:46 PM PST 24
Finished Feb 21 12:43:59 PM PST 24
Peak memory 240136 kb
Host smart-74862dc9-08ac-43ed-8238-dc8dc22bdfe4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1899193221 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_rw.1899193221
Directory /workspace/6.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.2295859397
Short name T796
Test name
Test status
Simulation time 10249484 ps
CPU time 1.55 seconds
Started Feb 21 12:43:16 PM PST 24
Finished Feb 21 12:43:19 PM PST 24
Peak memory 236220 kb
Host smart-643d3e92-a73b-4f7a-974e-c1091604406e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2295859397 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_intr_test.2295859397
Directory /workspace/6.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.4124617312
Short name T734
Test name
Test status
Simulation time 1466518957 ps
CPU time 24.35 seconds
Started Feb 21 12:43:15 PM PST 24
Finished Feb 21 12:43:41 PM PST 24
Peak memory 240116 kb
Host smart-0d779074-2949-4dac-951c-876190d2386a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4124617312 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_same_csr_out
standing.4124617312
Directory /workspace/6.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.2661748107
Short name T719
Test name
Test status
Simulation time 244450225 ps
CPU time 13.78 seconds
Started Feb 21 12:43:27 PM PST 24
Finished Feb 21 12:43:42 PM PST 24
Peak memory 253196 kb
Host smart-b8cb2835-34fc-42b2-8b30-99a1cf681483
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2661748107 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_errors.2661748107
Directory /workspace/6.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.1265492940
Short name T751
Test name
Test status
Simulation time 44164024 ps
CPU time 5.24 seconds
Started Feb 21 12:43:21 PM PST 24
Finished Feb 21 12:43:27 PM PST 24
Peak memory 255432 kb
Host smart-9732e178-5d76-4029-b4ec-77b5ee3cb7d2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265492940 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 7.alert_handler_csr_mem_rw_with_rand_reset.1265492940
Directory /workspace/7.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.3986417148
Short name T733
Test name
Test status
Simulation time 185919399 ps
CPU time 4.04 seconds
Started Feb 21 12:43:38 PM PST 24
Finished Feb 21 12:43:42 PM PST 24
Peak memory 236140 kb
Host smart-5f91d88f-ca72-48ed-8dcd-5b8e9fb2f3c5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3986417148 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_rw.3986417148
Directory /workspace/7.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.71934345
Short name T829
Test name
Test status
Simulation time 19445106 ps
CPU time 1.81 seconds
Started Feb 21 12:43:28 PM PST 24
Finished Feb 21 12:43:30 PM PST 24
Peak memory 236352 kb
Host smart-85c604f7-1f83-43ac-a939-17adfb56ad50
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=71934345 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_intr_test.71934345
Directory /workspace/7.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.2544015837
Short name T760
Test name
Test status
Simulation time 661390440 ps
CPU time 40.75 seconds
Started Feb 21 12:43:28 PM PST 24
Finished Feb 21 12:44:09 PM PST 24
Peak memory 244464 kb
Host smart-28b8c35b-59f8-4051-a755-2e6760d0cdae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2544015837 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_same_csr_out
standing.2544015837
Directory /workspace/7.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.160602520
Short name T135
Test name
Test status
Simulation time 23248137921 ps
CPU time 153.69 seconds
Started Feb 21 12:43:41 PM PST 24
Finished Feb 21 12:46:16 PM PST 24
Peak memory 256820 kb
Host smart-4b26be33-f2ff-4ee3-9af3-ac9079729ac9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=160602520 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shadow_reg_error
s.160602520
Directory /workspace/7.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.1353433706
Short name T756
Test name
Test status
Simulation time 178011391 ps
CPU time 11.31 seconds
Started Feb 21 12:43:30 PM PST 24
Finished Feb 21 12:43:41 PM PST 24
Peak memory 253556 kb
Host smart-61a2b26a-3136-4622-ac6c-4d3b43fd3529
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1353433706 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_errors.1353433706
Directory /workspace/7.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.3879499264
Short name T727
Test name
Test status
Simulation time 366122851 ps
CPU time 7.35 seconds
Started Feb 21 12:43:18 PM PST 24
Finished Feb 21 12:43:26 PM PST 24
Peak memory 239064 kb
Host smart-ee225e04-e87b-46e5-b51f-08331949ff83
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879499264 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 8.alert_handler_csr_mem_rw_with_rand_reset.3879499264
Directory /workspace/8.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.1180182867
Short name T351
Test name
Test status
Simulation time 96695219 ps
CPU time 7.19 seconds
Started Feb 21 12:43:37 PM PST 24
Finished Feb 21 12:43:45 PM PST 24
Peak memory 236260 kb
Host smart-7b585318-e4f2-414a-b633-d39c2ee958b7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1180182867 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_rw.1180182867
Directory /workspace/8.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.3114985483
Short name T766
Test name
Test status
Simulation time 15469669 ps
CPU time 1.46 seconds
Started Feb 21 12:43:50 PM PST 24
Finished Feb 21 12:43:55 PM PST 24
Peak memory 236300 kb
Host smart-b6e727c6-799f-47ee-b3e9-c23e739c542e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3114985483 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_intr_test.3114985483
Directory /workspace/8.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.538553559
Short name T748
Test name
Test status
Simulation time 338792609 ps
CPU time 23.08 seconds
Started Feb 21 12:43:37 PM PST 24
Finished Feb 21 12:44:00 PM PST 24
Peak memory 244420 kb
Host smart-6ec2bd49-fc93-43cc-8904-94381ed7e8ca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=538553559 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_same_csr_outs
tanding.538553559
Directory /workspace/8.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.3065015216
Short name T153
Test name
Test status
Simulation time 3403401516 ps
CPU time 192.82 seconds
Started Feb 21 12:43:43 PM PST 24
Finished Feb 21 12:46:58 PM PST 24
Peak memory 256856 kb
Host smart-945d9774-ecfd-4248-ac3e-1531ae260bd6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3065015216 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shadow_reg_erro
rs.3065015216
Directory /workspace/8.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.3338749271
Short name T151
Test name
Test status
Simulation time 28979142118 ps
CPU time 473.78 seconds
Started Feb 21 12:43:42 PM PST 24
Finished Feb 21 12:51:38 PM PST 24
Peak memory 265060 kb
Host smart-e13715af-2051-4192-9b56-56303b5956be
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338749271 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.alert_handler_shadow_reg_errors_with_csr_rw.3338749271
Directory /workspace/8.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.3600560426
Short name T801
Test name
Test status
Simulation time 55626213 ps
CPU time 7.89 seconds
Started Feb 21 12:43:46 PM PST 24
Finished Feb 21 12:43:58 PM PST 24
Peak memory 248280 kb
Host smart-6c521424-12a9-478b-9758-45b6a5960a99
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3600560426 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_errors.3600560426
Directory /workspace/8.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.3822651244
Short name T813
Test name
Test status
Simulation time 164454079 ps
CPU time 11.72 seconds
Started Feb 21 12:43:33 PM PST 24
Finished Feb 21 12:43:46 PM PST 24
Peak memory 250492 kb
Host smart-17f013c9-fd54-4080-abfc-b5da41ca90ab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822651244 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 9.alert_handler_csr_mem_rw_with_rand_reset.3822651244
Directory /workspace/9.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.5069069
Short name T746
Test name
Test status
Simulation time 145841124 ps
CPU time 8.47 seconds
Started Feb 21 12:43:44 PM PST 24
Finished Feb 21 12:43:54 PM PST 24
Peak memory 235376 kb
Host smart-a2841a61-79aa-4f1d-acf2-5f9f62118547
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=5069069 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_rw.5069069
Directory /workspace/9.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.3881223583
Short name T730
Test name
Test status
Simulation time 8615386 ps
CPU time 1.33 seconds
Started Feb 21 12:43:38 PM PST 24
Finished Feb 21 12:43:40 PM PST 24
Peak memory 236280 kb
Host smart-5c5878f0-a066-4dd0-a0b1-5b547059b2c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3881223583 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_intr_test.3881223583
Directory /workspace/9.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.1565771908
Short name T775
Test name
Test status
Simulation time 323501918 ps
CPU time 11.18 seconds
Started Feb 21 12:43:43 PM PST 24
Finished Feb 21 12:43:57 PM PST 24
Peak memory 244468 kb
Host smart-c3f8b123-3bf8-4584-bc16-3cfbf5f97ea1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1565771908 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_same_csr_out
standing.1565771908
Directory /workspace/9.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.1744708683
Short name T149
Test name
Test status
Simulation time 14817449366 ps
CPU time 490.99 seconds
Started Feb 21 12:43:41 PM PST 24
Finished Feb 21 12:51:52 PM PST 24
Peak memory 270380 kb
Host smart-ddf608bb-2748-4ed6-a275-ec81b22ebae0
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744708683 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.alert_handler_shadow_reg_errors_with_csr_rw.1744708683
Directory /workspace/9.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.1707157025
Short name T809
Test name
Test status
Simulation time 68952004 ps
CPU time 10.37 seconds
Started Feb 21 12:43:31 PM PST 24
Finished Feb 21 12:43:42 PM PST 24
Peak memory 248444 kb
Host smart-4cce3297-2908-4a54-b013-e9f6cebc5e8c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1707157025 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_errors.1707157025
Directory /workspace/9.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.1721865309
Short name T161
Test name
Test status
Simulation time 35490671 ps
CPU time 2.78 seconds
Started Feb 21 12:43:41 PM PST 24
Finished Feb 21 12:43:44 PM PST 24
Peak memory 236540 kb
Host smart-4518a59c-51aa-4d79-a57d-f8c271312b4f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1721865309 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_intg_err.1721865309
Directory /workspace/9.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/0.alert_handler_entropy.3177478288
Short name T583
Test name
Test status
Simulation time 24734801481 ps
CPU time 1585.23 seconds
Started Feb 21 03:53:37 PM PST 24
Finished Feb 21 04:20:02 PM PST 24
Peak memory 272724 kb
Host smart-4122cb95-5b32-4bd9-8bf8-610b8319527c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177478288 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy.3177478288
Directory /workspace/0.alert_handler_entropy/latest

Test location /workspace/coverage/default/0.alert_handler_esc_alert_accum.2530113487
Short name T246
Test name
Test status
Simulation time 1531323149 ps
CPU time 136.72 seconds
Started Feb 21 03:53:40 PM PST 24
Finished Feb 21 03:55:57 PM PST 24
Peak memory 255556 kb
Host smart-0c941ff0-db02-4ba7-9dda-35cf3eca5b57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25301
13487 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_alert_accum.2530113487
Directory /workspace/0.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/0.alert_handler_esc_intr_timeout.2040956901
Short name T454
Test name
Test status
Simulation time 538405482 ps
CPU time 10.39 seconds
Started Feb 21 03:53:37 PM PST 24
Finished Feb 21 03:53:48 PM PST 24
Peak memory 252256 kb
Host smart-b854d084-bf49-40ea-b43a-a98aa5e7fd00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20409
56901 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_intr_timeout.2040956901
Directory /workspace/0.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_lpg_stub_clk.3916911423
Short name T586
Test name
Test status
Simulation time 24271833340 ps
CPU time 911.38 seconds
Started Feb 21 03:53:36 PM PST 24
Finished Feb 21 04:08:48 PM PST 24
Peak memory 270964 kb
Host smart-71b7eb0d-9178-448d-8ce3-2a528b1a52fb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916911423 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg_stub_clk.3916911423
Directory /workspace/0.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/0.alert_handler_random_alerts.2070648097
Short name T631
Test name
Test status
Simulation time 603050982 ps
CPU time 4.37 seconds
Started Feb 21 03:53:38 PM PST 24
Finished Feb 21 03:53:43 PM PST 24
Peak memory 240072 kb
Host smart-d33fd3d2-96ec-4e2b-a50c-d7f873fdbfd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20706
48097 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_alerts.2070648097
Directory /workspace/0.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/0.alert_handler_random_classes.2512190742
Short name T108
Test name
Test status
Simulation time 178317542 ps
CPU time 17.75 seconds
Started Feb 21 03:53:35 PM PST 24
Finished Feb 21 03:53:54 PM PST 24
Peak memory 254452 kb
Host smart-2ff8a773-1bd3-4b00-b92c-994d08dd4184
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25121
90742 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_classes.2512190742
Directory /workspace/0.alert_handler_random_classes/latest

Test location /workspace/coverage/default/0.alert_handler_sig_int_fail.1635219860
Short name T477
Test name
Test status
Simulation time 647470749 ps
CPU time 42.86 seconds
Started Feb 21 03:53:38 PM PST 24
Finished Feb 21 03:54:22 PM PST 24
Peak memory 254756 kb
Host smart-3c328d94-8587-46fa-ba96-638ce8a520a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16352
19860 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sig_int_fail.1635219860
Directory /workspace/0.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/0.alert_handler_smoke.1211961059
Short name T567
Test name
Test status
Simulation time 46791592 ps
CPU time 5.16 seconds
Started Feb 21 03:53:35 PM PST 24
Finished Feb 21 03:53:41 PM PST 24
Peak memory 248204 kb
Host smart-b9e3a763-c972-48dd-b3ff-83a0e0ca0672
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12119
61059 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_smoke.1211961059
Directory /workspace/0.alert_handler_smoke/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all.4188023478
Short name T250
Test name
Test status
Simulation time 35683717814 ps
CPU time 843.9 seconds
Started Feb 21 03:53:38 PM PST 24
Finished Feb 21 04:07:42 PM PST 24
Peak memory 272932 kb
Host smart-77c7ed33-5807-4a48-afab-88f36842be0b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188023478 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_han
dler_stress_all.4188023478
Directory /workspace/0.alert_handler_stress_all/latest

Test location /workspace/coverage/default/1.alert_handler_alert_accum_saturation.2891772443
Short name T208
Test name
Test status
Simulation time 62898711 ps
CPU time 3.24 seconds
Started Feb 21 03:53:41 PM PST 24
Finished Feb 21 03:53:45 PM PST 24
Peak memory 248552 kb
Host smart-19b121fe-80f6-47f6-925b-906a039c2b19
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2891772443 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_alert_accum_saturation.2891772443
Directory /workspace/1.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/1.alert_handler_entropy.2937913745
Short name T87
Test name
Test status
Simulation time 29446762614 ps
CPU time 1684.47 seconds
Started Feb 21 03:53:40 PM PST 24
Finished Feb 21 04:21:45 PM PST 24
Peak memory 271892 kb
Host smart-4a970353-61ab-4ddd-b565-30acfc4fac99
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937913745 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy.2937913745
Directory /workspace/1.alert_handler_entropy/latest

Test location /workspace/coverage/default/1.alert_handler_entropy_stress.3751182019
Short name T525
Test name
Test status
Simulation time 379543478 ps
CPU time 19.74 seconds
Started Feb 21 03:53:44 PM PST 24
Finished Feb 21 03:54:05 PM PST 24
Peak memory 240040 kb
Host smart-028cdf11-3464-4cbc-9b78-27924e96cbf7
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3751182019 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy_stress.3751182019
Directory /workspace/1.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/1.alert_handler_esc_alert_accum.3463675439
Short name T452
Test name
Test status
Simulation time 2128201627 ps
CPU time 133.13 seconds
Started Feb 21 03:53:39 PM PST 24
Finished Feb 21 03:55:53 PM PST 24
Peak memory 249124 kb
Host smart-add15c81-d2dd-41fc-bb59-fbad6451d601
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34636
75439 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_alert_accum.3463675439
Directory /workspace/1.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/1.alert_handler_esc_intr_timeout.536689416
Short name T44
Test name
Test status
Simulation time 430399413 ps
CPU time 25.21 seconds
Started Feb 21 03:53:38 PM PST 24
Finished Feb 21 03:54:03 PM PST 24
Peak memory 255064 kb
Host smart-ba980b37-0332-4bd1-9fd4-b7709fec0cc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53668
9416 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_intr_timeout.536689416
Directory /workspace/1.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_lpg.2566437558
Short name T88
Test name
Test status
Simulation time 60293178241 ps
CPU time 1106.22 seconds
Started Feb 21 03:53:38 PM PST 24
Finished Feb 21 04:12:05 PM PST 24
Peak memory 272528 kb
Host smart-14ee6103-8a16-423b-92e6-2dd2b09fd5a5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566437558 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg.2566437558
Directory /workspace/1.alert_handler_lpg/latest

Test location /workspace/coverage/default/1.alert_handler_lpg_stub_clk.383072034
Short name T451
Test name
Test status
Simulation time 146544422747 ps
CPU time 2032.59 seconds
Started Feb 21 03:53:35 PM PST 24
Finished Feb 21 04:27:29 PM PST 24
Peak memory 271936 kb
Host smart-45beae4e-df84-46b8-b7dc-68904f398ed0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383072034 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg_stub_clk.383072034
Directory /workspace/1.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/1.alert_handler_ping_timeout.2717209402
Short name T308
Test name
Test status
Simulation time 24714954712 ps
CPU time 271.91 seconds
Started Feb 21 03:53:47 PM PST 24
Finished Feb 21 03:58:21 PM PST 24
Peak memory 247164 kb
Host smart-69cb74bd-0e04-4130-aad9-b23e684f2599
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717209402 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_ping_timeout.2717209402
Directory /workspace/1.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_random_alerts.2975304353
Short name T228
Test name
Test status
Simulation time 3173226794 ps
CPU time 52.03 seconds
Started Feb 21 03:53:47 PM PST 24
Finished Feb 21 03:54:41 PM PST 24
Peak memory 248276 kb
Host smart-2b2d6f29-c303-4700-b0c3-fbae4fc3e97c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29753
04353 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_alerts.2975304353
Directory /workspace/1.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/1.alert_handler_random_classes.1735030953
Short name T76
Test name
Test status
Simulation time 879451994 ps
CPU time 51.99 seconds
Started Feb 21 03:53:44 PM PST 24
Finished Feb 21 03:54:37 PM PST 24
Peak memory 246820 kb
Host smart-2225c0a7-c1ba-405e-86d3-22b0d56e53a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17350
30953 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_classes.1735030953
Directory /workspace/1.alert_handler_random_classes/latest

Test location /workspace/coverage/default/1.alert_handler_sec_cm.1801658643
Short name T10
Test name
Test status
Simulation time 687101059 ps
CPU time 10.63 seconds
Started Feb 21 03:53:44 PM PST 24
Finished Feb 21 03:53:56 PM PST 24
Peak memory 276744 kb
Host smart-776c973a-c2a9-4fc3-8c34-8f7826f2b137
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1801658643 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sec_cm.1801658643
Directory /workspace/1.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/1.alert_handler_sig_int_fail.2263026132
Short name T280
Test name
Test status
Simulation time 478720921 ps
CPU time 31.25 seconds
Started Feb 21 03:53:38 PM PST 24
Finished Feb 21 03:54:09 PM PST 24
Peak memory 255000 kb
Host smart-27e2ab74-60bc-488a-a2f5-0190b24c6241
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22630
26132 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sig_int_fail.2263026132
Directory /workspace/1.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/1.alert_handler_smoke.843364051
Short name T429
Test name
Test status
Simulation time 164173897 ps
CPU time 16.61 seconds
Started Feb 21 03:53:41 PM PST 24
Finished Feb 21 03:53:58 PM PST 24
Peak memory 248052 kb
Host smart-fb892b4e-1de9-44b1-9362-6d6423e11c86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84336
4051 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_smoke.843364051
Directory /workspace/1.alert_handler_smoke/latest

Test location /workspace/coverage/default/10.alert_handler_entropy.1935330660
Short name T677
Test name
Test status
Simulation time 23263174099 ps
CPU time 1153.64 seconds
Started Feb 21 03:54:38 PM PST 24
Finished Feb 21 04:13:52 PM PST 24
Peak memory 288744 kb
Host smart-a9ab88ee-9f15-4dc0-babb-6a139fc261bb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935330660 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy.1935330660
Directory /workspace/10.alert_handler_entropy/latest

Test location /workspace/coverage/default/10.alert_handler_entropy_stress.1324805374
Short name T589
Test name
Test status
Simulation time 1614782398 ps
CPU time 18.62 seconds
Started Feb 21 03:54:37 PM PST 24
Finished Feb 21 03:54:55 PM PST 24
Peak memory 240024 kb
Host smart-a51f08a8-bf53-4dc3-85ef-25688bd3ed7c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1324805374 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy_stress.1324805374
Directory /workspace/10.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/10.alert_handler_esc_alert_accum.3653182456
Short name T674
Test name
Test status
Simulation time 25720733721 ps
CPU time 261.35 seconds
Started Feb 21 03:54:41 PM PST 24
Finished Feb 21 03:59:05 PM PST 24
Peak memory 255940 kb
Host smart-f52dad39-1bab-4817-af7e-18241ad1f257
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36531
82456 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_alert_accum.3653182456
Directory /workspace/10.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/10.alert_handler_esc_intr_timeout.3965666051
Short name T469
Test name
Test status
Simulation time 3958210794 ps
CPU time 53.88 seconds
Started Feb 21 03:54:37 PM PST 24
Finished Feb 21 03:55:32 PM PST 24
Peak memory 254688 kb
Host smart-f3476d38-2dfe-426c-afd7-1c3e7abe99a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39656
66051 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_intr_timeout.3965666051
Directory /workspace/10.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_lpg.2762043593
Short name T4
Test name
Test status
Simulation time 42080643626 ps
CPU time 1214.86 seconds
Started Feb 21 03:54:45 PM PST 24
Finished Feb 21 04:15:01 PM PST 24
Peak memory 288776 kb
Host smart-7882df77-3c66-4b72-ba3c-0ce73d337752
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762043593 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg.2762043593
Directory /workspace/10.alert_handler_lpg/latest

Test location /workspace/coverage/default/10.alert_handler_lpg_stub_clk.1468529592
Short name T573
Test name
Test status
Simulation time 67614940169 ps
CPU time 1777.26 seconds
Started Feb 21 03:54:37 PM PST 24
Finished Feb 21 04:24:16 PM PST 24
Peak memory 272332 kb
Host smart-f9dba043-18f1-40e8-a17a-fa6a90d5d06b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468529592 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg_stub_clk.1468529592
Directory /workspace/10.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/10.alert_handler_ping_timeout.3958830936
Short name T608
Test name
Test status
Simulation time 2624655385 ps
CPU time 110.42 seconds
Started Feb 21 03:54:41 PM PST 24
Finished Feb 21 03:56:34 PM PST 24
Peak memory 247100 kb
Host smart-58f35791-3b43-4fb0-84de-b6b711be1c2d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958830936 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_ping_timeout.3958830936
Directory /workspace/10.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_random_alerts.2796897208
Short name T380
Test name
Test status
Simulation time 1406608204 ps
CPU time 55.07 seconds
Started Feb 21 03:54:37 PM PST 24
Finished Feb 21 03:55:33 PM PST 24
Peak memory 248240 kb
Host smart-042dfbd6-c2d3-42fd-b4f5-b865c2e83716
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27968
97208 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_alerts.2796897208
Directory /workspace/10.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/10.alert_handler_random_classes.149807108
Short name T221
Test name
Test status
Simulation time 1332295316 ps
CPU time 27.12 seconds
Started Feb 21 03:54:40 PM PST 24
Finished Feb 21 03:55:08 PM PST 24
Peak memory 253080 kb
Host smart-12a1544c-6b49-4e33-aa8d-93e1e7166a38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14980
7108 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_classes.149807108
Directory /workspace/10.alert_handler_random_classes/latest

Test location /workspace/coverage/default/10.alert_handler_sig_int_fail.3013258463
Short name T431
Test name
Test status
Simulation time 84473140 ps
CPU time 7.02 seconds
Started Feb 21 03:54:32 PM PST 24
Finished Feb 21 03:54:40 PM PST 24
Peak memory 249940 kb
Host smart-2b0bd9cc-bb58-4b61-8c6c-59687f0809c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30132
58463 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_sig_int_fail.3013258463
Directory /workspace/10.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/10.alert_handler_smoke.134951136
Short name T188
Test name
Test status
Simulation time 1828553773 ps
CPU time 12.44 seconds
Started Feb 21 03:54:46 PM PST 24
Finished Feb 21 03:54:59 PM PST 24
Peak memory 253188 kb
Host smart-f4f5c3f0-753f-405f-a215-06b07f8e5196
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13495
1136 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_smoke.134951136
Directory /workspace/10.alert_handler_smoke/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all.4180115914
Short name T373
Test name
Test status
Simulation time 891107899 ps
CPU time 27.77 seconds
Started Feb 21 03:54:48 PM PST 24
Finished Feb 21 03:55:17 PM PST 24
Peak memory 248268 kb
Host smart-da70831c-0d75-4203-b242-4feb1aaf45bb
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180115914 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_ha
ndler_stress_all.4180115914
Directory /workspace/10.alert_handler_stress_all/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all_with_rand_reset.777797380
Short name T642
Test name
Test status
Simulation time 552766692623 ps
CPU time 10675.9 seconds
Started Feb 21 03:54:47 PM PST 24
Finished Feb 21 06:52:44 PM PST 24
Peak memory 354744 kb
Host smart-7859ba80-87e3-43e6-8009-c0e0301e4edf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777797380 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 10.alert_handler_stress_all_with_rand_reset.777797380
Directory /workspace/10.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.alert_handler_alert_accum_saturation.1740544556
Short name T205
Test name
Test status
Simulation time 35528037 ps
CPU time 3.37 seconds
Started Feb 21 03:54:47 PM PST 24
Finished Feb 21 03:54:51 PM PST 24
Peak memory 248716 kb
Host smart-72ca2c06-f8e4-449d-a39a-20dcc05c4b4e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1740544556 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_alert_accum_saturation.1740544556
Directory /workspace/11.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/11.alert_handler_entropy.1683545427
Short name T575
Test name
Test status
Simulation time 35817265523 ps
CPU time 2103.79 seconds
Started Feb 21 03:54:45 PM PST 24
Finished Feb 21 04:29:51 PM PST 24
Peak memory 272732 kb
Host smart-b900096c-6fe9-4709-a274-f5f5caf9b17e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683545427 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy.1683545427
Directory /workspace/11.alert_handler_entropy/latest

Test location /workspace/coverage/default/11.alert_handler_entropy_stress.1906130812
Short name T436
Test name
Test status
Simulation time 545010557 ps
CPU time 14.23 seconds
Started Feb 21 03:54:44 PM PST 24
Finished Feb 21 03:55:00 PM PST 24
Peak memory 240080 kb
Host smart-f989e0fa-b4e4-442e-bc69-0a73ecbf194b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1906130812 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy_stress.1906130812
Directory /workspace/11.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/11.alert_handler_esc_alert_accum.4289423750
Short name T445
Test name
Test status
Simulation time 339909573 ps
CPU time 19.58 seconds
Started Feb 21 03:54:45 PM PST 24
Finished Feb 21 03:55:06 PM PST 24
Peak memory 252876 kb
Host smart-abee63a2-b05b-4880-82db-4d224c655c94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42894
23750 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_alert_accum.4289423750
Directory /workspace/11.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/11.alert_handler_esc_intr_timeout.1661122027
Short name T568
Test name
Test status
Simulation time 378468355 ps
CPU time 7.51 seconds
Started Feb 21 03:54:40 PM PST 24
Finished Feb 21 03:54:49 PM PST 24
Peak memory 250024 kb
Host smart-d068da2f-8ab6-4649-bca1-b5f62539dddf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16611
22027 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_intr_timeout.1661122027
Directory /workspace/11.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_lpg.3235935743
Short name T330
Test name
Test status
Simulation time 39756483123 ps
CPU time 1841.58 seconds
Started Feb 21 03:54:48 PM PST 24
Finished Feb 21 04:25:31 PM PST 24
Peak memory 271504 kb
Host smart-2c9a3b65-46c5-441c-b9f7-69d13fad20b9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235935743 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg.3235935743
Directory /workspace/11.alert_handler_lpg/latest

Test location /workspace/coverage/default/11.alert_handler_lpg_stub_clk.2203093640
Short name T664
Test name
Test status
Simulation time 29472355739 ps
CPU time 1676.95 seconds
Started Feb 21 03:54:49 PM PST 24
Finished Feb 21 04:22:46 PM PST 24
Peak memory 281568 kb
Host smart-46e17051-624f-4ecd-9de4-3f11726ef845
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203093640 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg_stub_clk.2203093640
Directory /workspace/11.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/11.alert_handler_random_alerts.1289912914
Short name T60
Test name
Test status
Simulation time 1074386385 ps
CPU time 27.94 seconds
Started Feb 21 03:54:41 PM PST 24
Finished Feb 21 03:55:12 PM PST 24
Peak memory 248232 kb
Host smart-94b32327-74ae-464b-b959-e2cb300b107d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12899
12914 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_alerts.1289912914
Directory /workspace/11.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/11.alert_handler_smoke.3388997601
Short name T623
Test name
Test status
Simulation time 588156053 ps
CPU time 26.6 seconds
Started Feb 21 03:54:46 PM PST 24
Finished Feb 21 03:55:14 PM PST 24
Peak memory 248224 kb
Host smart-0ac1d3b5-ecc2-4d27-927e-74a49c9ab48d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33889
97601 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_smoke.3388997601
Directory /workspace/11.alert_handler_smoke/latest

Test location /workspace/coverage/default/12.alert_handler_entropy_stress.3202139529
Short name T481
Test name
Test status
Simulation time 1199219303 ps
CPU time 49.9 seconds
Started Feb 21 03:54:44 PM PST 24
Finished Feb 21 03:55:36 PM PST 24
Peak memory 240052 kb
Host smart-1f871e13-fc7e-4b26-b539-80023e032702
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3202139529 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy_stress.3202139529
Directory /workspace/12.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/12.alert_handler_esc_alert_accum.753152108
Short name T564
Test name
Test status
Simulation time 7012041994 ps
CPU time 127.58 seconds
Started Feb 21 03:54:47 PM PST 24
Finished Feb 21 03:56:55 PM PST 24
Peak memory 256504 kb
Host smart-5054bc46-dea8-4d22-a49c-64708cba4295
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75315
2108 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_alert_accum.753152108
Directory /workspace/12.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/12.alert_handler_esc_intr_timeout.4266811325
Short name T628
Test name
Test status
Simulation time 3537731257 ps
CPU time 40.96 seconds
Started Feb 21 03:54:40 PM PST 24
Finished Feb 21 03:55:24 PM PST 24
Peak memory 254588 kb
Host smart-07c4c8fc-e463-4b79-81f7-5361549a21b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42668
11325 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_intr_timeout.4266811325
Directory /workspace/12.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_lpg.1878583117
Short name T187
Test name
Test status
Simulation time 28436429983 ps
CPU time 1547.33 seconds
Started Feb 21 03:54:44 PM PST 24
Finished Feb 21 04:20:34 PM PST 24
Peak memory 272576 kb
Host smart-34979c99-fd05-4d0f-8450-ab57e168377d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878583117 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg.1878583117
Directory /workspace/12.alert_handler_lpg/latest

Test location /workspace/coverage/default/12.alert_handler_lpg_stub_clk.1127328536
Short name T107
Test name
Test status
Simulation time 20001815350 ps
CPU time 1127.06 seconds
Started Feb 21 03:54:38 PM PST 24
Finished Feb 21 04:13:25 PM PST 24
Peak memory 264720 kb
Host smart-62f87ba5-0a73-4c23-b234-5cbfb134e389
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127328536 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg_stub_clk.1127328536
Directory /workspace/12.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/12.alert_handler_ping_timeout.1333659576
Short name T93
Test name
Test status
Simulation time 18034567486 ps
CPU time 190.73 seconds
Started Feb 21 03:54:44 PM PST 24
Finished Feb 21 03:57:57 PM PST 24
Peak memory 247216 kb
Host smart-e9f80ec8-32a7-438c-917b-a36e5cfe845b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333659576 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_ping_timeout.1333659576
Directory /workspace/12.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_random_alerts.390060256
Short name T521
Test name
Test status
Simulation time 4284934176 ps
CPU time 64.2 seconds
Started Feb 21 03:54:48 PM PST 24
Finished Feb 21 03:55:53 PM PST 24
Peak memory 256504 kb
Host smart-7a7807da-679a-43d6-b836-084433ddbad8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39006
0256 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_alerts.390060256
Directory /workspace/12.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/12.alert_handler_random_classes.1071430317
Short name T569
Test name
Test status
Simulation time 623921582 ps
CPU time 14.45 seconds
Started Feb 21 03:54:46 PM PST 24
Finished Feb 21 03:55:01 PM PST 24
Peak memory 247692 kb
Host smart-df41b7f4-aa8e-4f0e-ad95-d9ca804bc669
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10714
30317 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_classes.1071430317
Directory /workspace/12.alert_handler_random_classes/latest

Test location /workspace/coverage/default/12.alert_handler_sig_int_fail.3964942736
Short name T414
Test name
Test status
Simulation time 7004509539 ps
CPU time 22.32 seconds
Started Feb 21 03:54:38 PM PST 24
Finished Feb 21 03:55:01 PM PST 24
Peak memory 254608 kb
Host smart-81847524-a4b4-4a3e-a40e-0b2310cfa039
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39649
42736 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_sig_int_fail.3964942736
Directory /workspace/12.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/12.alert_handler_smoke.3802287964
Short name T422
Test name
Test status
Simulation time 339518160 ps
CPU time 19.69 seconds
Started Feb 21 03:54:48 PM PST 24
Finished Feb 21 03:55:08 PM PST 24
Peak memory 248252 kb
Host smart-6c59ce92-98bd-4d94-9a2d-d4f71f522423
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38022
87964 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_smoke.3802287964
Directory /workspace/12.alert_handler_smoke/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all.3981045059
Short name T64
Test name
Test status
Simulation time 15016084775 ps
CPU time 1485.33 seconds
Started Feb 21 03:54:46 PM PST 24
Finished Feb 21 04:19:32 PM PST 24
Peak memory 297512 kb
Host smart-03e50ccd-02f8-48e7-be00-75bd3a884130
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981045059 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_ha
ndler_stress_all.3981045059
Directory /workspace/12.alert_handler_stress_all/latest

Test location /workspace/coverage/default/13.alert_handler_alert_accum_saturation.473154233
Short name T209
Test name
Test status
Simulation time 195741769 ps
CPU time 3.82 seconds
Started Feb 21 03:54:49 PM PST 24
Finished Feb 21 03:54:54 PM PST 24
Peak memory 248532 kb
Host smart-59ecda0d-4b53-4be0-8fde-4b2697f3c9fa
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=473154233 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_alert_accum_saturation.473154233
Directory /workspace/13.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/13.alert_handler_entropy.1005891215
Short name T442
Test name
Test status
Simulation time 115452176410 ps
CPU time 1869.22 seconds
Started Feb 21 03:54:46 PM PST 24
Finished Feb 21 04:25:57 PM PST 24
Peak memory 271944 kb
Host smart-f63f3fe5-a7e7-4288-9561-91cb4106231e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005891215 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy.1005891215
Directory /workspace/13.alert_handler_entropy/latest

Test location /workspace/coverage/default/13.alert_handler_entropy_stress.3922888176
Short name T593
Test name
Test status
Simulation time 859665109 ps
CPU time 21.46 seconds
Started Feb 21 03:54:43 PM PST 24
Finished Feb 21 03:55:06 PM PST 24
Peak memory 240040 kb
Host smart-fea04f77-2527-46e0-b5ae-fa851e4e1152
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3922888176 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy_stress.3922888176
Directory /workspace/13.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/13.alert_handler_esc_alert_accum.4216772327
Short name T527
Test name
Test status
Simulation time 6247445334 ps
CPU time 82.74 seconds
Started Feb 21 03:54:47 PM PST 24
Finished Feb 21 03:56:11 PM PST 24
Peak memory 255848 kb
Host smart-a29da7e7-dfba-4044-ae02-79b386457066
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42167
72327 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_alert_accum.4216772327
Directory /workspace/13.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/13.alert_handler_esc_intr_timeout.61282783
Short name T656
Test name
Test status
Simulation time 497965288 ps
CPU time 34.1 seconds
Started Feb 21 03:54:48 PM PST 24
Finished Feb 21 03:55:23 PM PST 24
Peak memory 246520 kb
Host smart-b4c586b3-a90d-4daf-a42e-0f3f89cafd91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61282
783 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_intr_timeout.61282783
Directory /workspace/13.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_lpg.3598772036
Short name T683
Test name
Test status
Simulation time 49326959374 ps
CPU time 1173.27 seconds
Started Feb 21 03:54:40 PM PST 24
Finished Feb 21 04:14:16 PM PST 24
Peak memory 286208 kb
Host smart-c152224e-e6f4-4158-82ca-9fb8242c8460
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3598772036 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg.3598772036
Directory /workspace/13.alert_handler_lpg/latest

Test location /workspace/coverage/default/13.alert_handler_lpg_stub_clk.3078867813
Short name T244
Test name
Test status
Simulation time 26825499193 ps
CPU time 685.19 seconds
Started Feb 21 03:54:49 PM PST 24
Finished Feb 21 04:06:15 PM PST 24
Peak memory 264716 kb
Host smart-407e9d77-b4d1-424d-929e-a767e6a9ca90
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078867813 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg_stub_clk.3078867813
Directory /workspace/13.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/13.alert_handler_ping_timeout.730740442
Short name T289
Test name
Test status
Simulation time 25132172595 ps
CPU time 249.9 seconds
Started Feb 21 03:54:48 PM PST 24
Finished Feb 21 03:58:59 PM PST 24
Peak memory 254372 kb
Host smart-ddf2171c-8ca6-48b2-8652-a9399661f5ab
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730740442 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_ping_timeout.730740442
Directory /workspace/13.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_random_alerts.763657235
Short name T366
Test name
Test status
Simulation time 494122101 ps
CPU time 27.07 seconds
Started Feb 21 03:54:48 PM PST 24
Finished Feb 21 03:55:16 PM PST 24
Peak memory 254744 kb
Host smart-a2da37e3-9338-4e68-82ff-4ac81ff60990
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76365
7235 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_alerts.763657235
Directory /workspace/13.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/13.alert_handler_random_classes.3683589864
Short name T551
Test name
Test status
Simulation time 329281242 ps
CPU time 13.45 seconds
Started Feb 21 03:54:49 PM PST 24
Finished Feb 21 03:55:03 PM PST 24
Peak memory 252836 kb
Host smart-8b87269b-10ae-4894-8455-fdac380b39d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36835
89864 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_classes.3683589864
Directory /workspace/13.alert_handler_random_classes/latest

Test location /workspace/coverage/default/13.alert_handler_sig_int_fail.3925284206
Short name T259
Test name
Test status
Simulation time 777091036 ps
CPU time 50.13 seconds
Started Feb 21 03:54:45 PM PST 24
Finished Feb 21 03:55:37 PM PST 24
Peak memory 255680 kb
Host smart-2c8391a6-49b2-49a2-8d18-a4bbc1a622be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39252
84206 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_sig_int_fail.3925284206
Directory /workspace/13.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/13.alert_handler_smoke.2877669785
Short name T562
Test name
Test status
Simulation time 3681682122 ps
CPU time 60.17 seconds
Started Feb 21 03:54:42 PM PST 24
Finished Feb 21 03:55:44 PM PST 24
Peak memory 248360 kb
Host smart-d204d801-78e1-4d92-b2e5-f3511dd6c68e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28776
69785 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_smoke.2877669785
Directory /workspace/13.alert_handler_smoke/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all.18374219
Short name T79
Test name
Test status
Simulation time 9217374910 ps
CPU time 132.16 seconds
Started Feb 21 03:54:43 PM PST 24
Finished Feb 21 03:56:57 PM PST 24
Peak memory 256512 kb
Host smart-7d03ecbf-09af-437b-973d-de1b4ad35c20
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18374219 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_hand
ler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_hand
ler_stress_all.18374219
Directory /workspace/13.alert_handler_stress_all/latest

Test location /workspace/coverage/default/14.alert_handler_alert_accum_saturation.2545355599
Short name T89
Test name
Test status
Simulation time 61731810 ps
CPU time 3.43 seconds
Started Feb 21 03:54:48 PM PST 24
Finished Feb 21 03:54:52 PM PST 24
Peak memory 248548 kb
Host smart-b78e3a2d-8045-4614-9bf1-e47342e16df4
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2545355599 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_alert_accum_saturation.2545355599
Directory /workspace/14.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/14.alert_handler_entropy.2882217829
Short name T115
Test name
Test status
Simulation time 57620901142 ps
CPU time 2394.58 seconds
Started Feb 21 03:54:46 PM PST 24
Finished Feb 21 04:34:42 PM PST 24
Peak memory 288380 kb
Host smart-1265b04b-52a4-4717-b8c6-126f9457a65f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882217829 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy.2882217829
Directory /workspace/14.alert_handler_entropy/latest

Test location /workspace/coverage/default/14.alert_handler_entropy_stress.3709858711
Short name T427
Test name
Test status
Simulation time 349080106 ps
CPU time 9.97 seconds
Started Feb 21 03:54:46 PM PST 24
Finished Feb 21 03:54:57 PM PST 24
Peak memory 240060 kb
Host smart-270e0835-17dd-4e43-b3e7-47889adfeba1
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3709858711 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy_stress.3709858711
Directory /workspace/14.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/14.alert_handler_esc_alert_accum.389099503
Short name T412
Test name
Test status
Simulation time 1273782703 ps
CPU time 122.85 seconds
Started Feb 21 03:54:43 PM PST 24
Finished Feb 21 03:56:48 PM PST 24
Peak memory 248432 kb
Host smart-b576e33e-cd2e-4293-844f-b3db3028a741
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38909
9503 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_alert_accum.389099503
Directory /workspace/14.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/14.alert_handler_esc_intr_timeout.4088994885
Short name T594
Test name
Test status
Simulation time 339009783 ps
CPU time 19.99 seconds
Started Feb 21 03:54:40 PM PST 24
Finished Feb 21 03:55:01 PM PST 24
Peak memory 252668 kb
Host smart-def05cde-4187-4a84-bdf7-fc0e5b398555
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40889
94885 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_intr_timeout.4088994885
Directory /workspace/14.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_lpg_stub_clk.1517176266
Short name T17
Test name
Test status
Simulation time 6966315807 ps
CPU time 619.42 seconds
Started Feb 21 03:54:48 PM PST 24
Finished Feb 21 04:05:09 PM PST 24
Peak memory 264500 kb
Host smart-1d2e319b-7dcc-48fb-aaa6-52b9b2c7e65d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517176266 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg_stub_clk.1517176266
Directory /workspace/14.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/14.alert_handler_ping_timeout.1255206763
Short name T316
Test name
Test status
Simulation time 44197361308 ps
CPU time 493.31 seconds
Started Feb 21 03:54:48 PM PST 24
Finished Feb 21 04:03:02 PM PST 24
Peak memory 247236 kb
Host smart-24c55f06-2d42-41ea-b778-a78bc359cba2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255206763 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_ping_timeout.1255206763
Directory /workspace/14.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_random_alerts.3353149790
Short name T538
Test name
Test status
Simulation time 191766839 ps
CPU time 13.47 seconds
Started Feb 21 03:54:46 PM PST 24
Finished Feb 21 03:55:00 PM PST 24
Peak memory 251972 kb
Host smart-39b80ed1-743f-43e7-88b4-cc02850d46b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33531
49790 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_alerts.3353149790
Directory /workspace/14.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/14.alert_handler_random_classes.1607192825
Short name T618
Test name
Test status
Simulation time 1256789835 ps
CPU time 53.94 seconds
Started Feb 21 03:54:44 PM PST 24
Finished Feb 21 03:55:39 PM PST 24
Peak memory 254712 kb
Host smart-1144ef5c-7165-4fce-afef-e926b013492a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16071
92825 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_classes.1607192825
Directory /workspace/14.alert_handler_random_classes/latest

Test location /workspace/coverage/default/14.alert_handler_sig_int_fail.1016390230
Short name T543
Test name
Test status
Simulation time 147223624 ps
CPU time 7.98 seconds
Started Feb 21 03:54:46 PM PST 24
Finished Feb 21 03:54:55 PM PST 24
Peak memory 248252 kb
Host smart-8179aade-2750-422a-bae2-f2687f710a21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10163
90230 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_sig_int_fail.1016390230
Directory /workspace/14.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/14.alert_handler_smoke.2359802932
Short name T112
Test name
Test status
Simulation time 389493184 ps
CPU time 22.37 seconds
Started Feb 21 03:54:44 PM PST 24
Finished Feb 21 03:55:08 PM PST 24
Peak memory 248228 kb
Host smart-e4a13387-32ed-4360-aa6b-04dc280ee1e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23598
02932 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_smoke.2359802932
Directory /workspace/14.alert_handler_smoke/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all.1440836647
Short name T274
Test name
Test status
Simulation time 33093651902 ps
CPU time 1724.46 seconds
Started Feb 21 03:54:43 PM PST 24
Finished Feb 21 04:23:29 PM PST 24
Peak memory 300796 kb
Host smart-bcc96991-20c7-4840-80d0-ead0320d92a6
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440836647 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_ha
ndler_stress_all.1440836647
Directory /workspace/14.alert_handler_stress_all/latest

Test location /workspace/coverage/default/15.alert_handler_alert_accum_saturation.3965138323
Short name T207
Test name
Test status
Simulation time 17307947 ps
CPU time 2.59 seconds
Started Feb 21 03:54:49 PM PST 24
Finished Feb 21 03:54:52 PM PST 24
Peak memory 248532 kb
Host smart-f6f1498a-ffa0-4c40-8016-10aa96536250
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3965138323 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_alert_accum_saturation.3965138323
Directory /workspace/15.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/15.alert_handler_entropy.516098148
Short name T391
Test name
Test status
Simulation time 97392540101 ps
CPU time 2676.62 seconds
Started Feb 21 03:54:45 PM PST 24
Finished Feb 21 04:39:24 PM PST 24
Peak memory 289216 kb
Host smart-67ba4bed-4093-4b31-b47c-3c4e27f9bf7d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516098148 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy.516098148
Directory /workspace/15.alert_handler_entropy/latest

Test location /workspace/coverage/default/15.alert_handler_entropy_stress.393584619
Short name T384
Test name
Test status
Simulation time 1181482802 ps
CPU time 51.97 seconds
Started Feb 21 03:54:50 PM PST 24
Finished Feb 21 03:55:43 PM PST 24
Peak memory 240004 kb
Host smart-dd496a6a-62b7-44a7-9c64-3214bb23aa5f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=393584619 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy_stress.393584619
Directory /workspace/15.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/15.alert_handler_esc_alert_accum.1881650827
Short name T440
Test name
Test status
Simulation time 25685670992 ps
CPU time 264.81 seconds
Started Feb 21 03:54:46 PM PST 24
Finished Feb 21 03:59:12 PM PST 24
Peak memory 256456 kb
Host smart-dd0e0a93-4c61-4414-9985-b2fcd407dabc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18816
50827 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_alert_accum.1881650827
Directory /workspace/15.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/15.alert_handler_esc_intr_timeout.808560433
Short name T699
Test name
Test status
Simulation time 204525926 ps
CPU time 5.13 seconds
Started Feb 21 03:54:42 PM PST 24
Finished Feb 21 03:54:49 PM PST 24
Peak memory 249636 kb
Host smart-9e0a46d2-5c6d-4e42-a095-b469740c32d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80856
0433 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_intr_timeout.808560433
Directory /workspace/15.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_lpg.4289643474
Short name T513
Test name
Test status
Simulation time 43644671659 ps
CPU time 1178.81 seconds
Started Feb 21 03:54:43 PM PST 24
Finished Feb 21 04:14:24 PM PST 24
Peak memory 272384 kb
Host smart-479ec560-9cce-4a29-8568-9151183eb544
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289643474 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg.4289643474
Directory /workspace/15.alert_handler_lpg/latest

Test location /workspace/coverage/default/15.alert_handler_lpg_stub_clk.1425822155
Short name T226
Test name
Test status
Simulation time 37239268498 ps
CPU time 1463.38 seconds
Started Feb 21 03:54:43 PM PST 24
Finished Feb 21 04:19:09 PM PST 24
Peak memory 288568 kb
Host smart-de989bfb-e8d6-42f2-a2bb-1743afbb37f4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425822155 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg_stub_clk.1425822155
Directory /workspace/15.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/15.alert_handler_ping_timeout.4039349836
Short name T319
Test name
Test status
Simulation time 46249165891 ps
CPU time 391.54 seconds
Started Feb 21 03:54:49 PM PST 24
Finished Feb 21 04:01:21 PM PST 24
Peak memory 246904 kb
Host smart-12bb3c97-7c60-42ce-9128-c414d65267e0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039349836 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_ping_timeout.4039349836
Directory /workspace/15.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_random_alerts.4113691793
Short name T694
Test name
Test status
Simulation time 2401923271 ps
CPU time 50.32 seconds
Started Feb 21 03:54:49 PM PST 24
Finished Feb 21 03:55:40 PM PST 24
Peak memory 255192 kb
Host smart-1dc319b1-7815-4542-ad96-7c2706f128f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41136
91793 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_alerts.4113691793
Directory /workspace/15.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/15.alert_handler_random_classes.3152525234
Short name T668
Test name
Test status
Simulation time 532055146 ps
CPU time 36.93 seconds
Started Feb 21 03:54:45 PM PST 24
Finished Feb 21 03:55:24 PM PST 24
Peak memory 254952 kb
Host smart-0acac092-d118-44f3-a2aa-17eb476e53be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31525
25234 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_classes.3152525234
Directory /workspace/15.alert_handler_random_classes/latest

Test location /workspace/coverage/default/15.alert_handler_sig_int_fail.3015996682
Short name T601
Test name
Test status
Simulation time 6774668668 ps
CPU time 24.72 seconds
Started Feb 21 03:54:48 PM PST 24
Finished Feb 21 03:55:14 PM PST 24
Peak memory 255324 kb
Host smart-6fed2f62-0aec-42f8-b801-4e0a822e9a60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30159
96682 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_sig_int_fail.3015996682
Directory /workspace/15.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/15.alert_handler_smoke.4084792756
Short name T518
Test name
Test status
Simulation time 1688456011 ps
CPU time 29.29 seconds
Started Feb 21 03:54:44 PM PST 24
Finished Feb 21 03:55:16 PM PST 24
Peak memory 248308 kb
Host smart-06f66bba-c12d-4d2f-bec6-2d21a15bcaec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40847
92756 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_smoke.4084792756
Directory /workspace/15.alert_handler_smoke/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all.2665483336
Short name T468
Test name
Test status
Simulation time 21408571609 ps
CPU time 565.96 seconds
Started Feb 21 03:54:45 PM PST 24
Finished Feb 21 04:04:13 PM PST 24
Peak memory 256528 kb
Host smart-b2f23336-6f67-4f82-bead-ffcbf63e57e3
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665483336 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_ha
ndler_stress_all.2665483336
Directory /workspace/15.alert_handler_stress_all/latest

Test location /workspace/coverage/default/16.alert_handler_alert_accum_saturation.2507867183
Short name T201
Test name
Test status
Simulation time 31460195 ps
CPU time 2.81 seconds
Started Feb 21 03:54:48 PM PST 24
Finished Feb 21 03:54:52 PM PST 24
Peak memory 256728 kb
Host smart-c19c8b61-df4b-4e6c-87bd-a80638695054
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2507867183 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_alert_accum_saturation.2507867183
Directory /workspace/16.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/16.alert_handler_entropy.2710782005
Short name T96
Test name
Test status
Simulation time 35382926712 ps
CPU time 718.18 seconds
Started Feb 21 03:54:47 PM PST 24
Finished Feb 21 04:06:46 PM PST 24
Peak memory 272316 kb
Host smart-a74f70c1-17cb-4cc9-966f-c4d53a292f37
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710782005 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy.2710782005
Directory /workspace/16.alert_handler_entropy/latest

Test location /workspace/coverage/default/16.alert_handler_entropy_stress.2938665007
Short name T416
Test name
Test status
Simulation time 561961262 ps
CPU time 8.42 seconds
Started Feb 21 03:54:52 PM PST 24
Finished Feb 21 03:55:01 PM PST 24
Peak memory 240048 kb
Host smart-444fbbc3-cf2c-4323-98d8-b01405e51aa0
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2938665007 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy_stress.2938665007
Directory /workspace/16.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/16.alert_handler_esc_alert_accum.3323337436
Short name T614
Test name
Test status
Simulation time 16891540702 ps
CPU time 224.4 seconds
Started Feb 21 03:54:50 PM PST 24
Finished Feb 21 03:58:35 PM PST 24
Peak memory 256456 kb
Host smart-bfcd1602-70fe-41a3-8ba2-1f03fbc7164d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33233
37436 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_alert_accum.3323337436
Directory /workspace/16.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/16.alert_handler_esc_intr_timeout.136039369
Short name T556
Test name
Test status
Simulation time 505846550 ps
CPU time 25.38 seconds
Started Feb 21 03:54:50 PM PST 24
Finished Feb 21 03:55:16 PM PST 24
Peak memory 246604 kb
Host smart-e36eb2d8-d42e-496e-9a16-14a438b9f768
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13603
9369 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_intr_timeout.136039369
Directory /workspace/16.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_lpg_stub_clk.2538032221
Short name T100
Test name
Test status
Simulation time 22514593566 ps
CPU time 599.61 seconds
Started Feb 21 03:54:50 PM PST 24
Finished Feb 21 04:04:50 PM PST 24
Peak memory 271596 kb
Host smart-2c80ef67-345c-4fb5-abbb-06a8dc22f248
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538032221 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg_stub_clk.2538032221
Directory /workspace/16.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/16.alert_handler_ping_timeout.2265507432
Short name T696
Test name
Test status
Simulation time 15858513851 ps
CPU time 341.43 seconds
Started Feb 21 03:54:46 PM PST 24
Finished Feb 21 04:00:28 PM PST 24
Peak memory 247188 kb
Host smart-6e1a0a64-ce08-45c2-875b-bc9cf3dea29a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265507432 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_ping_timeout.2265507432
Directory /workspace/16.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_random_alerts.167460099
Short name T587
Test name
Test status
Simulation time 555946883 ps
CPU time 37.77 seconds
Started Feb 21 03:54:50 PM PST 24
Finished Feb 21 03:55:28 PM PST 24
Peak memory 248228 kb
Host smart-ce0d7356-e8a9-460b-815c-f28e0d596fc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16746
0099 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_alerts.167460099
Directory /workspace/16.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/16.alert_handler_random_classes.2314171970
Short name T512
Test name
Test status
Simulation time 1423702348 ps
CPU time 38.95 seconds
Started Feb 21 03:54:48 PM PST 24
Finished Feb 21 03:55:28 PM PST 24
Peak memory 247828 kb
Host smart-bbe5df7f-ef31-495b-b53b-f899af976415
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23141
71970 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_classes.2314171970
Directory /workspace/16.alert_handler_random_classes/latest

Test location /workspace/coverage/default/16.alert_handler_sig_int_fail.821984695
Short name T51
Test name
Test status
Simulation time 1584491848 ps
CPU time 54.26 seconds
Started Feb 21 03:54:51 PM PST 24
Finished Feb 21 03:55:46 PM PST 24
Peak memory 254176 kb
Host smart-20ff3bf6-71e2-48c5-84de-54a749e47835
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82198
4695 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_sig_int_fail.821984695
Directory /workspace/16.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/16.alert_handler_smoke.2937129743
Short name T361
Test name
Test status
Simulation time 755046169 ps
CPU time 20.99 seconds
Started Feb 21 03:54:46 PM PST 24
Finished Feb 21 03:55:08 PM PST 24
Peak memory 255080 kb
Host smart-304ea4f6-01df-4677-8f9c-816cf11bb209
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29371
29743 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_smoke.2937129743
Directory /workspace/16.alert_handler_smoke/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all.2213213261
Short name T236
Test name
Test status
Simulation time 14307710374 ps
CPU time 1244.64 seconds
Started Feb 21 03:54:47 PM PST 24
Finished Feb 21 04:15:32 PM PST 24
Peak memory 288724 kb
Host smart-5fd12990-a046-403e-b964-0d9184f87594
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213213261 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_ha
ndler_stress_all.2213213261
Directory /workspace/16.alert_handler_stress_all/latest

Test location /workspace/coverage/default/17.alert_handler_alert_accum_saturation.73032079
Short name T199
Test name
Test status
Simulation time 38400706 ps
CPU time 3.96 seconds
Started Feb 21 03:54:58 PM PST 24
Finished Feb 21 03:55:02 PM PST 24
Peak memory 248536 kb
Host smart-2c989f7b-b491-40c2-b1d7-321409c56467
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=73032079 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_alert_accum_saturation.73032079
Directory /workspace/17.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/17.alert_handler_entropy.2878592602
Short name T516
Test name
Test status
Simulation time 142042686012 ps
CPU time 2817.12 seconds
Started Feb 21 03:54:54 PM PST 24
Finished Feb 21 04:41:51 PM PST 24
Peak memory 288688 kb
Host smart-1991a155-c669-40af-8f3c-ea38f569852e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878592602 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy.2878592602
Directory /workspace/17.alert_handler_entropy/latest

Test location /workspace/coverage/default/17.alert_handler_entropy_stress.1861978986
Short name T14
Test name
Test status
Simulation time 508259051 ps
CPU time 23.48 seconds
Started Feb 21 03:54:54 PM PST 24
Finished Feb 21 03:55:18 PM PST 24
Peak memory 240068 kb
Host smart-80aab052-7921-4e6e-9a0f-2ce609eb1117
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1861978986 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy_stress.1861978986
Directory /workspace/17.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/17.alert_handler_esc_alert_accum.3096905323
Short name T635
Test name
Test status
Simulation time 2390812811 ps
CPU time 39.55 seconds
Started Feb 21 03:54:53 PM PST 24
Finished Feb 21 03:55:33 PM PST 24
Peak memory 253884 kb
Host smart-a3d6d366-9183-43f4-983e-3a428fad7d44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30969
05323 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_alert_accum.3096905323
Directory /workspace/17.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/17.alert_handler_esc_intr_timeout.3203843030
Short name T281
Test name
Test status
Simulation time 1868960737 ps
CPU time 31.87 seconds
Started Feb 21 03:54:49 PM PST 24
Finished Feb 21 03:55:22 PM PST 24
Peak memory 247876 kb
Host smart-67cfb7f3-97bb-47ab-9d09-521720eb59a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32038
43030 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_intr_timeout.3203843030
Directory /workspace/17.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_lpg.2209245322
Short name T329
Test name
Test status
Simulation time 32853779535 ps
CPU time 1903.12 seconds
Started Feb 21 03:54:58 PM PST 24
Finished Feb 21 04:26:41 PM PST 24
Peak memory 281764 kb
Host smart-17257be8-d968-4715-92d3-b6b621088de7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2209245322 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg.2209245322
Directory /workspace/17.alert_handler_lpg/latest

Test location /workspace/coverage/default/17.alert_handler_lpg_stub_clk.249345670
Short name T217
Test name
Test status
Simulation time 26623164157 ps
CPU time 1480.78 seconds
Started Feb 21 03:54:52 PM PST 24
Finished Feb 21 04:19:34 PM PST 24
Peak memory 272916 kb
Host smart-e672a4dd-92e5-41ac-b94a-2e3b7510102a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249345670 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg_stub_clk.249345670
Directory /workspace/17.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/17.alert_handler_ping_timeout.3412429901
Short name T48
Test name
Test status
Simulation time 17743640786 ps
CPU time 343.29 seconds
Started Feb 21 03:54:53 PM PST 24
Finished Feb 21 04:00:37 PM PST 24
Peak memory 246924 kb
Host smart-f123097b-261b-456d-a8e2-a7fe83c6948c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412429901 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_ping_timeout.3412429901
Directory /workspace/17.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_random_alerts.2833583617
Short name T437
Test name
Test status
Simulation time 3307729514 ps
CPU time 15.87 seconds
Started Feb 21 03:54:47 PM PST 24
Finished Feb 21 03:55:03 PM PST 24
Peak memory 248204 kb
Host smart-22527246-b33c-4602-9949-05e95ebd225f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28335
83617 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_alerts.2833583617
Directory /workspace/17.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/17.alert_handler_random_classes.2101385995
Short name T507
Test name
Test status
Simulation time 206695096 ps
CPU time 4.15 seconds
Started Feb 21 03:54:49 PM PST 24
Finished Feb 21 03:54:54 PM PST 24
Peak memory 238340 kb
Host smart-9b83ac62-72e6-452b-bad8-a8f2b20b7f80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21013
85995 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_classes.2101385995
Directory /workspace/17.alert_handler_random_classes/latest

Test location /workspace/coverage/default/17.alert_handler_sig_int_fail.2051518578
Short name T455
Test name
Test status
Simulation time 347996177 ps
CPU time 18.67 seconds
Started Feb 21 03:54:54 PM PST 24
Finished Feb 21 03:55:13 PM PST 24
Peak memory 246768 kb
Host smart-178f15d2-a693-4596-b44b-ec621302006d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20515
18578 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_sig_int_fail.2051518578
Directory /workspace/17.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/17.alert_handler_smoke.3519104497
Short name T517
Test name
Test status
Simulation time 671033577 ps
CPU time 39.47 seconds
Started Feb 21 03:54:52 PM PST 24
Finished Feb 21 03:55:32 PM PST 24
Peak memory 248252 kb
Host smart-301553a3-8107-4f60-bbb6-a679c602aeb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35191
04497 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_smoke.3519104497
Directory /workspace/17.alert_handler_smoke/latest

Test location /workspace/coverage/default/18.alert_handler_alert_accum_saturation.4276165802
Short name T212
Test name
Test status
Simulation time 35750528 ps
CPU time 3.67 seconds
Started Feb 21 03:55:00 PM PST 24
Finished Feb 21 03:55:04 PM PST 24
Peak memory 248520 kb
Host smart-921c5782-0984-436f-9db9-8fe80cbc0eac
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4276165802 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_alert_accum_saturation.4276165802
Directory /workspace/18.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/18.alert_handler_entropy.133794779
Short name T404
Test name
Test status
Simulation time 50667254483 ps
CPU time 880.51 seconds
Started Feb 21 03:55:02 PM PST 24
Finished Feb 21 04:09:43 PM PST 24
Peak memory 270940 kb
Host smart-b01bc157-7aea-461a-88dd-4c84c2c53055
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133794779 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy.133794779
Directory /workspace/18.alert_handler_entropy/latest

Test location /workspace/coverage/default/18.alert_handler_entropy_stress.1299598237
Short name T489
Test name
Test status
Simulation time 148681236 ps
CPU time 9.12 seconds
Started Feb 21 03:55:04 PM PST 24
Finished Feb 21 03:55:13 PM PST 24
Peak memory 240052 kb
Host smart-226d1a0b-8f17-4433-adcf-6171a0e74da5
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1299598237 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy_stress.1299598237
Directory /workspace/18.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/18.alert_handler_esc_alert_accum.2618069567
Short name T43
Test name
Test status
Simulation time 4813883995 ps
CPU time 154.94 seconds
Started Feb 21 03:55:00 PM PST 24
Finished Feb 21 03:57:35 PM PST 24
Peak memory 255532 kb
Host smart-bce68948-1f26-4995-981a-c7d0e400c3aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26180
69567 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_alert_accum.2618069567
Directory /workspace/18.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/18.alert_handler_esc_intr_timeout.2740655358
Short name T552
Test name
Test status
Simulation time 830321516 ps
CPU time 50.92 seconds
Started Feb 21 03:55:01 PM PST 24
Finished Feb 21 03:55:52 PM PST 24
Peak memory 254036 kb
Host smart-f086408a-d61a-4933-bbc7-4064c52b5fdb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27406
55358 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_intr_timeout.2740655358
Directory /workspace/18.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_lpg.1437748993
Short name T326
Test name
Test status
Simulation time 25497946018 ps
CPU time 1603.42 seconds
Started Feb 21 03:55:09 PM PST 24
Finished Feb 21 04:21:53 PM PST 24
Peak memory 285848 kb
Host smart-c8c28cd1-8702-4965-8ae0-5f93c21557ba
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437748993 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg.1437748993
Directory /workspace/18.alert_handler_lpg/latest

Test location /workspace/coverage/default/18.alert_handler_lpg_stub_clk.1656790543
Short name T649
Test name
Test status
Simulation time 10652795710 ps
CPU time 1094.93 seconds
Started Feb 21 03:55:00 PM PST 24
Finished Feb 21 04:13:15 PM PST 24
Peak memory 288064 kb
Host smart-642ce077-3e72-482b-9439-1a5e890a89fd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1656790543 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg_stub_clk.1656790543
Directory /workspace/18.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/18.alert_handler_ping_timeout.3808002279
Short name T606
Test name
Test status
Simulation time 11288107006 ps
CPU time 468.25 seconds
Started Feb 21 03:55:08 PM PST 24
Finished Feb 21 04:02:57 PM PST 24
Peak memory 246640 kb
Host smart-f1c571d4-36f4-44cb-8e0b-b6b74abea85f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808002279 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_ping_timeout.3808002279
Directory /workspace/18.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_random_alerts.3096531437
Short name T613
Test name
Test status
Simulation time 440002110 ps
CPU time 22.89 seconds
Started Feb 21 03:54:53 PM PST 24
Finished Feb 21 03:55:17 PM PST 24
Peak memory 248192 kb
Host smart-404ca841-46ca-46a5-82d1-e11670a82507
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30965
31437 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_alerts.3096531437
Directory /workspace/18.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/18.alert_handler_random_classes.374071587
Short name T648
Test name
Test status
Simulation time 1364343333 ps
CPU time 29.53 seconds
Started Feb 21 03:54:54 PM PST 24
Finished Feb 21 03:55:24 PM PST 24
Peak memory 247920 kb
Host smart-c8b8a729-9b9e-440c-a5cb-b160920bc9fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37407
1587 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_classes.374071587
Directory /workspace/18.alert_handler_random_classes/latest

Test location /workspace/coverage/default/18.alert_handler_sig_int_fail.3238539356
Short name T276
Test name
Test status
Simulation time 2011837663 ps
CPU time 34.63 seconds
Started Feb 21 03:55:04 PM PST 24
Finished Feb 21 03:55:39 PM PST 24
Peak memory 254912 kb
Host smart-5e01e7c0-4dc6-4cf7-98a9-14417acab576
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32385
39356 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_sig_int_fail.3238539356
Directory /workspace/18.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/18.alert_handler_smoke.2627180683
Short name T584
Test name
Test status
Simulation time 164072359 ps
CPU time 3.66 seconds
Started Feb 21 03:54:55 PM PST 24
Finished Feb 21 03:54:59 PM PST 24
Peak memory 240028 kb
Host smart-d1ddb14b-c3e9-4384-aabf-bb1233c28330
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26271
80683 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_smoke.2627180683
Directory /workspace/18.alert_handler_smoke/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all.1627183361
Short name T630
Test name
Test status
Simulation time 53116266845 ps
CPU time 2749.67 seconds
Started Feb 21 03:55:05 PM PST 24
Finished Feb 21 04:40:55 PM PST 24
Peak memory 288244 kb
Host smart-9229ed5b-d7b1-4f46-910d-cc447a1baa3d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627183361 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_ha
ndler_stress_all.1627183361
Directory /workspace/18.alert_handler_stress_all/latest

Test location /workspace/coverage/default/19.alert_handler_alert_accum_saturation.1623667111
Short name T203
Test name
Test status
Simulation time 112864147 ps
CPU time 3.33 seconds
Started Feb 21 03:55:19 PM PST 24
Finished Feb 21 03:55:24 PM PST 24
Peak memory 248576 kb
Host smart-3b7001b5-79aa-488c-9820-274437d680f5
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1623667111 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_alert_accum_saturation.1623667111
Directory /workspace/19.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/19.alert_handler_entropy.2500610863
Short name T443
Test name
Test status
Simulation time 43716776422 ps
CPU time 884.69 seconds
Started Feb 21 03:55:22 PM PST 24
Finished Feb 21 04:10:07 PM PST 24
Peak memory 269852 kb
Host smart-8425a71b-60a9-4ae6-a4b9-20b05fcf2cd6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2500610863 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy.2500610863
Directory /workspace/19.alert_handler_entropy/latest

Test location /workspace/coverage/default/19.alert_handler_entropy_stress.2607466872
Short name T688
Test name
Test status
Simulation time 399294624 ps
CPU time 11.81 seconds
Started Feb 21 03:55:24 PM PST 24
Finished Feb 21 03:55:36 PM PST 24
Peak memory 240076 kb
Host smart-0be7d67f-1b26-4343-b1e1-20d9b08dbbcc
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2607466872 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy_stress.2607466872
Directory /workspace/19.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/19.alert_handler_esc_alert_accum.1236656041
Short name T419
Test name
Test status
Simulation time 1356866444 ps
CPU time 90.64 seconds
Started Feb 21 03:55:20 PM PST 24
Finished Feb 21 03:56:52 PM PST 24
Peak memory 247924 kb
Host smart-a1b43230-f07b-4f32-9e20-99ac315fe3ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12366
56041 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_alert_accum.1236656041
Directory /workspace/19.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/19.alert_handler_esc_intr_timeout.1352083243
Short name T397
Test name
Test status
Simulation time 577240344 ps
CPU time 32.25 seconds
Started Feb 21 03:55:18 PM PST 24
Finished Feb 21 03:55:52 PM PST 24
Peak memory 255660 kb
Host smart-5e3f250f-36a3-4265-ae75-b5bca2b93da3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13520
83243 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_intr_timeout.1352083243
Directory /workspace/19.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_lpg.3310538925
Short name T322
Test name
Test status
Simulation time 98954765341 ps
CPU time 1264.49 seconds
Started Feb 21 03:55:53 PM PST 24
Finished Feb 21 04:16:58 PM PST 24
Peak memory 271044 kb
Host smart-70472387-1c34-4f0d-a2a7-a75ae51fea1c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310538925 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg.3310538925
Directory /workspace/19.alert_handler_lpg/latest

Test location /workspace/coverage/default/19.alert_handler_lpg_stub_clk.3412240675
Short name T500
Test name
Test status
Simulation time 8293147063 ps
CPU time 728.16 seconds
Started Feb 21 03:55:23 PM PST 24
Finished Feb 21 04:07:32 PM PST 24
Peak memory 272780 kb
Host smart-6d5be63a-3abf-4401-a971-e4c5774b8e03
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412240675 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg_stub_clk.3412240675
Directory /workspace/19.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/19.alert_handler_ping_timeout.2501964771
Short name T313
Test name
Test status
Simulation time 6282902795 ps
CPU time 258.7 seconds
Started Feb 21 03:55:21 PM PST 24
Finished Feb 21 03:59:41 PM PST 24
Peak memory 247116 kb
Host smart-0443488a-f408-4699-9dd3-17cdf7da5351
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501964771 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_ping_timeout.2501964771
Directory /workspace/19.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_random_alerts.2732344098
Short name T223
Test name
Test status
Simulation time 1112980585 ps
CPU time 29.49 seconds
Started Feb 21 03:55:18 PM PST 24
Finished Feb 21 03:55:49 PM PST 24
Peak memory 248232 kb
Host smart-8880d3f4-8578-4e7a-8eb2-694f42193d8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27323
44098 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_alerts.2732344098
Directory /workspace/19.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/19.alert_handler_random_classes.1672990182
Short name T650
Test name
Test status
Simulation time 1748720602 ps
CPU time 60.34 seconds
Started Feb 21 03:55:52 PM PST 24
Finished Feb 21 03:56:52 PM PST 24
Peak memory 254808 kb
Host smart-d402cb7a-48d2-4818-bdde-031dfb3b0df8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16729
90182 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_classes.1672990182
Directory /workspace/19.alert_handler_random_classes/latest

Test location /workspace/coverage/default/19.alert_handler_smoke.698822422
Short name T218
Test name
Test status
Simulation time 143100828 ps
CPU time 6.85 seconds
Started Feb 21 03:55:18 PM PST 24
Finished Feb 21 03:55:27 PM PST 24
Peak memory 248264 kb
Host smart-c3f9f477-0149-4629-9756-edc929d2296c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69882
2422 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_smoke.698822422
Directory /workspace/19.alert_handler_smoke/latest

Test location /workspace/coverage/default/2.alert_handler_alert_accum_saturation.350923384
Short name T200
Test name
Test status
Simulation time 35451571 ps
CPU time 2.63 seconds
Started Feb 21 03:53:38 PM PST 24
Finished Feb 21 03:53:41 PM PST 24
Peak memory 248520 kb
Host smart-06e63e52-9644-4b70-bfb2-5f73978f4f44
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=350923384 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_alert_accum_saturation.350923384
Directory /workspace/2.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/2.alert_handler_entropy.1691935419
Short name T110
Test name
Test status
Simulation time 192024891005 ps
CPU time 2032.55 seconds
Started Feb 21 03:53:44 PM PST 24
Finished Feb 21 04:27:38 PM PST 24
Peak memory 284036 kb
Host smart-10b161f1-4efd-4cd7-b632-2fe9bf273582
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691935419 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy.1691935419
Directory /workspace/2.alert_handler_entropy/latest

Test location /workspace/coverage/default/2.alert_handler_entropy_stress.2139359307
Short name T381
Test name
Test status
Simulation time 225589925 ps
CPU time 13.11 seconds
Started Feb 21 03:53:47 PM PST 24
Finished Feb 21 03:54:02 PM PST 24
Peak memory 240032 kb
Host smart-b57b703d-ccb7-4ae4-871c-52540b17e9ea
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2139359307 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy_stress.2139359307
Directory /workspace/2.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/2.alert_handler_esc_alert_accum.2708831583
Short name T603
Test name
Test status
Simulation time 4205478320 ps
CPU time 230.65 seconds
Started Feb 21 03:53:44 PM PST 24
Finished Feb 21 03:57:36 PM PST 24
Peak memory 255668 kb
Host smart-53ed56e9-fd5d-4079-89c9-727fca9f8753
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27088
31583 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_alert_accum.2708831583
Directory /workspace/2.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/2.alert_handler_esc_intr_timeout.1585704359
Short name T47
Test name
Test status
Simulation time 278163549 ps
CPU time 6.7 seconds
Started Feb 21 03:53:44 PM PST 24
Finished Feb 21 03:53:53 PM PST 24
Peak memory 250612 kb
Host smart-8a4af581-c659-428a-a132-9dcea3897030
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15857
04359 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_intr_timeout.1585704359
Directory /workspace/2.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_lpg.2977040656
Short name T535
Test name
Test status
Simulation time 17674133598 ps
CPU time 716.69 seconds
Started Feb 21 03:53:45 PM PST 24
Finished Feb 21 04:05:43 PM PST 24
Peak memory 272204 kb
Host smart-029718ee-1c13-497a-8eeb-a90b738bd2ed
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977040656 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg.2977040656
Directory /workspace/2.alert_handler_lpg/latest

Test location /workspace/coverage/default/2.alert_handler_lpg_stub_clk.1649169598
Short name T492
Test name
Test status
Simulation time 34681103987 ps
CPU time 2071.54 seconds
Started Feb 21 03:53:43 PM PST 24
Finished Feb 21 04:28:17 PM PST 24
Peak memory 285824 kb
Host smart-7b860e3b-bb1b-40ac-ab84-e55b34976ad1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1649169598 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg_stub_clk.1649169598
Directory /workspace/2.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/2.alert_handler_random_alerts.3261592975
Short name T33
Test name
Test status
Simulation time 329418541 ps
CPU time 31.64 seconds
Started Feb 21 03:53:47 PM PST 24
Finished Feb 21 03:54:21 PM PST 24
Peak memory 248248 kb
Host smart-352ca967-cca9-40e2-b6e1-7ebefc479647
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32615
92975 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_alerts.3261592975
Directory /workspace/2.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/2.alert_handler_random_classes.2480661839
Short name T565
Test name
Test status
Simulation time 152218750 ps
CPU time 3.64 seconds
Started Feb 21 03:53:41 PM PST 24
Finished Feb 21 03:53:46 PM PST 24
Peak memory 238316 kb
Host smart-5c164809-7377-4dd2-af42-c7817add958a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24806
61839 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_classes.2480661839
Directory /workspace/2.alert_handler_random_classes/latest

Test location /workspace/coverage/default/2.alert_handler_sec_cm.2718445738
Short name T38
Test name
Test status
Simulation time 1357662652 ps
CPU time 21.15 seconds
Started Feb 21 03:53:45 PM PST 24
Finished Feb 21 03:54:07 PM PST 24
Peak memory 268976 kb
Host smart-c8c0a491-001e-4c67-a35c-b4f888e98c76
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2718445738 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sec_cm.2718445738
Directory /workspace/2.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/2.alert_handler_sig_int_fail.3905618524
Short name T270
Test name
Test status
Simulation time 172317165 ps
CPU time 13.43 seconds
Started Feb 21 03:53:36 PM PST 24
Finished Feb 21 03:53:50 PM PST 24
Peak memory 246724 kb
Host smart-913a469f-df18-425b-94c1-a08651356827
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39056
18524 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sig_int_fail.3905618524
Directory /workspace/2.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/2.alert_handler_smoke.2311573892
Short name T186
Test name
Test status
Simulation time 346493564 ps
CPU time 8.14 seconds
Started Feb 21 03:53:42 PM PST 24
Finished Feb 21 03:53:51 PM PST 24
Peak memory 248268 kb
Host smart-86b84dff-e340-4ca7-8e7d-702771e9c5ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23115
73892 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_smoke.2311573892
Directory /workspace/2.alert_handler_smoke/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all.1098501416
Short name T2
Test name
Test status
Simulation time 65347139731 ps
CPU time 591.55 seconds
Started Feb 21 03:53:48 PM PST 24
Finished Feb 21 04:03:42 PM PST 24
Peak memory 256512 kb
Host smart-3122b05b-df9b-4cf7-95f2-f4289c2c318a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098501416 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_han
dler_stress_all.1098501416
Directory /workspace/2.alert_handler_stress_all/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all_with_rand_reset.1952886443
Short name T105
Test name
Test status
Simulation time 56100840617 ps
CPU time 5535.98 seconds
Started Feb 21 03:53:44 PM PST 24
Finished Feb 21 05:26:02 PM PST 24
Peak memory 354952 kb
Host smart-c9e04f51-232b-46ad-95d8-9533ef1b3372
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952886443 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.alert_handler_stress_all_with_rand_reset.1952886443
Directory /workspace/2.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.alert_handler_entropy.3512748054
Short name T111
Test name
Test status
Simulation time 34477851528 ps
CPU time 2130.21 seconds
Started Feb 21 03:55:36 PM PST 24
Finished Feb 21 04:31:06 PM PST 24
Peak memory 289304 kb
Host smart-42dda93c-7f58-4b19-a676-9ea4be6d1e4c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512748054 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_entropy.3512748054
Directory /workspace/20.alert_handler_entropy/latest

Test location /workspace/coverage/default/20.alert_handler_esc_alert_accum.418750273
Short name T591
Test name
Test status
Simulation time 713454221 ps
CPU time 62.1 seconds
Started Feb 21 03:55:50 PM PST 24
Finished Feb 21 03:56:52 PM PST 24
Peak memory 255776 kb
Host smart-5fa9918f-f552-4276-89ca-7dba01589a7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41875
0273 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_alert_accum.418750273
Directory /workspace/20.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/20.alert_handler_esc_intr_timeout.3101002700
Short name T515
Test name
Test status
Simulation time 5440929973 ps
CPU time 40.52 seconds
Started Feb 21 03:55:50 PM PST 24
Finished Feb 21 03:56:30 PM PST 24
Peak memory 254224 kb
Host smart-315d5120-fe09-4881-aa3f-4ea8c634e4d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31010
02700 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_intr_timeout.3101002700
Directory /workspace/20.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_lpg.274558382
Short name T103
Test name
Test status
Simulation time 20822028006 ps
CPU time 1335.1 seconds
Started Feb 21 03:55:38 PM PST 24
Finished Feb 21 04:17:53 PM PST 24
Peak memory 282780 kb
Host smart-da8fb853-f5d7-40f2-aee4-38a704603a04
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274558382 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg.274558382
Directory /workspace/20.alert_handler_lpg/latest

Test location /workspace/coverage/default/20.alert_handler_lpg_stub_clk.1800783151
Short name T701
Test name
Test status
Simulation time 169278165578 ps
CPU time 2484.42 seconds
Started Feb 21 03:55:52 PM PST 24
Finished Feb 21 04:37:17 PM PST 24
Peak memory 288724 kb
Host smart-b995d86e-d14b-4930-9d17-731953f19706
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800783151 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg_stub_clk.1800783151
Directory /workspace/20.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/20.alert_handler_ping_timeout.1362574675
Short name T420
Test name
Test status
Simulation time 3663802600 ps
CPU time 155.52 seconds
Started Feb 21 03:55:53 PM PST 24
Finished Feb 21 03:58:29 PM PST 24
Peak memory 246968 kb
Host smart-0e7ac7aa-4a3c-4f5d-bf49-2faf2a53d3b0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362574675 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_ping_timeout.1362574675
Directory /workspace/20.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_random_alerts.2645165021
Short name T464
Test name
Test status
Simulation time 804897239 ps
CPU time 16.63 seconds
Started Feb 21 03:55:50 PM PST 24
Finished Feb 21 03:56:07 PM PST 24
Peak memory 248272 kb
Host smart-1a1d1ede-9e20-4624-aaa5-29d0886af846
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26451
65021 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_alerts.2645165021
Directory /workspace/20.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/20.alert_handler_random_classes.1160764860
Short name T558
Test name
Test status
Simulation time 5405779417 ps
CPU time 36.38 seconds
Started Feb 21 03:55:34 PM PST 24
Finished Feb 21 03:56:11 PM PST 24
Peak memory 253948 kb
Host smart-952eabaf-c443-475c-9901-9efb8a9d307f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11607
64860 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_classes.1160764860
Directory /workspace/20.alert_handler_random_classes/latest

Test location /workspace/coverage/default/20.alert_handler_sig_int_fail.1463105356
Short name T240
Test name
Test status
Simulation time 1669563737 ps
CPU time 30.53 seconds
Started Feb 21 03:55:57 PM PST 24
Finished Feb 21 03:56:27 PM PST 24
Peak memory 254912 kb
Host smart-ea58ceac-441f-4887-936d-22dfcf8bf699
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14631
05356 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_sig_int_fail.1463105356
Directory /workspace/20.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/20.alert_handler_smoke.783387920
Short name T66
Test name
Test status
Simulation time 316653367 ps
CPU time 28.12 seconds
Started Feb 21 03:55:21 PM PST 24
Finished Feb 21 03:55:50 PM PST 24
Peak memory 255040 kb
Host smart-dd3c3f23-90f1-471b-b73f-810175264a87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78338
7920 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_smoke.783387920
Directory /workspace/20.alert_handler_smoke/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all.2547401802
Short name T700
Test name
Test status
Simulation time 29076543876 ps
CPU time 1754.31 seconds
Started Feb 21 03:55:34 PM PST 24
Finished Feb 21 04:24:48 PM PST 24
Peak memory 285520 kb
Host smart-e3560b6e-9b59-4ef9-836f-ffa2dbf95c89
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547401802 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_ha
ndler_stress_all.2547401802
Directory /workspace/20.alert_handler_stress_all/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all_with_rand_reset.3858933844
Short name T235
Test name
Test status
Simulation time 91319967051 ps
CPU time 1560.33 seconds
Started Feb 21 03:55:20 PM PST 24
Finished Feb 21 04:21:22 PM PST 24
Peak memory 287060 kb
Host smart-a046e57f-9fc9-4e0c-bdb9-d4aa8b47d1ac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858933844 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 20.alert_handler_stress_all_with_rand_reset.3858933844
Directory /workspace/20.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.alert_handler_entropy.2114432147
Short name T462
Test name
Test status
Simulation time 23850928759 ps
CPU time 1619.48 seconds
Started Feb 21 03:55:57 PM PST 24
Finished Feb 21 04:22:57 PM PST 24
Peak memory 272652 kb
Host smart-791dd7a9-427f-4628-8bd6-f0bd7cb50c4e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114432147 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_entropy.2114432147
Directory /workspace/21.alert_handler_entropy/latest

Test location /workspace/coverage/default/21.alert_handler_esc_alert_accum.4135830587
Short name T396
Test name
Test status
Simulation time 4846276012 ps
CPU time 264.49 seconds
Started Feb 21 03:55:54 PM PST 24
Finished Feb 21 04:00:19 PM PST 24
Peak memory 256484 kb
Host smart-dfb09317-e3b3-4c95-aa27-8010646579a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41358
30587 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_alert_accum.4135830587
Directory /workspace/21.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/21.alert_handler_esc_intr_timeout.1451308896
Short name T665
Test name
Test status
Simulation time 282714083 ps
CPU time 13.65 seconds
Started Feb 21 03:55:57 PM PST 24
Finished Feb 21 03:56:11 PM PST 24
Peak memory 253748 kb
Host smart-b6d627ab-f7b2-40c1-94c2-479e85ec260d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14513
08896 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_intr_timeout.1451308896
Directory /workspace/21.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_lpg_stub_clk.3673306272
Short name T424
Test name
Test status
Simulation time 121365646340 ps
CPU time 1532.33 seconds
Started Feb 21 03:55:38 PM PST 24
Finished Feb 21 04:21:10 PM PST 24
Peak memory 271832 kb
Host smart-03a4babf-cca1-4daf-adff-a1d3b37da1bf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673306272 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg_stub_clk.3673306272
Directory /workspace/21.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/21.alert_handler_ping_timeout.881233112
Short name T312
Test name
Test status
Simulation time 81163845722 ps
CPU time 494.01 seconds
Started Feb 21 03:55:52 PM PST 24
Finished Feb 21 04:04:06 PM PST 24
Peak memory 247180 kb
Host smart-d1ff72a6-ce02-47df-80ff-86b26cddbb9a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881233112 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_ping_timeout.881233112
Directory /workspace/21.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_random_alerts.1002954635
Short name T510
Test name
Test status
Simulation time 180814186 ps
CPU time 11.41 seconds
Started Feb 21 03:55:20 PM PST 24
Finished Feb 21 03:55:33 PM PST 24
Peak memory 252976 kb
Host smart-092b97bc-e755-47ab-ae6d-b478e237ab13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10029
54635 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_alerts.1002954635
Directory /workspace/21.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/21.alert_handler_random_classes.26122740
Short name T213
Test name
Test status
Simulation time 1396131858 ps
CPU time 28.28 seconds
Started Feb 21 03:55:23 PM PST 24
Finished Feb 21 03:55:52 PM PST 24
Peak memory 255228 kb
Host smart-82121383-72d8-4d5c-810f-5c0313d23b7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26122
740 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_classes.26122740
Directory /workspace/21.alert_handler_random_classes/latest

Test location /workspace/coverage/default/21.alert_handler_sig_int_fail.1705680459
Short name T580
Test name
Test status
Simulation time 2979931570 ps
CPU time 37.4 seconds
Started Feb 21 03:55:20 PM PST 24
Finished Feb 21 03:55:59 PM PST 24
Peak memory 254300 kb
Host smart-801db353-9103-4eff-80ef-6cae9fa94ef9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17056
80459 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_sig_int_fail.1705680459
Directory /workspace/21.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/21.alert_handler_smoke.666958904
Short name T596
Test name
Test status
Simulation time 1274715434 ps
CPU time 29.87 seconds
Started Feb 21 03:55:51 PM PST 24
Finished Feb 21 03:56:21 PM PST 24
Peak memory 248232 kb
Host smart-fc10d3d7-1c42-4feb-b52c-8feca394fafc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66695
8904 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_smoke.666958904
Directory /workspace/21.alert_handler_smoke/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all.829791154
Short name T85
Test name
Test status
Simulation time 21102048341 ps
CPU time 554.33 seconds
Started Feb 21 03:55:49 PM PST 24
Finished Feb 21 04:05:04 PM PST 24
Peak memory 264728 kb
Host smart-49a70b37-7e72-4677-a99a-24c1b4bb27d7
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829791154 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_han
dler_stress_all.829791154
Directory /workspace/21.alert_handler_stress_all/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all_with_rand_reset.1363266071
Short name T261
Test name
Test status
Simulation time 191203749642 ps
CPU time 4828.16 seconds
Started Feb 21 03:55:36 PM PST 24
Finished Feb 21 05:16:04 PM PST 24
Peak memory 347424 kb
Host smart-a63e1b42-a5f5-49a2-8836-5e4fa394a00f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363266071 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.alert_handler_stress_all_with_rand_reset.1363266071
Directory /workspace/21.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.alert_handler_entropy.170664207
Short name T609
Test name
Test status
Simulation time 12629289774 ps
CPU time 1342.64 seconds
Started Feb 21 03:55:52 PM PST 24
Finished Feb 21 04:18:15 PM PST 24
Peak memory 289132 kb
Host smart-de46134b-2687-4062-a7a0-adca9ea04fd3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=170664207 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_entropy.170664207
Directory /workspace/22.alert_handler_entropy/latest

Test location /workspace/coverage/default/22.alert_handler_esc_alert_accum.699020102
Short name T557
Test name
Test status
Simulation time 15210228501 ps
CPU time 241.38 seconds
Started Feb 21 03:55:52 PM PST 24
Finished Feb 21 03:59:54 PM PST 24
Peak memory 256512 kb
Host smart-e50cb09f-b8c5-428e-9c25-1e6129e48068
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69902
0102 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_alert_accum.699020102
Directory /workspace/22.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/22.alert_handler_esc_intr_timeout.2175101545
Short name T446
Test name
Test status
Simulation time 208545856 ps
CPU time 13.35 seconds
Started Feb 21 03:55:51 PM PST 24
Finished Feb 21 03:56:05 PM PST 24
Peak memory 251060 kb
Host smart-c6e6275a-75e0-4c90-8cd1-878dc6ac9c86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21751
01545 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_intr_timeout.2175101545
Directory /workspace/22.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_lpg_stub_clk.3506680169
Short name T264
Test name
Test status
Simulation time 165364051587 ps
CPU time 2439.31 seconds
Started Feb 21 03:55:51 PM PST 24
Finished Feb 21 04:36:31 PM PST 24
Peak memory 288608 kb
Host smart-bc91b043-2786-4e3b-b94a-16251e63d0a5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506680169 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg_stub_clk.3506680169
Directory /workspace/22.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/22.alert_handler_ping_timeout.828519907
Short name T292
Test name
Test status
Simulation time 12518967977 ps
CPU time 555.67 seconds
Started Feb 21 03:55:34 PM PST 24
Finished Feb 21 04:04:50 PM PST 24
Peak memory 248316 kb
Host smart-f78fecde-69bd-4a0e-9ed8-6435f17008ed
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=828519907 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_ping_timeout.828519907
Directory /workspace/22.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_random_alerts.4179842330
Short name T363
Test name
Test status
Simulation time 1588403279 ps
CPU time 47.69 seconds
Started Feb 21 03:55:54 PM PST 24
Finished Feb 21 03:56:42 PM PST 24
Peak memory 255128 kb
Host smart-d511ed5a-746f-4366-a7c8-84e85a80ac74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41798
42330 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_alerts.4179842330
Directory /workspace/22.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/22.alert_handler_random_classes.1732695508
Short name T598
Test name
Test status
Simulation time 317677667 ps
CPU time 5.6 seconds
Started Feb 21 03:55:49 PM PST 24
Finished Feb 21 03:55:55 PM PST 24
Peak memory 238348 kb
Host smart-5ac30938-6011-486a-8c46-dffb72a1718b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17326
95508 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_classes.1732695508
Directory /workspace/22.alert_handler_random_classes/latest

Test location /workspace/coverage/default/22.alert_handler_sig_int_fail.825340533
Short name T607
Test name
Test status
Simulation time 1672172882 ps
CPU time 32.29 seconds
Started Feb 21 03:55:50 PM PST 24
Finished Feb 21 03:56:23 PM PST 24
Peak memory 254064 kb
Host smart-bfde5e58-9798-411c-9285-db3f28cfd843
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82534
0533 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_sig_int_fail.825340533
Directory /workspace/22.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/22.alert_handler_smoke.4205542029
Short name T505
Test name
Test status
Simulation time 898474389 ps
CPU time 58.04 seconds
Started Feb 21 03:55:21 PM PST 24
Finished Feb 21 03:56:20 PM PST 24
Peak memory 248188 kb
Host smart-249de9ab-96f6-444f-9173-49da21a3fcc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42055
42029 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_smoke.4205542029
Directory /workspace/22.alert_handler_smoke/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all.3304397345
Short name T514
Test name
Test status
Simulation time 1145544015 ps
CPU time 120.04 seconds
Started Feb 21 03:55:52 PM PST 24
Finished Feb 21 03:57:52 PM PST 24
Peak memory 256452 kb
Host smart-b782d3fd-63c5-4b90-8af6-65136dbf4cbd
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304397345 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_ha
ndler_stress_all.3304397345
Directory /workspace/22.alert_handler_stress_all/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all_with_rand_reset.3001400154
Short name T499
Test name
Test status
Simulation time 100123206932 ps
CPU time 2609.79 seconds
Started Feb 21 03:56:04 PM PST 24
Finished Feb 21 04:39:35 PM PST 24
Peak memory 330240 kb
Host smart-d9572010-be9e-4faf-a170-ffcb28fc160e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001400154 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 22.alert_handler_stress_all_with_rand_reset.3001400154
Directory /workspace/22.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.alert_handler_entropy.1529228400
Short name T407
Test name
Test status
Simulation time 19482956044 ps
CPU time 896.73 seconds
Started Feb 21 03:55:50 PM PST 24
Finished Feb 21 04:10:47 PM PST 24
Peak memory 288732 kb
Host smart-fc4f0b0c-003b-4b4b-a1f0-a9ac01015c68
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529228400 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_entropy.1529228400
Directory /workspace/23.alert_handler_entropy/latest

Test location /workspace/coverage/default/23.alert_handler_esc_alert_accum.2567580551
Short name T476
Test name
Test status
Simulation time 748261665 ps
CPU time 53.94 seconds
Started Feb 21 03:55:59 PM PST 24
Finished Feb 21 03:56:54 PM PST 24
Peak memory 255612 kb
Host smart-8223d68e-ab56-4200-a566-657db42f43a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25675
80551 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_alert_accum.2567580551
Directory /workspace/23.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/23.alert_handler_esc_intr_timeout.2191764469
Short name T617
Test name
Test status
Simulation time 1240906303 ps
CPU time 68.75 seconds
Started Feb 21 03:55:53 PM PST 24
Finished Feb 21 03:57:02 PM PST 24
Peak memory 254508 kb
Host smart-85863885-1a8b-4832-bdcd-61d124d8a705
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21917
64469 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_intr_timeout.2191764469
Directory /workspace/23.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_lpg.1982363657
Short name T219
Test name
Test status
Simulation time 173351650165 ps
CPU time 2269 seconds
Started Feb 21 03:55:50 PM PST 24
Finished Feb 21 04:33:39 PM PST 24
Peak memory 272304 kb
Host smart-f85fb6a3-aabd-464f-8b55-529b8b168354
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982363657 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg.1982363657
Directory /workspace/23.alert_handler_lpg/latest

Test location /workspace/coverage/default/23.alert_handler_lpg_stub_clk.1580438973
Short name T13
Test name
Test status
Simulation time 9248325448 ps
CPU time 916.43 seconds
Started Feb 21 03:55:45 PM PST 24
Finished Feb 21 04:11:02 PM PST 24
Peak memory 288212 kb
Host smart-3984ef8f-7000-428a-a8c2-f4be2114d65e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580438973 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg_stub_clk.1580438973
Directory /workspace/23.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/23.alert_handler_random_alerts.539700145
Short name T488
Test name
Test status
Simulation time 459428192 ps
CPU time 14.57 seconds
Started Feb 21 03:55:57 PM PST 24
Finished Feb 21 03:56:11 PM PST 24
Peak memory 248252 kb
Host smart-cf540c89-61f3-4eda-8391-1ea22bfa7ef2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53970
0145 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_alerts.539700145
Directory /workspace/23.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/23.alert_handler_random_classes.1722572929
Short name T117
Test name
Test status
Simulation time 228359800 ps
CPU time 24.24 seconds
Started Feb 21 03:56:02 PM PST 24
Finished Feb 21 03:56:26 PM PST 24
Peak memory 254424 kb
Host smart-9bbaeb60-90ad-48a2-be21-c521d6ea89a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17225
72929 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_classes.1722572929
Directory /workspace/23.alert_handler_random_classes/latest

Test location /workspace/coverage/default/23.alert_handler_sig_int_fail.2001962176
Short name T555
Test name
Test status
Simulation time 934934415 ps
CPU time 29.3 seconds
Started Feb 21 03:55:36 PM PST 24
Finished Feb 21 03:56:05 PM PST 24
Peak memory 253880 kb
Host smart-83f398dd-aa3f-4abb-bf06-33749b9fe4ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20019
62176 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_sig_int_fail.2001962176
Directory /workspace/23.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/23.alert_handler_smoke.2530065533
Short name T533
Test name
Test status
Simulation time 3617398583 ps
CPU time 41.94 seconds
Started Feb 21 03:55:48 PM PST 24
Finished Feb 21 03:56:30 PM PST 24
Peak memory 248316 kb
Host smart-55b7eaf6-9298-4b0f-9b94-2978f3ddac0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25300
65533 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_smoke.2530065533
Directory /workspace/23.alert_handler_smoke/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all.1013601373
Short name T58
Test name
Test status
Simulation time 149487125424 ps
CPU time 1968.64 seconds
Started Feb 21 03:55:52 PM PST 24
Finished Feb 21 04:28:41 PM PST 24
Peak memory 283232 kb
Host smart-66495a3a-44a0-4165-a884-c5fb42f54f6d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013601373 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_ha
ndler_stress_all.1013601373
Directory /workspace/23.alert_handler_stress_all/latest

Test location /workspace/coverage/default/24.alert_handler_entropy.592931166
Short name T588
Test name
Test status
Simulation time 24522555077 ps
CPU time 1320.6 seconds
Started Feb 21 03:55:46 PM PST 24
Finished Feb 21 04:17:47 PM PST 24
Peak memory 264708 kb
Host smart-9ac38449-eee8-4a39-872d-36f23d187a11
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592931166 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_entropy.592931166
Directory /workspace/24.alert_handler_entropy/latest

Test location /workspace/coverage/default/24.alert_handler_esc_alert_accum.4205860193
Short name T616
Test name
Test status
Simulation time 560041336 ps
CPU time 42.52 seconds
Started Feb 21 03:55:36 PM PST 24
Finished Feb 21 03:56:18 PM PST 24
Peak memory 255020 kb
Host smart-a88db50e-26d2-443f-9111-bd3530986965
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42058
60193 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_alert_accum.4205860193
Directory /workspace/24.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/24.alert_handler_esc_intr_timeout.2383687022
Short name T82
Test name
Test status
Simulation time 314193575 ps
CPU time 24.77 seconds
Started Feb 21 03:55:38 PM PST 24
Finished Feb 21 03:56:03 PM PST 24
Peak memory 254628 kb
Host smart-ee4b6d52-fa11-42a4-a3c6-617ceff99faa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23836
87022 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_intr_timeout.2383687022
Directory /workspace/24.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_lpg.1413087787
Short name T675
Test name
Test status
Simulation time 147704037351 ps
CPU time 1944.23 seconds
Started Feb 21 03:55:53 PM PST 24
Finished Feb 21 04:28:17 PM PST 24
Peak memory 272308 kb
Host smart-bb027b0a-327b-411a-9701-67b5dab8dfe1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413087787 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg.1413087787
Directory /workspace/24.alert_handler_lpg/latest

Test location /workspace/coverage/default/24.alert_handler_lpg_stub_clk.1578888782
Short name T506
Test name
Test status
Simulation time 17970613471 ps
CPU time 1120.01 seconds
Started Feb 21 03:55:51 PM PST 24
Finished Feb 21 04:14:31 PM PST 24
Peak memory 264296 kb
Host smart-efa271c0-e2a0-48e3-ba45-24810914603e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578888782 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg_stub_clk.1578888782
Directory /workspace/24.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/24.alert_handler_ping_timeout.2887902664
Short name T293
Test name
Test status
Simulation time 4101431488 ps
CPU time 165.2 seconds
Started Feb 21 03:55:57 PM PST 24
Finished Feb 21 03:58:42 PM PST 24
Peak memory 246808 kb
Host smart-7e5096c8-82e7-489d-bb40-3cc65b387e06
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887902664 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_ping_timeout.2887902664
Directory /workspace/24.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_random_alerts.973083098
Short name T711
Test name
Test status
Simulation time 2547840503 ps
CPU time 74.52 seconds
Started Feb 21 03:55:51 PM PST 24
Finished Feb 21 03:57:06 PM PST 24
Peak memory 248316 kb
Host smart-040f3b00-c39a-49ea-b47b-4fb6240b347a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97308
3098 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_alerts.973083098
Directory /workspace/24.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/24.alert_handler_sig_int_fail.3996136800
Short name T620
Test name
Test status
Simulation time 980104240 ps
CPU time 16.98 seconds
Started Feb 21 03:55:36 PM PST 24
Finished Feb 21 03:55:53 PM PST 24
Peak memory 253824 kb
Host smart-adc4b84f-34ac-4b20-be66-c0f7df7fb70d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39961
36800 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_sig_int_fail.3996136800
Directory /workspace/24.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/24.alert_handler_smoke.4286450601
Short name T566
Test name
Test status
Simulation time 389158814 ps
CPU time 33.79 seconds
Started Feb 21 03:55:54 PM PST 24
Finished Feb 21 03:56:28 PM PST 24
Peak memory 248228 kb
Host smart-aca4b25f-6f16-4ac5-a1a2-c6fe9acff106
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42864
50601 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_smoke.4286450601
Directory /workspace/24.alert_handler_smoke/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all.1481514017
Short name T685
Test name
Test status
Simulation time 117669289542 ps
CPU time 1851.18 seconds
Started Feb 21 03:55:49 PM PST 24
Finished Feb 21 04:26:40 PM PST 24
Peak memory 281044 kb
Host smart-0c9f1cf2-7b80-47e3-ac8a-7440b252635f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481514017 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_ha
ndler_stress_all.1481514017
Directory /workspace/24.alert_handler_stress_all/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all_with_rand_reset.3975424704
Short name T183
Test name
Test status
Simulation time 19365162817 ps
CPU time 1257.76 seconds
Started Feb 21 03:55:49 PM PST 24
Finished Feb 21 04:16:47 PM PST 24
Peak memory 273036 kb
Host smart-2040b605-33b6-49c5-815e-40a15978ff26
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975424704 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 24.alert_handler_stress_all_with_rand_reset.3975424704
Directory /workspace/24.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.alert_handler_entropy.3614736149
Short name T375
Test name
Test status
Simulation time 10714150027 ps
CPU time 800.29 seconds
Started Feb 21 03:55:53 PM PST 24
Finished Feb 21 04:09:13 PM PST 24
Peak memory 273072 kb
Host smart-e9475cd7-06c6-4404-9fe7-2d8ab3760129
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614736149 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_entropy.3614736149
Directory /workspace/25.alert_handler_entropy/latest

Test location /workspace/coverage/default/25.alert_handler_esc_alert_accum.131657001
Short name T415
Test name
Test status
Simulation time 1555071541 ps
CPU time 144.74 seconds
Started Feb 21 03:56:07 PM PST 24
Finished Feb 21 03:58:33 PM PST 24
Peak memory 255748 kb
Host smart-514c5a72-3097-4f73-a049-1f2549bee86b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13165
7001 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_alert_accum.131657001
Directory /workspace/25.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/25.alert_handler_esc_intr_timeout.3723848805
Short name T75
Test name
Test status
Simulation time 494875156 ps
CPU time 32.39 seconds
Started Feb 21 03:56:04 PM PST 24
Finished Feb 21 03:56:37 PM PST 24
Peak memory 254444 kb
Host smart-dc108c0b-6823-4cef-ae87-22dc5f38e1ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37238
48805 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_intr_timeout.3723848805
Directory /workspace/25.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_lpg.1190218885
Short name T340
Test name
Test status
Simulation time 109203368426 ps
CPU time 1863.31 seconds
Started Feb 21 03:56:04 PM PST 24
Finished Feb 21 04:27:08 PM PST 24
Peak memory 272668 kb
Host smart-219bc85d-f8f2-412c-89a2-5e05a6ade4b7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190218885 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg.1190218885
Directory /workspace/25.alert_handler_lpg/latest

Test location /workspace/coverage/default/25.alert_handler_lpg_stub_clk.1112282953
Short name T624
Test name
Test status
Simulation time 51112509390 ps
CPU time 1568.08 seconds
Started Feb 21 03:56:04 PM PST 24
Finished Feb 21 04:22:13 PM PST 24
Peak memory 264672 kb
Host smart-63eb8d7a-c94c-4957-9657-412b5fb7fecd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112282953 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg_stub_clk.1112282953
Directory /workspace/25.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/25.alert_handler_ping_timeout.2638814176
Short name T657
Test name
Test status
Simulation time 7830449187 ps
CPU time 133.86 seconds
Started Feb 21 03:56:04 PM PST 24
Finished Feb 21 03:58:18 PM PST 24
Peak memory 246212 kb
Host smart-a43d5a0f-7df4-4fbc-b552-a5640a248b00
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638814176 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_ping_timeout.2638814176
Directory /workspace/25.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_random_alerts.1929580523
Short name T655
Test name
Test status
Simulation time 29054343 ps
CPU time 3.85 seconds
Started Feb 21 03:55:37 PM PST 24
Finished Feb 21 03:55:41 PM PST 24
Peak memory 240032 kb
Host smart-bdbbd0ad-80a7-487e-9e7e-f76472e885b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19295
80523 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_alerts.1929580523
Directory /workspace/25.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/25.alert_handler_random_classes.451697191
Short name T466
Test name
Test status
Simulation time 1669276173 ps
CPU time 27.37 seconds
Started Feb 21 03:55:53 PM PST 24
Finished Feb 21 03:56:20 PM PST 24
Peak memory 255452 kb
Host smart-3fdb0728-6051-432a-988b-6110d828968d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45169
7191 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_classes.451697191
Directory /workspace/25.alert_handler_random_classes/latest

Test location /workspace/coverage/default/25.alert_handler_sig_int_fail.76324462
Short name T698
Test name
Test status
Simulation time 193380627 ps
CPU time 15.4 seconds
Started Feb 21 03:55:57 PM PST 24
Finished Feb 21 03:56:13 PM PST 24
Peak memory 252960 kb
Host smart-29c54dd5-d431-4f4c-98a6-bee98fc060f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76324
462 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_sig_int_fail.76324462
Directory /workspace/25.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/25.alert_handler_smoke.3792651374
Short name T382
Test name
Test status
Simulation time 44932797 ps
CPU time 4.13 seconds
Started Feb 21 03:55:48 PM PST 24
Finished Feb 21 03:55:53 PM PST 24
Peak memory 240048 kb
Host smart-4add1632-f9a1-4e82-9408-5a40b8144d7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37926
51374 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_smoke.3792651374
Directory /workspace/25.alert_handler_smoke/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all.887185110
Short name T708
Test name
Test status
Simulation time 36404890089 ps
CPU time 1710.56 seconds
Started Feb 21 03:56:02 PM PST 24
Finished Feb 21 04:24:33 PM PST 24
Peak memory 302072 kb
Host smart-5c777523-6998-4e0d-94aa-c20d8dd48494
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887185110 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_han
dler_stress_all.887185110
Directory /workspace/25.alert_handler_stress_all/latest

Test location /workspace/coverage/default/26.alert_handler_entropy.653211305
Short name T441
Test name
Test status
Simulation time 35828010700 ps
CPU time 1909.21 seconds
Started Feb 21 03:56:05 PM PST 24
Finished Feb 21 04:27:55 PM PST 24
Peak memory 283600 kb
Host smart-ab0e483c-ade9-4280-9c9a-dea1b5ed13a1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653211305 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_entropy.653211305
Directory /workspace/26.alert_handler_entropy/latest

Test location /workspace/coverage/default/26.alert_handler_esc_alert_accum.424999571
Short name T239
Test name
Test status
Simulation time 7097022803 ps
CPU time 28.55 seconds
Started Feb 21 03:55:58 PM PST 24
Finished Feb 21 03:56:26 PM PST 24
Peak memory 255304 kb
Host smart-ffb94a96-2f63-4077-bf20-a746e16a5332
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42499
9571 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_alert_accum.424999571
Directory /workspace/26.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/26.alert_handler_esc_intr_timeout.1853629901
Short name T539
Test name
Test status
Simulation time 163986238 ps
CPU time 15.47 seconds
Started Feb 21 03:55:49 PM PST 24
Finished Feb 21 03:56:04 PM PST 24
Peak memory 253596 kb
Host smart-64edcf40-160c-43c8-a05d-1789510a5b88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18536
29901 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_intr_timeout.1853629901
Directory /workspace/26.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_lpg.1633574958
Short name T611
Test name
Test status
Simulation time 128167069838 ps
CPU time 1757.75 seconds
Started Feb 21 03:55:59 PM PST 24
Finished Feb 21 04:25:17 PM PST 24
Peak memory 282688 kb
Host smart-3ba3bce0-1ce4-449a-8a13-14e977f36ded
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633574958 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg.1633574958
Directory /workspace/26.alert_handler_lpg/latest

Test location /workspace/coverage/default/26.alert_handler_ping_timeout.3409108942
Short name T315
Test name
Test status
Simulation time 10177025106 ps
CPU time 419.76 seconds
Started Feb 21 03:55:54 PM PST 24
Finished Feb 21 04:02:54 PM PST 24
Peak memory 247188 kb
Host smart-ea9574ec-84c6-4626-8aef-04c87f69c7f6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409108942 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_ping_timeout.3409108942
Directory /workspace/26.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_random_alerts.375103121
Short name T679
Test name
Test status
Simulation time 1017471563 ps
CPU time 14.06 seconds
Started Feb 21 03:55:52 PM PST 24
Finished Feb 21 03:56:06 PM PST 24
Peak memory 256424 kb
Host smart-966d3c5e-94ae-4f79-b380-06e789a0c20f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37510
3121 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_alerts.375103121
Directory /workspace/26.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/26.alert_handler_random_classes.2450356004
Short name T53
Test name
Test status
Simulation time 459560261 ps
CPU time 36.71 seconds
Started Feb 21 03:55:49 PM PST 24
Finished Feb 21 03:56:26 PM PST 24
Peak memory 247596 kb
Host smart-3f4ed36d-851f-4c84-bfd7-0cdead72d0b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24503
56004 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_classes.2450356004
Directory /workspace/26.alert_handler_random_classes/latest

Test location /workspace/coverage/default/26.alert_handler_sig_int_fail.1672970029
Short name T284
Test name
Test status
Simulation time 35739414 ps
CPU time 3.14 seconds
Started Feb 21 03:56:02 PM PST 24
Finished Feb 21 03:56:06 PM PST 24
Peak memory 240052 kb
Host smart-1de5bed4-7caf-41fc-bb7b-43154f28f69c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16729
70029 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_sig_int_fail.1672970029
Directory /workspace/26.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/26.alert_handler_smoke.176881779
Short name T485
Test name
Test status
Simulation time 2574924203 ps
CPU time 74.25 seconds
Started Feb 21 03:56:04 PM PST 24
Finished Feb 21 03:57:19 PM PST 24
Peak memory 248240 kb
Host smart-15c9e99f-b012-4bfe-879e-eef1ce9cf41b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17688
1779 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_smoke.176881779
Directory /workspace/26.alert_handler_smoke/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all.1497166411
Short name T55
Test name
Test status
Simulation time 520929782620 ps
CPU time 2352.99 seconds
Started Feb 21 03:56:02 PM PST 24
Finished Feb 21 04:35:16 PM PST 24
Peak memory 288428 kb
Host smart-4e2d130f-b65f-4e79-8634-283eb9b2b7ec
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497166411 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_ha
ndler_stress_all.1497166411
Directory /workspace/26.alert_handler_stress_all/latest

Test location /workspace/coverage/default/27.alert_handler_entropy.975089995
Short name T435
Test name
Test status
Simulation time 48145987864 ps
CPU time 2604.92 seconds
Started Feb 21 03:56:03 PM PST 24
Finished Feb 21 04:39:28 PM PST 24
Peak memory 288784 kb
Host smart-82bd7f61-2fd0-4223-b9aa-044ebed30860
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975089995 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_entropy.975089995
Directory /workspace/27.alert_handler_entropy/latest

Test location /workspace/coverage/default/27.alert_handler_esc_alert_accum.3219312225
Short name T3
Test name
Test status
Simulation time 1484998398 ps
CPU time 141.22 seconds
Started Feb 21 03:56:12 PM PST 24
Finished Feb 21 03:58:34 PM PST 24
Peak memory 255516 kb
Host smart-2fc701f7-1387-42e0-a604-72765718043e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32193
12225 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_alert_accum.3219312225
Directory /workspace/27.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/27.alert_handler_esc_intr_timeout.3523855187
Short name T425
Test name
Test status
Simulation time 350817469 ps
CPU time 11.7 seconds
Started Feb 21 03:56:04 PM PST 24
Finished Feb 21 03:56:17 PM PST 24
Peak memory 253264 kb
Host smart-7895946f-eeb7-499b-a7da-47d00a1d00a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35238
55187 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_intr_timeout.3523855187
Directory /workspace/27.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_lpg.3143193545
Short name T334
Test name
Test status
Simulation time 186687556681 ps
CPU time 2520.09 seconds
Started Feb 21 03:56:10 PM PST 24
Finished Feb 21 04:38:11 PM PST 24
Peak memory 284012 kb
Host smart-d5bdf0dd-a393-4a26-a599-819e7314588f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143193545 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg.3143193545
Directory /workspace/27.alert_handler_lpg/latest

Test location /workspace/coverage/default/27.alert_handler_lpg_stub_clk.2269978291
Short name T400
Test name
Test status
Simulation time 202450926722 ps
CPU time 2326.57 seconds
Started Feb 21 03:56:07 PM PST 24
Finished Feb 21 04:34:54 PM PST 24
Peak memory 284976 kb
Host smart-47dc858a-aae2-4b64-915f-46812f3b3fa1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269978291 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg_stub_clk.2269978291
Directory /workspace/27.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/27.alert_handler_ping_timeout.47896082
Short name T666
Test name
Test status
Simulation time 9238522888 ps
CPU time 201.79 seconds
Started Feb 21 03:56:15 PM PST 24
Finished Feb 21 03:59:37 PM PST 24
Peak memory 247164 kb
Host smart-dd4cdae4-a82a-4043-a0c8-e8e78fe2d6c7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47896082 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_ping_timeout.47896082
Directory /workspace/27.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_random_alerts.2877328459
Short name T388
Test name
Test status
Simulation time 188751039 ps
CPU time 5.97 seconds
Started Feb 21 03:56:05 PM PST 24
Finished Feb 21 03:56:12 PM PST 24
Peak memory 248188 kb
Host smart-0a9d5034-8eb1-4a7d-a803-1971a832f846
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28773
28459 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_alerts.2877328459
Directory /workspace/27.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/27.alert_handler_random_classes.297412597
Short name T95
Test name
Test status
Simulation time 2289089944 ps
CPU time 33.13 seconds
Started Feb 21 03:56:04 PM PST 24
Finished Feb 21 03:56:38 PM PST 24
Peak memory 246660 kb
Host smart-26c70cb6-7428-47c0-b9ff-ea7072308f82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29741
2597 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_classes.297412597
Directory /workspace/27.alert_handler_random_classes/latest

Test location /workspace/coverage/default/27.alert_handler_sig_int_fail.1031859815
Short name T692
Test name
Test status
Simulation time 34754487 ps
CPU time 3.63 seconds
Started Feb 21 03:56:04 PM PST 24
Finished Feb 21 03:56:08 PM PST 24
Peak memory 238276 kb
Host smart-44937a4a-dcdd-4e69-8f66-19201dc9abc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10318
59815 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_sig_int_fail.1031859815
Directory /workspace/27.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/27.alert_handler_smoke.1002405784
Short name T390
Test name
Test status
Simulation time 1590554045 ps
CPU time 17.88 seconds
Started Feb 21 03:56:07 PM PST 24
Finished Feb 21 03:56:26 PM PST 24
Peak memory 248268 kb
Host smart-3b4bc688-a253-42c4-aa3b-7cba60dc4612
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10024
05784 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_smoke.1002405784
Directory /workspace/27.alert_handler_smoke/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all.3333600293
Short name T654
Test name
Test status
Simulation time 38437759129 ps
CPU time 520.77 seconds
Started Feb 21 03:56:04 PM PST 24
Finished Feb 21 04:04:45 PM PST 24
Peak memory 256468 kb
Host smart-de16d73f-21ce-4f4a-ad02-a6700bf80e75
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333600293 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_ha
ndler_stress_all.3333600293
Directory /workspace/27.alert_handler_stress_all/latest

Test location /workspace/coverage/default/28.alert_handler_entropy.1939212739
Short name T487
Test name
Test status
Simulation time 9918805375 ps
CPU time 979.48 seconds
Started Feb 21 03:56:12 PM PST 24
Finished Feb 21 04:12:33 PM PST 24
Peak memory 272376 kb
Host smart-a4005449-562a-48a4-98d5-74d7e208f7c6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939212739 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_entropy.1939212739
Directory /workspace/28.alert_handler_entropy/latest

Test location /workspace/coverage/default/28.alert_handler_esc_alert_accum.2346710832
Short name T494
Test name
Test status
Simulation time 7368140463 ps
CPU time 119.12 seconds
Started Feb 21 03:56:06 PM PST 24
Finished Feb 21 03:58:07 PM PST 24
Peak memory 256472 kb
Host smart-a5268a24-0d0e-443a-9b70-a8c5d3497045
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23467
10832 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_alert_accum.2346710832
Directory /workspace/28.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/28.alert_handler_esc_intr_timeout.3337462557
Short name T641
Test name
Test status
Simulation time 506603155 ps
CPU time 9.66 seconds
Started Feb 21 03:56:02 PM PST 24
Finished Feb 21 03:56:12 PM PST 24
Peak memory 239768 kb
Host smart-7310f6aa-4d96-4a30-8cc1-16c811da27fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33374
62557 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_intr_timeout.3337462557
Directory /workspace/28.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_lpg.2975507115
Short name T339
Test name
Test status
Simulation time 7864765654 ps
CPU time 657.94 seconds
Started Feb 21 03:56:12 PM PST 24
Finished Feb 21 04:07:10 PM PST 24
Peak memory 264740 kb
Host smart-4db4c4b9-796f-465c-8bc3-293c5037413c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975507115 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg.2975507115
Directory /workspace/28.alert_handler_lpg/latest

Test location /workspace/coverage/default/28.alert_handler_lpg_stub_clk.430501775
Short name T680
Test name
Test status
Simulation time 31082484237 ps
CPU time 704.48 seconds
Started Feb 21 03:56:12 PM PST 24
Finished Feb 21 04:07:57 PM PST 24
Peak memory 271808 kb
Host smart-f49f274b-cf37-4fa2-8761-17661676e1e9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430501775 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg_stub_clk.430501775
Directory /workspace/28.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/28.alert_handler_random_alerts.1011262261
Short name T554
Test name
Test status
Simulation time 259263129 ps
CPU time 28.05 seconds
Started Feb 21 03:56:15 PM PST 24
Finished Feb 21 03:56:44 PM PST 24
Peak memory 248308 kb
Host smart-85eda044-e1d2-4899-a106-35b0610d5dd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10112
62261 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_alerts.1011262261
Directory /workspace/28.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/28.alert_handler_random_classes.4214696981
Short name T693
Test name
Test status
Simulation time 291457780 ps
CPU time 7.47 seconds
Started Feb 21 03:56:10 PM PST 24
Finished Feb 21 03:56:18 PM PST 24
Peak memory 247568 kb
Host smart-9a30cb2e-2131-4238-95c7-6a46213976ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42146
96981 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_classes.4214696981
Directory /workspace/28.alert_handler_random_classes/latest

Test location /workspace/coverage/default/28.alert_handler_smoke.3292357832
Short name T667
Test name
Test status
Simulation time 150189361 ps
CPU time 5.3 seconds
Started Feb 21 03:56:09 PM PST 24
Finished Feb 21 03:56:15 PM PST 24
Peak memory 240024 kb
Host smart-3fe15a90-945d-4d8d-80aa-4407d26ec72b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32923
57832 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_smoke.3292357832
Directory /workspace/28.alert_handler_smoke/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all.715827387
Short name T121
Test name
Test status
Simulation time 44843355344 ps
CPU time 2864.92 seconds
Started Feb 21 03:56:04 PM PST 24
Finished Feb 21 04:43:49 PM PST 24
Peak memory 299688 kb
Host smart-1132f013-9f82-4ab3-9f6e-680de64bb108
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715827387 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_han
dler_stress_all.715827387
Directory /workspace/28.alert_handler_stress_all/latest

Test location /workspace/coverage/default/29.alert_handler_entropy.521143548
Short name T532
Test name
Test status
Simulation time 17471413987 ps
CPU time 1403.81 seconds
Started Feb 21 03:56:08 PM PST 24
Finished Feb 21 04:19:33 PM PST 24
Peak memory 281116 kb
Host smart-cf0ce465-17e5-4515-b496-9ae34f3ee136
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521143548 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_entropy.521143548
Directory /workspace/29.alert_handler_entropy/latest

Test location /workspace/coverage/default/29.alert_handler_esc_alert_accum.1992717777
Short name T548
Test name
Test status
Simulation time 2154782033 ps
CPU time 152.08 seconds
Started Feb 21 03:56:05 PM PST 24
Finished Feb 21 03:58:37 PM PST 24
Peak memory 256472 kb
Host smart-f2491e39-7e77-420a-bf59-cd715d41a68a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19927
17777 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_alert_accum.1992717777
Directory /workspace/29.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/29.alert_handler_esc_intr_timeout.3642832672
Short name T524
Test name
Test status
Simulation time 3971004092 ps
CPU time 56.09 seconds
Started Feb 21 03:56:06 PM PST 24
Finished Feb 21 03:57:04 PM PST 24
Peak memory 254656 kb
Host smart-3e190490-d66c-4160-b6d1-5cd1959ef686
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36428
32672 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_intr_timeout.3642832672
Directory /workspace/29.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_lpg.411753371
Short name T123
Test name
Test status
Simulation time 79464418234 ps
CPU time 2022.73 seconds
Started Feb 21 03:56:08 PM PST 24
Finished Feb 21 04:29:51 PM PST 24
Peak memory 272288 kb
Host smart-f1fc44c8-3667-4620-b353-e8765a8e4934
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411753371 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg.411753371
Directory /workspace/29.alert_handler_lpg/latest

Test location /workspace/coverage/default/29.alert_handler_lpg_stub_clk.197646043
Short name T550
Test name
Test status
Simulation time 39017566101 ps
CPU time 2193.09 seconds
Started Feb 21 03:56:08 PM PST 24
Finished Feb 21 04:32:42 PM PST 24
Peak memory 289284 kb
Host smart-322c10c3-5c3a-4e8a-b0ae-243270074f81
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197646043 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg_stub_clk.197646043
Directory /workspace/29.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/29.alert_handler_ping_timeout.1119381216
Short name T296
Test name
Test status
Simulation time 29171904341 ps
CPU time 304.15 seconds
Started Feb 21 03:55:59 PM PST 24
Finished Feb 21 04:01:04 PM PST 24
Peak memory 246180 kb
Host smart-bc4b9508-0a0f-4b0b-b888-48c884ca7281
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119381216 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_ping_timeout.1119381216
Directory /workspace/29.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_random_alerts.1383248507
Short name T50
Test name
Test status
Simulation time 3891537446 ps
CPU time 61.64 seconds
Started Feb 21 03:56:08 PM PST 24
Finished Feb 21 03:57:11 PM PST 24
Peak memory 248312 kb
Host smart-66042dc2-4160-4dc7-8773-13af25d81d44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13832
48507 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_alerts.1383248507
Directory /workspace/29.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/29.alert_handler_random_classes.229060454
Short name T109
Test name
Test status
Simulation time 295243606 ps
CPU time 28.06 seconds
Started Feb 21 03:56:10 PM PST 24
Finished Feb 21 03:56:39 PM PST 24
Peak memory 247896 kb
Host smart-66127753-1acd-493c-8ab9-6f60f2283cf6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22906
0454 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_classes.229060454
Directory /workspace/29.alert_handler_random_classes/latest

Test location /workspace/coverage/default/29.alert_handler_sig_int_fail.2243138112
Short name T465
Test name
Test status
Simulation time 214096873 ps
CPU time 21.66 seconds
Started Feb 21 03:56:07 PM PST 24
Finished Feb 21 03:56:30 PM PST 24
Peak memory 254940 kb
Host smart-bcd9eed9-a387-4ca6-be62-72f45a2adefc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22431
38112 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_sig_int_fail.2243138112
Directory /workspace/29.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/29.alert_handler_smoke.2900620904
Short name T376
Test name
Test status
Simulation time 3126820729 ps
CPU time 51.97 seconds
Started Feb 21 03:56:01 PM PST 24
Finished Feb 21 03:56:54 PM PST 24
Peak memory 248324 kb
Host smart-18599ff1-adca-4784-ab40-0b99b69e4f29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29006
20904 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_smoke.2900620904
Directory /workspace/29.alert_handler_smoke/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all_with_rand_reset.1069077641
Short name T439
Test name
Test status
Simulation time 741254289584 ps
CPU time 4613.88 seconds
Started Feb 21 03:56:12 PM PST 24
Finished Feb 21 05:13:08 PM PST 24
Peak memory 332132 kb
Host smart-164f4ab4-32bc-4c23-97eb-20d8fdc0d5bb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069077641 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.alert_handler_stress_all_with_rand_reset.1069077641
Directory /workspace/29.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.alert_handler_alert_accum_saturation.3252482887
Short name T99
Test name
Test status
Simulation time 17429608 ps
CPU time 2.72 seconds
Started Feb 21 03:53:51 PM PST 24
Finished Feb 21 03:53:55 PM PST 24
Peak memory 248548 kb
Host smart-51dce747-ea2c-4595-a00b-b8cac90ef241
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3252482887 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_alert_accum_saturation.3252482887
Directory /workspace/3.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/3.alert_handler_entropy.425928514
Short name T652
Test name
Test status
Simulation time 136702216737 ps
CPU time 1229.02 seconds
Started Feb 21 03:53:43 PM PST 24
Finished Feb 21 04:14:14 PM PST 24
Peak memory 264640 kb
Host smart-1384a900-54d5-485b-86f5-d8ff22ba0ca2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425928514 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy.425928514
Directory /workspace/3.alert_handler_entropy/latest

Test location /workspace/coverage/default/3.alert_handler_entropy_stress.1764802272
Short name T474
Test name
Test status
Simulation time 542148991 ps
CPU time 9.45 seconds
Started Feb 21 03:53:47 PM PST 24
Finished Feb 21 03:53:59 PM PST 24
Peak memory 240056 kb
Host smart-90a729c5-4c29-4bb8-ab7d-542924d93e64
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1764802272 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy_stress.1764802272
Directory /workspace/3.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/3.alert_handler_esc_alert_accum.3258681659
Short name T369
Test name
Test status
Simulation time 859082305 ps
CPU time 69.38 seconds
Started Feb 21 03:53:47 PM PST 24
Finished Feb 21 03:54:58 PM PST 24
Peak memory 247592 kb
Host smart-e163fee1-f17c-45c3-a0af-bfcb88634697
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32586
81659 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_alert_accum.3258681659
Directory /workspace/3.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/3.alert_handler_esc_intr_timeout.3904683328
Short name T23
Test name
Test status
Simulation time 504570051 ps
CPU time 27.85 seconds
Started Feb 21 03:53:38 PM PST 24
Finished Feb 21 03:54:06 PM PST 24
Peak memory 246468 kb
Host smart-00a9ec48-33df-4657-bddc-6c1aac3a9c81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39046
83328 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_intr_timeout.3904683328
Directory /workspace/3.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_lpg_stub_clk.2108875464
Short name T560
Test name
Test status
Simulation time 114937130630 ps
CPU time 1906.5 seconds
Started Feb 21 03:53:48 PM PST 24
Finished Feb 21 04:25:37 PM PST 24
Peak memory 271260 kb
Host smart-1a8507bb-66c6-4633-ad12-ae1e9e161b48
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108875464 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg_stub_clk.2108875464
Directory /workspace/3.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/3.alert_handler_ping_timeout.4052470970
Short name T311
Test name
Test status
Simulation time 9567662200 ps
CPU time 103.51 seconds
Started Feb 21 03:53:47 PM PST 24
Finished Feb 21 03:55:33 PM PST 24
Peak memory 247156 kb
Host smart-5fe010a1-e003-4bc2-95b0-92fe2c1f729a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052470970 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_ping_timeout.4052470970
Directory /workspace/3.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_random_alerts.553622855
Short name T615
Test name
Test status
Simulation time 282764307 ps
CPU time 16.19 seconds
Started Feb 21 03:53:44 PM PST 24
Finished Feb 21 03:54:03 PM PST 24
Peak memory 248240 kb
Host smart-18eb6562-b4de-4fdf-b911-93a232013279
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55362
2855 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_alerts.553622855
Directory /workspace/3.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/3.alert_handler_random_classes.3831061078
Short name T537
Test name
Test status
Simulation time 954298176 ps
CPU time 23.38 seconds
Started Feb 21 03:53:41 PM PST 24
Finished Feb 21 03:54:05 PM PST 24
Peak memory 255172 kb
Host smart-a3fd1b45-ce8d-4156-883a-8341c53c8fc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38310
61078 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_classes.3831061078
Directory /workspace/3.alert_handler_random_classes/latest

Test location /workspace/coverage/default/3.alert_handler_sec_cm.640825
Short name T39
Test name
Test status
Simulation time 862813974 ps
CPU time 24.8 seconds
Started Feb 21 03:53:51 PM PST 24
Finished Feb 21 03:54:17 PM PST 24
Peak memory 269776 kb
Host smart-89ecb294-a00a-463a-88ca-98f3f73cc8eb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=640825 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sec_cm.640825
Directory /workspace/3.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/3.alert_handler_sig_int_fail.2355978339
Short name T374
Test name
Test status
Simulation time 5149281551 ps
CPU time 43.92 seconds
Started Feb 21 03:53:47 PM PST 24
Finished Feb 21 03:54:33 PM PST 24
Peak memory 255336 kb
Host smart-26c093ac-0f1d-418a-bb7f-dd2fa028ec5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23559
78339 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sig_int_fail.2355978339
Directory /workspace/3.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/3.alert_handler_smoke.2556895231
Short name T673
Test name
Test status
Simulation time 1770519450 ps
CPU time 28.31 seconds
Started Feb 21 03:53:47 PM PST 24
Finished Feb 21 03:54:18 PM PST 24
Peak memory 248256 kb
Host smart-49dabb0b-498e-41a3-b54b-5a35450c2591
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25568
95231 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_smoke.2556895231
Directory /workspace/3.alert_handler_smoke/latest

Test location /workspace/coverage/default/30.alert_handler_entropy.1227778527
Short name T101
Test name
Test status
Simulation time 653929807287 ps
CPU time 2115.05 seconds
Started Feb 21 03:56:10 PM PST 24
Finished Feb 21 04:31:26 PM PST 24
Peak memory 288404 kb
Host smart-29ba39f5-7f22-434d-9e44-2c0eb9bd4de6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1227778527 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_entropy.1227778527
Directory /workspace/30.alert_handler_entropy/latest

Test location /workspace/coverage/default/30.alert_handler_esc_alert_accum.2848021342
Short name T627
Test name
Test status
Simulation time 391996389 ps
CPU time 20.22 seconds
Started Feb 21 03:56:13 PM PST 24
Finished Feb 21 03:56:35 PM PST 24
Peak memory 248248 kb
Host smart-53928d7c-b7c2-437a-9f76-f4642be76245
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28480
21342 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_alert_accum.2848021342
Directory /workspace/30.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/30.alert_handler_esc_intr_timeout.570256675
Short name T423
Test name
Test status
Simulation time 1200787649 ps
CPU time 69.14 seconds
Started Feb 21 03:56:12 PM PST 24
Finished Feb 21 03:57:22 PM PST 24
Peak memory 254536 kb
Host smart-ebfea710-7e8f-4147-bf44-6b291e32faf8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57025
6675 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_intr_timeout.570256675
Directory /workspace/30.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_lpg.3467514358
Short name T647
Test name
Test status
Simulation time 82553867063 ps
CPU time 1392.08 seconds
Started Feb 21 03:56:10 PM PST 24
Finished Feb 21 04:19:23 PM PST 24
Peak memory 287896 kb
Host smart-b40a7803-4fa2-4a12-a6e0-ec1bfe371b2c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467514358 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg.3467514358
Directory /workspace/30.alert_handler_lpg/latest

Test location /workspace/coverage/default/30.alert_handler_lpg_stub_clk.2416088006
Short name T392
Test name
Test status
Simulation time 44426824729 ps
CPU time 978.34 seconds
Started Feb 21 03:56:05 PM PST 24
Finished Feb 21 04:12:24 PM PST 24
Peak memory 272308 kb
Host smart-b08f1984-3183-47f5-ae92-949e12bd0d1e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2416088006 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg_stub_clk.2416088006
Directory /workspace/30.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/30.alert_handler_ping_timeout.416276995
Short name T317
Test name
Test status
Simulation time 6406974100 ps
CPU time 279.56 seconds
Started Feb 21 03:56:12 PM PST 24
Finished Feb 21 04:00:52 PM PST 24
Peak memory 246828 kb
Host smart-823d42b9-4281-47a3-9f0e-f86d79dd4205
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416276995 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_ping_timeout.416276995
Directory /workspace/30.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_random_alerts.3247231509
Short name T571
Test name
Test status
Simulation time 1330701325 ps
CPU time 27.69 seconds
Started Feb 21 03:56:13 PM PST 24
Finished Feb 21 03:56:42 PM PST 24
Peak memory 255080 kb
Host smart-cb5961f9-33e0-4102-9bbf-8fe89dbdc983
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32472
31509 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_alerts.3247231509
Directory /workspace/30.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/30.alert_handler_random_classes.1650461526
Short name T545
Test name
Test status
Simulation time 1144548719 ps
CPU time 30.96 seconds
Started Feb 21 03:56:10 PM PST 24
Finished Feb 21 03:56:42 PM PST 24
Peak memory 246556 kb
Host smart-cc6f90ee-f640-4223-9b9d-ca9207978579
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16504
61526 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_classes.1650461526
Directory /workspace/30.alert_handler_random_classes/latest

Test location /workspace/coverage/default/30.alert_handler_smoke.3644023422
Short name T90
Test name
Test status
Simulation time 128897005 ps
CPU time 5.28 seconds
Started Feb 21 03:56:10 PM PST 24
Finished Feb 21 03:56:16 PM PST 24
Peak memory 240048 kb
Host smart-3bc5a764-33fd-4bce-a2de-443716cd900e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36440
23422 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_smoke.3644023422
Directory /workspace/30.alert_handler_smoke/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all.1057091249
Short name T268
Test name
Test status
Simulation time 2362808448 ps
CPU time 153.39 seconds
Started Feb 21 03:56:13 PM PST 24
Finished Feb 21 03:58:47 PM PST 24
Peak memory 250404 kb
Host smart-90366bf6-ca30-4545-81be-5e614987afd9
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057091249 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_ha
ndler_stress_all.1057091249
Directory /workspace/30.alert_handler_stress_all/latest

Test location /workspace/coverage/default/31.alert_handler_entropy.127621423
Short name T526
Test name
Test status
Simulation time 9626723253 ps
CPU time 767.03 seconds
Started Feb 21 03:56:07 PM PST 24
Finished Feb 21 04:08:55 PM PST 24
Peak memory 272836 kb
Host smart-c2686c9d-dcd3-4720-8968-9b30ac55f188
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127621423 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_entropy.127621423
Directory /workspace/31.alert_handler_entropy/latest

Test location /workspace/coverage/default/31.alert_handler_esc_intr_timeout.1904920797
Short name T434
Test name
Test status
Simulation time 410164462 ps
CPU time 23.54 seconds
Started Feb 21 03:56:12 PM PST 24
Finished Feb 21 03:56:37 PM PST 24
Peak memory 253604 kb
Host smart-c491f979-66ff-42cd-b5b9-938cd030736a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19049
20797 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_intr_timeout.1904920797
Directory /workspace/31.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_lpg.1201212355
Short name T671
Test name
Test status
Simulation time 9995075318 ps
CPU time 832.18 seconds
Started Feb 21 03:56:13 PM PST 24
Finished Feb 21 04:10:06 PM PST 24
Peak memory 272544 kb
Host smart-e4f9026c-0f8a-441e-90bf-bd3135ac3c2b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201212355 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg.1201212355
Directory /workspace/31.alert_handler_lpg/latest

Test location /workspace/coverage/default/31.alert_handler_lpg_stub_clk.830817456
Short name T433
Test name
Test status
Simulation time 16050843335 ps
CPU time 684.62 seconds
Started Feb 21 03:56:10 PM PST 24
Finished Feb 21 04:07:35 PM PST 24
Peak memory 264416 kb
Host smart-285174d9-189f-44f0-98d4-eafc0e63d1f4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830817456 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg_stub_clk.830817456
Directory /workspace/31.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/31.alert_handler_ping_timeout.2674410108
Short name T295
Test name
Test status
Simulation time 31358223044 ps
CPU time 325.81 seconds
Started Feb 21 03:56:12 PM PST 24
Finished Feb 21 04:01:39 PM PST 24
Peak memory 246208 kb
Host smart-e56d79a3-bd25-4941-be6d-9b74155cf924
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674410108 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_ping_timeout.2674410108
Directory /workspace/31.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_random_alerts.946373912
Short name T389
Test name
Test status
Simulation time 757721606 ps
CPU time 26.84 seconds
Started Feb 21 03:56:13 PM PST 24
Finished Feb 21 03:56:41 PM PST 24
Peak memory 248236 kb
Host smart-4666b9ae-5710-45bd-b369-77e24d6c1654
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94637
3912 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_alerts.946373912
Directory /workspace/31.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/31.alert_handler_random_classes.1725044198
Short name T119
Test name
Test status
Simulation time 1182566830 ps
CPU time 34.13 seconds
Started Feb 21 03:56:12 PM PST 24
Finished Feb 21 03:56:47 PM PST 24
Peak memory 254920 kb
Host smart-4253fc1a-940f-4f1b-8700-db461933f1fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17250
44198 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_classes.1725044198
Directory /workspace/31.alert_handler_random_classes/latest

Test location /workspace/coverage/default/31.alert_handler_sig_int_fail.872627473
Short name T383
Test name
Test status
Simulation time 557153072 ps
CPU time 40.51 seconds
Started Feb 21 03:56:12 PM PST 24
Finished Feb 21 03:56:54 PM PST 24
Peak memory 248292 kb
Host smart-e185263b-3a6d-4e4e-bb40-8e8bbfe130ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87262
7473 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_sig_int_fail.872627473
Directory /workspace/31.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/31.alert_handler_smoke.4132877799
Short name T472
Test name
Test status
Simulation time 916053054 ps
CPU time 62.03 seconds
Started Feb 21 03:56:10 PM PST 24
Finished Feb 21 03:57:13 PM PST 24
Peak memory 248440 kb
Host smart-12585501-18df-49a3-ac8f-7426c05a8068
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41328
77799 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_smoke.4132877799
Directory /workspace/31.alert_handler_smoke/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all.2581961094
Short name T662
Test name
Test status
Simulation time 2939058820 ps
CPU time 239.02 seconds
Started Feb 21 03:56:11 PM PST 24
Finished Feb 21 04:00:11 PM PST 24
Peak memory 256492 kb
Host smart-5d550886-9621-465f-8991-05a68d0340f2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581961094 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_ha
ndler_stress_all.2581961094
Directory /workspace/31.alert_handler_stress_all/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all_with_rand_reset.3424466628
Short name T80
Test name
Test status
Simulation time 411190721027 ps
CPU time 4561.38 seconds
Started Feb 21 03:56:12 PM PST 24
Finished Feb 21 05:12:15 PM PST 24
Peak memory 354168 kb
Host smart-19ce3f9a-ace2-4716-a0f0-af54b04fb32f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424466628 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 31.alert_handler_stress_all_with_rand_reset.3424466628
Directory /workspace/31.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.alert_handler_entropy.3790222497
Short name T536
Test name
Test status
Simulation time 83276759375 ps
CPU time 1133.48 seconds
Started Feb 21 03:56:23 PM PST 24
Finished Feb 21 04:15:17 PM PST 24
Peak memory 272044 kb
Host smart-5a674c10-c214-432a-9eb4-764c4e751487
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790222497 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_entropy.3790222497
Directory /workspace/32.alert_handler_entropy/latest

Test location /workspace/coverage/default/32.alert_handler_esc_alert_accum.1885034093
Short name T68
Test name
Test status
Simulation time 18665671654 ps
CPU time 238.54 seconds
Started Feb 21 03:56:15 PM PST 24
Finished Feb 21 04:00:14 PM PST 24
Peak memory 256420 kb
Host smart-ecdc4eac-283c-4f93-8a51-85df95320ecb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18850
34093 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_alert_accum.1885034093
Directory /workspace/32.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/32.alert_handler_esc_intr_timeout.1326900277
Short name T73
Test name
Test status
Simulation time 5660773560 ps
CPU time 49.5 seconds
Started Feb 21 03:56:15 PM PST 24
Finished Feb 21 03:57:06 PM PST 24
Peak memory 254232 kb
Host smart-4ca27abe-c5f5-41e1-a67f-5340ec1b48b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13269
00277 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_intr_timeout.1326900277
Directory /workspace/32.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_lpg.4057176815
Short name T449
Test name
Test status
Simulation time 6409467135 ps
CPU time 544.77 seconds
Started Feb 21 03:56:23 PM PST 24
Finished Feb 21 04:05:29 PM PST 24
Peak memory 264752 kb
Host smart-9b1c0582-9454-4d52-b013-4f4144a4fc84
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4057176815 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg.4057176815
Directory /workspace/32.alert_handler_lpg/latest

Test location /workspace/coverage/default/32.alert_handler_ping_timeout.4237015876
Short name T705
Test name
Test status
Simulation time 36101293035 ps
CPU time 354.74 seconds
Started Feb 21 03:56:23 PM PST 24
Finished Feb 21 04:02:18 PM PST 24
Peak memory 247140 kb
Host smart-811015ab-e35a-4e77-a8e8-b1522c824404
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237015876 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_ping_timeout.4237015876
Directory /workspace/32.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_random_alerts.1742150627
Short name T450
Test name
Test status
Simulation time 714997814 ps
CPU time 42.6 seconds
Started Feb 21 03:56:07 PM PST 24
Finished Feb 21 03:56:51 PM PST 24
Peak memory 256424 kb
Host smart-a534e19a-5b29-47c2-8588-01cc3a72348d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17421
50627 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_alerts.1742150627
Directory /workspace/32.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/32.alert_handler_random_classes.3521780863
Short name T251
Test name
Test status
Simulation time 14093327316 ps
CPU time 58.56 seconds
Started Feb 21 03:56:12 PM PST 24
Finished Feb 21 03:57:12 PM PST 24
Peak memory 255224 kb
Host smart-db09f7b2-9c98-4ba9-a0d7-8229617dca7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35217
80863 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_classes.3521780863
Directory /workspace/32.alert_handler_random_classes/latest

Test location /workspace/coverage/default/32.alert_handler_sig_int_fail.83260141
Short name T378
Test name
Test status
Simulation time 597840015 ps
CPU time 5.52 seconds
Started Feb 21 03:56:23 PM PST 24
Finished Feb 21 03:56:29 PM PST 24
Peak memory 249708 kb
Host smart-286cde71-28fa-4cc0-946b-5f79b73e5f8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83260
141 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_sig_int_fail.83260141
Directory /workspace/32.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/32.alert_handler_smoke.3923419223
Short name T496
Test name
Test status
Simulation time 1774318895 ps
CPU time 33.4 seconds
Started Feb 21 03:56:12 PM PST 24
Finished Feb 21 03:56:47 PM PST 24
Peak memory 248236 kb
Host smart-d733d0e7-9867-409c-940c-d97f305bd299
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39234
19223 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_smoke.3923419223
Directory /workspace/32.alert_handler_smoke/latest

Test location /workspace/coverage/default/33.alert_handler_entropy.1468075331
Short name T253
Test name
Test status
Simulation time 16911825842 ps
CPU time 1067.81 seconds
Started Feb 21 03:56:23 PM PST 24
Finished Feb 21 04:14:11 PM PST 24
Peak memory 272048 kb
Host smart-1c01ae7e-9ec3-42b9-897e-ed6eb3523193
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468075331 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_entropy.1468075331
Directory /workspace/33.alert_handler_entropy/latest

Test location /workspace/coverage/default/33.alert_handler_esc_alert_accum.3082174554
Short name T387
Test name
Test status
Simulation time 1956402132 ps
CPU time 23.99 seconds
Started Feb 21 03:56:15 PM PST 24
Finished Feb 21 03:56:40 PM PST 24
Peak memory 248240 kb
Host smart-84adb3bf-8ae9-46ad-b1f9-d31749a9335b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30821
74554 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_alert_accum.3082174554
Directory /workspace/33.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/33.alert_handler_esc_intr_timeout.833586488
Short name T418
Test name
Test status
Simulation time 1653783642 ps
CPU time 30.52 seconds
Started Feb 21 03:56:23 PM PST 24
Finished Feb 21 03:56:54 PM PST 24
Peak memory 247936 kb
Host smart-b28eb9e6-286a-4d26-b009-15a79c5643ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83358
6488 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_intr_timeout.833586488
Directory /workspace/33.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_lpg.745169380
Short name T595
Test name
Test status
Simulation time 19913700863 ps
CPU time 920.98 seconds
Started Feb 21 03:56:21 PM PST 24
Finished Feb 21 04:11:42 PM PST 24
Peak memory 272488 kb
Host smart-4d812257-abc8-4bee-ab4a-d2e3524ad9e5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=745169380 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg.745169380
Directory /workspace/33.alert_handler_lpg/latest

Test location /workspace/coverage/default/33.alert_handler_lpg_stub_clk.2266006840
Short name T394
Test name
Test status
Simulation time 20109878175 ps
CPU time 552.7 seconds
Started Feb 21 03:56:20 PM PST 24
Finished Feb 21 04:05:33 PM PST 24
Peak memory 264348 kb
Host smart-a6abe843-07ff-4219-bc16-4b84f53ad03a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2266006840 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg_stub_clk.2266006840
Directory /workspace/33.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/33.alert_handler_ping_timeout.3071689289
Short name T306
Test name
Test status
Simulation time 46766522775 ps
CPU time 112.52 seconds
Started Feb 21 03:56:12 PM PST 24
Finished Feb 21 03:58:05 PM PST 24
Peak memory 247084 kb
Host smart-691489a0-8c23-42d8-a862-5d8512f24611
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071689289 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_ping_timeout.3071689289
Directory /workspace/33.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_random_alerts.341752069
Short name T604
Test name
Test status
Simulation time 4082196563 ps
CPU time 52.91 seconds
Started Feb 21 03:56:15 PM PST 24
Finished Feb 21 03:57:08 PM PST 24
Peak memory 248428 kb
Host smart-fe9f596f-804d-420e-8bbc-3d648e6d66ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34175
2069 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_alerts.341752069
Directory /workspace/33.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/33.alert_handler_random_classes.1694534139
Short name T703
Test name
Test status
Simulation time 867301855 ps
CPU time 19.78 seconds
Started Feb 21 03:56:18 PM PST 24
Finished Feb 21 03:56:38 PM PST 24
Peak memory 246524 kb
Host smart-eaed6911-ff76-4a6b-afee-de0325e551c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16945
34139 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_classes.1694534139
Directory /workspace/33.alert_handler_random_classes/latest

Test location /workspace/coverage/default/33.alert_handler_sig_int_fail.2223287216
Short name T271
Test name
Test status
Simulation time 241789163 ps
CPU time 10.63 seconds
Started Feb 21 03:56:12 PM PST 24
Finished Feb 21 03:56:24 PM PST 24
Peak memory 251836 kb
Host smart-7563525d-4439-4243-aa52-1cb7a2dbad46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22232
87216 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_sig_int_fail.2223287216
Directory /workspace/33.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/33.alert_handler_smoke.4249113938
Short name T395
Test name
Test status
Simulation time 254076718 ps
CPU time 7.71 seconds
Started Feb 21 03:56:16 PM PST 24
Finished Feb 21 03:56:24 PM PST 24
Peak memory 248256 kb
Host smart-d27d5ee2-9c57-4d71-999b-75b31dbc6a0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42491
13938 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_smoke.4249113938
Directory /workspace/33.alert_handler_smoke/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all.2088916696
Short name T216
Test name
Test status
Simulation time 54130065071 ps
CPU time 2964.58 seconds
Started Feb 21 03:56:21 PM PST 24
Finished Feb 21 04:45:47 PM PST 24
Peak memory 288848 kb
Host smart-ad39aca9-9701-42bb-aa55-6b9ff0cea5e3
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088916696 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_ha
ndler_stress_all.2088916696
Directory /workspace/33.alert_handler_stress_all/latest

Test location /workspace/coverage/default/34.alert_handler_entropy.1194575245
Short name T457
Test name
Test status
Simulation time 23026236139 ps
CPU time 1001 seconds
Started Feb 21 03:56:21 PM PST 24
Finished Feb 21 04:13:03 PM PST 24
Peak memory 271696 kb
Host smart-41a9acf1-9f8c-424e-bdb1-8f538054c14b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194575245 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_entropy.1194575245
Directory /workspace/34.alert_handler_entropy/latest

Test location /workspace/coverage/default/34.alert_handler_esc_alert_accum.209965942
Short name T576
Test name
Test status
Simulation time 7428872103 ps
CPU time 139.85 seconds
Started Feb 21 03:56:19 PM PST 24
Finished Feb 21 03:58:40 PM PST 24
Peak memory 256472 kb
Host smart-8c9aecd0-bb94-4a96-a0cf-d23eb7d7d616
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20996
5942 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_alert_accum.209965942
Directory /workspace/34.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/34.alert_handler_esc_intr_timeout.3637396071
Short name T72
Test name
Test status
Simulation time 88736840 ps
CPU time 7.25 seconds
Started Feb 21 03:56:21 PM PST 24
Finished Feb 21 03:56:29 PM PST 24
Peak memory 239596 kb
Host smart-718c9001-382e-4f16-9f1e-675723c965fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36373
96071 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_intr_timeout.3637396071
Directory /workspace/34.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_lpg_stub_clk.542451784
Short name T534
Test name
Test status
Simulation time 15906994736 ps
CPU time 1384.12 seconds
Started Feb 21 03:56:33 PM PST 24
Finished Feb 21 04:19:37 PM PST 24
Peak memory 288396 kb
Host smart-44d735e7-2cc5-4846-a5d3-2999a2436c28
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542451784 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg_stub_clk.542451784
Directory /workspace/34.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/34.alert_handler_ping_timeout.383826361
Short name T300
Test name
Test status
Simulation time 12050151948 ps
CPU time 469.38 seconds
Started Feb 21 03:56:21 PM PST 24
Finished Feb 21 04:04:11 PM PST 24
Peak memory 253852 kb
Host smart-f9128442-d387-42fd-8c22-c2034e0cac50
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383826361 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_ping_timeout.383826361
Directory /workspace/34.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_random_alerts.2757411759
Short name T417
Test name
Test status
Simulation time 220089941 ps
CPU time 20.88 seconds
Started Feb 21 03:56:21 PM PST 24
Finished Feb 21 03:56:43 PM PST 24
Peak memory 255396 kb
Host smart-e064a6c7-f482-47bd-aa1d-40ff4e4fa6fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27574
11759 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_alerts.2757411759
Directory /workspace/34.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/34.alert_handler_random_classes.785550898
Short name T379
Test name
Test status
Simulation time 457229387 ps
CPU time 32.64 seconds
Started Feb 21 03:56:25 PM PST 24
Finished Feb 21 03:56:59 PM PST 24
Peak memory 247664 kb
Host smart-88ef8114-5cfc-428b-87b4-10acac0570ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78555
0898 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_classes.785550898
Directory /workspace/34.alert_handler_random_classes/latest

Test location /workspace/coverage/default/34.alert_handler_sig_int_fail.2295467756
Short name T78
Test name
Test status
Simulation time 2945830897 ps
CPU time 52.99 seconds
Started Feb 21 03:56:24 PM PST 24
Finished Feb 21 03:57:17 PM PST 24
Peak memory 254972 kb
Host smart-86a4b310-2f5a-4207-af15-9c36206f8ec7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22954
67756 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_sig_int_fail.2295467756
Directory /workspace/34.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/34.alert_handler_smoke.1778790811
Short name T456
Test name
Test status
Simulation time 1189605615 ps
CPU time 38.21 seconds
Started Feb 21 03:56:23 PM PST 24
Finished Feb 21 03:57:01 PM PST 24
Peak memory 248224 kb
Host smart-fe435af2-5698-40bc-b6e0-578b4c3fa802
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17787
90811 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_smoke.1778790811
Directory /workspace/34.alert_handler_smoke/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all_with_rand_reset.3076309202
Short name T234
Test name
Test status
Simulation time 35543436591 ps
CPU time 2066.84 seconds
Started Feb 21 03:56:30 PM PST 24
Finished Feb 21 04:30:58 PM PST 24
Peak memory 288632 kb
Host smart-d5d07a0c-15ed-4d19-891a-0c0a4b70d2aa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076309202 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.alert_handler_stress_all_with_rand_reset.3076309202
Directory /workspace/34.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.alert_handler_entropy.3658579359
Short name T59
Test name
Test status
Simulation time 8034936893 ps
CPU time 940.64 seconds
Started Feb 21 03:56:30 PM PST 24
Finished Feb 21 04:12:11 PM PST 24
Peak memory 284088 kb
Host smart-3e6b582d-6b22-449e-8f8a-8b0b5e7dacbd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658579359 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_entropy.3658579359
Directory /workspace/35.alert_handler_entropy/latest

Test location /workspace/coverage/default/35.alert_handler_esc_alert_accum.3895863017
Short name T490
Test name
Test status
Simulation time 23742065246 ps
CPU time 197.49 seconds
Started Feb 21 03:56:30 PM PST 24
Finished Feb 21 03:59:48 PM PST 24
Peak memory 256448 kb
Host smart-b2eac52b-5ca9-4638-93fe-4b2e3a0870b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38958
63017 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_alert_accum.3895863017
Directory /workspace/35.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/35.alert_handler_esc_intr_timeout.967668570
Short name T71
Test name
Test status
Simulation time 680355658 ps
CPU time 22.39 seconds
Started Feb 21 03:56:31 PM PST 24
Finished Feb 21 03:56:54 PM PST 24
Peak memory 252984 kb
Host smart-b19a7b93-9910-481b-a9d0-f2f8bf49768c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96766
8570 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_intr_timeout.967668570
Directory /workspace/35.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_lpg.3147484596
Short name T337
Test name
Test status
Simulation time 71869903501 ps
CPU time 2013 seconds
Started Feb 21 03:56:28 PM PST 24
Finished Feb 21 04:30:02 PM PST 24
Peak memory 288916 kb
Host smart-27056d8a-6a96-46b9-9488-96f3a7eade82
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147484596 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg.3147484596
Directory /workspace/35.alert_handler_lpg/latest

Test location /workspace/coverage/default/35.alert_handler_lpg_stub_clk.4174467977
Short name T255
Test name
Test status
Simulation time 27925698856 ps
CPU time 663.48 seconds
Started Feb 21 03:56:28 PM PST 24
Finished Feb 21 04:07:32 PM PST 24
Peak memory 272904 kb
Host smart-cebca754-55fe-43b3-bc63-3c3adc25772e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174467977 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg_stub_clk.4174467977
Directory /workspace/35.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/35.alert_handler_ping_timeout.2274432140
Short name T294
Test name
Test status
Simulation time 42484661598 ps
CPU time 430.28 seconds
Started Feb 21 03:56:27 PM PST 24
Finished Feb 21 04:03:38 PM PST 24
Peak memory 247196 kb
Host smart-f3332564-4afb-4cb9-8091-36732ffb5d01
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2274432140 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_ping_timeout.2274432140
Directory /workspace/35.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_random_alerts.1607238668
Short name T399
Test name
Test status
Simulation time 27900466 ps
CPU time 4.1 seconds
Started Feb 21 03:56:29 PM PST 24
Finished Feb 21 03:56:33 PM PST 24
Peak memory 240016 kb
Host smart-cf08d087-abdf-4740-ab6d-426a60fef765
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16072
38668 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_alerts.1607238668
Directory /workspace/35.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/35.alert_handler_random_classes.2914075505
Short name T629
Test name
Test status
Simulation time 829654236 ps
CPU time 35.68 seconds
Started Feb 21 03:56:29 PM PST 24
Finished Feb 21 03:57:06 PM PST 24
Peak memory 246400 kb
Host smart-0dc09c58-89ad-495f-ab8a-f05d693e6f47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29140
75505 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_classes.2914075505
Directory /workspace/35.alert_handler_random_classes/latest

Test location /workspace/coverage/default/35.alert_handler_sig_int_fail.3058830201
Short name T273
Test name
Test status
Simulation time 3754692662 ps
CPU time 50.21 seconds
Started Feb 21 03:56:27 PM PST 24
Finished Feb 21 03:57:18 PM PST 24
Peak memory 255408 kb
Host smart-52abe717-a390-445c-a384-7fc79a0de94c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30588
30201 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_sig_int_fail.3058830201
Directory /workspace/35.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/35.alert_handler_smoke.1522169406
Short name T248
Test name
Test status
Simulation time 330515030 ps
CPU time 21.68 seconds
Started Feb 21 03:56:29 PM PST 24
Finished Feb 21 03:56:51 PM PST 24
Peak memory 248288 kb
Host smart-73b30636-d99f-4c3e-82ad-07bbc63597b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15221
69406 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_smoke.1522169406
Directory /workspace/35.alert_handler_smoke/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all_with_rand_reset.2716999114
Short name T282
Test name
Test status
Simulation time 176285127813 ps
CPU time 2689.65 seconds
Started Feb 21 03:56:49 PM PST 24
Finished Feb 21 04:41:40 PM PST 24
Peak memory 297616 kb
Host smart-59bb087b-984e-4d9f-8eca-cf1cd6a29ede
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716999114 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 35.alert_handler_stress_all_with_rand_reset.2716999114
Directory /workspace/35.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.alert_handler_entropy.4067727780
Short name T710
Test name
Test status
Simulation time 78778524197 ps
CPU time 1407.63 seconds
Started Feb 21 03:56:53 PM PST 24
Finished Feb 21 04:20:21 PM PST 24
Peak memory 272908 kb
Host smart-50b70f86-aafe-4901-b8f7-93fa14a5faca
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067727780 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_entropy.4067727780
Directory /workspace/36.alert_handler_entropy/latest

Test location /workspace/coverage/default/36.alert_handler_esc_alert_accum.4093279705
Short name T491
Test name
Test status
Simulation time 4281364611 ps
CPU time 125.65 seconds
Started Feb 21 03:56:54 PM PST 24
Finished Feb 21 03:59:00 PM PST 24
Peak memory 255884 kb
Host smart-295b80a9-9b1e-46cb-8f23-6f206d4dcd68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40932
79705 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_alert_accum.4093279705
Directory /workspace/36.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/36.alert_handler_esc_intr_timeout.842240424
Short name T463
Test name
Test status
Simulation time 247261512 ps
CPU time 8.71 seconds
Started Feb 21 03:56:55 PM PST 24
Finished Feb 21 03:57:04 PM PST 24
Peak memory 249732 kb
Host smart-7484e4f0-96d8-4474-9f59-cbd6dcb71efe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84224
0424 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_intr_timeout.842240424
Directory /workspace/36.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_lpg_stub_clk.582765919
Short name T497
Test name
Test status
Simulation time 28000711483 ps
CPU time 780.86 seconds
Started Feb 21 03:57:03 PM PST 24
Finished Feb 21 04:10:04 PM PST 24
Peak memory 272004 kb
Host smart-16cdcacf-bcac-4e5e-b685-3b48fe35682f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=582765919 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg_stub_clk.582765919
Directory /workspace/36.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/36.alert_handler_random_alerts.1918420185
Short name T540
Test name
Test status
Simulation time 140472696 ps
CPU time 16.72 seconds
Started Feb 21 03:56:40 PM PST 24
Finished Feb 21 03:56:57 PM PST 24
Peak memory 253988 kb
Host smart-32d2146e-1e74-44ed-8e95-6d6c0014a257
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19184
20185 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_alerts.1918420185
Directory /workspace/36.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/36.alert_handler_random_classes.1190170995
Short name T504
Test name
Test status
Simulation time 388877968 ps
CPU time 22.46 seconds
Started Feb 21 03:56:54 PM PST 24
Finished Feb 21 03:57:17 PM PST 24
Peak memory 252996 kb
Host smart-f88e3f9c-974a-49f7-9572-518bfd109e2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11901
70995 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_classes.1190170995
Directory /workspace/36.alert_handler_random_classes/latest

Test location /workspace/coverage/default/36.alert_handler_sig_int_fail.3612205854
Short name T377
Test name
Test status
Simulation time 53020240 ps
CPU time 5.64 seconds
Started Feb 21 03:56:53 PM PST 24
Finished Feb 21 03:56:59 PM PST 24
Peak memory 238320 kb
Host smart-e3ca2bbf-d5b9-4bc0-8970-3058266c7256
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36122
05854 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_sig_int_fail.3612205854
Directory /workspace/36.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/36.alert_handler_smoke.1375488596
Short name T411
Test name
Test status
Simulation time 703636269 ps
CPU time 40.65 seconds
Started Feb 21 03:57:06 PM PST 24
Finished Feb 21 03:57:47 PM PST 24
Peak memory 248208 kb
Host smart-1ea293a2-09ea-416f-b542-859377648eeb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13754
88596 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_smoke.1375488596
Directory /workspace/36.alert_handler_smoke/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all.3887859898
Short name T279
Test name
Test status
Simulation time 11799768776 ps
CPU time 1417.13 seconds
Started Feb 21 03:56:39 PM PST 24
Finished Feb 21 04:20:16 PM PST 24
Peak memory 288812 kb
Host smart-e71e3491-ce83-4328-9bb7-7c9ee473075a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887859898 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_ha
ndler_stress_all.3887859898
Directory /workspace/36.alert_handler_stress_all/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all_with_rand_reset.2919014711
Short name T62
Test name
Test status
Simulation time 35973036340 ps
CPU time 477.59 seconds
Started Feb 21 03:57:03 PM PST 24
Finished Feb 21 04:05:01 PM PST 24
Peak memory 266144 kb
Host smart-2666252c-c673-4442-ab06-41932b697bfd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919014711 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 36.alert_handler_stress_all_with_rand_reset.2919014711
Directory /workspace/36.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.alert_handler_entropy.3241291580
Short name T61
Test name
Test status
Simulation time 34367703068 ps
CPU time 1115.61 seconds
Started Feb 21 03:56:55 PM PST 24
Finished Feb 21 04:15:31 PM PST 24
Peak memory 264788 kb
Host smart-533db1b0-9ef4-4ba2-8744-87b21efe9864
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241291580 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_entropy.3241291580
Directory /workspace/37.alert_handler_entropy/latest

Test location /workspace/coverage/default/37.alert_handler_esc_alert_accum.1964351819
Short name T448
Test name
Test status
Simulation time 2716096093 ps
CPU time 107.53 seconds
Started Feb 21 03:57:03 PM PST 24
Finished Feb 21 03:58:51 PM PST 24
Peak memory 255864 kb
Host smart-89543754-4eb4-416f-a44b-cc3820adeb30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19643
51819 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_alert_accum.1964351819
Directory /workspace/37.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/37.alert_handler_esc_intr_timeout.1452751047
Short name T401
Test name
Test status
Simulation time 566044471 ps
CPU time 14.37 seconds
Started Feb 21 03:56:54 PM PST 24
Finished Feb 21 03:57:08 PM PST 24
Peak memory 253916 kb
Host smart-786d119e-0f6e-490f-a8ff-c28041d18aab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14527
51047 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_intr_timeout.1452751047
Directory /workspace/37.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_lpg.1774193765
Short name T314
Test name
Test status
Simulation time 20870944692 ps
CPU time 1455.64 seconds
Started Feb 21 03:57:03 PM PST 24
Finished Feb 21 04:21:19 PM PST 24
Peak memory 288516 kb
Host smart-0feba7ae-6fe0-4df4-99a2-f86a9cb6f162
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774193765 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg.1774193765
Directory /workspace/37.alert_handler_lpg/latest

Test location /workspace/coverage/default/37.alert_handler_lpg_stub_clk.2634830728
Short name T220
Test name
Test status
Simulation time 122834016615 ps
CPU time 2141.36 seconds
Started Feb 21 03:57:03 PM PST 24
Finished Feb 21 04:32:45 PM PST 24
Peak memory 282824 kb
Host smart-874d3d89-2e1f-4140-b99c-d02f57a93b12
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634830728 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg_stub_clk.2634830728
Directory /workspace/37.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/37.alert_handler_random_alerts.2689807616
Short name T687
Test name
Test status
Simulation time 1554812063 ps
CPU time 26.7 seconds
Started Feb 21 03:57:01 PM PST 24
Finished Feb 21 03:57:28 PM PST 24
Peak memory 254968 kb
Host smart-7374c7d1-33c5-4101-a43f-0431afb30651
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26898
07616 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_alerts.2689807616
Directory /workspace/37.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/37.alert_handler_random_classes.3054456748
Short name T578
Test name
Test status
Simulation time 244049925 ps
CPU time 20.79 seconds
Started Feb 21 03:57:05 PM PST 24
Finished Feb 21 03:57:26 PM PST 24
Peak memory 253848 kb
Host smart-4f42f387-0a6b-4981-9b07-cb8b46bfe1bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30544
56748 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_classes.3054456748
Directory /workspace/37.alert_handler_random_classes/latest

Test location /workspace/coverage/default/37.alert_handler_sig_int_fail.3277516551
Short name T262
Test name
Test status
Simulation time 573245441 ps
CPU time 40.26 seconds
Started Feb 21 03:57:01 PM PST 24
Finished Feb 21 03:57:41 PM PST 24
Peak memory 246364 kb
Host smart-66eb03f3-c54e-4831-aa1e-5c270ca1dcb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32775
16551 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_sig_int_fail.3277516551
Directory /workspace/37.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/37.alert_handler_smoke.621937275
Short name T646
Test name
Test status
Simulation time 219646072 ps
CPU time 18.19 seconds
Started Feb 21 03:57:02 PM PST 24
Finished Feb 21 03:57:21 PM PST 24
Peak memory 248256 kb
Host smart-06c78a7d-13ca-4a35-9241-bdaafaaaeb4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62193
7275 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_smoke.621937275
Directory /workspace/37.alert_handler_smoke/latest

Test location /workspace/coverage/default/38.alert_handler_entropy.1806494708
Short name T70
Test name
Test status
Simulation time 29164969848 ps
CPU time 1803.07 seconds
Started Feb 21 03:57:02 PM PST 24
Finished Feb 21 04:27:06 PM PST 24
Peak memory 281064 kb
Host smart-739809bf-3df2-4b54-bdf9-9a33a314ccfc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806494708 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_entropy.1806494708
Directory /workspace/38.alert_handler_entropy/latest

Test location /workspace/coverage/default/38.alert_handler_esc_alert_accum.692166495
Short name T46
Test name
Test status
Simulation time 1464977815 ps
CPU time 119.44 seconds
Started Feb 21 03:57:03 PM PST 24
Finished Feb 21 03:59:03 PM PST 24
Peak memory 255796 kb
Host smart-0e04ab03-74a8-41a4-b0fa-57940ba84229
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69216
6495 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_alert_accum.692166495
Directory /workspace/38.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/38.alert_handler_esc_intr_timeout.1260045201
Short name T495
Test name
Test status
Simulation time 8201073539 ps
CPU time 41.91 seconds
Started Feb 21 03:57:05 PM PST 24
Finished Feb 21 03:57:47 PM PST 24
Peak memory 254504 kb
Host smart-4d4161ce-b1a9-43d3-b07a-5286159c5bb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12600
45201 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_intr_timeout.1260045201
Directory /workspace/38.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_lpg.1690498886
Short name T305
Test name
Test status
Simulation time 67324448374 ps
CPU time 2583.14 seconds
Started Feb 21 03:57:02 PM PST 24
Finished Feb 21 04:40:06 PM PST 24
Peak memory 288788 kb
Host smart-c4a4935b-7323-46a9-8365-8f1a2286d647
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690498886 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg.1690498886
Directory /workspace/38.alert_handler_lpg/latest

Test location /workspace/coverage/default/38.alert_handler_lpg_stub_clk.3725916495
Short name T577
Test name
Test status
Simulation time 11009878700 ps
CPU time 1148.68 seconds
Started Feb 21 03:57:03 PM PST 24
Finished Feb 21 04:16:12 PM PST 24
Peak memory 288392 kb
Host smart-ebc249ba-b972-4d57-bcc3-4a07c0f77884
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725916495 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg_stub_clk.3725916495
Directory /workspace/38.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/38.alert_handler_random_alerts.1995397666
Short name T572
Test name
Test status
Simulation time 496306827 ps
CPU time 24.99 seconds
Started Feb 21 03:57:04 PM PST 24
Finished Feb 21 03:57:29 PM PST 24
Peak memory 248268 kb
Host smart-81715d1c-b75e-476d-a45b-16b4b48fd7fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19953
97666 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_alerts.1995397666
Directory /workspace/38.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/38.alert_handler_random_classes.3178408694
Short name T530
Test name
Test status
Simulation time 48226502 ps
CPU time 7.45 seconds
Started Feb 21 03:57:02 PM PST 24
Finished Feb 21 03:57:09 PM PST 24
Peak memory 246592 kb
Host smart-f61fcdaa-bf8f-4dd3-9ac0-19067835df25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31784
08694 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_classes.3178408694
Directory /workspace/38.alert_handler_random_classes/latest

Test location /workspace/coverage/default/38.alert_handler_sig_int_fail.2524861044
Short name T478
Test name
Test status
Simulation time 114480309 ps
CPU time 4.74 seconds
Started Feb 21 03:57:02 PM PST 24
Finished Feb 21 03:57:08 PM PST 24
Peak memory 240052 kb
Host smart-be289389-4146-4011-ab90-220e793bb9f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25248
61044 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_sig_int_fail.2524861044
Directory /workspace/38.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/38.alert_handler_smoke.2242055047
Short name T364
Test name
Test status
Simulation time 148453930 ps
CPU time 9.98 seconds
Started Feb 21 03:57:02 PM PST 24
Finished Feb 21 03:57:12 PM PST 24
Peak memory 248244 kb
Host smart-7816c607-be26-4cb3-8c8f-3b6723ad998b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22420
55047 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_smoke.2242055047
Directory /workspace/38.alert_handler_smoke/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all.1423090946
Short name T91
Test name
Test status
Simulation time 13334507276 ps
CPU time 1228.19 seconds
Started Feb 21 03:57:05 PM PST 24
Finished Feb 21 04:17:34 PM PST 24
Peak memory 288596 kb
Host smart-8017f034-3e3c-4fb1-b8cb-4862bc19cd74
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423090946 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_ha
ndler_stress_all.1423090946
Directory /workspace/38.alert_handler_stress_all/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all_with_rand_reset.2055675384
Short name T413
Test name
Test status
Simulation time 33489441625 ps
CPU time 1565.05 seconds
Started Feb 21 03:57:04 PM PST 24
Finished Feb 21 04:23:09 PM PST 24
Peak memory 304796 kb
Host smart-ebdaffc0-f49b-4e20-a49d-2c2831640ecf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055675384 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.alert_handler_stress_all_with_rand_reset.2055675384
Directory /workspace/38.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.alert_handler_entropy.457964840
Short name T659
Test name
Test status
Simulation time 33784182940 ps
CPU time 1742.99 seconds
Started Feb 21 03:57:07 PM PST 24
Finished Feb 21 04:26:10 PM PST 24
Peak memory 282076 kb
Host smart-57607800-b860-413d-8e73-d8bc0fbd12ce
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457964840 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_entropy.457964840
Directory /workspace/39.alert_handler_entropy/latest

Test location /workspace/coverage/default/39.alert_handler_esc_alert_accum.1392460880
Short name T653
Test name
Test status
Simulation time 74205225520 ps
CPU time 225.52 seconds
Started Feb 21 03:57:03 PM PST 24
Finished Feb 21 04:00:49 PM PST 24
Peak memory 255768 kb
Host smart-d1a689e2-03e1-4f94-ad23-a04de01be400
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13924
60880 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_alert_accum.1392460880
Directory /workspace/39.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/39.alert_handler_esc_intr_timeout.2546341836
Short name T502
Test name
Test status
Simulation time 103896882 ps
CPU time 6.51 seconds
Started Feb 21 03:57:01 PM PST 24
Finished Feb 21 03:57:08 PM PST 24
Peak memory 250896 kb
Host smart-9e595d7c-5fa9-475b-8ae3-ef16088e9a5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25463
41836 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_intr_timeout.2546341836
Directory /workspace/39.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_lpg_stub_clk.383434618
Short name T486
Test name
Test status
Simulation time 92711356112 ps
CPU time 2768.82 seconds
Started Feb 21 03:57:07 PM PST 24
Finished Feb 21 04:43:16 PM PST 24
Peak memory 288736 kb
Host smart-ec4ceb84-5590-4fb2-80bd-94f2e0016d8f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383434618 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg_stub_clk.383434618
Directory /workspace/39.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/39.alert_handler_ping_timeout.3950846071
Short name T298
Test name
Test status
Simulation time 2940248880 ps
CPU time 121.9 seconds
Started Feb 21 03:57:07 PM PST 24
Finished Feb 21 03:59:09 PM PST 24
Peak memory 246988 kb
Host smart-c0ba237e-f294-4e77-9990-97fa6a1fc6f7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950846071 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_ping_timeout.3950846071
Directory /workspace/39.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_random_alerts.2955960099
Short name T707
Test name
Test status
Simulation time 60468989 ps
CPU time 3.34 seconds
Started Feb 21 03:57:02 PM PST 24
Finished Feb 21 03:57:06 PM PST 24
Peak memory 240036 kb
Host smart-7ccc28c3-5bb5-4b92-92a3-01bf1dbf565c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29559
60099 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_alerts.2955960099
Directory /workspace/39.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/39.alert_handler_random_classes.2876268034
Short name T432
Test name
Test status
Simulation time 321781594 ps
CPU time 29.95 seconds
Started Feb 21 03:57:02 PM PST 24
Finished Feb 21 03:57:32 PM PST 24
Peak memory 246480 kb
Host smart-e6c6aa37-d0d9-4f93-b06c-60706dde623f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28762
68034 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_classes.2876268034
Directory /workspace/39.alert_handler_random_classes/latest

Test location /workspace/coverage/default/39.alert_handler_sig_int_fail.1714380546
Short name T278
Test name
Test status
Simulation time 2342469255 ps
CPU time 59.48 seconds
Started Feb 21 03:57:02 PM PST 24
Finished Feb 21 03:58:03 PM PST 24
Peak memory 254204 kb
Host smart-48c1ee0f-0f2f-47b9-baa6-7f0143ca84fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17143
80546 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_sig_int_fail.1714380546
Directory /workspace/39.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/39.alert_handler_smoke.4039013994
Short name T19
Test name
Test status
Simulation time 1145970038 ps
CPU time 19.61 seconds
Started Feb 21 03:57:03 PM PST 24
Finished Feb 21 03:57:23 PM PST 24
Peak memory 248248 kb
Host smart-926fe8f7-0273-4da0-9391-39d5b61f83c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40390
13994 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_smoke.4039013994
Directory /workspace/39.alert_handler_smoke/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all.4039359596
Short name T625
Test name
Test status
Simulation time 116415132449 ps
CPU time 3277.18 seconds
Started Feb 21 03:57:05 PM PST 24
Finished Feb 21 04:51:43 PM PST 24
Peak memory 289272 kb
Host smart-32896c33-4014-4744-913a-33419a812945
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039359596 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_ha
ndler_stress_all.4039359596
Directory /workspace/39.alert_handler_stress_all/latest

Test location /workspace/coverage/default/4.alert_handler_alert_accum_saturation.2638755149
Short name T196
Test name
Test status
Simulation time 276271426 ps
CPU time 3.01 seconds
Started Feb 21 03:53:52 PM PST 24
Finished Feb 21 03:53:56 PM PST 24
Peak memory 248536 kb
Host smart-e13432fc-7ddd-4938-85f0-59801816a2cf
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2638755149 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_alert_accum_saturation.2638755149
Directory /workspace/4.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/4.alert_handler_entropy.1591165043
Short name T672
Test name
Test status
Simulation time 61365168197 ps
CPU time 610.86 seconds
Started Feb 21 03:53:52 PM PST 24
Finished Feb 21 04:04:04 PM PST 24
Peak memory 272568 kb
Host smart-8e081746-1725-4d44-abbe-143d62620f3e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1591165043 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy.1591165043
Directory /workspace/4.alert_handler_entropy/latest

Test location /workspace/coverage/default/4.alert_handler_entropy_stress.1593587388
Short name T214
Test name
Test status
Simulation time 705894945 ps
CPU time 29.74 seconds
Started Feb 21 03:53:50 PM PST 24
Finished Feb 21 03:54:21 PM PST 24
Peak memory 240072 kb
Host smart-dd5b49aa-6bce-4b0c-80a3-914d8520540e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1593587388 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy_stress.1593587388
Directory /workspace/4.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/4.alert_handler_esc_alert_accum.3330370609
Short name T224
Test name
Test status
Simulation time 7178277044 ps
CPU time 127.21 seconds
Started Feb 21 03:53:52 PM PST 24
Finished Feb 21 03:56:00 PM PST 24
Peak memory 256452 kb
Host smart-40de044b-04e9-4f54-956d-2ee3fc4cd250
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33303
70609 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_alert_accum.3330370609
Directory /workspace/4.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/4.alert_handler_esc_intr_timeout.3075131867
Short name T645
Test name
Test status
Simulation time 858140230 ps
CPU time 52.93 seconds
Started Feb 21 03:53:47 PM PST 24
Finished Feb 21 03:54:42 PM PST 24
Peak memory 254696 kb
Host smart-d0fe11df-ca2d-4313-9e8b-2f2b80fb8dfa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30751
31867 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_intr_timeout.3075131867
Directory /workspace/4.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_lpg.2010698006
Short name T331
Test name
Test status
Simulation time 57160854434 ps
CPU time 1579.87 seconds
Started Feb 21 03:53:50 PM PST 24
Finished Feb 21 04:20:11 PM PST 24
Peak memory 272464 kb
Host smart-7242b49d-1dfa-4089-9963-1d805d71a274
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2010698006 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg.2010698006
Directory /workspace/4.alert_handler_lpg/latest

Test location /workspace/coverage/default/4.alert_handler_lpg_stub_clk.236942835
Short name T643
Test name
Test status
Simulation time 209845412551 ps
CPU time 3093.9 seconds
Started Feb 21 03:53:52 PM PST 24
Finished Feb 21 04:45:28 PM PST 24
Peak memory 289256 kb
Host smart-f8d2ee5e-477b-4c88-ae75-9be83589d7d1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236942835 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg_stub_clk.236942835
Directory /workspace/4.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/4.alert_handler_ping_timeout.1507647803
Short name T549
Test name
Test status
Simulation time 6464181021 ps
CPU time 138.71 seconds
Started Feb 21 03:53:50 PM PST 24
Finished Feb 21 03:56:11 PM PST 24
Peak memory 246184 kb
Host smart-0aed823b-6d44-4fc0-8799-4ca9136e1fa4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507647803 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_ping_timeout.1507647803
Directory /workspace/4.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_random_alerts.3543006571
Short name T473
Test name
Test status
Simulation time 666610355 ps
CPU time 23.13 seconds
Started Feb 21 03:53:47 PM PST 24
Finished Feb 21 03:54:12 PM PST 24
Peak memory 256440 kb
Host smart-3ba1ce68-57f3-45c5-807b-85b55eac39d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35430
06571 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_alerts.3543006571
Directory /workspace/4.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/4.alert_handler_random_classes.2628614746
Short name T430
Test name
Test status
Simulation time 72974903 ps
CPU time 8.41 seconds
Started Feb 21 03:53:50 PM PST 24
Finished Feb 21 03:54:00 PM PST 24
Peak memory 252248 kb
Host smart-d25d1a6a-4af2-43f5-80f8-6a9979dc9dd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26286
14746 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_classes.2628614746
Directory /workspace/4.alert_handler_random_classes/latest

Test location /workspace/coverage/default/4.alert_handler_sec_cm.1259760552
Short name T12
Test name
Test status
Simulation time 2616733678 ps
CPU time 48.6 seconds
Started Feb 21 03:53:58 PM PST 24
Finished Feb 21 03:54:46 PM PST 24
Peak memory 272244 kb
Host smart-7274d79b-c4a8-4cf4-b6b8-8acef942b54c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1259760552 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sec_cm.1259760552
Directory /workspace/4.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/4.alert_handler_sig_int_fail.2420157336
Short name T40
Test name
Test status
Simulation time 1204120031 ps
CPU time 29.47 seconds
Started Feb 21 03:53:50 PM PST 24
Finished Feb 21 03:54:22 PM PST 24
Peak memory 246528 kb
Host smart-e5cfab19-9cde-446c-bdf4-f2fe60fa5a3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24201
57336 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sig_int_fail.2420157336
Directory /workspace/4.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/4.alert_handler_smoke.1655696444
Short name T553
Test name
Test status
Simulation time 50346479 ps
CPU time 3.64 seconds
Started Feb 21 03:53:49 PM PST 24
Finished Feb 21 03:53:55 PM PST 24
Peak memory 240028 kb
Host smart-6e58143b-2b1d-4748-bc90-50f803242e75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16556
96444 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_smoke.1655696444
Directory /workspace/4.alert_handler_smoke/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all.4228518436
Short name T651
Test name
Test status
Simulation time 32872407776 ps
CPU time 435.04 seconds
Started Feb 21 03:53:54 PM PST 24
Finished Feb 21 04:01:10 PM PST 24
Peak memory 256524 kb
Host smart-522022f6-dc8c-4750-ac9a-7550b5a92be3
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228518436 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_han
dler_stress_all.4228518436
Directory /workspace/4.alert_handler_stress_all/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all_with_rand_reset.506027679
Short name T267
Test name
Test status
Simulation time 58188835554 ps
CPU time 5613.74 seconds
Started Feb 21 03:53:52 PM PST 24
Finished Feb 21 05:27:28 PM PST 24
Peak memory 354284 kb
Host smart-212e2d59-29cb-43a2-b774-f08f17dc1b90
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506027679 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 4.alert_handler_stress_all_with_rand_reset.506027679
Directory /workspace/4.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.alert_handler_entropy.426212270
Short name T690
Test name
Test status
Simulation time 7359237918 ps
CPU time 626.5 seconds
Started Feb 21 03:57:05 PM PST 24
Finished Feb 21 04:07:32 PM PST 24
Peak memory 264732 kb
Host smart-bec3047a-edcc-4950-b733-fe345431a44e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426212270 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_entropy.426212270
Directory /workspace/40.alert_handler_entropy/latest

Test location /workspace/coverage/default/40.alert_handler_esc_alert_accum.1067460049
Short name T114
Test name
Test status
Simulation time 862320843 ps
CPU time 79.98 seconds
Started Feb 21 03:57:07 PM PST 24
Finished Feb 21 03:58:27 PM PST 24
Peak memory 248228 kb
Host smart-7e12c40b-15a5-4fd9-af64-a0b2e96864b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10674
60049 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_alert_accum.1067460049
Directory /workspace/40.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/40.alert_handler_esc_intr_timeout.1870160283
Short name T639
Test name
Test status
Simulation time 517443177 ps
CPU time 29.14 seconds
Started Feb 21 03:57:02 PM PST 24
Finished Feb 21 03:57:32 PM PST 24
Peak memory 253992 kb
Host smart-ec05c33d-53fe-4cfe-ad61-4727d0e2ada3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18701
60283 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_intr_timeout.1870160283
Directory /workspace/40.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_lpg.782484695
Short name T304
Test name
Test status
Simulation time 831502493682 ps
CPU time 2280.78 seconds
Started Feb 21 03:57:04 PM PST 24
Finished Feb 21 04:35:05 PM PST 24
Peak memory 288608 kb
Host smart-ded8e695-99b5-4c9c-9397-ce8f1de7c286
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782484695 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg.782484695
Directory /workspace/40.alert_handler_lpg/latest

Test location /workspace/coverage/default/40.alert_handler_lpg_stub_clk.954263135
Short name T678
Test name
Test status
Simulation time 47522129873 ps
CPU time 890.57 seconds
Started Feb 21 03:57:06 PM PST 24
Finished Feb 21 04:11:57 PM PST 24
Peak memory 265876 kb
Host smart-d5be6d1f-e70e-4a69-a856-20c0b37f9c57
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954263135 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg_stub_clk.954263135
Directory /workspace/40.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/40.alert_handler_ping_timeout.728217421
Short name T634
Test name
Test status
Simulation time 7421080400 ps
CPU time 283.19 seconds
Started Feb 21 03:57:13 PM PST 24
Finished Feb 21 04:01:56 PM PST 24
Peak memory 246216 kb
Host smart-7b3038ff-81d9-4881-ac32-5e3946df5246
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728217421 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_ping_timeout.728217421
Directory /workspace/40.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_random_alerts.2890005480
Short name T406
Test name
Test status
Simulation time 778730974 ps
CPU time 27.43 seconds
Started Feb 21 03:57:07 PM PST 24
Finished Feb 21 03:57:34 PM PST 24
Peak memory 248260 kb
Host smart-c06d15cf-4c4f-4765-9f04-0e243bc649b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28900
05480 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_alerts.2890005480
Directory /workspace/40.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/40.alert_handler_random_classes.994724704
Short name T479
Test name
Test status
Simulation time 932980994 ps
CPU time 19.54 seconds
Started Feb 21 03:57:04 PM PST 24
Finished Feb 21 03:57:24 PM PST 24
Peak memory 253788 kb
Host smart-4261dcfc-5ed6-4006-9c55-bd66d38a5fef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99472
4704 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_classes.994724704
Directory /workspace/40.alert_handler_random_classes/latest

Test location /workspace/coverage/default/40.alert_handler_sig_int_fail.441315232
Short name T65
Test name
Test status
Simulation time 567848347 ps
CPU time 20.27 seconds
Started Feb 21 03:57:05 PM PST 24
Finished Feb 21 03:57:25 PM PST 24
Peak memory 253716 kb
Host smart-920fd5a9-68ed-4e46-9024-fa105960efd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44131
5232 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_sig_int_fail.441315232
Directory /workspace/40.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/40.alert_handler_smoke.3586360653
Short name T184
Test name
Test status
Simulation time 1388065761 ps
CPU time 53.75 seconds
Started Feb 21 03:57:03 PM PST 24
Finished Feb 21 03:57:57 PM PST 24
Peak memory 254364 kb
Host smart-9b9101f1-2ea6-485d-9faa-bf26402633d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35863
60653 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_smoke.3586360653
Directory /workspace/40.alert_handler_smoke/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all.1164633442
Short name T638
Test name
Test status
Simulation time 26814446241 ps
CPU time 466.41 seconds
Started Feb 21 03:57:07 PM PST 24
Finished Feb 21 04:04:54 PM PST 24
Peak memory 264700 kb
Host smart-b2e1cdad-632d-431c-b437-4d87c85ad5a6
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164633442 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_ha
ndler_stress_all.1164633442
Directory /workspace/40.alert_handler_stress_all/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all_with_rand_reset.2933845019
Short name T42
Test name
Test status
Simulation time 91510022527 ps
CPU time 2778.91 seconds
Started Feb 21 03:57:12 PM PST 24
Finished Feb 21 04:43:31 PM PST 24
Peak memory 304220 kb
Host smart-9ab040ca-bc95-4492-b6c9-5880f7a9e873
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933845019 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 40.alert_handler_stress_all_with_rand_reset.2933845019
Directory /workspace/40.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.alert_handler_entropy.1594501696
Short name T16
Test name
Test status
Simulation time 77723757841 ps
CPU time 1094.15 seconds
Started Feb 21 03:57:15 PM PST 24
Finished Feb 21 04:15:29 PM PST 24
Peak memory 282144 kb
Host smart-2d8b824d-afe3-4937-ac96-124987597236
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594501696 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_entropy.1594501696
Directory /workspace/41.alert_handler_entropy/latest

Test location /workspace/coverage/default/41.alert_handler_esc_alert_accum.2769142197
Short name T403
Test name
Test status
Simulation time 5345453056 ps
CPU time 296.51 seconds
Started Feb 21 03:57:07 PM PST 24
Finished Feb 21 04:02:04 PM PST 24
Peak memory 250268 kb
Host smart-5cae4d34-bba7-4355-915a-eb2a626490b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27691
42197 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_alert_accum.2769142197
Directory /workspace/41.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/41.alert_handler_esc_intr_timeout.2912556228
Short name T453
Test name
Test status
Simulation time 882146415 ps
CPU time 26.45 seconds
Started Feb 21 03:57:07 PM PST 24
Finished Feb 21 03:57:34 PM PST 24
Peak memory 254496 kb
Host smart-b4feaebf-8c43-4b2a-a258-1d1bac3e09c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29125
56228 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_intr_timeout.2912556228
Directory /workspace/41.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_lpg_stub_clk.2333352628
Short name T113
Test name
Test status
Simulation time 71249032909 ps
CPU time 1305.22 seconds
Started Feb 21 03:57:13 PM PST 24
Finished Feb 21 04:18:58 PM PST 24
Peak memory 271892 kb
Host smart-1fea3960-9d0b-40ae-b0f4-0707e9a088ef
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333352628 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg_stub_clk.2333352628
Directory /workspace/41.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/41.alert_handler_ping_timeout.318038119
Short name T302
Test name
Test status
Simulation time 42437297944 ps
CPU time 486.3 seconds
Started Feb 21 03:57:15 PM PST 24
Finished Feb 21 04:05:21 PM PST 24
Peak memory 247144 kb
Host smart-7eefe0c9-05ed-47f4-a3a2-2476987afea8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318038119 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_ping_timeout.318038119
Directory /workspace/41.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_random_alerts.3216200125
Short name T684
Test name
Test status
Simulation time 7715543205 ps
CPU time 46.2 seconds
Started Feb 21 03:57:07 PM PST 24
Finished Feb 21 03:57:54 PM PST 24
Peak memory 248252 kb
Host smart-8a9f8721-7256-4545-a567-04dff0456e37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32162
00125 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_alerts.3216200125
Directory /workspace/41.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/41.alert_handler_random_classes.3674595212
Short name T632
Test name
Test status
Simulation time 2514959371 ps
CPU time 19.12 seconds
Started Feb 21 03:57:04 PM PST 24
Finished Feb 21 03:57:23 PM PST 24
Peak memory 252144 kb
Host smart-e37ddd9f-449a-4601-a549-96b8390a0994
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36745
95212 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_classes.3674595212
Directory /workspace/41.alert_handler_random_classes/latest

Test location /workspace/coverage/default/41.alert_handler_sig_int_fail.1032551934
Short name T49
Test name
Test status
Simulation time 489443156 ps
CPU time 31.31 seconds
Started Feb 21 03:57:12 PM PST 24
Finished Feb 21 03:57:43 PM PST 24
Peak memory 254604 kb
Host smart-051c3838-c258-47f3-80cb-728677ba9e38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10325
51934 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_sig_int_fail.1032551934
Directory /workspace/41.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/41.alert_handler_smoke.1619377742
Short name T579
Test name
Test status
Simulation time 133299045 ps
CPU time 13.6 seconds
Started Feb 21 03:57:13 PM PST 24
Finished Feb 21 03:57:26 PM PST 24
Peak memory 254024 kb
Host smart-d1974fbb-96b6-4f07-9ee3-e2f9ac0bffce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16193
77742 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_smoke.1619377742
Directory /workspace/41.alert_handler_smoke/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all.1191467759
Short name T254
Test name
Test status
Simulation time 25200200384 ps
CPU time 1556.58 seconds
Started Feb 21 03:57:12 PM PST 24
Finished Feb 21 04:23:09 PM PST 24
Peak memory 272728 kb
Host smart-bef29199-f486-44e4-b607-d9df4f79dbec
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191467759 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_ha
ndler_stress_all.1191467759
Directory /workspace/41.alert_handler_stress_all/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all_with_rand_reset.4037738885
Short name T670
Test name
Test status
Simulation time 70510882181 ps
CPU time 1690.78 seconds
Started Feb 21 03:57:11 PM PST 24
Finished Feb 21 04:25:22 PM PST 24
Peak memory 283572 kb
Host smart-dba8ad31-f083-4289-b145-e8fa5278d6e5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037738885 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 41.alert_handler_stress_all_with_rand_reset.4037738885
Directory /workspace/41.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.alert_handler_entropy.3121738550
Short name T597
Test name
Test status
Simulation time 8201510627 ps
CPU time 738.22 seconds
Started Feb 21 03:57:13 PM PST 24
Finished Feb 21 04:09:31 PM PST 24
Peak memory 272584 kb
Host smart-b07fb034-a79c-4f26-898e-4fdd9581488e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121738550 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_entropy.3121738550
Directory /workspace/42.alert_handler_entropy/latest

Test location /workspace/coverage/default/42.alert_handler_esc_alert_accum.842565054
Short name T185
Test name
Test status
Simulation time 2174688747 ps
CPU time 41.71 seconds
Started Feb 21 03:57:18 PM PST 24
Finished Feb 21 03:58:00 PM PST 24
Peak memory 254640 kb
Host smart-5d6c6165-278f-4fd6-b02c-f90185180418
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84256
5054 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_alert_accum.842565054
Directory /workspace/42.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/42.alert_handler_esc_intr_timeout.3064629431
Short name T22
Test name
Test status
Simulation time 857539166 ps
CPU time 18.61 seconds
Started Feb 21 03:57:14 PM PST 24
Finished Feb 21 03:57:33 PM PST 24
Peak memory 248264 kb
Host smart-cb4505e5-8d8e-46a5-83db-a259bccaaf7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30646
29431 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_intr_timeout.3064629431
Directory /workspace/42.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_lpg.238263195
Short name T323
Test name
Test status
Simulation time 213246633142 ps
CPU time 1686.55 seconds
Started Feb 21 03:57:13 PM PST 24
Finished Feb 21 04:25:20 PM PST 24
Peak memory 282224 kb
Host smart-0343c8ea-9f5d-46c1-97a0-b9ee35d31a1d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238263195 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg.238263195
Directory /workspace/42.alert_handler_lpg/latest

Test location /workspace/coverage/default/42.alert_handler_lpg_stub_clk.266286885
Short name T104
Test name
Test status
Simulation time 74675397269 ps
CPU time 1058.17 seconds
Started Feb 21 03:57:18 PM PST 24
Finished Feb 21 04:14:57 PM PST 24
Peak memory 271996 kb
Host smart-a393dbfb-c4a1-4353-ba3c-95b12452d9ce
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266286885 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg_stub_clk.266286885
Directory /workspace/42.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/42.alert_handler_ping_timeout.3196945635
Short name T689
Test name
Test status
Simulation time 11783850554 ps
CPU time 255.44 seconds
Started Feb 21 03:57:11 PM PST 24
Finished Feb 21 04:01:26 PM PST 24
Peak memory 247244 kb
Host smart-f89ef4fc-bf4e-4b27-a1a5-81ecd7601cb6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196945635 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_ping_timeout.3196945635
Directory /workspace/42.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_random_alerts.1396487918
Short name T706
Test name
Test status
Simulation time 844929086 ps
CPU time 54.02 seconds
Started Feb 21 03:57:13 PM PST 24
Finished Feb 21 03:58:08 PM PST 24
Peak memory 248272 kb
Host smart-3e9479f3-9a31-49f9-83d7-3144ca1adfe8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13964
87918 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_alerts.1396487918
Directory /workspace/42.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/42.alert_handler_random_classes.918995013
Short name T34
Test name
Test status
Simulation time 930772357 ps
CPU time 61.21 seconds
Started Feb 21 03:57:11 PM PST 24
Finished Feb 21 03:58:13 PM PST 24
Peak memory 253156 kb
Host smart-10ea2cbb-3b7c-424e-86b8-5650316f1a60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91899
5013 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_classes.918995013
Directory /workspace/42.alert_handler_random_classes/latest

Test location /workspace/coverage/default/42.alert_handler_sig_int_fail.4039113485
Short name T238
Test name
Test status
Simulation time 1185012966 ps
CPU time 42.48 seconds
Started Feb 21 03:57:12 PM PST 24
Finished Feb 21 03:57:55 PM PST 24
Peak memory 247812 kb
Host smart-2546d6e6-c27b-4865-8752-34e8cca44172
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40391
13485 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_sig_int_fail.4039113485
Directory /workspace/42.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/42.alert_handler_smoke.2634632999
Short name T480
Test name
Test status
Simulation time 862958271 ps
CPU time 25.32 seconds
Started Feb 21 03:57:13 PM PST 24
Finished Feb 21 03:57:39 PM PST 24
Peak memory 248280 kb
Host smart-2acd37ce-23e4-4a55-9ff4-09d4eacd3ae1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26346
32999 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_smoke.2634632999
Directory /workspace/42.alert_handler_smoke/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all.4161549652
Short name T709
Test name
Test status
Simulation time 13172729524 ps
CPU time 1130.77 seconds
Started Feb 21 03:57:17 PM PST 24
Finished Feb 21 04:16:08 PM PST 24
Peak memory 288964 kb
Host smart-2d79eecb-23ad-4164-bbe9-ecae01500967
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161549652 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_ha
ndler_stress_all.4161549652
Directory /workspace/42.alert_handler_stress_all/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all_with_rand_reset.2644528266
Short name T272
Test name
Test status
Simulation time 34612317801 ps
CPU time 697.99 seconds
Started Feb 21 03:57:23 PM PST 24
Finished Feb 21 04:09:01 PM PST 24
Peak memory 270548 kb
Host smart-3636370c-9412-4f0d-b797-29e594f1b428
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644528266 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 42.alert_handler_stress_all_with_rand_reset.2644528266
Directory /workspace/42.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.alert_handler_entropy.2237863295
Short name T585
Test name
Test status
Simulation time 14679826975 ps
CPU time 1059.8 seconds
Started Feb 21 03:57:19 PM PST 24
Finished Feb 21 04:14:59 PM PST 24
Peak memory 281084 kb
Host smart-3e512029-4fbb-4f27-9ed7-fb07aeae5dc9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2237863295 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_entropy.2237863295
Directory /workspace/43.alert_handler_entropy/latest

Test location /workspace/coverage/default/43.alert_handler_esc_alert_accum.2993723241
Short name T367
Test name
Test status
Simulation time 856574769 ps
CPU time 28.51 seconds
Started Feb 21 03:57:17 PM PST 24
Finished Feb 21 03:57:46 PM PST 24
Peak memory 255100 kb
Host smart-f2918658-fe86-44ea-a86a-b9794e3981dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29937
23241 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_alert_accum.2993723241
Directory /workspace/43.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/43.alert_handler_esc_intr_timeout.2286937572
Short name T21
Test name
Test status
Simulation time 464192789 ps
CPU time 10.04 seconds
Started Feb 21 03:57:19 PM PST 24
Finished Feb 21 03:57:29 PM PST 24
Peak memory 254036 kb
Host smart-de611608-cc5a-4d61-9e2c-dfaaaec68f9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22869
37572 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_intr_timeout.2286937572
Directory /workspace/43.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_lpg.4238341062
Short name T335
Test name
Test status
Simulation time 86528933232 ps
CPU time 1537.03 seconds
Started Feb 21 03:57:19 PM PST 24
Finished Feb 21 04:22:56 PM PST 24
Peak memory 288648 kb
Host smart-49bcde59-f464-4be7-8636-71d00bdf3d5d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238341062 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg.4238341062
Directory /workspace/43.alert_handler_lpg/latest

Test location /workspace/coverage/default/43.alert_handler_lpg_stub_clk.3051890574
Short name T663
Test name
Test status
Simulation time 54525448687 ps
CPU time 3065.42 seconds
Started Feb 21 03:57:20 PM PST 24
Finished Feb 21 04:48:26 PM PST 24
Peak memory 288684 kb
Host smart-d66023f2-1262-4669-92be-6492ce4b182d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051890574 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg_stub_clk.3051890574
Directory /workspace/43.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/43.alert_handler_ping_timeout.3356095995
Short name T301
Test name
Test status
Simulation time 46494266560 ps
CPU time 487.14 seconds
Started Feb 21 03:57:18 PM PST 24
Finished Feb 21 04:05:25 PM PST 24
Peak memory 247212 kb
Host smart-95b9b962-951d-4af1-af94-22ce46f9c37b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3356095995 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_ping_timeout.3356095995
Directory /workspace/43.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_random_alerts.4018754677
Short name T56
Test name
Test status
Simulation time 154204629 ps
CPU time 10.63 seconds
Started Feb 21 03:57:19 PM PST 24
Finished Feb 21 03:57:30 PM PST 24
Peak memory 253448 kb
Host smart-3bd569ce-2219-488c-a83d-c271dbdd918a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40187
54677 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_alerts.4018754677
Directory /workspace/43.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/43.alert_handler_random_classes.2100466499
Short name T263
Test name
Test status
Simulation time 2549526929 ps
CPU time 28.4 seconds
Started Feb 21 03:57:18 PM PST 24
Finished Feb 21 03:57:47 PM PST 24
Peak memory 253952 kb
Host smart-e937ad20-711c-4b4a-8a9d-0f84f92ccb03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21004
66499 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_classes.2100466499
Directory /workspace/43.alert_handler_random_classes/latest

Test location /workspace/coverage/default/43.alert_handler_sig_int_fail.2042332123
Short name T559
Test name
Test status
Simulation time 90152005 ps
CPU time 12.09 seconds
Started Feb 21 03:57:20 PM PST 24
Finished Feb 21 03:57:32 PM PST 24
Peak memory 252700 kb
Host smart-0d37ca56-6d59-4962-b153-5ce557014f1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20423
32123 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_sig_int_fail.2042332123
Directory /workspace/43.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/43.alert_handler_smoke.4039459381
Short name T622
Test name
Test status
Simulation time 790429080 ps
CPU time 24.5 seconds
Started Feb 21 03:57:20 PM PST 24
Finished Feb 21 03:57:45 PM PST 24
Peak memory 248192 kb
Host smart-efaa7cf0-6474-414d-96e8-95c74b147669
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40394
59381 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_smoke.4039459381
Directory /workspace/43.alert_handler_smoke/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all_with_rand_reset.3481407689
Short name T493
Test name
Test status
Simulation time 236169156694 ps
CPU time 5513.5 seconds
Started Feb 21 03:57:23 PM PST 24
Finished Feb 21 05:29:17 PM PST 24
Peak memory 354644 kb
Host smart-5995ef7a-53be-40da-8a0d-7e3987342ae9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481407689 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 43.alert_handler_stress_all_with_rand_reset.3481407689
Directory /workspace/43.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.alert_handler_entropy.91302927
Short name T258
Test name
Test status
Simulation time 66155465885 ps
CPU time 571.9 seconds
Started Feb 21 03:57:45 PM PST 24
Finished Feb 21 04:07:18 PM PST 24
Peak memory 271964 kb
Host smart-e3065116-d369-40e3-9110-da26058761b9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91302927 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_entropy.91302927
Directory /workspace/44.alert_handler_entropy/latest

Test location /workspace/coverage/default/44.alert_handler_esc_alert_accum.152077022
Short name T428
Test name
Test status
Simulation time 21546938870 ps
CPU time 271.65 seconds
Started Feb 21 03:57:44 PM PST 24
Finished Feb 21 04:02:17 PM PST 24
Peak memory 255532 kb
Host smart-3d3aae63-6ef2-4d96-8331-6fe8acbb5e3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15207
7022 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_alert_accum.152077022
Directory /workspace/44.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/44.alert_handler_esc_intr_timeout.1344721354
Short name T467
Test name
Test status
Simulation time 368765217 ps
CPU time 16.46 seconds
Started Feb 21 03:57:23 PM PST 24
Finished Feb 21 03:57:40 PM PST 24
Peak memory 248264 kb
Host smart-086340cf-5455-4ff8-b151-ee80dd8e8ae8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13447
21354 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_intr_timeout.1344721354
Directory /workspace/44.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_lpg.1914321511
Short name T633
Test name
Test status
Simulation time 893160272163 ps
CPU time 2554.16 seconds
Started Feb 21 03:57:44 PM PST 24
Finished Feb 21 04:40:19 PM PST 24
Peak memory 288748 kb
Host smart-7efcd48b-4b94-4cee-832b-ab452d5ceb7d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914321511 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg.1914321511
Directory /workspace/44.alert_handler_lpg/latest

Test location /workspace/coverage/default/44.alert_handler_lpg_stub_clk.2952769625
Short name T531
Test name
Test status
Simulation time 138672491976 ps
CPU time 1933.07 seconds
Started Feb 21 03:57:44 PM PST 24
Finished Feb 21 04:29:58 PM PST 24
Peak memory 272372 kb
Host smart-8bfc7398-a5a8-4a2b-8a06-e44486cc901c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952769625 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg_stub_clk.2952769625
Directory /workspace/44.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/44.alert_handler_ping_timeout.198135443
Short name T309
Test name
Test status
Simulation time 6845150625 ps
CPU time 275.06 seconds
Started Feb 21 03:57:48 PM PST 24
Finished Feb 21 04:02:26 PM PST 24
Peak memory 248328 kb
Host smart-88687957-b456-43ad-8159-9b70be6f96a8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198135443 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_ping_timeout.198135443
Directory /workspace/44.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_random_alerts.3884164131
Short name T682
Test name
Test status
Simulation time 446326682 ps
CPU time 28.5 seconds
Started Feb 21 03:57:19 PM PST 24
Finished Feb 21 03:57:47 PM PST 24
Peak memory 248260 kb
Host smart-8e591b9b-7be2-49da-8249-db19f7f34662
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38841
64131 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_alerts.3884164131
Directory /workspace/44.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/44.alert_handler_random_classes.1465260356
Short name T528
Test name
Test status
Simulation time 539473984 ps
CPU time 31.8 seconds
Started Feb 21 03:57:33 PM PST 24
Finished Feb 21 03:58:05 PM PST 24
Peak memory 254616 kb
Host smart-530a8771-d305-49c3-b5ae-7ee6738eeca4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14652
60356 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_classes.1465260356
Directory /workspace/44.alert_handler_random_classes/latest

Test location /workspace/coverage/default/44.alert_handler_sig_int_fail.2090123115
Short name T475
Test name
Test status
Simulation time 4688360396 ps
CPU time 51.38 seconds
Started Feb 21 03:57:43 PM PST 24
Finished Feb 21 03:58:35 PM PST 24
Peak memory 246532 kb
Host smart-238edd55-54e8-4046-978e-fdd7e485a900
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20901
23115 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_sig_int_fail.2090123115
Directory /workspace/44.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/44.alert_handler_smoke.2180951275
Short name T362
Test name
Test status
Simulation time 624534349 ps
CPU time 13.29 seconds
Started Feb 21 03:57:21 PM PST 24
Finished Feb 21 03:57:34 PM PST 24
Peak memory 248240 kb
Host smart-dec8f70a-b470-410b-aac0-42b1d38c6368
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21809
51275 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_smoke.2180951275
Directory /workspace/44.alert_handler_smoke/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all.2276305435
Short name T460
Test name
Test status
Simulation time 2838728085 ps
CPU time 155.71 seconds
Started Feb 21 03:57:49 PM PST 24
Finished Feb 21 04:00:26 PM PST 24
Peak memory 254860 kb
Host smart-afb0e0f9-1bcd-43d4-8a7b-8f406e54984a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276305435 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_ha
ndler_stress_all.2276305435
Directory /workspace/44.alert_handler_stress_all/latest

Test location /workspace/coverage/default/45.alert_handler_entropy.1178075933
Short name T605
Test name
Test status
Simulation time 75213042785 ps
CPU time 1498.18 seconds
Started Feb 21 03:57:46 PM PST 24
Finished Feb 21 04:22:44 PM PST 24
Peak memory 289296 kb
Host smart-f0380eba-ef23-4743-9070-14cf98e9186f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178075933 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_entropy.1178075933
Directory /workspace/45.alert_handler_entropy/latest

Test location /workspace/coverage/default/45.alert_handler_esc_alert_accum.3266017126
Short name T695
Test name
Test status
Simulation time 15127893021 ps
CPU time 142.75 seconds
Started Feb 21 03:57:49 PM PST 24
Finished Feb 21 04:00:13 PM PST 24
Peak memory 256496 kb
Host smart-d02f7f5d-b330-4090-9d50-e65ba70b6a17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32660
17126 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_alert_accum.3266017126
Directory /workspace/45.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/45.alert_handler_esc_intr_timeout.3446150666
Short name T483
Test name
Test status
Simulation time 734025769 ps
CPU time 55.28 seconds
Started Feb 21 03:57:50 PM PST 24
Finished Feb 21 03:58:46 PM PST 24
Peak memory 254744 kb
Host smart-e783b9be-92cb-4dd2-a7b4-356838c3a3ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34461
50666 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_intr_timeout.3446150666
Directory /workspace/45.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_lpg.1767192025
Short name T333
Test name
Test status
Simulation time 84303279380 ps
CPU time 2531.69 seconds
Started Feb 21 03:57:48 PM PST 24
Finished Feb 21 04:40:02 PM PST 24
Peak memory 288776 kb
Host smart-8607abf6-135c-4215-b226-e89f4a7cae38
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767192025 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg.1767192025
Directory /workspace/45.alert_handler_lpg/latest

Test location /workspace/coverage/default/45.alert_handler_lpg_stub_clk.4105159231
Short name T402
Test name
Test status
Simulation time 68167328103 ps
CPU time 1111.35 seconds
Started Feb 21 03:57:47 PM PST 24
Finished Feb 21 04:16:19 PM PST 24
Peak memory 272524 kb
Host smart-02c21b3b-4fa9-4f5b-b449-80f292ef2e69
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105159231 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg_stub_clk.4105159231
Directory /workspace/45.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/45.alert_handler_ping_timeout.4194091444
Short name T291
Test name
Test status
Simulation time 52813191809 ps
CPU time 557.42 seconds
Started Feb 21 03:57:58 PM PST 24
Finished Feb 21 04:07:17 PM PST 24
Peak memory 246996 kb
Host smart-0a5147de-24d4-4066-a32d-a90d95a82f59
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4194091444 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_ping_timeout.4194091444
Directory /workspace/45.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_random_alerts.2397586361
Short name T501
Test name
Test status
Simulation time 1575788073 ps
CPU time 42.53 seconds
Started Feb 21 03:57:47 PM PST 24
Finished Feb 21 03:58:31 PM PST 24
Peak memory 248232 kb
Host smart-b1b36706-6342-4e66-914e-14078c5cea16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23975
86361 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_alerts.2397586361
Directory /workspace/45.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/45.alert_handler_random_classes.3622715924
Short name T691
Test name
Test status
Simulation time 748376954 ps
CPU time 22.67 seconds
Started Feb 21 03:57:44 PM PST 24
Finished Feb 21 03:58:08 PM PST 24
Peak memory 253864 kb
Host smart-5844d8b3-e29b-438b-8ce0-dd33ed62ef8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36227
15924 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_classes.3622715924
Directory /workspace/45.alert_handler_random_classes/latest

Test location /workspace/coverage/default/45.alert_handler_sig_int_fail.1925804123
Short name T86
Test name
Test status
Simulation time 186531085 ps
CPU time 14.21 seconds
Started Feb 21 03:57:48 PM PST 24
Finished Feb 21 03:58:04 PM PST 24
Peak memory 252172 kb
Host smart-918d39f5-002c-490b-8cfd-45eb59896162
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19258
04123 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_sig_int_fail.1925804123
Directory /workspace/45.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/45.alert_handler_smoke.3302798817
Short name T410
Test name
Test status
Simulation time 7937074059 ps
CPU time 64.65 seconds
Started Feb 21 03:57:34 PM PST 24
Finished Feb 21 03:58:39 PM PST 24
Peak memory 256436 kb
Host smart-8663f666-2649-4b5f-ba73-b36262428cb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33027
98817 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_smoke.3302798817
Directory /workspace/45.alert_handler_smoke/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all.1017791443
Short name T36
Test name
Test status
Simulation time 299974144 ps
CPU time 25.86 seconds
Started Feb 21 03:58:00 PM PST 24
Finished Feb 21 03:58:28 PM PST 24
Peak memory 252424 kb
Host smart-219a7315-d057-4c03-8b0c-23a86bca88c8
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017791443 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_ha
ndler_stress_all.1017791443
Directory /workspace/45.alert_handler_stress_all/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all_with_rand_reset.2707043668
Short name T57
Test name
Test status
Simulation time 50267631024 ps
CPU time 3969.68 seconds
Started Feb 21 03:57:49 PM PST 24
Finished Feb 21 05:04:01 PM PST 24
Peak memory 322176 kb
Host smart-3d69b556-3749-4022-961a-5c4e97ac02ec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707043668 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 45.alert_handler_stress_all_with_rand_reset.2707043668
Directory /workspace/45.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.alert_handler_entropy.1448279349
Short name T523
Test name
Test status
Simulation time 170295545537 ps
CPU time 2334.51 seconds
Started Feb 21 03:57:48 PM PST 24
Finished Feb 21 04:36:45 PM PST 24
Peak memory 288876 kb
Host smart-eefad9c9-c578-4ee8-bb36-b79a6f243ec3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448279349 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_entropy.1448279349
Directory /workspace/46.alert_handler_entropy/latest

Test location /workspace/coverage/default/46.alert_handler_esc_alert_accum.2065687393
Short name T508
Test name
Test status
Simulation time 2272698874 ps
CPU time 144.64 seconds
Started Feb 21 03:57:46 PM PST 24
Finished Feb 21 04:00:11 PM PST 24
Peak memory 255752 kb
Host smart-74e47a66-ace1-45ae-b550-1b91b70072cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20656
87393 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_alert_accum.2065687393
Directory /workspace/46.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/46.alert_handler_esc_intr_timeout.1888077134
Short name T503
Test name
Test status
Simulation time 60530096 ps
CPU time 4.98 seconds
Started Feb 21 03:57:48 PM PST 24
Finished Feb 21 03:57:54 PM PST 24
Peak memory 238408 kb
Host smart-aa243381-b671-4d42-b64d-1c8619b845f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18880
77134 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_intr_timeout.1888077134
Directory /workspace/46.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_lpg.2617891719
Short name T287
Test name
Test status
Simulation time 16925083116 ps
CPU time 626.69 seconds
Started Feb 21 03:57:50 PM PST 24
Finished Feb 21 04:08:17 PM PST 24
Peak memory 270640 kb
Host smart-214c387b-f479-416e-a36f-91c7fb9205db
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2617891719 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg.2617891719
Directory /workspace/46.alert_handler_lpg/latest

Test location /workspace/coverage/default/46.alert_handler_lpg_stub_clk.2098955266
Short name T37
Test name
Test status
Simulation time 317902161854 ps
CPU time 1537.84 seconds
Started Feb 21 03:57:50 PM PST 24
Finished Feb 21 04:23:29 PM PST 24
Peak memory 271880 kb
Host smart-2c1b77e8-abc7-4b98-9a4b-10905b9bca22
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098955266 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg_stub_clk.2098955266
Directory /workspace/46.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/46.alert_handler_ping_timeout.1406889485
Short name T307
Test name
Test status
Simulation time 5186239061 ps
CPU time 215.27 seconds
Started Feb 21 03:57:48 PM PST 24
Finished Feb 21 04:01:26 PM PST 24
Peak memory 246944 kb
Host smart-f7fa88ea-2760-4b5f-9a64-8951c24ee61f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406889485 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_ping_timeout.1406889485
Directory /workspace/46.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_random_alerts.4010854121
Short name T393
Test name
Test status
Simulation time 1298134466 ps
CPU time 7.18 seconds
Started Feb 21 03:57:48 PM PST 24
Finished Feb 21 03:57:58 PM PST 24
Peak memory 248268 kb
Host smart-9ceaae21-a869-4f58-bd27-f94e3c9c80e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40108
54121 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_alerts.4010854121
Directory /workspace/46.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/46.alert_handler_random_classes.3642697678
Short name T438
Test name
Test status
Simulation time 48720894 ps
CPU time 5.74 seconds
Started Feb 21 03:57:46 PM PST 24
Finished Feb 21 03:57:52 PM PST 24
Peak memory 248844 kb
Host smart-3c345c15-8156-4a5b-8276-c79cf1182661
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36426
97678 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_classes.3642697678
Directory /workspace/46.alert_handler_random_classes/latest

Test location /workspace/coverage/default/46.alert_handler_sig_int_fail.1180512918
Short name T621
Test name
Test status
Simulation time 74327438 ps
CPU time 5.86 seconds
Started Feb 21 03:57:59 PM PST 24
Finished Feb 21 03:58:05 PM PST 24
Peak memory 250816 kb
Host smart-3b7c898e-739a-46b8-82f3-4b46b7962096
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11805
12918 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_sig_int_fail.1180512918
Directory /workspace/46.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/46.alert_handler_smoke.843373178
Short name T498
Test name
Test status
Simulation time 533341804 ps
CPU time 12.54 seconds
Started Feb 21 03:57:48 PM PST 24
Finished Feb 21 03:58:03 PM PST 24
Peak memory 248380 kb
Host smart-d622ec64-fc09-4592-9cfc-338abf7fc8a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84337
3178 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_smoke.843373178
Directory /workspace/46.alert_handler_smoke/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all.4135007521
Short name T227
Test name
Test status
Simulation time 10001821801 ps
CPU time 272.76 seconds
Started Feb 21 03:57:48 PM PST 24
Finished Feb 21 04:02:23 PM PST 24
Peak memory 250476 kb
Host smart-b7d5e19a-21f5-407d-97ea-4592dc3fae8b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135007521 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_ha
ndler_stress_all.4135007521
Directory /workspace/46.alert_handler_stress_all/latest

Test location /workspace/coverage/default/47.alert_handler_entropy.3655959300
Short name T385
Test name
Test status
Simulation time 626912344305 ps
CPU time 1664.99 seconds
Started Feb 21 03:57:48 PM PST 24
Finished Feb 21 04:25:34 PM PST 24
Peak memory 272864 kb
Host smart-038133d2-a99e-492a-9806-4fa1ff088bd8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655959300 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_entropy.3655959300
Directory /workspace/47.alert_handler_entropy/latest

Test location /workspace/coverage/default/47.alert_handler_esc_alert_accum.1703632650
Short name T600
Test name
Test status
Simulation time 8117654405 ps
CPU time 97.14 seconds
Started Feb 21 03:57:46 PM PST 24
Finished Feb 21 03:59:24 PM PST 24
Peak memory 255740 kb
Host smart-4ba8ab5d-5c7d-4e1e-b734-85f5ec3aa918
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17036
32650 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_alert_accum.1703632650
Directory /workspace/47.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/47.alert_handler_esc_intr_timeout.3070466741
Short name T368
Test name
Test status
Simulation time 1096486237 ps
CPU time 20.48 seconds
Started Feb 21 03:57:49 PM PST 24
Finished Feb 21 03:58:11 PM PST 24
Peak memory 253336 kb
Host smart-dedd3729-20b1-42d8-928d-04c2a4be7d35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30704
66741 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_intr_timeout.3070466741
Directory /workspace/47.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_lpg.708708053
Short name T338
Test name
Test status
Simulation time 415235576144 ps
CPU time 3144.89 seconds
Started Feb 21 03:57:48 PM PST 24
Finished Feb 21 04:50:15 PM PST 24
Peak memory 288752 kb
Host smart-df1fda43-af40-4bc3-b568-3a743acc4c23
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=708708053 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg.708708053
Directory /workspace/47.alert_handler_lpg/latest

Test location /workspace/coverage/default/47.alert_handler_lpg_stub_clk.2762020366
Short name T447
Test name
Test status
Simulation time 22702364841 ps
CPU time 759.07 seconds
Started Feb 21 03:57:59 PM PST 24
Finished Feb 21 04:10:39 PM PST 24
Peak memory 272868 kb
Host smart-00ef419f-5c74-4e14-beb7-3baf3fee1ad7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762020366 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg_stub_clk.2762020366
Directory /workspace/47.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/47.alert_handler_ping_timeout.4208116476
Short name T102
Test name
Test status
Simulation time 21553246177 ps
CPU time 238.77 seconds
Started Feb 21 03:57:46 PM PST 24
Finished Feb 21 04:01:47 PM PST 24
Peak memory 247204 kb
Host smart-ec184440-fb2d-4538-93fa-06eaedb3feb4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208116476 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_ping_timeout.4208116476
Directory /workspace/47.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_random_alerts.1651623782
Short name T371
Test name
Test status
Simulation time 2673232009 ps
CPU time 31.74 seconds
Started Feb 21 03:57:47 PM PST 24
Finished Feb 21 03:58:21 PM PST 24
Peak memory 256476 kb
Host smart-51296b26-9442-4b13-9e6a-a00e45ff1001
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16516
23782 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_alerts.1651623782
Directory /workspace/47.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/47.alert_handler_random_classes.286878521
Short name T529
Test name
Test status
Simulation time 111495603 ps
CPU time 11.65 seconds
Started Feb 21 03:57:45 PM PST 24
Finished Feb 21 03:57:57 PM PST 24
Peak memory 246552 kb
Host smart-ae98454c-696d-459a-b9c5-00686b35c84c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28687
8521 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_classes.286878521
Directory /workspace/47.alert_handler_random_classes/latest

Test location /workspace/coverage/default/47.alert_handler_sig_int_fail.2094622766
Short name T637
Test name
Test status
Simulation time 3007013277 ps
CPU time 51.89 seconds
Started Feb 21 03:57:47 PM PST 24
Finished Feb 21 03:58:40 PM PST 24
Peak memory 248360 kb
Host smart-8d4ec77d-e9f8-4b51-8b78-ede57b7d9609
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20946
22766 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_sig_int_fail.2094622766
Directory /workspace/47.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/47.alert_handler_smoke.3455492778
Short name T45
Test name
Test status
Simulation time 1110913823 ps
CPU time 16.01 seconds
Started Feb 21 03:57:47 PM PST 24
Finished Feb 21 03:58:04 PM PST 24
Peak memory 252064 kb
Host smart-7c5d42b4-4bb8-4928-80aa-22bf6d6706e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34554
92778 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_smoke.3455492778
Directory /workspace/47.alert_handler_smoke/latest

Test location /workspace/coverage/default/48.alert_handler_entropy.90502299
Short name T522
Test name
Test status
Simulation time 106595582880 ps
CPU time 1494.98 seconds
Started Feb 21 03:58:13 PM PST 24
Finished Feb 21 04:23:09 PM PST 24
Peak memory 272672 kb
Host smart-9a7781dd-1191-44fe-a608-b7332ea98fbd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90502299 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_entropy.90502299
Directory /workspace/48.alert_handler_entropy/latest

Test location /workspace/coverage/default/48.alert_handler_esc_alert_accum.3703858795
Short name T484
Test name
Test status
Simulation time 343966099 ps
CPU time 28.21 seconds
Started Feb 21 03:58:02 PM PST 24
Finished Feb 21 03:58:32 PM PST 24
Peak memory 254900 kb
Host smart-aee04822-540f-4cc6-a86f-ac3c7e12cf3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37038
58795 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_alert_accum.3703858795
Directory /workspace/48.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/48.alert_handler_esc_intr_timeout.170380877
Short name T365
Test name
Test status
Simulation time 378846675 ps
CPU time 26.02 seconds
Started Feb 21 03:58:14 PM PST 24
Finished Feb 21 03:58:41 PM PST 24
Peak memory 254640 kb
Host smart-7ef6a2f0-fa6d-45a7-8f12-c936454f6f04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17038
0877 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_intr_timeout.170380877
Directory /workspace/48.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_lpg.4113861485
Short name T336
Test name
Test status
Simulation time 25922334115 ps
CPU time 1540.95 seconds
Started Feb 21 03:58:02 PM PST 24
Finished Feb 21 04:23:44 PM PST 24
Peak memory 264716 kb
Host smart-82f585a2-0daa-43f6-a1db-22b69c04adc0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113861485 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg.4113861485
Directory /workspace/48.alert_handler_lpg/latest

Test location /workspace/coverage/default/48.alert_handler_lpg_stub_clk.4252346836
Short name T421
Test name
Test status
Simulation time 25213751190 ps
CPU time 1502.73 seconds
Started Feb 21 03:58:03 PM PST 24
Finished Feb 21 04:23:07 PM PST 24
Peak memory 272828 kb
Host smart-295630cc-d8ba-4393-9996-aaf75aedc341
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252346836 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg_stub_clk.4252346836
Directory /workspace/48.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/48.alert_handler_ping_timeout.1258603125
Short name T590
Test name
Test status
Simulation time 9274787458 ps
CPU time 398.87 seconds
Started Feb 21 03:58:03 PM PST 24
Finished Feb 21 04:04:44 PM PST 24
Peak memory 247116 kb
Host smart-a237ed78-2f3a-4ab4-a564-fef3fc0b673a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258603125 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_ping_timeout.1258603125
Directory /workspace/48.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_random_alerts.1715623343
Short name T686
Test name
Test status
Simulation time 4967926527 ps
CPU time 32.44 seconds
Started Feb 21 03:58:02 PM PST 24
Finished Feb 21 03:58:36 PM PST 24
Peak memory 255172 kb
Host smart-a52f7b8c-f076-481b-a2bf-5264c5f051b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17156
23343 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_alerts.1715623343
Directory /workspace/48.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/48.alert_handler_random_classes.3262649226
Short name T408
Test name
Test status
Simulation time 783884051 ps
CPU time 48.57 seconds
Started Feb 21 03:58:02 PM PST 24
Finished Feb 21 03:58:52 PM PST 24
Peak memory 254620 kb
Host smart-3570f654-b915-46c4-8f06-30a21c247d57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32626
49226 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_classes.3262649226
Directory /workspace/48.alert_handler_random_classes/latest

Test location /workspace/coverage/default/48.alert_handler_sig_int_fail.1120654077
Short name T582
Test name
Test status
Simulation time 200205383 ps
CPU time 21.69 seconds
Started Feb 21 03:58:01 PM PST 24
Finished Feb 21 03:58:24 PM PST 24
Peak memory 255584 kb
Host smart-f3f13ccd-7c92-4608-bc23-da8ff4568913
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11206
54077 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_sig_int_fail.1120654077
Directory /workspace/48.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/48.alert_handler_smoke.780966178
Short name T561
Test name
Test status
Simulation time 450617268 ps
CPU time 27.36 seconds
Started Feb 21 03:57:44 PM PST 24
Finished Feb 21 03:58:12 PM PST 24
Peak memory 248240 kb
Host smart-e30fd8a0-7354-42f5-ad37-7dcbb1722c5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78096
6178 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_smoke.780966178
Directory /workspace/48.alert_handler_smoke/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all.3561503863
Short name T704
Test name
Test status
Simulation time 1982747402 ps
CPU time 177.09 seconds
Started Feb 21 03:58:04 PM PST 24
Finished Feb 21 04:01:02 PM PST 24
Peak memory 256472 kb
Host smart-92f0c246-1fcf-4057-984e-b5188b4a0b09
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561503863 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_ha
ndler_stress_all.3561503863
Directory /workspace/48.alert_handler_stress_all/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all_with_rand_reset.844183577
Short name T519
Test name
Test status
Simulation time 258169826863 ps
CPU time 6458.27 seconds
Started Feb 21 03:58:01 PM PST 24
Finished Feb 21 05:45:42 PM PST 24
Peak memory 403668 kb
Host smart-c72ae543-de7a-422d-a17a-d4ca28458639
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844183577 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 48.alert_handler_stress_all_with_rand_reset.844183577
Directory /workspace/48.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.alert_handler_entropy.2913279493
Short name T63
Test name
Test status
Simulation time 31858289476 ps
CPU time 2031.28 seconds
Started Feb 21 03:58:01 PM PST 24
Finished Feb 21 04:31:54 PM PST 24
Peak memory 283612 kb
Host smart-8c32daac-e366-450f-8acd-ff334f3f7fae
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2913279493 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_entropy.2913279493
Directory /workspace/49.alert_handler_entropy/latest

Test location /workspace/coverage/default/49.alert_handler_esc_alert_accum.3412811267
Short name T370
Test name
Test status
Simulation time 390765379 ps
CPU time 41.18 seconds
Started Feb 21 03:58:01 PM PST 24
Finished Feb 21 03:58:43 PM PST 24
Peak memory 247800 kb
Host smart-6ba38521-6ae9-4806-8837-9619f2e60dda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34128
11267 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_alert_accum.3412811267
Directory /workspace/49.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/49.alert_handler_esc_intr_timeout.3879765357
Short name T612
Test name
Test status
Simulation time 462587133 ps
CPU time 12.12 seconds
Started Feb 21 03:58:02 PM PST 24
Finished Feb 21 03:58:15 PM PST 24
Peak memory 250864 kb
Host smart-f87c5b98-f15e-4338-8da6-e7897b0cb785
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38797
65357 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_intr_timeout.3879765357
Directory /workspace/49.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_lpg.1609224170
Short name T332
Test name
Test status
Simulation time 168131008173 ps
CPU time 2320.43 seconds
Started Feb 21 03:58:13 PM PST 24
Finished Feb 21 04:36:55 PM PST 24
Peak memory 288672 kb
Host smart-dbf8ca41-ef8f-4e66-9a3a-7544711827c0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609224170 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg.1609224170
Directory /workspace/49.alert_handler_lpg/latest

Test location /workspace/coverage/default/49.alert_handler_lpg_stub_clk.1174657090
Short name T541
Test name
Test status
Simulation time 153793683835 ps
CPU time 2316.71 seconds
Started Feb 21 03:58:13 PM PST 24
Finished Feb 21 04:36:50 PM PST 24
Peak memory 289056 kb
Host smart-a7714309-f964-4d95-a3ef-fb219c1d38c7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174657090 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg_stub_clk.1174657090
Directory /workspace/49.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/49.alert_handler_ping_timeout.2886740785
Short name T658
Test name
Test status
Simulation time 2187766493 ps
CPU time 91.93 seconds
Started Feb 21 03:58:14 PM PST 24
Finished Feb 21 03:59:46 PM PST 24
Peak memory 254444 kb
Host smart-e28c04e1-742b-4f69-acc3-a0b77aa476a8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886740785 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_ping_timeout.2886740785
Directory /workspace/49.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_random_alerts.3962862094
Short name T54
Test name
Test status
Simulation time 803286204 ps
CPU time 38.5 seconds
Started Feb 21 03:58:01 PM PST 24
Finished Feb 21 03:58:40 PM PST 24
Peak memory 248468 kb
Host smart-ebccb7ea-f1c7-48fb-8461-bf82c3457d5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39628
62094 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_alerts.3962862094
Directory /workspace/49.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/49.alert_handler_random_classes.547012878
Short name T118
Test name
Test status
Simulation time 47220573 ps
CPU time 4.39 seconds
Started Feb 21 03:58:11 PM PST 24
Finished Feb 21 03:58:15 PM PST 24
Peak memory 248932 kb
Host smart-0918d02e-2d5a-45d1-8f71-2b3a5966ec59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54701
2878 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_classes.547012878
Directory /workspace/49.alert_handler_random_classes/latest

Test location /workspace/coverage/default/49.alert_handler_smoke.130846024
Short name T644
Test name
Test status
Simulation time 1087948212 ps
CPU time 17.67 seconds
Started Feb 21 03:58:03 PM PST 24
Finished Feb 21 03:58:22 PM PST 24
Peak memory 254876 kb
Host smart-5f413a1d-6a78-427e-802f-13d6d2257e55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13084
6024 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_smoke.130846024
Directory /workspace/49.alert_handler_smoke/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all.532953571
Short name T237
Test name
Test status
Simulation time 13886184109 ps
CPU time 1329.21 seconds
Started Feb 21 03:58:12 PM PST 24
Finished Feb 21 04:20:22 PM PST 24
Peak memory 298936 kb
Host smart-5bc85711-ed6f-44bf-9f59-423686368241
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532953571 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_han
dler_stress_all.532953571
Directory /workspace/49.alert_handler_stress_all/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all_with_rand_reset.2149262536
Short name T31
Test name
Test status
Simulation time 142830970592 ps
CPU time 2163.58 seconds
Started Feb 21 03:58:04 PM PST 24
Finished Feb 21 04:34:09 PM PST 24
Peak memory 289440 kb
Host smart-fbbefb03-2fcb-4855-87cd-baadd38b5719
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149262536 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 49.alert_handler_stress_all_with_rand_reset.2149262536
Directory /workspace/49.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.alert_handler_alert_accum_saturation.4001876918
Short name T198
Test name
Test status
Simulation time 38357967 ps
CPU time 3.25 seconds
Started Feb 21 03:54:04 PM PST 24
Finished Feb 21 03:54:08 PM PST 24
Peak memory 248588 kb
Host smart-963cf72e-bcc3-42b7-8466-dbf782a78ff9
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4001876918 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_alert_accum_saturation.4001876918
Directory /workspace/5.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/5.alert_handler_entropy.36652768
Short name T222
Test name
Test status
Simulation time 59193767427 ps
CPU time 1486.7 seconds
Started Feb 21 03:53:59 PM PST 24
Finished Feb 21 04:18:46 PM PST 24
Peak memory 288788 kb
Host smart-4a712b3c-c36a-4049-b996-a9044e168b84
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36652768 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy.36652768
Directory /workspace/5.alert_handler_entropy/latest

Test location /workspace/coverage/default/5.alert_handler_entropy_stress.511762861
Short name T92
Test name
Test status
Simulation time 733269346 ps
CPU time 17.09 seconds
Started Feb 21 03:53:58 PM PST 24
Finished Feb 21 03:54:15 PM PST 24
Peak memory 240020 kb
Host smart-83c3fd88-bdd8-44e9-ad2f-c02895bd4ed8
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=511762861 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy_stress.511762861
Directory /workspace/5.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/5.alert_handler_esc_alert_accum.227288478
Short name T681
Test name
Test status
Simulation time 765083682 ps
CPU time 39.83 seconds
Started Feb 21 03:53:57 PM PST 24
Finished Feb 21 03:54:37 PM PST 24
Peak memory 254064 kb
Host smart-74d6b785-d5b7-4743-ac5a-e75581fe948b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22728
8478 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_alert_accum.227288478
Directory /workspace/5.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/5.alert_handler_esc_intr_timeout.2160597071
Short name T405
Test name
Test status
Simulation time 1390727225 ps
CPU time 18.97 seconds
Started Feb 21 03:53:52 PM PST 24
Finished Feb 21 03:54:12 PM PST 24
Peak memory 247900 kb
Host smart-22155cdd-5745-44f2-9204-27dbce72413b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21605
97071 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_intr_timeout.2160597071
Directory /workspace/5.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_lpg_stub_clk.1192996767
Short name T444
Test name
Test status
Simulation time 11086397058 ps
CPU time 914.55 seconds
Started Feb 21 03:53:58 PM PST 24
Finished Feb 21 04:09:13 PM PST 24
Peak memory 272896 kb
Host smart-3c4d916b-4771-4747-ae4d-947cd2d6ee5a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192996767 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg_stub_clk.1192996767
Directory /workspace/5.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/5.alert_handler_ping_timeout.3467324963
Short name T299
Test name
Test status
Simulation time 6682443798 ps
CPU time 285.84 seconds
Started Feb 21 03:53:59 PM PST 24
Finished Feb 21 03:58:45 PM PST 24
Peak memory 246976 kb
Host smart-a9de4094-7e48-4c68-8f35-3a6821116404
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467324963 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_ping_timeout.3467324963
Directory /workspace/5.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_random_alerts.1721897701
Short name T29
Test name
Test status
Simulation time 2103314535 ps
CPU time 36.83 seconds
Started Feb 21 03:53:58 PM PST 24
Finished Feb 21 03:54:35 PM PST 24
Peak memory 248188 kb
Host smart-cd95f5ea-fc22-41f0-abc7-ebceab1be9db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17218
97701 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_alerts.1721897701
Directory /workspace/5.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/5.alert_handler_random_classes.437102986
Short name T626
Test name
Test status
Simulation time 143934878 ps
CPU time 10.83 seconds
Started Feb 21 03:53:58 PM PST 24
Finished Feb 21 03:54:09 PM PST 24
Peak memory 254724 kb
Host smart-55ad39ba-2578-4c35-8bf6-6d499c820de6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43710
2986 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_classes.437102986
Directory /workspace/5.alert_handler_random_classes/latest

Test location /workspace/coverage/default/5.alert_handler_sig_int_fail.1404555215
Short name T471
Test name
Test status
Simulation time 926580563 ps
CPU time 25.02 seconds
Started Feb 21 03:53:50 PM PST 24
Finished Feb 21 03:54:17 PM PST 24
Peak memory 246728 kb
Host smart-1d9b26cd-1439-440e-896c-ed35c1d9cd0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14045
55215 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_sig_int_fail.1404555215
Directory /workspace/5.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/5.alert_handler_smoke.1090906843
Short name T697
Test name
Test status
Simulation time 961715539 ps
CPU time 54.56 seconds
Started Feb 21 03:53:58 PM PST 24
Finished Feb 21 03:54:53 PM PST 24
Peak memory 255260 kb
Host smart-a69f0f46-d38f-4b04-8e80-689e09020dec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10909
06843 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_smoke.1090906843
Directory /workspace/5.alert_handler_smoke/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all.3608455738
Short name T547
Test name
Test status
Simulation time 266894081259 ps
CPU time 3602.57 seconds
Started Feb 21 03:54:04 PM PST 24
Finished Feb 21 04:54:07 PM PST 24
Peak memory 298780 kb
Host smart-834898cb-90bc-46be-a07a-967d459fa5ff
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608455738 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_han
dler_stress_all.3608455738
Directory /workspace/5.alert_handler_stress_all/latest

Test location /workspace/coverage/default/6.alert_handler_alert_accum_saturation.2133258100
Short name T204
Test name
Test status
Simulation time 32117378 ps
CPU time 3.15 seconds
Started Feb 21 03:54:06 PM PST 24
Finished Feb 21 03:54:10 PM PST 24
Peak memory 248548 kb
Host smart-46769276-59a2-416b-888c-6062766aff42
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2133258100 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_alert_accum_saturation.2133258100
Directory /workspace/6.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/6.alert_handler_entropy.2164111202
Short name T599
Test name
Test status
Simulation time 39383833256 ps
CPU time 2480.88 seconds
Started Feb 21 03:54:04 PM PST 24
Finished Feb 21 04:35:26 PM PST 24
Peak memory 289000 kb
Host smart-5c46c719-c300-4c21-a55c-be3e8e495eda
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164111202 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy.2164111202
Directory /workspace/6.alert_handler_entropy/latest

Test location /workspace/coverage/default/6.alert_handler_entropy_stress.2138872889
Short name T15
Test name
Test status
Simulation time 8632308415 ps
CPU time 58.84 seconds
Started Feb 21 03:54:03 PM PST 24
Finished Feb 21 03:55:02 PM PST 24
Peak memory 248344 kb
Host smart-15cf6817-6158-46fd-a453-56825dece9b6
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2138872889 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy_stress.2138872889
Directory /workspace/6.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/6.alert_handler_esc_alert_accum.1145324783
Short name T570
Test name
Test status
Simulation time 6065708014 ps
CPU time 190.62 seconds
Started Feb 21 03:54:02 PM PST 24
Finished Feb 21 03:57:13 PM PST 24
Peak memory 255660 kb
Host smart-a5b5ce32-535e-48ed-8ca0-39991cc36f77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11453
24783 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_alert_accum.1145324783
Directory /workspace/6.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/6.alert_handler_esc_intr_timeout.2347879530
Short name T640
Test name
Test status
Simulation time 2161986044 ps
CPU time 40.86 seconds
Started Feb 21 03:54:06 PM PST 24
Finished Feb 21 03:54:47 PM PST 24
Peak memory 254620 kb
Host smart-296db9e6-72ec-42f8-8dc7-03992cda96b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23478
79530 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_intr_timeout.2347879530
Directory /workspace/6.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_lpg.2052067872
Short name T592
Test name
Test status
Simulation time 86618868350 ps
CPU time 1235.9 seconds
Started Feb 21 03:54:02 PM PST 24
Finished Feb 21 04:14:39 PM PST 24
Peak memory 283636 kb
Host smart-329ee1e9-01ed-4714-930b-315a57e3c86f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052067872 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg.2052067872
Directory /workspace/6.alert_handler_lpg/latest

Test location /workspace/coverage/default/6.alert_handler_lpg_stub_clk.599443842
Short name T98
Test name
Test status
Simulation time 183628521447 ps
CPU time 2317.47 seconds
Started Feb 21 03:54:03 PM PST 24
Finished Feb 21 04:32:41 PM PST 24
Peak memory 283624 kb
Host smart-266948f1-e114-48d8-8537-fcd1eea85d6b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599443842 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg_stub_clk.599443842
Directory /workspace/6.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/6.alert_handler_ping_timeout.1073251673
Short name T225
Test name
Test status
Simulation time 34418024911 ps
CPU time 367.91 seconds
Started Feb 21 03:54:06 PM PST 24
Finished Feb 21 04:00:14 PM PST 24
Peak memory 247212 kb
Host smart-be3a0d65-b2d7-4250-8517-82ab3a79fe51
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073251673 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_ping_timeout.1073251673
Directory /workspace/6.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_random_alerts.2368207994
Short name T266
Test name
Test status
Simulation time 596708188 ps
CPU time 28.26 seconds
Started Feb 21 03:54:03 PM PST 24
Finished Feb 21 03:54:32 PM PST 24
Peak memory 255280 kb
Host smart-4e5ac4a8-6090-4cc9-a980-c995a663c522
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23682
07994 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_alerts.2368207994
Directory /workspace/6.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/6.alert_handler_random_classes.2711047508
Short name T77
Test name
Test status
Simulation time 1469785916 ps
CPU time 23.48 seconds
Started Feb 21 03:54:02 PM PST 24
Finished Feb 21 03:54:26 PM PST 24
Peak memory 253936 kb
Host smart-90143d05-1dc4-48d4-8e3a-2e4254b21dc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27110
47508 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_classes.2711047508
Directory /workspace/6.alert_handler_random_classes/latest

Test location /workspace/coverage/default/6.alert_handler_sig_int_fail.1242550785
Short name T52
Test name
Test status
Simulation time 222767159 ps
CPU time 13.59 seconds
Started Feb 21 03:54:06 PM PST 24
Finished Feb 21 03:54:20 PM PST 24
Peak memory 246380 kb
Host smart-a4e969a0-3040-4ad0-bded-b5ad7ac24fad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12425
50785 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_sig_int_fail.1242550785
Directory /workspace/6.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/6.alert_handler_smoke.1016269168
Short name T41
Test name
Test status
Simulation time 44130192 ps
CPU time 3.75 seconds
Started Feb 21 03:54:03 PM PST 24
Finished Feb 21 03:54:07 PM PST 24
Peak memory 240056 kb
Host smart-5387430c-7468-4e7b-8dd4-241baf070b96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10162
69168 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_smoke.1016269168
Directory /workspace/6.alert_handler_smoke/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all_with_rand_reset.3802708310
Short name T189
Test name
Test status
Simulation time 391230721065 ps
CPU time 1581.72 seconds
Started Feb 21 03:54:17 PM PST 24
Finished Feb 21 04:20:39 PM PST 24
Peak memory 289408 kb
Host smart-52fdd12e-9037-463e-9de9-4c0f577b5046
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802708310 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 6.alert_handler_stress_all_with_rand_reset.3802708310
Directory /workspace/6.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.alert_handler_alert_accum_saturation.92296699
Short name T210
Test name
Test status
Simulation time 36409989 ps
CPU time 2.43 seconds
Started Feb 21 03:54:28 PM PST 24
Finished Feb 21 03:54:31 PM PST 24
Peak memory 248744 kb
Host smart-8e627e3a-4d8d-411e-93d0-3a102d74a79b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=92296699 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_alert_accum_saturation.92296699
Directory /workspace/7.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/7.alert_handler_entropy.3197723744
Short name T398
Test name
Test status
Simulation time 69100853551 ps
CPU time 2175.98 seconds
Started Feb 21 03:54:22 PM PST 24
Finished Feb 21 04:30:39 PM PST 24
Peak memory 288544 kb
Host smart-e50965a4-36f6-48d3-b4af-56743819daaa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197723744 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy.3197723744
Directory /workspace/7.alert_handler_entropy/latest

Test location /workspace/coverage/default/7.alert_handler_entropy_stress.85503947
Short name T409
Test name
Test status
Simulation time 1553734828 ps
CPU time 17.73 seconds
Started Feb 21 03:54:23 PM PST 24
Finished Feb 21 03:54:41 PM PST 24
Peak memory 240080 kb
Host smart-a59a50bf-895e-4c51-b4b7-40938f9422ed
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=85503947 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy_stress.85503947
Directory /workspace/7.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/7.alert_handler_esc_alert_accum.474367726
Short name T610
Test name
Test status
Simulation time 858194164 ps
CPU time 61.64 seconds
Started Feb 21 03:54:19 PM PST 24
Finished Feb 21 03:55:21 PM PST 24
Peak memory 255600 kb
Host smart-3bc2ac7b-c9d0-45a0-9c23-531ae9af613f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47436
7726 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_alert_accum.474367726
Directory /workspace/7.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/7.alert_handler_esc_intr_timeout.1513102346
Short name T470
Test name
Test status
Simulation time 81317977 ps
CPU time 7.91 seconds
Started Feb 21 03:54:19 PM PST 24
Finished Feb 21 03:54:27 PM PST 24
Peak memory 251128 kb
Host smart-9fdaf35f-1f9c-4d8f-8505-48907d5f63f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15131
02346 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_intr_timeout.1513102346
Directory /workspace/7.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_lpg.1812391173
Short name T288
Test name
Test status
Simulation time 216781852539 ps
CPU time 2730.71 seconds
Started Feb 21 03:54:23 PM PST 24
Finished Feb 21 04:39:54 PM PST 24
Peak memory 289176 kb
Host smart-3f83da34-f630-424f-b6b7-4dcedbccf02d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812391173 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg.1812391173
Directory /workspace/7.alert_handler_lpg/latest

Test location /workspace/coverage/default/7.alert_handler_lpg_stub_clk.1561573688
Short name T574
Test name
Test status
Simulation time 22693624964 ps
CPU time 1298.48 seconds
Started Feb 21 03:54:18 PM PST 24
Finished Feb 21 04:15:57 PM PST 24
Peak memory 288692 kb
Host smart-254f9f25-7c6d-4172-85d6-5048087ecef3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1561573688 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg_stub_clk.1561573688
Directory /workspace/7.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/7.alert_handler_ping_timeout.3503328309
Short name T546
Test name
Test status
Simulation time 4783728930 ps
CPU time 131.42 seconds
Started Feb 21 03:54:18 PM PST 24
Finished Feb 21 03:56:30 PM PST 24
Peak memory 246864 kb
Host smart-11d97e88-9b4a-40bd-a666-b7b40db8dcbc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503328309 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_ping_timeout.3503328309
Directory /workspace/7.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_random_alerts.556584700
Short name T542
Test name
Test status
Simulation time 533719247 ps
CPU time 9.38 seconds
Started Feb 21 03:54:18 PM PST 24
Finished Feb 21 03:54:28 PM PST 24
Peak memory 248272 kb
Host smart-c535a74e-410d-4a27-8aff-cd2b742f93ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55658
4700 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_alerts.556584700
Directory /workspace/7.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/7.alert_handler_random_classes.952321382
Short name T32
Test name
Test status
Simulation time 551667229 ps
CPU time 34.55 seconds
Started Feb 21 03:54:18 PM PST 24
Finished Feb 21 03:54:53 PM PST 24
Peak memory 254340 kb
Host smart-7eed1c9c-736b-4003-b876-661771bdb2d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95232
1382 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_classes.952321382
Directory /workspace/7.alert_handler_random_classes/latest

Test location /workspace/coverage/default/7.alert_handler_sig_int_fail.667227812
Short name T459
Test name
Test status
Simulation time 1222567217 ps
CPU time 34.37 seconds
Started Feb 21 03:54:18 PM PST 24
Finished Feb 21 03:54:53 PM PST 24
Peak memory 254048 kb
Host smart-39d6d3cd-fde0-46fb-ae62-bc591563b9fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66722
7812 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_sig_int_fail.667227812
Directory /workspace/7.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/7.alert_handler_smoke.2867704305
Short name T67
Test name
Test status
Simulation time 4723233341 ps
CPU time 47.48 seconds
Started Feb 21 03:54:17 PM PST 24
Finished Feb 21 03:55:04 PM PST 24
Peak memory 248320 kb
Host smart-80d514dd-dbe8-4b9f-89fc-3ce64e353ed9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28677
04305 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_smoke.2867704305
Directory /workspace/7.alert_handler_smoke/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all.305294142
Short name T275
Test name
Test status
Simulation time 44955270242 ps
CPU time 1221.64 seconds
Started Feb 21 03:54:19 PM PST 24
Finished Feb 21 04:14:41 PM PST 24
Peak memory 288920 kb
Host smart-0750f5b8-b46b-4a6d-ab0c-a298a93e76a2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305294142 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_hand
ler_stress_all.305294142
Directory /workspace/7.alert_handler_stress_all/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all_with_rand_reset.801310215
Short name T83
Test name
Test status
Simulation time 27439738694 ps
CPU time 2699.8 seconds
Started Feb 21 03:54:19 PM PST 24
Finished Feb 21 04:39:19 PM PST 24
Peak memory 317400 kb
Host smart-e1c3cede-081f-4e2c-8130-2239accc8935
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801310215 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 7.alert_handler_stress_all_with_rand_reset.801310215
Directory /workspace/7.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.alert_handler_entropy.2697955392
Short name T509
Test name
Test status
Simulation time 11956564928 ps
CPU time 1476.77 seconds
Started Feb 21 03:54:30 PM PST 24
Finished Feb 21 04:19:08 PM PST 24
Peak memory 285776 kb
Host smart-912676a6-2ad4-40c2-967e-7be09c5010b5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697955392 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy.2697955392
Directory /workspace/8.alert_handler_entropy/latest

Test location /workspace/coverage/default/8.alert_handler_entropy_stress.778025347
Short name T482
Test name
Test status
Simulation time 918220599 ps
CPU time 9.99 seconds
Started Feb 21 03:54:31 PM PST 24
Finished Feb 21 03:54:42 PM PST 24
Peak memory 240048 kb
Host smart-2ae4f310-87d2-4dc3-9425-9bce293c10f9
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=778025347 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy_stress.778025347
Directory /workspace/8.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/8.alert_handler_esc_alert_accum.1387856844
Short name T702
Test name
Test status
Simulation time 2482232370 ps
CPU time 107.23 seconds
Started Feb 21 03:54:20 PM PST 24
Finished Feb 21 03:56:08 PM PST 24
Peak memory 255728 kb
Host smart-84e3d73c-6147-4e43-9f66-861b3038892e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13878
56844 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_alert_accum.1387856844
Directory /workspace/8.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/8.alert_handler_esc_intr_timeout.227214693
Short name T74
Test name
Test status
Simulation time 1851481027 ps
CPU time 25.39 seconds
Started Feb 21 03:54:28 PM PST 24
Finished Feb 21 03:54:53 PM PST 24
Peak memory 254708 kb
Host smart-172dc268-d7d7-4485-b466-c12628403592
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22721
4693 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_intr_timeout.227214693
Directory /workspace/8.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_lpg.2547611066
Short name T325
Test name
Test status
Simulation time 103693852303 ps
CPU time 2694.3 seconds
Started Feb 21 03:54:23 PM PST 24
Finished Feb 21 04:39:17 PM PST 24
Peak memory 281104 kb
Host smart-df4d3f6d-5194-4d17-9f46-5213bebf0f68
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547611066 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg.2547611066
Directory /workspace/8.alert_handler_lpg/latest

Test location /workspace/coverage/default/8.alert_handler_lpg_stub_clk.541932175
Short name T511
Test name
Test status
Simulation time 26207862429 ps
CPU time 1455.86 seconds
Started Feb 21 03:54:17 PM PST 24
Finished Feb 21 04:18:33 PM PST 24
Peak memory 271936 kb
Host smart-ff635a43-f074-47a2-a7eb-7f7539061156
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541932175 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg_stub_clk.541932175
Directory /workspace/8.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/8.alert_handler_ping_timeout.1227585880
Short name T94
Test name
Test status
Simulation time 2465853952 ps
CPU time 106.99 seconds
Started Feb 21 03:54:19 PM PST 24
Finished Feb 21 03:56:07 PM PST 24
Peak memory 245964 kb
Host smart-9295b3ea-2f6a-430b-a542-84fa9c76313e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1227585880 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_ping_timeout.1227585880
Directory /workspace/8.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_random_alerts.2541404696
Short name T426
Test name
Test status
Simulation time 2112184639 ps
CPU time 68.46 seconds
Started Feb 21 03:54:17 PM PST 24
Finished Feb 21 03:55:26 PM PST 24
Peak memory 248256 kb
Host smart-897011e0-ab54-40eb-8fb1-7b062686f887
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25414
04696 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_alerts.2541404696
Directory /workspace/8.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/8.alert_handler_random_classes.1244796511
Short name T676
Test name
Test status
Simulation time 1296271990 ps
CPU time 41 seconds
Started Feb 21 03:54:28 PM PST 24
Finished Feb 21 03:55:10 PM PST 24
Peak memory 246980 kb
Host smart-3ed386a4-85f5-4146-9c80-f597f394f4c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12447
96511 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_classes.1244796511
Directory /workspace/8.alert_handler_random_classes/latest

Test location /workspace/coverage/default/8.alert_handler_sig_int_fail.3707659073
Short name T122
Test name
Test status
Simulation time 676423916 ps
CPU time 35.96 seconds
Started Feb 21 03:54:28 PM PST 24
Finished Feb 21 03:55:04 PM PST 24
Peak memory 248248 kb
Host smart-1e767382-8cae-4b30-837e-71760f6f2f2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37076
59073 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_sig_int_fail.3707659073
Directory /workspace/8.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/8.alert_handler_smoke.1377930849
Short name T544
Test name
Test status
Simulation time 658225478 ps
CPU time 41.49 seconds
Started Feb 21 03:54:23 PM PST 24
Finished Feb 21 03:55:05 PM PST 24
Peak memory 256428 kb
Host smart-d56ff3da-6963-4809-8841-74c2896745b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13779
30849 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_smoke.1377930849
Directory /workspace/8.alert_handler_smoke/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all.2514644210
Short name T619
Test name
Test status
Simulation time 32188561168 ps
CPU time 1811.84 seconds
Started Feb 21 03:54:30 PM PST 24
Finished Feb 21 04:24:43 PM PST 24
Peak memory 284456 kb
Host smart-c692f49d-b0d0-4f68-89b6-892e28e264cf
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514644210 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_han
dler_stress_all.2514644210
Directory /workspace/8.alert_handler_stress_all/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all_with_rand_reset.3079108795
Short name T232
Test name
Test status
Simulation time 3489403274 ps
CPU time 143.56 seconds
Started Feb 21 03:54:17 PM PST 24
Finished Feb 21 03:56:41 PM PST 24
Peak memory 264812 kb
Host smart-b50e8b8c-0176-413a-96cd-ea0027e12519
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079108795 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 8.alert_handler_stress_all_with_rand_reset.3079108795
Directory /workspace/8.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.alert_handler_alert_accum_saturation.340472754
Short name T197
Test name
Test status
Simulation time 36450100 ps
CPU time 3.2 seconds
Started Feb 21 03:54:46 PM PST 24
Finished Feb 21 03:54:50 PM PST 24
Peak memory 248720 kb
Host smart-12a59301-31f6-4d75-940e-eaf436bfd041
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=340472754 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_alert_accum_saturation.340472754
Directory /workspace/9.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/9.alert_handler_entropy.332592683
Short name T458
Test name
Test status
Simulation time 145124737818 ps
CPU time 2407.37 seconds
Started Feb 21 03:54:30 PM PST 24
Finished Feb 21 04:34:38 PM PST 24
Peak memory 282280 kb
Host smart-c77f78f4-b2ed-4ac4-9bd8-27e0cdcee47a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332592683 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy.332592683
Directory /workspace/9.alert_handler_entropy/latest

Test location /workspace/coverage/default/9.alert_handler_entropy_stress.1575127777
Short name T372
Test name
Test status
Simulation time 599859040 ps
CPU time 26.81 seconds
Started Feb 21 03:54:35 PM PST 24
Finished Feb 21 03:55:02 PM PST 24
Peak memory 240060 kb
Host smart-50bf147e-ea9d-40a3-acf1-f1a55f5203d4
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1575127777 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy_stress.1575127777
Directory /workspace/9.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/9.alert_handler_esc_alert_accum.1532049196
Short name T461
Test name
Test status
Simulation time 416952496 ps
CPU time 33.86 seconds
Started Feb 21 03:54:35 PM PST 24
Finished Feb 21 03:55:10 PM PST 24
Peak memory 246604 kb
Host smart-75e96bad-5bf0-4867-b2bb-7fc5f29173c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15320
49196 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_alert_accum.1532049196
Directory /workspace/9.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/9.alert_handler_esc_intr_timeout.1543381891
Short name T386
Test name
Test status
Simulation time 275189596 ps
CPU time 9.16 seconds
Started Feb 21 03:54:29 PM PST 24
Finished Feb 21 03:54:39 PM PST 24
Peak memory 246536 kb
Host smart-b40c6fde-09b8-4faa-9651-bcd5191f3087
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15433
81891 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_intr_timeout.1543381891
Directory /workspace/9.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_lpg.2828079537
Short name T661
Test name
Test status
Simulation time 10435506563 ps
CPU time 902.87 seconds
Started Feb 21 03:54:44 PM PST 24
Finished Feb 21 04:09:49 PM PST 24
Peak memory 272420 kb
Host smart-99338f0c-2bb3-4f25-b8b1-256b479fb930
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828079537 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg.2828079537
Directory /workspace/9.alert_handler_lpg/latest

Test location /workspace/coverage/default/9.alert_handler_lpg_stub_clk.38887507
Short name T215
Test name
Test status
Simulation time 29825716460 ps
CPU time 1763.63 seconds
Started Feb 21 03:54:47 PM PST 24
Finished Feb 21 04:24:12 PM PST 24
Peak memory 289232 kb
Host smart-557bc525-2b85-4e21-bb95-267dfbc433a3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38887507 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg_stub_clk.38887507
Directory /workspace/9.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/9.alert_handler_ping_timeout.1821965693
Short name T290
Test name
Test status
Simulation time 8882956272 ps
CPU time 192.67 seconds
Started Feb 21 03:54:35 PM PST 24
Finished Feb 21 03:57:48 PM PST 24
Peak memory 246976 kb
Host smart-5defc7de-e89f-4016-b619-b9ef6e4d1b3a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821965693 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_ping_timeout.1821965693
Directory /workspace/9.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_random_alerts.4174313105
Short name T247
Test name
Test status
Simulation time 278811798 ps
CPU time 30.36 seconds
Started Feb 21 03:54:18 PM PST 24
Finished Feb 21 03:54:48 PM PST 24
Peak memory 254408 kb
Host smart-1a5c5d7d-bd39-4476-b318-ae1366e7b104
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41743
13105 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_alerts.4174313105
Directory /workspace/9.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/9.alert_handler_random_classes.109538723
Short name T563
Test name
Test status
Simulation time 596747037 ps
CPU time 9.64 seconds
Started Feb 21 03:54:31 PM PST 24
Finished Feb 21 03:54:42 PM PST 24
Peak memory 251252 kb
Host smart-5b961b08-8197-4b84-82e9-998a8bcf48fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10953
8723 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_classes.109538723
Directory /workspace/9.alert_handler_random_classes/latest

Test location /workspace/coverage/default/9.alert_handler_smoke.89209383
Short name T520
Test name
Test status
Simulation time 395287341 ps
CPU time 16.5 seconds
Started Feb 21 03:54:18 PM PST 24
Finished Feb 21 03:54:34 PM PST 24
Peak memory 248260 kb
Host smart-f50f478c-33eb-4d38-a0ea-9ba7596933ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89209
383 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_smoke.89209383
Directory /workspace/9.alert_handler_smoke/latest
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