Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
esc_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	8	0	8	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	76172	1			T18	13		T46	84		T71	2
class_i[0x1]	81119	1			T8	3587		T18	12		T10	6
class_i[0x2]	71825	1			T2	3356		T19	773		T8	2
class_i[0x3]	56027	1			T2	3		T19	10		T15	4326

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Summary for Variable esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	71790	1			T2	841		T19	1		T15	1088
alert[0x1]	73037	1			T2	876		T19	295		T15	970
alert[0x2]	71648	1			T2	838		T19	485		T15	1151
alert[0x3]	68668	1			T2	804		T19	2		T15	1117

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Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

esc_integrity_fail

284889

1

T2

3359

T19

783

T15

4326

esc_ping_fail

254

1

T9

5

T10

6

T11

4

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Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	esc_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	alert[0x0]	71716	1			T2	841		T19	1		T15	1088
esc_integrity_fail	alert[0x1]	72974	1			T2	876		T19	295		T15	970
esc_integrity_fail	alert[0x2]	71592	1			T2	838		T19	485		T15	1151
esc_integrity_fail	alert[0x3]	68607	1			T2	804		T19	2		T15	1117
esc_ping_fail	alert[0x0]	74	1			T9	3		T10	3		T11	2
esc_ping_fail	alert[0x1]	63	1			T9	1		T10	1		T290	1
esc_ping_fail	alert[0x2]	56	1			T9	1		T11	1		T273	2
esc_ping_fail	alert[0x3]	61	1			T10	2		T11	1		T290	2

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Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	class_i[0x0]	76101	1			T18	13		T46	84		T71	2
esc_integrity_fail	class_i[0x1]	81053	1			T8	3587		T18	12		T29	9
esc_integrity_fail	class_i[0x2]	71756	1			T2	3356		T19	773		T8	2
esc_integrity_fail	class_i[0x3]	55979	1			T2	3		T19	10		T15	4326
esc_ping_fail	class_i[0x0]	71	1			T11	2		T290	1		T27	1
esc_ping_fail	class_i[0x1]	66	1			T10	6		T11	2		T103	1
esc_ping_fail	class_i[0x2]	69	1			T9	5		T290	3		T103	2
esc_ping_fail	class_i[0x3]	48	1			T313	2		T40	1		T306	7