Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_edn_req.u_prim_packer_fifo.DataOStableWhenPending_A	0	0	745477658	0	0	631
tb.dut.u_edn_req.u_prim_packer_fifo.ValidOPairedWithReadyI_A	0	0	745477658	0	0	0

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.AckPKnownO_A	0	0	745477658	745305173	0	0
tb.dut.CheckAccuCntDw	0	0	631	631	0	0
tb.dut.CheckEscCntDw	0	0	631	631	0	0
tb.dut.CheckNAlerts	0	0	631	631	0	0
tb.dut.CheckNClasses	0	0	631	631	0	0
tb.dut.CheckNEscSev	0	0	631	631	0	0
tb.dut.CrashdumpKnownO_A	0	0	745477658	745305173	0	0
tb.dut.EdnKnownO_A	0	0	745477658	745305173	0	0
tb.dut.EscPKnownO_A	0	0	745477658	745305173	0	0
tb.dut.FpvSecCmPingTimerCnterCheck_A	0	0	745477658	80	0	0
tb.dut.FpvSecCmPingTimerDoubleLfsrCheck_A	0	0	745477658	80	0	0
tb.dut.FpvSecCmPingTimerEscCnterCheck_A	0	0	745477658	80	0	0
tb.dut.FpvSecCmPingTimerFsmCheck_A	0	0	745477658	80	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	745477658	80	0	0
tb.dut.IrqAKnownO_A	0	0	745477658	745305173	0	0
tb.dut.IrqBKnownO_A	0	0	745477658	745305173	0	0
tb.dut.IrqCKnownO_A	0	0	745477658	745305173	0	0
tb.dut.IrqDKnownO_A	0	0	745477658	745305173	0	0
tb.dut.TlAReadyKnownO_A	0	0	745477658	745305173	0	0
tb.dut.TlDValidKnownO_A	0	0	745477658	745305173	0	0
tb.dut.alert_handler_csr_assert.TlulOOBAddrErr_A	0	0	769142776	4523046	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_0_rd_A	0	0	769142776	8162	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_10_rd_A	0	0	769142776	8949	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_11_rd_A	0	0	769142776	7902	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_12_rd_A	0	0	769142776	7801	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_13_rd_A	0	0	769142776	8002	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_14_rd_A	0	0	769142776	7966	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_15_rd_A	0	0	769142776	7816	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_16_rd_A	0	0	769142776	8526	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_17_rd_A	0	0	769142776	7730	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_18_rd_A	0	0	769142776	7865	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_19_rd_A	0	0	769142776	8011	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_1_rd_A	0	0	769142776	7865	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_20_rd_A	0	0	769142776	7857	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_21_rd_A	0	0	769142776	7937	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_22_rd_A	0	0	769142776	7790	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_23_rd_A	0	0	769142776	8115	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_24_rd_A	0	0	769142776	7937	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_25_rd_A	0	0	769142776	8166	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_26_rd_A	0	0	769142776	8126	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_27_rd_A	0	0	769142776	7726	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_28_rd_A	0	0	769142776	8038	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_29_rd_A	0	0	769142776	7991	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_2_rd_A	0	0	769142776	7806	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_30_rd_A	0	0	769142776	7731	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_31_rd_A	0	0	769142776	7844	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_32_rd_A	0	0	769142776	8476	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_33_rd_A	0	0	769142776	7709	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_34_rd_A	0	0	769142776	8020	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_35_rd_A	0	0	769142776	8036	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_36_rd_A	0	0	769142776	7920	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_37_rd_A	0	0	769142776	7777	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_38_rd_A	0	0	769142776	8756	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_39_rd_A	0	0	769142776	8078	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_3_rd_A	0	0	769142776	8614	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_40_rd_A	0	0	769142776	8152	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_41_rd_A	0	0	769142776	7882	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_42_rd_A	0	0	769142776	8525	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_43_rd_A	0	0	769142776	8415	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_44_rd_A	0	0	769142776	8161	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_45_rd_A	0	0	769142776	7933	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_46_rd_A	0	0	769142776	7834	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_47_rd_A	0	0	769142776	8769	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_48_rd_A	0	0	769142776	7559	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_49_rd_A	0	0	769142776	8565	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_4_rd_A	0	0	769142776	8191	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_50_rd_A	0	0	769142776	8116	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_51_rd_A	0	0	769142776	7968	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_52_rd_A	0	0	769142776	7812	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_53_rd_A	0	0	769142776	8247	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_54_rd_A	0	0	769142776	7877	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_55_rd_A	0	0	769142776	8029	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_56_rd_A	0	0	769142776	7688	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_57_rd_A	0	0	769142776	8443	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_58_rd_A	0	0	769142776	7993	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_59_rd_A	0	0	769142776	7861	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_5_rd_A	0	0	769142776	7636	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_60_rd_A	0	0	769142776	8761	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_61_rd_A	0	0	769142776	8040	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_62_rd_A	0	0	769142776	8248	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_63_rd_A	0	0	769142776	7683	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_64_rd_A	0	0	769142776	8629	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_6_rd_A	0	0	769142776	8726	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_7_rd_A	0	0	769142776	7671	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_8_rd_A	0	0	769142776	7733	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_9_rd_A	0	0	769142776	7925	0	0
tb.dut.alert_handler_csr_assert.classa_regwen_rd_A	0	0	769142776	7985	0	0
tb.dut.alert_handler_csr_assert.classb_regwen_rd_A	0	0	769142776	8270	0	0
tb.dut.alert_handler_csr_assert.classc_regwen_rd_A	0	0	769142776	8182	0	0
tb.dut.alert_handler_csr_assert.classd_regwen_rd_A	0	0	769142776	7838	0	0
tb.dut.alert_handler_csr_assert.intr_enable_rd_A	0	0	769142776	14257	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_0_rd_A	0	0	769142776	8694	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_1_rd_A	0	0	769142776	8673	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_2_rd_A	0	0	769142776	7701	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_3_rd_A	0	0	769142776	8568	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_4_rd_A	0	0	769142776	8623	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_5_rd_A	0	0	769142776	7892	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_6_rd_A	0	0	769142776	7950	0	0
tb.dut.alert_handler_csr_assert.ping_timer_regwen_rd_A	0	0	769142776	7987	0	0
tb.dut.gen_classes[0].FpvSecCmAccuCnterCheck_A	0	0	745477658	80	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerCnterCheck_A	0	0	745477658	80	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerFsmCheck_A	0	0	745477658	80	0	0
tb.dut.gen_classes[0].u_accu.CountSaturateStable_A	0	0	745477658	3021	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigBkwd_A	0	0	745477658	279519	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigFwd_A	0	0	745477658	360052827	0	0
tb.dut.gen_classes[0].u_esc_timer.AccuFailToFsmError_A	0	0	745477658	256	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig0_A	0	0	745477658	894	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig1_A	0	0	745477658	55	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckClr_A	0	0	745477658	445	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckEn_A	0	0	745161462	262318168	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase0_A	0	0	745477658	990	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase1_A	0	0	745477658	971	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase2_A	0	0	745477658	947	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase3_A	0	0	745477658	921	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeout0_A	0	0	745477658	1174	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt1_A	0	0	745477658	105068	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt2_A	0	0	745477658	1060	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutStTrig_A	0	0	745477658	59	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStAllEscAsserted_A	0	0	745477658	1487	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStIsTerminal_A	0	0	745477658	1247	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs.AssertConnected_A	0	0	631	631	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs_A	0	0	745477658	745305173	0	0
tb.dut.gen_classes[1].FpvSecCmAccuCnterCheck_A	0	0	745477658	80	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerCnterCheck_A	0	0	745477658	80	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerFsmCheck_A	0	0	745477658	80	0	0
tb.dut.gen_classes[1].u_accu.CountSaturateStable_A	0	0	745477658	2350	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigBkwd_A	0	0	745477658	243541	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigFwd_A	0	0	745477658	418714190	0	0
tb.dut.gen_classes[1].u_esc_timer.AccuFailToFsmError_A	0	0	745477658	277	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig0_A	0	0	745477658	547	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig1_A	0	0	745477658	23	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckClr_A	0	0	745477658	259	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckEn_A	0	0	745161462	322941513	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase0_A	0	0	745477658	625	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase1_A	0	0	745477658	613	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase2_A	0	0	745477658	598	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase3_A	0	0	745477658	589	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeout0_A	0	0	745477658	1288	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt1_A	0	0	745477658	109550	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt2_A	0	0	745477658	1199	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutStTrig_A	0	0	745477658	66	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStAllEscAsserted_A	0	0	745477658	1453	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStIsTerminal_A	0	0	745477658	1213	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs.AssertConnected_A	0	0	631	631	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs_A	0	0	745477658	745305173	0	0
tb.dut.gen_classes[2].FpvSecCmAccuCnterCheck_A	0	0	745477658	80	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerCnterCheck_A	0	0	745477658	80	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerFsmCheck_A	0	0	745477658	80	0	0
tb.dut.gen_classes[2].u_accu.CountSaturateStable_A	0	0	745477658	4518	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigBkwd_A	0	0	745477658	186932	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigFwd_A	0	0	745477658	442145464	0	0
tb.dut.gen_classes[2].u_esc_timer.AccuFailToFsmError_A	0	0	745477658	280	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig0_A	0	0	745477658	528	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig1_A	0	0	745477658	18	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckClr_A	0	0	745477658	235	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckEn_A	0	0	745161462	363120153	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase0_A	0	0	745477658	593	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase1_A	0	0	745477658	585	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase2_A	0	0	745477658	571	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase3_A	0	0	745477658	564	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeout0_A	0	0	745477658	1215	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt1_A	0	0	745477658	98297	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt2_A	0	0	745477658	1141	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutStTrig_A	0	0	745477658	53	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStAllEscAsserted_A	0	0	745477658	1371	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStIsTerminal_A	0	0	745477658	1131	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs.AssertConnected_A	0	0	631	631	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs_A	0	0	745477658	745305173	0	0
tb.dut.gen_classes[3].FpvSecCmAccuCnterCheck_A	0	0	745477658	80	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerCnterCheck_A	0	0	745477658	80	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerFsmCheck_A	0	0	745477658	80	0	0
tb.dut.gen_classes[3].u_accu.CountSaturateStable_A	0	0	745477658	4135	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigBkwd_A	0	0	745477658	190527	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigFwd_A	0	0	745477658	430767972	0	0
tb.dut.gen_classes[3].u_esc_timer.AccuFailToFsmError_A	0	0	745477658	292	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig0_A	0	0	745477658	532	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig1_A	0	0	745477658	25	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckClr_A	0	0	745477658	256	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckEn_A	0	0	745161462	363885896	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase0_A	0	0	745477658	598	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase1_A	0	0	745477658	579	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase2_A	0	0	745477658	567	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase3_A	0	0	745477658	559	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeout0_A	0	0	745477658	947	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt1_A	0	0	745477658	100775	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt2_A	0	0	745477658	871	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutStTrig_A	0	0	745477658	49	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStAllEscAsserted_A	0	0	745477658	1388	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStIsTerminal_A	0	0	745477658	1148	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs.AssertConnected_A	0	0	631	631	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs_A	0	0	745477658	745305173	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	769142776	157025159	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	769142776	768476952	0	0
tb.dut.tlul_assert_device.aReadyKnown_A	0	0	769142776	768476952	0	0
tb.dut.tlul_assert_device.dKnown_A	0	0	769142776	208122744	0	0
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