Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.89	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	40	6	34	85.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
intr_timeout_cnt_cp	10	0	10	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	40	6	34	85.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	59	1			T18	1		T46	1		T73	1
class_index[0x1]	66	1			T19	1		T8	2		T18	1
class_index[0x2]	54	1			T19	2		T29	1		T73	1
class_index[0x3]	49	1			T18	1		T48	1		T51	1

---

Summary for Variable intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for intr_timeout_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
intr_timeout_cnt[0]	100	1			T8	2		T29	1		T73	1
intr_timeout_cnt[1]	52	1			T19	1		T18	1		T31	1
intr_timeout_cnt[2]	29	1			T19	2		T18	1		T73	1
intr_timeout_cnt[3]	7	1			T75	1		T31	1		T79	1
intr_timeout_cnt[4]	5	1			T46	1		T80	1		T109	1
intr_timeout_cnt[5]	4	1			T236	1		T241	1		T197	1
intr_timeout_cnt[6]	13	1			T79	1		T25	1		T57	1
intr_timeout_cnt[7]	4	1			T18	1		T25	1		T244	1
intr_timeout_cnt[8]	6	1			T25	1		T42	2		T245	1
intr_timeout_cnt[9]	8	1			T51	1		T80	1		T57	1

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	6	34	85.00	6

Automatically Generated Cross Bins for class_cnt_cross

Uncovered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	NUMBER	STATUS
[class_index[0x0]]	[intr_timeout_cnt[8]]	0	1	1
[class_index[0x1]]	[intr_timeout_cnt[4]]	0	1	1
[class_index[0x1]]	[intr_timeout_cnt[9]]	0	1	1
[class_index[0x2]]	[intr_timeout_cnt[4]]	0	1	1
[class_index[0x3]]	[intr_timeout_cnt[3]]	0	1	1
[class_index[0x3]]	[intr_timeout_cnt[7]]	0	1	1

Covered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	intr_timeout_cnt[0]	24	1			T73	1		T50	1		T28	2
class_index[0x0]	intr_timeout_cnt[1]	14	1			T79	1		T22	1		T246	1
class_index[0x0]	intr_timeout_cnt[2]	5	1			T18	1		T27	1		T54	1
class_index[0x0]	intr_timeout_cnt[3]	2	1			T120	1		T247	1		-	-
class_index[0x0]	intr_timeout_cnt[4]	4	1			T46	1		T80	1		T109	1
class_index[0x0]	intr_timeout_cnt[5]	1	1			T248	1		-	-		-	-
class_index[0x0]	intr_timeout_cnt[6]	5	1			T120	1		T249	1		T250	1
class_index[0x0]	intr_timeout_cnt[7]	1	1			T244	1		-	-		-	-
class_index[0x0]	intr_timeout_cnt[9]	3	1			T57	1		T197	1		T251	1
class_index[0x1]	intr_timeout_cnt[0]	28	1			T8	2		T27	6		T120	2
class_index[0x1]	intr_timeout_cnt[1]	21	1			T19	1		T57	1		T84	6
class_index[0x1]	intr_timeout_cnt[2]	8	1			T75	1		T31	1		T25	1
class_index[0x1]	intr_timeout_cnt[3]	1	1			T96	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[5]	1	1			T241	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[6]	3	1			T79	1		T25	1		T252	1
class_index[0x1]	intr_timeout_cnt[7]	2	1			T18	1		T253	1		-	-
class_index[0x1]	intr_timeout_cnt[8]	2	1			T42	2		-	-		-	-
class_index[0x2]	intr_timeout_cnt[0]	21	1			T29	1		T81	1		T83	1
class_index[0x2]	intr_timeout_cnt[1]	11	1			T31	1		T79	1		T82	1
class_index[0x2]	intr_timeout_cnt[2]	10	1			T19	2		T73	1		T80	1
class_index[0x2]	intr_timeout_cnt[3]	4	1			T75	1		T31	1		T79	1
class_index[0x2]	intr_timeout_cnt[5]	1	1			T236	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[6]	2	1			T57	1		T244	1		-	-
class_index[0x2]	intr_timeout_cnt[7]	1	1			T25	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[8]	2	1			T25	1		T244	1		-	-
class_index[0x2]	intr_timeout_cnt[9]	2	1			T254	1		T197	1		-	-
class_index[0x3]	intr_timeout_cnt[0]	27	1			T48	1		T53	1		T28	1
class_index[0x3]	intr_timeout_cnt[1]	6	1			T18	1		T255	1		T91	1
class_index[0x3]	intr_timeout_cnt[2]	6	1			T82	1		T252	1		T256	1
class_index[0x3]	intr_timeout_cnt[4]	1	1			T257	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[5]	1	1			T197	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[6]	3	1			T236	1		T197	1		T251	1
class_index[0x3]	intr_timeout_cnt[8]	2	1			T245	1		T219	1		-	-
class_index[0x3]	intr_timeout_cnt[9]	3	1			T51	1		T80	1		T258	1