Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	377782	1			T1	161		T2	1297		T6	27
all_values[1]	377782	1			T1	161		T2	1297		T6	27
all_values[2]	377782	1			T1	161		T2	1297		T6	27
all_values[3]	377782	1			T1	161		T2	1297		T6	27

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

751872

1

T1

318

T2

2507

T6

55

auto[1]

759256

1

T1

326

T2

2681

T6

53

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

909507

1

T1

329

T2

2617

T6

95

auto[1]

601621

1

T1

315

T2

2571

T6

13

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	108546	1			T1	41		T2	322		T6	6
all_values[0]	auto[0]	auto[1]	79761	1			T1	40		T2	312		T6	5
all_values[0]	auto[1]	auto[0]	109617	1			T1	40		T2	336		T6	8
all_values[0]	auto[1]	auto[1]	79858	1			T1	40		T2	327		T6	8
all_values[1]	auto[0]	auto[0]	113752	1			T1	37		T2	332		T6	10
all_values[1]	auto[0]	auto[1]	74524	1			T1	33		T2	320		T19	3
all_values[1]	auto[1]	auto[0]	114921	1			T1	49		T2	324		T6	17
all_values[1]	auto[1]	auto[1]	74585	1			T1	42		T2	321		T19	13
all_values[2]	auto[0]	auto[0]	114765	1			T1	42		T2	307		T6	17
all_values[2]	auto[0]	auto[1]	72531	1			T1	42		T2	306		T19	9
all_values[2]	auto[1]	auto[0]	117225	1			T1	39		T2	343		T6	10
all_values[2]	auto[1]	auto[1]	73261	1			T1	38		T2	341		T19	7
all_values[3]	auto[0]	auto[0]	114550	1			T1	42		T2	305		T6	17
all_values[3]	auto[0]	auto[1]	73443	1			T1	41		T2	303		T19	8
all_values[3]	auto[1]	auto[0]	116131	1			T1	39		T2	348		T6	10
all_values[3]	auto[1]	auto[1]	73658	1			T1	39		T2	341		T19	9