Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	4	0	4	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	377782	1			T1	161		T2	1297		T6	27
all_pins[1]	377782	1			T1	161		T2	1297		T6	27
all_pins[2]	377782	1			T1	161		T2	1297		T6	27
all_pins[3]	377782	1			T1	161		T2	1297		T6	27

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1209766	1			T1	485		T2	3858		T6	100
values[0x1]	301362	1			T1	159		T2	1330		T6	8
transitions[0x0=>0x1]	200657	1			T1	100		T2	822		T6	7
transitions[0x1=>0x0]	200912	1			T1	100		T2	822		T6	8

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	297924	1			T1	121		T2	970		T6	19
all_pins[0]	values[0x1]	79858	1			T1	40		T2	327		T6	8
all_pins[0]	transitions[0x0=>0x1]	79194	1			T1	40		T2	327		T6	7
all_pins[0]	transitions[0x1=>0x0]	73249	1			T1	39		T2	341		T19	5
all_pins[1]	values[0x0]	303197	1			T1	119		T2	976		T6	27
all_pins[1]	values[0x1]	74585	1			T1	42		T2	321		T19	13
all_pins[1]	transitions[0x0=>0x1]	41028	1			T1	17		T2	160		T19	8
all_pins[1]	transitions[0x1=>0x0]	46301	1			T1	15		T2	166		T6	8
all_pins[2]	values[0x0]	304521	1			T1	123		T2	956		T6	27
all_pins[2]	values[0x1]	73261	1			T1	38		T2	341		T19	7
all_pins[2]	transitions[0x0=>0x1]	39939	1			T1	23		T2	169		T19	3
all_pins[2]	transitions[0x1=>0x0]	41263	1			T1	27		T2	149		T19	9
all_pins[3]	values[0x0]	304124	1			T1	122		T2	956		T6	27
all_pins[3]	values[0x1]	73658	1			T1	39		T2	341		T19	9
all_pins[3]	transitions[0x0=>0x1]	40496	1			T1	20		T2	166		T19	6
all_pins[3]	transitions[0x1=>0x0]	40099	1			T1	19		T2	166		T19	4