Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	269	1			T165	7		T166	4		T167	7
all_values[1]	269	1			T165	7		T166	4		T167	7
all_values[2]	269	1			T165	7		T166	4		T167	7
all_values[3]	269	1			T165	7		T166	4		T167	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

603

1

T165

15

T166

6

T167

15

auto[1]

473

1

T165

13

T166

10

T167

13

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

466

1

T165

13

T166

8

T167

8

auto[1]

610

1

T165

15

T166

8

T167

20

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

655

1

T165

17

T166

10

T167

15

auto[1]

421

1

T165

11

T166

6

T167

13

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	24	0	24	100.00
Automatically Generated Cross Bins	24	0	24	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr

cp_intr_test

cp_intr_en

cp_intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_values[0]

auto[0]

auto[0]

auto[0]

69

1

T165

3

T226

3

T345

1

all_values[0]

auto[0]

auto[0]

auto[1]

23

1

T166

2

T167

1

T226

1

all_values[0]

auto[0]

auto[1]

auto[0]

48

1

T165

1

T167

1

T233

1

all_values[0]

auto[0]

auto[1]

auto[1]

24

1

T167

1

T345

2

T233

2

all_values[0]

auto[1]

auto[0]

auto[1]

51

1

T167

2

T226

2

T345

1

all_values[0]

auto[1]

auto[1]

auto[1]

54

1

T165

3

T166

2

T167

2

all_values[1]

auto[0]

auto[0]

auto[0]

73

1

T167

1

T345

1

T233

2

all_values[1]

auto[0]

auto[0]

auto[1]

27

1

T165

2

T226

1

T345

2

all_values[1]

auto[0]

auto[1]

auto[0]

42

1

T165

3

T166

2

T167

2

all_values[1]

auto[0]

auto[1]

auto[1]

14

1

T233

1

T346

1

T347

1

all_values[1]

auto[1]

auto[0]

auto[1]

64

1

T165

1

T167

4

T226

4

all_values[1]

auto[1]

auto[1]

auto[1]

49

1

T165

1

T166

2

T234

2

all_values[2]

auto[0]

auto[0]

auto[0]

60

1

T165

5

T166

2

T226

2

all_values[2]

auto[0]

auto[0]

auto[1]

32

1

T167

1

T226

2

T345

1

all_values[2]

auto[0]

auto[1]

auto[0]

54

1

T165

1

T166

2

T167

2

all_values[2]

auto[0]

auto[1]

auto[1]

20

1

T167

1

T235

1

T347

2

all_values[2]

auto[1]

auto[0]

auto[1]

57

1

T165

1

T167

1

T226

3

all_values[2]

auto[1]

auto[1]

auto[1]

46

1

T167

2

T233

3

T348

1

all_values[3]

auto[0]

auto[0]

auto[0]

71

1

T166

1

T167

2

T226

4

all_values[3]

auto[0]

auto[0]

auto[1]

20

1

T165

1

T167

1

T226

1

all_values[3]

auto[0]

auto[1]

auto[0]

49

1

T166

1

T233

2

T234

1

all_values[3]

auto[0]

auto[1]

auto[1]

29

1

T165

1

T167

2

T345

1

all_values[3]

auto[1]

auto[0]

auto[1]

56

1

T165

2

T166

1

T167

2

all_values[3]

auto[1]

auto[1]

auto[1]

44

1

T165

3

T166

1

T226

1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal