Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
accum_cnt_cp	6	0	6	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	24	0	24	100.00	100	1	1	0

Summary for Variable accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for accum_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
accum_cnt_2000	99466	1			T2	364		T5	1173		T15	1109
accum_cnt_1000	243928	1			T2	516		T4	914		T5	1059
accum_cnt_100	27844	1			T2	28		T4	228		T5	52
accum_cnt_50	72070	1			T2	34		T6	12		T19	11
accum_cnt_10	179533	1			T1	80		T2	18		T6	8
accum_cnt_0	436448	1			T1	240		T2	2900		T6	68

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Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	278628	1			T1	80		T2	965		T6	22
class_index[0x1]	278628	1			T1	80		T2	965		T6	22
class_index[0x2]	278628	1			T1	80		T2	965		T6	22
class_index[0x3]	278628	1			T1	80		T2	965		T6	22

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Summary for Cross class_cnt_cross

Samples crossed: class_index_cp accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for class_cnt_cross

Bins

class_index_cp	accum_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	accum_cnt_2000	26695	1			T15	574		T8	449		T73	237
class_index[0x0]	accum_cnt_1000	62223	1			T4	390		T15	504		T8	554
class_index[0x0]	accum_cnt_100	8464	1			T4	139		T15	24		T8	59
class_index[0x0]	accum_cnt_50	19835	1			T6	12		T4	119		T20	8
class_index[0x0]	accum_cnt_10	51758	1			T6	8		T19	2		T4	29
class_index[0x0]	accum_cnt_0	91251	1			T1	80		T2	965		T6	2
class_index[0x1]	accum_cnt_2000	23909	1			T15	535		T17	674		T289	230
class_index[0x1]	accum_cnt_1000	59005	1			T15	638		T7	416		T8	42
class_index[0x1]	accum_cnt_100	6638	1			T15	33		T7	171		T8	29
class_index[0x1]	accum_cnt_50	17637	1			T15	25		T7	133		T43	3
class_index[0x1]	accum_cnt_10	45606	1			T1	80		T2	1		T19	3
class_index[0x1]	accum_cnt_0	110140	1			T2	964		T6	22		T19	24
class_index[0x2]	accum_cnt_2000	22810	1			T5	651		T71	470		T49	237
class_index[0x2]	accum_cnt_1000	58811	1			T4	524		T5	580		T7	587
class_index[0x2]	accum_cnt_100	6792	1			T4	89		T5	28		T7	76
class_index[0x2]	accum_cnt_50	16368	1			T19	11		T4	59		T5	24
class_index[0x2]	accum_cnt_10	44396	1			T2	1		T19	13		T4	24
class_index[0x2]	accum_cnt_0	117707	1			T1	80		T2	964		T6	22
class_index[0x3]	accum_cnt_2000	26052	1			T2	364		T5	522		T71	629
class_index[0x3]	accum_cnt_1000	63889	1			T2	516		T5	479		T44	47
class_index[0x3]	accum_cnt_100	5950	1			T2	28		T5	24		T44	18
class_index[0x3]	accum_cnt_50	18230	1			T2	34		T5	19		T15	1248
class_index[0x3]	accum_cnt_10	37773	1			T2	16		T19	2		T5	14
class_index[0x3]	accum_cnt_0	117350	1			T1	80		T2	7		T6	22