Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	71	0	71	100.00
Crosses	138	0	138	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
alert_index_cp	65	0	65	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	130	0	130	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for alert_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	3851	1			T19	2		T46	2		T73	20
alert[0x1]	5348	1			T46	36		T71	19		T29	1
alert[0x2]	5022	1			T18	1		T49	422		T273	1
alert[0x3]	5163	1			T8	16		T73	1		T290	1
alert[0x4]	5908	1			T9	1		T46	3		T71	5
alert[0x5]	8528	1			T46	75		T10	2		T11	1
alert[0x6]	3031	1			T27	27		T67	1		T51	831
alert[0x7]	5935	1			T7	1		T46	100		T27	53
alert[0x8]	7437	1			T9	1		T18	4		T46	482
alert[0x9]	3233	1			T19	1		T9	1		T103	1
alert[0xa]	8419	1			T9	1		T72	3		T291	1
alert[0xb]	2674	1			T46	1		T49	131		T27	92
alert[0xc]	2426	1			T71	11		T73	2		T290	1
alert[0xd]	4150	1			T9	1		T71	4		T49	335
alert[0xe]	11050	1			T19	16		T15	1		T9	1
alert[0xf]	2027	1			T19	1		T9	1		T46	25
alert[0x10]	3321	1			T18	26		T290	2		T103	2
alert[0x11]	7365	1			T9	1		T71	6		T11	1
alert[0x12]	4507	1			T9	1		T73	2		T49	286
alert[0x13]	6885	1			T18	11		T11	1		T49	2183
alert[0x14]	18258	1			T46	20		T10	1		T292	1
alert[0x15]	4033	1			T10	1		T29	20		T49	98
alert[0x16]	10600	1			T46	36		T73	2		T49	16
alert[0x17]	5997	1			T19	7		T18	4		T46	3
alert[0x18]	10095	1			T9	1		T71	2		T290	1
alert[0x19]	3189	1			T18	32		T46	12		T10	1
alert[0x1a]	5730	1			T75	7		T49	14		T27	187
alert[0x1b]	11079	1			T46	4		T27	3662		T79	9
alert[0x1c]	5689	1			T19	3		T46	1		T51	44
alert[0x1d]	5988	1			T19	2		T10	1		T71	5
alert[0x1e]	7719	1			T46	7		T10	1		T72	4
alert[0x1f]	8854	1			T18	2		T46	9		T290	2
alert[0x20]	3366	1			T8	1		T72	1		T27	153
alert[0x21]	5113	1			T2	14		T19	2		T290	1
alert[0x22]	4746	1			T18	16		T71	1		T290	1
alert[0x23]	5466	1			T46	16		T72	1		T27	53
alert[0x24]	9779	1			T2	1		T18	1		T46	1
alert[0x25]	5374	1			T46	2		T73	2		T11	1
alert[0x26]	7764	1			T9	2		T290	2		T50	6
alert[0x27]	6925	1			T8	5		T29	2		T27	292
alert[0x28]	10094	1			T72	2		T290	1		T49	32
alert[0x29]	2291	1			T8	2		T18	38		T73	2
alert[0x2a]	5186	1			T46	1		T49	10		T273	2
alert[0x2b]	6131	1			T18	1		T290	1		T75	3
alert[0x2c]	8393	1			T7	1		T18	5		T75	2
alert[0x2d]	2725	1			T49	5		T27	127		T273	1
alert[0x2e]	4186	1			T10	1		T29	2		T49	25
alert[0x2f]	10302	1			T10	1		T71	1		T290	1
alert[0x30]	3768	1			T46	160		T49	12		T27	64
alert[0x31]	12076	1			T8	1		T10	2		T72	6
alert[0x32]	5567	1			T51	16		T31	2		T52	526
alert[0x33]	4336	1			T2	2		T15	7		T8	2
alert[0x34]	1312	1			T2	2		T15	3		T46	5
alert[0x35]	3246	1			T9	1		T71	1		T29	2
alert[0x36]	4900	1			T46	4		T73	23		T49	191
alert[0x37]	5100	1			T10	1		T71	1		T27	102
alert[0x38]	6885	1			T290	1		T31	8		T273	1
alert[0x39]	5370	1			T9	1		T29	28		T73	2
alert[0x3a]	5739	1			T273	1		T52	75		T28	77
alert[0x3b]	3917	1			T46	4		T49	695		T27	76
alert[0x3c]	5551	1			T18	93		T46	5		T27	22
alert[0x3d]	9728	1			T73	110		T49	33		T27	12
alert[0x3e]	5718	1			T49	74		T52	1916		T293	19
alert[0x3f]	7023	1			T46	22		T27	224		T67	1
alert[0x40]	5470	1			T2	2		T19	3		T11	1

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	127953	1			T19	36		T9	1		T71	21
class_i[0x1]	122417	1			T7	2		T18	6		T46	965
class_i[0x2]	59353	1			T2	7		T19	1		T8	27
class_i[0x3]	87335	1			T2	14		T15	11		T18	3

---

Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

alert_integrity_fail

396399

1

T2

21

T19

37

T15

11

alert_ping_fail

659

1

T7

2

T9

14

T10

13

---

Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	0	130	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	alert_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	alert[0x0]	3848	1			T19	2		T46	2		T73	20
alert_integrity_fail	alert[0x1]	5344	1			T46	36		T71	19		T29	1
alert_integrity_fail	alert[0x2]	5015	1			T18	1		T49	422		T52	204
alert_integrity_fail	alert[0x3]	5156	1			T8	16		T73	1		T51	584
alert_integrity_fail	alert[0x4]	5903	1			T46	3		T71	5		T72	1
alert_integrity_fail	alert[0x5]	8519	1			T46	75		T75	1		T49	124
alert_integrity_fail	alert[0x6]	3014	1			T27	27		T51	831		T260	7
alert_integrity_fail	alert[0x7]	5928	1			T46	100		T27	53		T52	131
alert_integrity_fail	alert[0x8]	7419	1			T18	4		T46	482		T75	2
alert_integrity_fail	alert[0x9]	3220	1			T19	1		T27	5		T52	40
alert_integrity_fail	alert[0xa]	8403	1			T72	3		T28	353		T281	8
alert_integrity_fail	alert[0xb]	2669	1			T46	1		T49	131		T27	92
alert_integrity_fail	alert[0xc]	2412	1			T71	11		T73	2		T31	38
alert_integrity_fail	alert[0xd]	4134	1			T71	4		T49	335		T50	1
alert_integrity_fail	alert[0xe]	11043	1			T19	16		T15	1		T71	7
alert_integrity_fail	alert[0xf]	2018	1			T19	1		T46	25		T52	78
alert_integrity_fail	alert[0x10]	3305	1			T18	26		T27	591		T79	1
alert_integrity_fail	alert[0x11]	7355	1			T71	6		T49	4		T52	269
alert_integrity_fail	alert[0x12]	4500	1			T73	2		T49	286		T51	103
alert_integrity_fail	alert[0x13]	6875	1			T18	11		T49	2183		T27	143
alert_integrity_fail	alert[0x14]	18245	1			T46	20		T52	194		T294	384
alert_integrity_fail	alert[0x15]	4025	1			T29	20		T49	98		T27	3
alert_integrity_fail	alert[0x16]	10594	1			T46	36		T73	2		T49	16
alert_integrity_fail	alert[0x17]	5985	1			T19	7		T18	4		T46	3
alert_integrity_fail	alert[0x18]	10087	1			T71	2		T49	25		T27	237
alert_integrity_fail	alert[0x19]	3179	1			T18	32		T46	12		T49	223
alert_integrity_fail	alert[0x1a]	5727	1			T75	7		T49	14		T27	187
alert_integrity_fail	alert[0x1b]	11068	1			T46	4		T27	3662		T79	9
alert_integrity_fail	alert[0x1c]	5680	1			T19	3		T46	1		T51	44
alert_integrity_fail	alert[0x1d]	5977	1			T19	2		T71	5		T49	356
alert_integrity_fail	alert[0x1e]	7706	1			T46	7		T72	4		T49	3200
alert_integrity_fail	alert[0x1f]	8841	1			T18	2		T46	9		T75	7
alert_integrity_fail	alert[0x20]	3360	1			T8	1		T72	1		T27	153
alert_integrity_fail	alert[0x21]	5106	1			T2	14		T19	2		T50	1
alert_integrity_fail	alert[0x22]	4734	1			T18	16		T71	1		T51	635
alert_integrity_fail	alert[0x23]	5453	1			T46	16		T72	1		T27	53
alert_integrity_fail	alert[0x24]	9771	1			T2	1		T18	1		T46	1
alert_integrity_fail	alert[0x25]	5361	1			T46	2		T73	2		T49	1424
alert_integrity_fail	alert[0x26]	7754	1			T50	6		T51	274		T31	1
alert_integrity_fail	alert[0x27]	6911	1			T8	5		T29	2		T27	292
alert_integrity_fail	alert[0x28]	10084	1			T72	2		T49	32		T51	122
alert_integrity_fail	alert[0x29]	2282	1			T8	2		T18	38		T73	2
alert_integrity_fail	alert[0x2a]	5169	1			T46	1		T49	10		T54	1
alert_integrity_fail	alert[0x2b]	6121	1			T18	1		T75	3		T49	4
alert_integrity_fail	alert[0x2c]	8378	1			T18	5		T75	2		T27	19
alert_integrity_fail	alert[0x2d]	2715	1			T49	5		T27	127		T294	33
alert_integrity_fail	alert[0x2e]	4170	1			T29	2		T49	25		T260	8
alert_integrity_fail	alert[0x2f]	10293	1			T71	1		T75	9		T49	2081
alert_integrity_fail	alert[0x30]	3758	1			T46	160		T49	12		T27	64
alert_integrity_fail	alert[0x31]	12064	1			T8	1		T72	6		T73	2
alert_integrity_fail	alert[0x32]	5555	1			T51	16		T31	2		T52	526
alert_integrity_fail	alert[0x33]	4327	1			T2	2		T15	7		T8	2
alert_integrity_fail	alert[0x34]	1303	1			T2	2		T15	3		T46	5
alert_integrity_fail	alert[0x35]	3234	1			T71	1		T29	2		T49	27
alert_integrity_fail	alert[0x36]	4891	1			T46	4		T73	23		T49	191
alert_integrity_fail	alert[0x37]	5086	1			T71	1		T27	102		T52	796
alert_integrity_fail	alert[0x38]	6870	1			T31	8		T79	6		T114	211
alert_integrity_fail	alert[0x39]	5363	1			T29	28		T73	2		T75	1
alert_integrity_fail	alert[0x3a]	5734	1			T52	75		T28	77		T82	2
alert_integrity_fail	alert[0x3b]	3905	1			T46	4		T49	695		T27	76
alert_integrity_fail	alert[0x3c]	5542	1			T18	93		T46	5		T27	22
alert_integrity_fail	alert[0x3d]	9720	1			T73	110		T49	33		T27	12
alert_integrity_fail	alert[0x3e]	5710	1			T49	74		T52	1916		T293	19
alert_integrity_fail	alert[0x3f]	7020	1			T46	22		T27	224		T54	2
alert_integrity_fail	alert[0x40]	5461	1			T2	2		T19	3		T27	56
alert_ping_fail	alert[0x0]	3	1			T295	1		T296	1		T297	1
alert_ping_fail	alert[0x1]	4	1			T298	1		T299	2		T300	1
alert_ping_fail	alert[0x2]	7	1			T273	1		T301	1		T298	1
alert_ping_fail	alert[0x3]	7	1			T290	1		T273	1		T302	1
alert_ping_fail	alert[0x4]	5	1			T9	1		T303	1		T304	2
alert_ping_fail	alert[0x5]	9	1			T10	2		T11	1		T284	1
alert_ping_fail	alert[0x6]	17	1			T67	1		T284	1		T305	2
alert_ping_fail	alert[0x7]	7	1			T7	1		T296	1		T306	1
alert_ping_fail	alert[0x8]	18	1			T9	1		T295	1		T307	1
alert_ping_fail	alert[0x9]	13	1			T9	1		T103	1		T273	1
alert_ping_fail	alert[0xa]	16	1			T9	1		T291	1		T308	1
alert_ping_fail	alert[0xb]	5	1			T309	1		T310	1		T311	1
alert_ping_fail	alert[0xc]	14	1			T290	1		T301	1		T291	1
alert_ping_fail	alert[0xd]	16	1			T9	1		T103	1		T273	1
alert_ping_fail	alert[0xe]	7	1			T9	1		T10	1		T292	1
alert_ping_fail	alert[0xf]	9	1			T9	1		T312	1		T296	1
alert_ping_fail	alert[0x10]	16	1			T290	2		T103	2		T67	1
alert_ping_fail	alert[0x11]	10	1			T9	1		T11	1		T273	1
alert_ping_fail	alert[0x12]	7	1			T9	1		T67	1		T312	1
alert_ping_fail	alert[0x13]	10	1			T11	1		T307	1		T312	1
alert_ping_fail	alert[0x14]	13	1			T10	1		T292	1		T301	1
alert_ping_fail	alert[0x15]	8	1			T10	1		T313	1		T36	1
alert_ping_fail	alert[0x16]	6	1			T67	1		T273	1		T305	1
alert_ping_fail	alert[0x17]	12	1			T313	2		T314	1		T312	1
alert_ping_fail	alert[0x18]	8	1			T9	1		T290	1		T288	1
alert_ping_fail	alert[0x19]	10	1			T10	1		T67	1		T301	1
alert_ping_fail	alert[0x1a]	3	1			T292	1		T312	1		T315	1
alert_ping_fail	alert[0x1b]	11	1			T314	2		T305	1		T306	1
alert_ping_fail	alert[0x1c]	9	1			T314	1		T312	1		T296	1
alert_ping_fail	alert[0x1d]	11	1			T10	1		T291	1		T296	1
alert_ping_fail	alert[0x1e]	13	1			T10	1		T290	1		T67	1
alert_ping_fail	alert[0x1f]	13	1			T290	2		T103	1		T301	1
alert_ping_fail	alert[0x20]	6	1			T67	1		T316	1		T310	1
alert_ping_fail	alert[0x21]	7	1			T290	1		T306	1		T317	1
alert_ping_fail	alert[0x22]	12	1			T290	1		T273	1		T301	1
alert_ping_fail	alert[0x23]	13	1			T296	1		T306	2		T297	1
alert_ping_fail	alert[0x24]	8	1			T67	1		T314	1		T312	1
alert_ping_fail	alert[0x25]	13	1			T11	1		T292	1		T312	2
alert_ping_fail	alert[0x26]	10	1			T9	2		T290	2		T291	1
alert_ping_fail	alert[0x27]	14	1			T295	1		T318	2		T297	1
alert_ping_fail	alert[0x28]	10	1			T290	1		T285	1		T312	1
alert_ping_fail	alert[0x29]	9	1			T11	1		T290	1		T312	1
alert_ping_fail	alert[0x2a]	17	1			T273	2		T301	1		T283	1
alert_ping_fail	alert[0x2b]	10	1			T290	1		T287	1		T291	1
alert_ping_fail	alert[0x2c]	15	1			T7	1		T283	1		T319	1
alert_ping_fail	alert[0x2d]	10	1			T273	1		T291	1		T312	1
alert_ping_fail	alert[0x2e]	16	1			T10	1		T67	1		T273	1
alert_ping_fail	alert[0x2f]	9	1			T10	1		T290	1		T103	1
alert_ping_fail	alert[0x30]	10	1			T301	1		T291	1		T314	1
alert_ping_fail	alert[0x31]	12	1			T10	2		T290	1		T301	1
alert_ping_fail	alert[0x32]	12	1			T306	1		T318	1		T320	2
alert_ping_fail	alert[0x33]	9	1			T290	1		T40	1		T312	1
alert_ping_fail	alert[0x34]	9	1			T67	1		T314	1		T312	1
alert_ping_fail	alert[0x35]	12	1			T9	1		T290	1		T273	1
alert_ping_fail	alert[0x36]	9	1			T305	1		T312	1		T306	1
alert_ping_fail	alert[0x37]	14	1			T10	1		T67	1		T301	1
alert_ping_fail	alert[0x38]	15	1			T290	1		T273	1		T296	1
alert_ping_fail	alert[0x39]	7	1			T9	1		T290	1		T321	1
alert_ping_fail	alert[0x3a]	5	1			T273	1		T312	1		T318	1
alert_ping_fail	alert[0x3b]	12	1			T291	1		T40	1		T296	2
alert_ping_fail	alert[0x3c]	9	1			T67	1		T296	1		T306	1
alert_ping_fail	alert[0x3d]	8	1			T67	1		T305	1		T306	1
alert_ping_fail	alert[0x3e]	8	1			T305	1		T40	1		T306	1
alert_ping_fail	alert[0x3f]	3	1			T67	1		T304	1		T322	1
alert_ping_fail	alert[0x40]	9	1			T11	1		T273	1		T295	1

---

Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	class_i[0x0]	127828	1			T19	36		T71	21		T29	3
alert_integrity_fail	class_i[0x1]	122240	1			T18	6		T46	965		T71	30
alert_integrity_fail	class_i[0x2]	59193	1			T2	7		T19	1		T8	27
alert_integrity_fail	class_i[0x3]	87138	1			T2	14		T15	11		T18	3
alert_ping_fail	class_i[0x0]	125	1			T9	1		T11	5		T290	2
alert_ping_fail	class_i[0x1]	177	1			T7	2		T11	1		T290	2
alert_ping_fail	class_i[0x2]	160	1			T9	13		T10	13		T290	16
alert_ping_fail	class_i[0x3]	197	1			T290	1		T103	2		T67	13