Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.64 99.99 98.66 100.00 100.00 100.00 99.38 99.44


Total test records in report: 836
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html
T777 /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.790137777 Feb 25 03:00:06 PM PST 24 Feb 25 03:00:08 PM PST 24 18677917 ps
T168 /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.1994791972 Feb 25 02:59:41 PM PST 24 Feb 25 03:00:20 PM PST 24 1212720600 ps
T139 /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.3818130785 Feb 25 02:59:26 PM PST 24 Feb 25 03:02:52 PM PST 24 3224971192 ps
T150 /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.1711784344 Feb 25 02:59:48 PM PST 24 Feb 25 03:16:00 PM PST 24 13569410796 ps
T778 /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.3373136791 Feb 25 02:59:43 PM PST 24 Feb 25 02:59:59 PM PST 24 898618498 ps
T779 /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.1187095975 Feb 25 03:00:02 PM PST 24 Feb 25 03:00:08 PM PST 24 131599288 ps
T780 /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.1274364537 Feb 25 02:59:27 PM PST 24 Feb 25 03:00:13 PM PST 24 635470318 ps
T781 /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.1505503504 Feb 25 03:00:10 PM PST 24 Feb 25 03:00:12 PM PST 24 12318028 ps
T782 /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.307712324 Feb 25 03:00:07 PM PST 24 Feb 25 03:00:09 PM PST 24 7737145 ps
T144 /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.1792362681 Feb 25 02:59:43 PM PST 24 Feb 25 03:03:54 PM PST 24 14215717777 ps
T152 /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.25732698 Feb 25 02:59:28 PM PST 24 Feb 25 03:01:21 PM PST 24 819194660 ps
T783 /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.2281447892 Feb 25 02:59:28 PM PST 24 Feb 25 02:59:34 PM PST 24 58017303 ps
T179 /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.2505822811 Feb 25 03:00:02 PM PST 24 Feb 25 03:00:42 PM PST 24 1725432435 ps
T784 /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.2051043827 Feb 25 03:00:06 PM PST 24 Feb 25 03:00:07 PM PST 24 18337763 ps
T185 /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.1906992722 Feb 25 02:59:30 PM PST 24 Feb 25 03:00:07 PM PST 24 491982584 ps
T785 /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.3668389484 Feb 25 02:59:28 PM PST 24 Feb 25 03:00:46 PM PST 24 1085813480 ps
T153 /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.1948203733 Feb 25 02:59:42 PM PST 24 Feb 25 03:02:02 PM PST 24 7001321451 ps
T173 /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.2740318075 Feb 25 03:00:09 PM PST 24 Feb 25 03:01:25 PM PST 24 2098766600 ps
T786 /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.1574708053 Feb 25 02:59:24 PM PST 24 Feb 25 02:59:29 PM PST 24 117064939 ps
T787 /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.3358062372 Feb 25 02:59:25 PM PST 24 Feb 25 02:59:30 PM PST 24 101275960 ps
T788 /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.1522147281 Feb 25 03:00:06 PM PST 24 Feb 25 03:00:44 PM PST 24 1359097961 ps
T789 /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.2252674483 Feb 25 03:00:02 PM PST 24 Feb 25 03:00:18 PM PST 24 914388497 ps
T133 /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.753400788 Feb 25 02:59:38 PM PST 24 Feb 25 03:03:07 PM PST 24 3495532955 ps
T171 /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.2702533733 Feb 25 02:59:29 PM PST 24 Feb 25 02:59:34 PM PST 24 63008335 ps
T790 /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.560625853 Feb 25 02:59:37 PM PST 24 Feb 25 02:59:38 PM PST 24 10592098 ps
T791 /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.2278382535 Feb 25 02:59:41 PM PST 24 Feb 25 02:59:53 PM PST 24 456865748 ps
T792 /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.5696761 Feb 25 02:59:26 PM PST 24 Feb 25 03:02:57 PM PST 24 3861453815 ps
T793 /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.1497534038 Feb 25 02:59:40 PM PST 24 Feb 25 02:59:48 PM PST 24 500522668 ps
T177 /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.597520769 Feb 25 02:59:29 PM PST 24 Feb 25 02:59:53 PM PST 24 633976821 ps
T794 /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.1479008270 Feb 25 02:59:44 PM PST 24 Feb 25 02:59:53 PM PST 24 108581822 ps
T795 /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.598190628 Feb 25 02:59:42 PM PST 24 Feb 25 02:59:44 PM PST 24 27789557 ps
T796 /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.4018239580 Feb 25 02:59:28 PM PST 24 Feb 25 03:01:23 PM PST 24 3270460753 ps
T797 /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.2286156188 Feb 25 03:00:10 PM PST 24 Feb 25 03:00:12 PM PST 24 15158580 ps
T798 /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.1960642280 Feb 25 02:59:48 PM PST 24 Feb 25 02:59:54 PM PST 24 604867845 ps
T799 /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.261428515 Feb 25 02:59:29 PM PST 24 Feb 25 02:59:35 PM PST 24 43465960 ps
T154 /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.1632883857 Feb 25 03:00:04 PM PST 24 Feb 25 03:01:40 PM PST 24 756706657 ps
T800 /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.1698900555 Feb 25 02:59:43 PM PST 24 Feb 25 02:59:45 PM PST 24 13251864 ps
T170 /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.718834728 Feb 25 02:59:37 PM PST 24 Feb 25 02:59:41 PM PST 24 117077260 ps
T801 /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.2686719999 Feb 25 03:00:12 PM PST 24 Feb 25 03:00:13 PM PST 24 7825132 ps
T802 /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.595107091 Feb 25 03:00:00 PM PST 24 Feb 25 03:00:11 PM PST 24 142137417 ps
T803 /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.472806463 Feb 25 02:59:29 PM PST 24 Feb 25 02:59:31 PM PST 24 18981016 ps
T151 /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.2408390872 Feb 25 02:59:48 PM PST 24 Feb 25 03:02:34 PM PST 24 2321069643 ps
T804 /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.2236825289 Feb 25 02:59:54 PM PST 24 Feb 25 03:00:37 PM PST 24 1281538881 ps
T805 /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.1236332575 Feb 25 03:00:10 PM PST 24 Feb 25 03:00:11 PM PST 24 11603370 ps
T806 /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.3043633191 Feb 25 02:59:39 PM PST 24 Feb 25 03:00:00 PM PST 24 591250290 ps
T807 /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.1419422956 Feb 25 03:00:31 PM PST 24 Feb 25 03:00:32 PM PST 24 17132678 ps
T808 /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.1277538205 Feb 25 03:00:09 PM PST 24 Feb 25 03:00:11 PM PST 24 7582445 ps
T809 /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.874077160 Feb 25 02:59:25 PM PST 24 Feb 25 02:59:26 PM PST 24 10763914 ps
T810 /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.2770385670 Feb 25 03:00:12 PM PST 24 Feb 25 03:00:13 PM PST 24 9374267 ps
T174 /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.2760405687 Feb 25 03:00:05 PM PST 24 Feb 25 03:00:09 PM PST 24 62896835 ps
T811 /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.1124661884 Feb 25 03:00:02 PM PST 24 Feb 25 03:00:04 PM PST 24 12339567 ps
T172 /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.3065684372 Feb 25 02:59:37 PM PST 24 Feb 25 03:00:17 PM PST 24 757510393 ps
T812 /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.3668020887 Feb 25 02:59:40 PM PST 24 Feb 25 03:00:00 PM PST 24 253323869 ps
T813 /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.687890086 Feb 25 02:59:26 PM PST 24 Feb 25 02:59:37 PM PST 24 229876879 ps
T814 /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.735540524 Feb 25 03:00:07 PM PST 24 Feb 25 03:00:09 PM PST 24 13155983 ps
T815 /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.311380267 Feb 25 02:59:51 PM PST 24 Feb 25 03:01:31 PM PST 24 774069445 ps
T816 /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.3414864898 Feb 25 03:00:05 PM PST 24 Feb 25 03:00:07 PM PST 24 10416368 ps
T817 /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.3787967399 Feb 25 03:00:02 PM PST 24 Feb 25 03:00:44 PM PST 24 3926170886 ps
T818 /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.881157179 Feb 25 03:00:03 PM PST 24 Feb 25 03:00:09 PM PST 24 38242307 ps
T134 /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.2123961471 Feb 25 02:59:37 PM PST 24 Feb 25 03:05:09 PM PST 24 4852814810 ps
T157 /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.1530352821 Feb 25 02:59:26 PM PST 24 Feb 25 03:05:11 PM PST 24 2145787740 ps
T819 /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.160529737 Feb 25 02:59:59 PM PST 24 Feb 25 03:00:04 PM PST 24 161779129 ps
T159 /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.3598928239 Feb 25 02:59:44 PM PST 24 Feb 25 03:05:26 PM PST 24 4314185060 ps
T161 /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.1176183145 Feb 25 02:59:59 PM PST 24 Feb 25 03:03:44 PM PST 24 2397265972 ps
T820 /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.506724353 Feb 25 03:00:16 PM PST 24 Feb 25 03:00:18 PM PST 24 22658587 ps
T821 /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.2632847926 Feb 25 02:59:55 PM PST 24 Feb 25 03:00:04 PM PST 24 446066513 ps
T822 /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.3881896140 Feb 25 03:00:00 PM PST 24 Feb 25 03:00:06 PM PST 24 39989928 ps
T823 /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.626722797 Feb 25 03:00:02 PM PST 24 Feb 25 03:00:11 PM PST 24 87487641 ps
T824 /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.1026520461 Feb 25 02:59:48 PM PST 24 Feb 25 03:00:12 PM PST 24 1229215763 ps
T158 /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.580406581 Feb 25 02:59:44 PM PST 24 Feb 25 03:18:20 PM PST 24 73899989289 ps
T825 /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.1879113521 Feb 25 03:00:01 PM PST 24 Feb 25 03:00:40 PM PST 24 626198650 ps
T826 /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.810652499 Feb 25 02:59:26 PM PST 24 Feb 25 02:59:36 PM PST 24 394175655 ps
T827 /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.771900978 Feb 25 02:59:46 PM PST 24 Feb 25 03:00:34 PM PST 24 691369717 ps
T180 /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.1042823910 Feb 25 02:59:51 PM PST 24 Feb 25 03:00:37 PM PST 24 5380507708 ps
T828 /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.2975543281 Feb 25 03:00:03 PM PST 24 Feb 25 03:00:04 PM PST 24 7742732 ps
T155 /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.2148234369 Feb 25 03:00:05 PM PST 24 Feb 25 03:01:47 PM PST 24 1480161059 ps
T829 /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.3963358056 Feb 25 03:00:11 PM PST 24 Feb 25 03:00:12 PM PST 24 13967315 ps
T830 /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.3696891155 Feb 25 02:59:27 PM PST 24 Feb 25 02:59:32 PM PST 24 58464892 ps
T831 /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.3888642953 Feb 25 02:59:23 PM PST 24 Feb 25 02:59:33 PM PST 24 130093836 ps
T832 /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.3422505052 Feb 25 02:59:31 PM PST 24 Feb 25 02:59:50 PM PST 24 229409791 ps
T833 /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.189513469 Feb 25 02:59:27 PM PST 24 Feb 25 02:59:29 PM PST 24 6390764 ps
T156 /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.2802881528 Feb 25 02:59:37 PM PST 24 Feb 25 03:15:15 PM PST 24 12175986973 ps
T834 /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.160140930 Feb 25 03:00:00 PM PST 24 Feb 25 03:00:09 PM PST 24 472994322 ps
T160 /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.3489516176 Feb 25 03:00:04 PM PST 24 Feb 25 03:10:49 PM PST 24 19977106985 ps
T835 /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.220217 Feb 25 02:59:43 PM PST 24 Feb 25 02:59:44 PM PST 24 12151425 ps
T836 /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.3396291025 Feb 25 03:00:05 PM PST 24 Feb 25 03:01:39 PM PST 24 13597612738 ps

Test location /workspace/coverage/default/40.alert_handler_entropy.2944974169
Short name T15
Test name
Test status
Simulation time 33506358492 ps
CPU time 1259.8 seconds
Started Feb 25 03:22:02 PM PST 24
Finished Feb 25 03:43:02 PM PST 24
Peak memory 286308 kb
Host smart-b8fd17cc-a20c-4c27-8acf-6aa6964206b9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944974169 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_entropy.2944974169
Directory /workspace/40.alert_handler_entropy/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all_with_rand_reset.1530438689
Short name T18
Test name
Test status
Simulation time 32309081226 ps
CPU time 575.61 seconds
Started Feb 25 03:21:34 PM PST 24
Finished Feb 25 03:31:10 PM PST 24
Peak memory 266236 kb
Host smart-1347c010-afdc-4dea-a7ea-39ded61a86dc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530438689 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.alert_handler_stress_all_with_rand_reset.1530438689
Directory /workspace/34.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.alert_handler_sec_cm.2085915885
Short name T14
Test name
Test status
Simulation time 569144394 ps
CPU time 26.68 seconds
Started Feb 25 03:19:59 PM PST 24
Finished Feb 25 03:20:26 PM PST 24
Peak memory 276212 kb
Host smart-c9d04dc0-e36c-4c23-b4ac-50928bb6b1fa
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2085915885 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sec_cm.2085915885
Directory /workspace/2.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/18.alert_handler_entropy.3146156443
Short name T5
Test name
Test status
Simulation time 51503269710 ps
CPU time 2632.83 seconds
Started Feb 25 03:20:39 PM PST 24
Finished Feb 25 04:04:32 PM PST 24
Peak memory 288188 kb
Host smart-0537e6d9-0ba4-45a3-92fa-bef0f2fa1899
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146156443 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy.3146156443
Directory /workspace/18.alert_handler_entropy/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all_with_rand_reset.981204008
Short name T51
Test name
Test status
Simulation time 68055298472 ps
CPU time 4533.03 seconds
Started Feb 25 03:20:21 PM PST 24
Finished Feb 25 04:35:54 PM PST 24
Peak memory 313956 kb
Host smart-a89ad9bf-4f33-4462-8088-fee9f6608339
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981204008 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 4.alert_handler_stress_all_with_rand_reset.981204008
Directory /workspace/4.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.2543804872
Short name T189
Test name
Test status
Simulation time 3477733273 ps
CPU time 237.04 seconds
Started Feb 25 02:59:24 PM PST 24
Finished Feb 25 03:03:21 PM PST 24
Peak memory 236556 kb
Host smart-1b755463-c806-4cf3-a533-81e1931b3c10
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2543804872 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_bit_bash.2543804872
Directory /workspace/3.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all.2449276108
Short name T29
Test name
Test status
Simulation time 22774279693 ps
CPU time 1196.45 seconds
Started Feb 25 03:21:27 PM PST 24
Finished Feb 25 03:41:24 PM PST 24
Peak memory 272440 kb
Host smart-d5757b3a-9e55-49ab-ae84-6dec3bdaceee
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449276108 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_ha
ndler_stress_all.2449276108
Directory /workspace/31.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.3407782611
Short name T138
Test name
Test status
Simulation time 3078575678 ps
CPU time 172.44 seconds
Started Feb 25 02:59:59 PM PST 24
Finished Feb 25 03:02:52 PM PST 24
Peak memory 265536 kb
Host smart-62f04758-6525-446c-97d1-b1f2a458a402
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3407782611 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shadow_reg_err
ors.3407782611
Directory /workspace/18.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all_with_rand_reset.2403323085
Short name T94
Test name
Test status
Simulation time 531438989117 ps
CPU time 5017.43 seconds
Started Feb 25 03:20:48 PM PST 24
Finished Feb 25 04:44:26 PM PST 24
Peak memory 338460 kb
Host smart-dfbc23e9-e23e-49fe-9e29-a3f1f4f1436c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403323085 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.alert_handler_stress_all_with_rand_reset.2403323085
Directory /workspace/21.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.alert_handler_entropy.1894635588
Short name T52
Test name
Test status
Simulation time 44324090079 ps
CPU time 2750.82 seconds
Started Feb 25 03:22:25 PM PST 24
Finished Feb 25 04:08:17 PM PST 24
Peak memory 289216 kb
Host smart-eabb05af-3e07-4f01-b2af-5cadb32b99a3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1894635588 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_entropy.1894635588
Directory /workspace/45.alert_handler_entropy/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.791932996
Short name T140
Test name
Test status
Simulation time 25255288463 ps
CPU time 1121.85 seconds
Started Feb 25 02:59:54 PM PST 24
Finished Feb 25 03:18:36 PM PST 24
Peak memory 265492 kb
Host smart-dbcea9de-f7b5-4d69-989d-11f3fd8683ee
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791932996 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 13.alert_handler_shadow_reg_errors_with_csr_rw.791932996
Directory /workspace/13.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/6.alert_handler_lpg.371323020
Short name T7
Test name
Test status
Simulation time 58549453460 ps
CPU time 1648.73 seconds
Started Feb 25 03:20:27 PM PST 24
Finished Feb 25 03:47:56 PM PST 24
Peak memory 272232 kb
Host smart-d6cf014d-e24b-4831-b52f-a081af2d6bde
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371323020 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg.371323020
Directory /workspace/6.alert_handler_lpg/latest

Test location /workspace/coverage/default/2.alert_handler_lpg_stub_clk.2948033160
Short name T108
Test name
Test status
Simulation time 17368022513 ps
CPU time 1046.81 seconds
Started Feb 25 03:19:55 PM PST 24
Finished Feb 25 03:37:23 PM PST 24
Peak memory 272872 kb
Host smart-a29784e8-3bf4-4fca-8d82-16fb06056758
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948033160 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg_stub_clk.2948033160
Directory /workspace/2.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all_with_rand_reset.60503000
Short name T27
Test name
Test status
Simulation time 80050921500 ps
CPU time 7017.64 seconds
Started Feb 25 03:21:22 PM PST 24
Finished Feb 25 05:18:20 PM PST 24
Peak memory 394200 kb
Host smart-b543a22a-4eaf-4769-a103-aa4025a55cac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60503000 -assert nopostproc +UVM_TESTNAME=alert_
handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 31.alert_handler_stress_all_with_rand_reset.60503000
Directory /workspace/31.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.2792415163
Short name T124
Test name
Test status
Simulation time 194667875743 ps
CPU time 939.18 seconds
Started Feb 25 02:59:33 PM PST 24
Finished Feb 25 03:15:13 PM PST 24
Peak memory 265492 kb
Host smart-37f6a396-7ea8-4125-9464-c52e438d213d
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792415163 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.alert_handler_shadow_reg_errors_with_csr_rw.2792415163
Directory /workspace/3.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all_with_rand_reset.2409891616
Short name T96
Test name
Test status
Simulation time 205611045888 ps
CPU time 3500.05 seconds
Started Feb 25 03:20:40 PM PST 24
Finished Feb 25 04:19:01 PM PST 24
Peak memory 302576 kb
Host smart-e7691af2-b585-42d2-838e-690b24b56528
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409891616 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.alert_handler_stress_all_with_rand_reset.2409891616
Directory /workspace/12.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.3986501137
Short name T135
Test name
Test status
Simulation time 6782539420 ps
CPU time 469.19 seconds
Started Feb 25 02:59:26 PM PST 24
Finished Feb 25 03:07:15 PM PST 24
Peak memory 265808 kb
Host smart-f3e17b0e-8ec3-46f2-9755-b75f18ae4bdb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3986501137 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shadow_reg_erro
rs.3986501137
Directory /workspace/0.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/42.alert_handler_lpg.2630717206
Short name T36
Test name
Test status
Simulation time 50229454083 ps
CPU time 2841.94 seconds
Started Feb 25 03:22:07 PM PST 24
Finished Feb 25 04:09:30 PM PST 24
Peak memory 287220 kb
Host smart-33ecbab9-80b1-473e-ab22-1f2da39145b8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630717206 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg.2630717206
Directory /workspace/42.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.4203568166
Short name T184
Test name
Test status
Simulation time 216737246 ps
CPU time 11.37 seconds
Started Feb 25 03:00:01 PM PST 24
Finished Feb 25 03:00:12 PM PST 24
Peak memory 252288 kb
Host smart-d7da6ab7-0346-4e28-904f-a4679ab2e11e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203568166 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 13.alert_handler_csr_mem_rw_with_rand_reset.4203568166
Directory /workspace/13.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.4202669003
Short name T167
Test name
Test status
Simulation time 12287560 ps
CPU time 1.5 seconds
Started Feb 25 02:59:28 PM PST 24
Finished Feb 25 02:59:30 PM PST 24
Peak memory 235780 kb
Host smart-8706accc-b292-4a63-bae6-ee10e9935fb8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4202669003 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_intr_test.4202669003
Directory /workspace/4.alert_handler_intr_test/latest

Test location /workspace/coverage/default/12.alert_handler_entropy_stress.3799161939
Short name T85
Test name
Test status
Simulation time 857145337 ps
CPU time 20.37 seconds
Started Feb 25 03:20:38 PM PST 24
Finished Feb 25 03:20:58 PM PST 24
Peak memory 240032 kb
Host smart-4a12d824-1885-4a2a-bda0-2b501b702b36
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3799161939 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy_stress.3799161939
Directory /workspace/12.alert_handler_entropy_stress/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.2123961471
Short name T134
Test name
Test status
Simulation time 4852814810 ps
CPU time 332.4 seconds
Started Feb 25 02:59:37 PM PST 24
Finished Feb 25 03:05:09 PM PST 24
Peak memory 271360 kb
Host smart-c9c4a8b4-30ee-4dbb-8743-356d4c0ebf27
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2123961471 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shadow_reg_erro
rs.2123961471
Directory /workspace/8.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/5.alert_handler_ping_timeout.4248197209
Short name T290
Test name
Test status
Simulation time 214651660429 ps
CPU time 713.02 seconds
Started Feb 25 03:20:30 PM PST 24
Finished Feb 25 03:32:23 PM PST 24
Peak memory 246972 kb
Host smart-b0be60b3-23e9-45c6-88b4-01bf9401bbad
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248197209 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_ping_timeout.4248197209
Directory /workspace/5.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_lpg.2615022148
Short name T68
Test name
Test status
Simulation time 41031978842 ps
CPU time 1068.26 seconds
Started Feb 25 03:20:30 PM PST 24
Finished Feb 25 03:38:19 PM PST 24
Peak memory 264692 kb
Host smart-e7f776ec-72d4-4125-a802-6733443fd80c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2615022148 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg.2615022148
Directory /workspace/11.alert_handler_lpg/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all.4148814371
Short name T8
Test name
Test status
Simulation time 83235798745 ps
CPU time 3603.87 seconds
Started Feb 25 03:21:34 PM PST 24
Finished Feb 25 04:21:39 PM PST 24
Peak memory 304036 kb
Host smart-a555dc5c-57fc-4938-b169-69343305507e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148814371 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_ha
ndler_stress_all.4148814371
Directory /workspace/34.alert_handler_stress_all/latest

Test location /workspace/coverage/default/20.alert_handler_ping_timeout.2061097973
Short name T315
Test name
Test status
Simulation time 22761130929 ps
CPU time 576.55 seconds
Started Feb 25 03:20:41 PM PST 24
Finished Feb 25 03:30:18 PM PST 24
Peak memory 247180 kb
Host smart-c88f4a72-2739-40bf-b9fd-6df559d67c13
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061097973 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_ping_timeout.2061097973
Directory /workspace/20.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.2802881528
Short name T156
Test name
Test status
Simulation time 12175986973 ps
CPU time 938.12 seconds
Started Feb 25 02:59:37 PM PST 24
Finished Feb 25 03:15:15 PM PST 24
Peak memory 265724 kb
Host smart-0939119a-f643-4573-88e2-de8035bc67fb
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802881528 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 10.alert_handler_shadow_reg_errors_with_csr_rw.2802881528
Directory /workspace/10.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/49.alert_handler_lpg.1494475135
Short name T323
Test name
Test status
Simulation time 244375763349 ps
CPU time 3318.14 seconds
Started Feb 25 03:22:54 PM PST 24
Finished Feb 25 04:18:12 PM PST 24
Peak memory 288728 kb
Host smart-0e0e0989-ae23-4f28-acac-b5be662fa589
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494475135 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg.1494475135
Directory /workspace/49.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.4198180777
Short name T136
Test name
Test status
Simulation time 3041129268 ps
CPU time 186.77 seconds
Started Feb 25 02:59:40 PM PST 24
Finished Feb 25 03:02:47 PM PST 24
Peak memory 265592 kb
Host smart-029a6316-89f6-46bb-bcfa-b44995be4291
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4198180777 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shadow_reg_erro
rs.4198180777
Directory /workspace/7.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/0.alert_handler_lpg.1373789061
Short name T334
Test name
Test status
Simulation time 51278369662 ps
CPU time 2871.22 seconds
Started Feb 25 03:20:08 PM PST 24
Finished Feb 25 04:08:00 PM PST 24
Peak memory 283896 kb
Host smart-4edd4ab4-9459-4e0e-9721-73473fd85e90
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1373789061 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg.1373789061
Directory /workspace/0.alert_handler_lpg/latest

Test location /workspace/coverage/default/38.alert_handler_ping_timeout.1723727543
Short name T273
Test name
Test status
Simulation time 9517746502 ps
CPU time 393.97 seconds
Started Feb 25 03:22:04 PM PST 24
Finished Feb 25 03:28:38 PM PST 24
Peak memory 247180 kb
Host smart-a71e3ebf-03ec-468a-94f1-04ddccde983d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1723727543 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_ping_timeout.1723727543
Directory /workspace/38.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.2872242391
Short name T178
Test name
Test status
Simulation time 61446839 ps
CPU time 3.4 seconds
Started Feb 25 02:59:44 PM PST 24
Finished Feb 25 02:59:47 PM PST 24
Peak memory 236612 kb
Host smart-465d1d84-15d7-42e2-b200-aaeb2d94f00a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2872242391 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_intg_err.2872242391
Directory /workspace/12.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all_with_rand_reset.965839363
Short name T197
Test name
Test status
Simulation time 203197495081 ps
CPU time 4531.22 seconds
Started Feb 25 03:22:04 PM PST 24
Finished Feb 25 04:37:36 PM PST 24
Peak memory 322164 kb
Host smart-9341ee86-6cee-474b-961a-7f821974bca3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965839363 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 38.alert_handler_stress_all_with_rand_reset.965839363
Directory /workspace/38.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all_with_rand_reset.2184673162
Short name T31
Test name
Test status
Simulation time 146817905263 ps
CPU time 2460.41 seconds
Started Feb 25 03:20:25 PM PST 24
Finished Feb 25 04:01:26 PM PST 24
Peak memory 289040 kb
Host smart-46dd5031-2f3d-4506-81bd-6ea899651d3a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184673162 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.alert_handler_stress_all_with_rand_reset.2184673162
Directory /workspace/3.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.1357885047
Short name T128
Test name
Test status
Simulation time 23263618609 ps
CPU time 622.1 seconds
Started Feb 25 02:59:59 PM PST 24
Finished Feb 25 03:10:21 PM PST 24
Peak memory 265664 kb
Host smart-cc4c4aad-a4d2-448a-8e37-8dd2d0ae0f2e
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357885047 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 19.alert_handler_shadow_reg_errors_with_csr_rw.1357885047
Directory /workspace/19.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all.2568616239
Short name T244
Test name
Test status
Simulation time 253196276753 ps
CPU time 4072.35 seconds
Started Feb 25 03:22:46 PM PST 24
Finished Feb 25 04:30:40 PM PST 24
Peak memory 305384 kb
Host smart-986df995-8248-4005-9083-b548cf408507
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568616239 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_ha
ndler_stress_all.2568616239
Directory /workspace/47.alert_handler_stress_all/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all_with_rand_reset.2714446943
Short name T46
Test name
Test status
Simulation time 60392784947 ps
CPU time 4564.55 seconds
Started Feb 25 03:20:41 PM PST 24
Finished Feb 25 04:36:46 PM PST 24
Peak memory 305772 kb
Host smart-ceeb6370-971d-4657-88be-22f470b2bfa2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714446943 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.alert_handler_stress_all_with_rand_reset.2714446943
Directory /workspace/13.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.alert_handler_ping_timeout.1010459856
Short name T306
Test name
Test status
Simulation time 50842505816 ps
CPU time 558.57 seconds
Started Feb 25 03:20:33 PM PST 24
Finished Feb 25 03:29:51 PM PST 24
Peak memory 246972 kb
Host smart-bebac20f-1f17-4659-a081-37bd63d18a94
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010459856 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_ping_timeout.1010459856
Directory /workspace/13.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.4119370370
Short name T233
Test name
Test status
Simulation time 14381426 ps
CPU time 1.82 seconds
Started Feb 25 03:00:02 PM PST 24
Finished Feb 25 03:00:04 PM PST 24
Peak memory 235856 kb
Host smart-544c9b40-0552-4e62-affe-8c75a6f617b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4119370370 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_intr_test.4119370370
Directory /workspace/14.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.2096583569
Short name T126
Test name
Test status
Simulation time 8232259220 ps
CPU time 292.92 seconds
Started Feb 25 02:59:43 PM PST 24
Finished Feb 25 03:04:36 PM PST 24
Peak memory 268780 kb
Host smart-f6d8a3db-9b95-479c-8184-c42346fdbb3d
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096583569 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.alert_handler_shadow_reg_errors_with_csr_rw.2096583569
Directory /workspace/7.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/38.alert_handler_lpg.3049440474
Short name T331
Test name
Test status
Simulation time 58703911941 ps
CPU time 2988.94 seconds
Started Feb 25 03:22:01 PM PST 24
Finished Feb 25 04:11:50 PM PST 24
Peak memory 287512 kb
Host smart-41022d24-faee-412c-8646-ff98b6f918ea
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3049440474 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg.3049440474
Directory /workspace/38.alert_handler_lpg/latest

Test location /workspace/coverage/default/0.alert_handler_sec_cm.2632816426
Short name T12
Test name
Test status
Simulation time 3124410470 ps
CPU time 20.06 seconds
Started Feb 25 03:19:45 PM PST 24
Finished Feb 25 03:20:05 PM PST 24
Peak memory 273260 kb
Host smart-ada8febb-634e-4b17-bc29-9ee62644e5c2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2632816426 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sec_cm.2632816426
Directory /workspace/0.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all.2472892273
Short name T63
Test name
Test status
Simulation time 14441110295 ps
CPU time 1675.11 seconds
Started Feb 25 03:20:33 PM PST 24
Finished Feb 25 03:48:28 PM PST 24
Peak memory 304484 kb
Host smart-7601c6a9-61b9-42fe-8adf-51ac67f77251
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472892273 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_han
dler_stress_all.2472892273
Directory /workspace/8.alert_handler_stress_all/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all.1889894198
Short name T28
Test name
Test status
Simulation time 67550449911 ps
CPU time 3815.59 seconds
Started Feb 25 03:20:26 PM PST 24
Finished Feb 25 04:24:03 PM PST 24
Peak memory 299920 kb
Host smart-2e6bd19f-c9b7-48ca-892b-be2a458c6726
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889894198 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_ha
ndler_stress_all.1889894198
Directory /workspace/10.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.3497792466
Short name T132
Test name
Test status
Simulation time 14600598633 ps
CPU time 480.25 seconds
Started Feb 25 02:59:43 PM PST 24
Finished Feb 25 03:07:43 PM PST 24
Peak memory 265656 kb
Host smart-11bf4f19-8f12-4853-a68a-22b3fd8a02b2
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497792466 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.alert_handler_shadow_reg_errors_with_csr_rw.3497792466
Directory /workspace/6.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/21.alert_handler_ping_timeout.2963595390
Short name T314
Test name
Test status
Simulation time 3591053044 ps
CPU time 158.53 seconds
Started Feb 25 03:20:59 PM PST 24
Finished Feb 25 03:23:38 PM PST 24
Peak memory 247192 kb
Host smart-455356e5-71ac-4a35-b632-9cf2a69bbc9d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963595390 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_ping_timeout.2963595390
Directory /workspace/21.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_ping_timeout.577415821
Short name T322
Test name
Test status
Simulation time 2727493722 ps
CPU time 118.61 seconds
Started Feb 25 03:20:31 PM PST 24
Finished Feb 25 03:22:29 PM PST 24
Peak memory 247156 kb
Host smart-956f5a89-8d19-49b1-b7d7-4601f2637424
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577415821 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_ping_timeout.577415821
Directory /workspace/15.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_lpg.406130863
Short name T344
Test name
Test status
Simulation time 58169461912 ps
CPU time 1874.8 seconds
Started Feb 25 03:21:22 PM PST 24
Finished Feb 25 03:52:37 PM PST 24
Peak memory 272348 kb
Host smart-c5704abe-b8b2-4524-9687-53b6d18e28f9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406130863 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg.406130863
Directory /workspace/30.alert_handler_lpg/latest

Test location /workspace/coverage/default/8.alert_handler_lpg.186846955
Short name T335
Test name
Test status
Simulation time 106316716620 ps
CPU time 2138.03 seconds
Started Feb 25 03:20:27 PM PST 24
Finished Feb 25 03:56:05 PM PST 24
Peak memory 281072 kb
Host smart-c2e34e98-e820-4bd5-9edf-36eaec6779c4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186846955 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg.186846955
Directory /workspace/8.alert_handler_lpg/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all.4082634325
Short name T250
Test name
Test status
Simulation time 250216053158 ps
CPU time 2885.17 seconds
Started Feb 25 03:22:00 PM PST 24
Finished Feb 25 04:10:05 PM PST 24
Peak memory 289160 kb
Host smart-fb7189d2-9874-4154-8008-08fbafec337c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082634325 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_ha
ndler_stress_all.4082634325
Directory /workspace/38.alert_handler_stress_all/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all.4234034368
Short name T25
Test name
Test status
Simulation time 71217237632 ps
CPU time 3642.75 seconds
Started Feb 25 03:22:12 PM PST 24
Finished Feb 25 04:22:56 PM PST 24
Peak memory 297420 kb
Host smart-da02315c-5c26-478f-ba95-d3d5ad03a36c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234034368 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_ha
ndler_stress_all.4234034368
Directory /workspace/41.alert_handler_stress_all/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all_with_rand_reset.2492085438
Short name T111
Test name
Test status
Simulation time 29870364179 ps
CPU time 3144.1 seconds
Started Feb 25 03:19:58 PM PST 24
Finished Feb 25 04:12:23 PM PST 24
Peak memory 305640 kb
Host smart-fd753f08-be29-4419-bad7-637b18b57307
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492085438 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.alert_handler_stress_all_with_rand_reset.2492085438
Directory /workspace/1.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.1632883857
Short name T154
Test name
Test status
Simulation time 756706657 ps
CPU time 95.15 seconds
Started Feb 25 03:00:04 PM PST 24
Finished Feb 25 03:01:40 PM PST 24
Peak memory 257164 kb
Host smart-98dc5bdd-35e8-4210-9d7f-c299a92d90c4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1632883857 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shadow_reg_err
ors.1632883857
Directory /workspace/15.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.339834595
Short name T127
Test name
Test status
Simulation time 36481453099 ps
CPU time 530.15 seconds
Started Feb 25 02:59:30 PM PST 24
Finished Feb 25 03:08:21 PM PST 24
Peak memory 268012 kb
Host smart-e077858a-dfe4-4084-9e6c-d848baa26fa0
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339834595 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.alert_handler_shadow_reg_errors_with_csr_rw.339834595
Directory /workspace/4.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/0.alert_handler_alert_accum_saturation.2193494195
Short name T3
Test name
Test status
Simulation time 43923238 ps
CPU time 3.66 seconds
Started Feb 25 03:19:47 PM PST 24
Finished Feb 25 03:19:51 PM PST 24
Peak memory 248516 kb
Host smart-7b5309e7-f4e8-4ed2-9457-1518bed03b28
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2193494195 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_alert_accum_saturation.2193494195
Directory /workspace/0.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/1.alert_handler_alert_accum_saturation.1205221533
Short name T215
Test name
Test status
Simulation time 45892292 ps
CPU time 3.86 seconds
Started Feb 25 03:19:57 PM PST 24
Finished Feb 25 03:20:01 PM PST 24
Peak memory 248508 kb
Host smart-559ada93-8a76-4674-a9c9-8e9d0ec379a5
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1205221533 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_alert_accum_saturation.1205221533
Directory /workspace/1.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/11.alert_handler_alert_accum_saturation.3064213293
Short name T201
Test name
Test status
Simulation time 35004487 ps
CPU time 3.19 seconds
Started Feb 25 03:20:36 PM PST 24
Finished Feb 25 03:20:39 PM PST 24
Peak memory 248492 kb
Host smart-11cc8004-78d2-494a-8b51-392cf6433e9d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3064213293 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_alert_accum_saturation.3064213293
Directory /workspace/11.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/13.alert_handler_alert_accum_saturation.556003141
Short name T205
Test name
Test status
Simulation time 41307890 ps
CPU time 2.31 seconds
Started Feb 25 03:20:36 PM PST 24
Finished Feb 25 03:20:38 PM PST 24
Peak memory 248496 kb
Host smart-a36440b1-a438-424e-af26-f42c40a3607c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=556003141 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_alert_accum_saturation.556003141
Directory /workspace/13.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/18.alert_handler_lpg.3744658738
Short name T65
Test name
Test status
Simulation time 105718513119 ps
CPU time 1683.72 seconds
Started Feb 25 03:20:44 PM PST 24
Finished Feb 25 03:48:48 PM PST 24
Peak memory 288408 kb
Host smart-0e4846cf-eeae-4524-ace6-6251a7fc3f77
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744658738 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg.3744658738
Directory /workspace/18.alert_handler_lpg/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all_with_rand_reset.1073662834
Short name T219
Test name
Test status
Simulation time 125440425443 ps
CPU time 6024.08 seconds
Started Feb 25 03:21:07 PM PST 24
Finished Feb 25 05:01:32 PM PST 24
Peak memory 371236 kb
Host smart-a70936c3-180a-474b-a53c-bcc22f3606f0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073662834 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 26.alert_handler_stress_all_with_rand_reset.1073662834
Directory /workspace/26.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.alert_handler_ping_timeout.3270511242
Short name T310
Test name
Test status
Simulation time 73054979839 ps
CPU time 769.06 seconds
Started Feb 25 03:20:14 PM PST 24
Finished Feb 25 03:33:04 PM PST 24
Peak memory 247192 kb
Host smart-ee7f257a-690a-40bb-92a8-29661e1c6601
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270511242 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_ping_timeout.3270511242
Directory /workspace/3.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all_with_rand_reset.505290562
Short name T236
Test name
Test status
Simulation time 47155817210 ps
CPU time 5188.62 seconds
Started Feb 25 03:22:13 PM PST 24
Finished Feb 25 04:48:42 PM PST 24
Peak memory 354364 kb
Host smart-dd2f2bed-75e5-4ffb-9316-6b4a4c7c41aa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505290562 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 41.alert_handler_stress_all_with_rand_reset.505290562
Directory /workspace/41.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.3818130785
Short name T139
Test name
Test status
Simulation time 3224971192 ps
CPU time 205.83 seconds
Started Feb 25 02:59:26 PM PST 24
Finished Feb 25 03:02:52 PM PST 24
Peak memory 271736 kb
Host smart-25fd8d02-a8c8-4398-8f4f-fee1413490c5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3818130785 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shadow_reg_erro
rs.3818130785
Directory /workspace/3.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.2408390872
Short name T151
Test name
Test status
Simulation time 2321069643 ps
CPU time 165.23 seconds
Started Feb 25 02:59:48 PM PST 24
Finished Feb 25 03:02:34 PM PST 24
Peak memory 265484 kb
Host smart-1add5af5-ba00-48eb-a38d-ff21a0f2c327
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2408390872 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shadow_reg_err
ors.2408390872
Directory /workspace/11.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.2476032052
Short name T235
Test name
Test status
Simulation time 9643033 ps
CPU time 1.67 seconds
Started Feb 25 02:59:29 PM PST 24
Finished Feb 25 02:59:31 PM PST 24
Peak memory 235744 kb
Host smart-002ec63c-078a-4c2e-a603-27afe2ba0b19
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2476032052 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_intr_test.2476032052
Directory /workspace/1.alert_handler_intr_test/latest

Test location /workspace/coverage/default/1.alert_handler_sig_int_fail.3222956527
Short name T19
Test name
Test status
Simulation time 1787913180 ps
CPU time 53.63 seconds
Started Feb 25 03:19:57 PM PST 24
Finished Feb 25 03:20:51 PM PST 24
Peak memory 246680 kb
Host smart-73d5d423-134c-49d0-a04b-66c48b0ad150
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32229
56527 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sig_int_fail.3222956527
Directory /workspace/1.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/10.alert_handler_lpg.2940814484
Short name T593
Test name
Test status
Simulation time 49341147638 ps
CPU time 2809.57 seconds
Started Feb 25 03:21:00 PM PST 24
Finished Feb 25 04:07:51 PM PST 24
Peak memory 281092 kb
Host smart-08cadc90-3725-4620-ab5b-4759f2382e14
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940814484 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg.2940814484
Directory /workspace/10.alert_handler_lpg/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all.3354063018
Short name T73
Test name
Test status
Simulation time 30474851595 ps
CPU time 1817.59 seconds
Started Feb 25 03:20:31 PM PST 24
Finished Feb 25 03:50:48 PM PST 24
Peak memory 288892 kb
Host smart-8a5a7005-2d82-4898-898e-e62a910d7e76
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354063018 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_ha
ndler_stress_all.3354063018
Directory /workspace/12.alert_handler_stress_all/latest

Test location /workspace/coverage/default/15.alert_handler_random_classes.1666253608
Short name T267
Test name
Test status
Simulation time 13509897685 ps
CPU time 51.41 seconds
Started Feb 25 03:20:33 PM PST 24
Finished Feb 25 03:21:24 PM PST 24
Peak memory 246660 kb
Host smart-a791678e-39b1-432e-8f44-1d3e45e5a75a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16662
53608 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_classes.1666253608
Directory /workspace/15.alert_handler_random_classes/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all.2733023384
Short name T109
Test name
Test status
Simulation time 96788926975 ps
CPU time 2621.4 seconds
Started Feb 25 03:20:32 PM PST 24
Finished Feb 25 04:04:14 PM PST 24
Peak memory 288736 kb
Host smart-9c52d32e-facd-454d-8ddd-109093eb5d19
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733023384 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_ha
ndler_stress_all.2733023384
Directory /workspace/15.alert_handler_stress_all/latest

Test location /workspace/coverage/default/16.alert_handler_ping_timeout.1004808920
Short name T542
Test name
Test status
Simulation time 6978956485 ps
CPU time 61.89 seconds
Started Feb 25 03:20:41 PM PST 24
Finished Feb 25 03:21:43 PM PST 24
Peak memory 247188 kb
Host smart-3f1381bc-bd5e-4573-8199-4ffb137532ae
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004808920 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_ping_timeout.1004808920
Directory /workspace/16.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_sig_int_fail.2844541100
Short name T260
Test name
Test status
Simulation time 186726119 ps
CPU time 25.34 seconds
Started Feb 25 03:20:40 PM PST 24
Finished Feb 25 03:21:05 PM PST 24
Peak memory 246624 kb
Host smart-df0b129e-38c4-4489-9a59-e0ce4eaefefe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28445
41100 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_sig_int_fail.2844541100
Directory /workspace/16.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/18.alert_handler_sig_int_fail.130830888
Short name T241
Test name
Test status
Simulation time 779552239 ps
CPU time 44.82 seconds
Started Feb 25 03:20:41 PM PST 24
Finished Feb 25 03:21:26 PM PST 24
Peak memory 254880 kb
Host smart-fab22d0c-8f47-40cc-8737-517eb5930cc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13083
0888 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_sig_int_fail.130830888
Directory /workspace/18.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/19.alert_handler_ping_timeout.856155920
Short name T295
Test name
Test status
Simulation time 73182013303 ps
CPU time 173.07 seconds
Started Feb 25 03:20:50 PM PST 24
Finished Feb 25 03:23:43 PM PST 24
Peak memory 247184 kb
Host smart-93132b62-a4d2-4e82-a93d-247222b213b1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856155920 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_ping_timeout.856155920
Directory /workspace/19.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all.3447399857
Short name T589
Test name
Test status
Simulation time 77190835878 ps
CPU time 2302.46 seconds
Started Feb 25 03:20:11 PM PST 24
Finished Feb 25 03:58:35 PM PST 24
Peak memory 285784 kb
Host smart-1d551ed7-510d-4dde-aef9-aece3addebd2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447399857 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_han
dler_stress_all.3447399857
Directory /workspace/2.alert_handler_stress_all/latest

Test location /workspace/coverage/default/22.alert_handler_sig_int_fail.1819632351
Short name T248
Test name
Test status
Simulation time 393805018 ps
CPU time 14.98 seconds
Started Feb 25 03:20:42 PM PST 24
Finished Feb 25 03:20:57 PM PST 24
Peak memory 252504 kb
Host smart-98d65908-a653-4eb2-b921-fdffe03b93e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18196
32351 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_sig_int_fail.1819632351
Directory /workspace/22.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all_with_rand_reset.3198246305
Short name T120
Test name
Test status
Simulation time 77736713808 ps
CPU time 7013.08 seconds
Started Feb 25 03:20:58 PM PST 24
Finished Feb 25 05:17:52 PM PST 24
Peak memory 370976 kb
Host smart-33ca4283-2c4f-45b9-a21c-3f80fa828100
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198246305 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 24.alert_handler_stress_all_with_rand_reset.3198246305
Directory /workspace/24.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.alert_handler_ping_timeout.1698827789
Short name T298
Test name
Test status
Simulation time 12873039422 ps
CPU time 63.94 seconds
Started Feb 25 03:21:09 PM PST 24
Finished Feb 25 03:22:14 PM PST 24
Peak memory 247200 kb
Host smart-597a261d-5d51-4b7e-a0dd-e8097cc91ac4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698827789 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_ping_timeout.1698827789
Directory /workspace/28.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all_with_rand_reset.4009140016
Short name T42
Test name
Test status
Simulation time 368111845768 ps
CPU time 8093.33 seconds
Started Feb 25 03:21:11 PM PST 24
Finished Feb 25 05:36:05 PM PST 24
Peak memory 436276 kb
Host smart-3e1ca865-a5ba-4e8a-a4dd-7a88002066d2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009140016 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.alert_handler_stress_all_with_rand_reset.4009140016
Directory /workspace/28.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.alert_handler_sig_int_fail.1069939635
Short name T257
Test name
Test status
Simulation time 2628425447 ps
CPU time 46.29 seconds
Started Feb 25 03:20:02 PM PST 24
Finished Feb 25 03:20:49 PM PST 24
Peak memory 255356 kb
Host smart-da91c10c-2bbf-47e5-8759-f8a09103d93b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10699
39635 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sig_int_fail.1069939635
Directory /workspace/3.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.1948203733
Short name T153
Test name
Test status
Simulation time 7001321451 ps
CPU time 140.29 seconds
Started Feb 25 02:59:42 PM PST 24
Finished Feb 25 03:02:02 PM PST 24
Peak memory 257260 kb
Host smart-230e114a-4c03-41c0-8e5c-5f2ffba22464
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1948203733 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shadow_reg_erro
rs.1948203733
Directory /workspace/6.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.3598928239
Short name T159
Test name
Test status
Simulation time 4314185060 ps
CPU time 341.22 seconds
Started Feb 25 02:59:44 PM PST 24
Finished Feb 25 03:05:26 PM PST 24
Peak memory 265480 kb
Host smart-f9428ba4-06d1-42ab-a54f-13e2bb576709
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598928239 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.alert_handler_shadow_reg_errors_with_csr_rw.3598928239
Directory /workspace/8.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.2540236530
Short name T176
Test name
Test status
Simulation time 929652809 ps
CPU time 65.89 seconds
Started Feb 25 02:59:53 PM PST 24
Finished Feb 25 03:01:00 PM PST 24
Peak memory 236800 kb
Host smart-34beffff-6d67-4ced-8132-6854a576246e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2540236530 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_intg_err.2540236530
Directory /workspace/10.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.3884770208
Short name T137
Test name
Test status
Simulation time 25373537593 ps
CPU time 909.2 seconds
Started Feb 25 03:00:01 PM PST 24
Finished Feb 25 03:15:11 PM PST 24
Peak memory 265484 kb
Host smart-b4cc6c32-7e61-49b3-b238-46ddb1325672
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884770208 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 15.alert_handler_shadow_reg_errors_with_csr_rw.3884770208
Directory /workspace/15.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.154109263
Short name T169
Test name
Test status
Simulation time 920466179 ps
CPU time 66.03 seconds
Started Feb 25 02:59:59 PM PST 24
Finished Feb 25 03:01:06 PM PST 24
Peak memory 236836 kb
Host smart-e21aecfa-ec45-488a-8100-07bdeff84ce4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=154109263 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_intg_err.154109263
Directory /workspace/16.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.661623449
Short name T181
Test name
Test status
Simulation time 1036385920 ps
CPU time 36.4 seconds
Started Feb 25 03:00:05 PM PST 24
Finished Feb 25 03:00:42 PM PST 24
Peak memory 248732 kb
Host smart-9d73947e-a955-4849-bd4c-ac880eb92756
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=661623449 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_intg_err.661623449
Directory /workspace/19.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.718834728
Short name T170
Test name
Test status
Simulation time 117077260 ps
CPU time 4.49 seconds
Started Feb 25 02:59:37 PM PST 24
Finished Feb 25 02:59:41 PM PST 24
Peak memory 237040 kb
Host smart-5fb6e794-0eb0-4fcf-b7c3-daf892bb3762
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=718834728 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_intg_err.718834728
Directory /workspace/6.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.2740318075
Short name T173
Test name
Test status
Simulation time 2098766600 ps
CPU time 75.82 seconds
Started Feb 25 03:00:09 PM PST 24
Finished Feb 25 03:01:25 PM PST 24
Peak memory 239468 kb
Host smart-bdd668b7-6588-4ed4-b3ed-9287ed8b46d6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2740318075 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_intg_err.2740318075
Directory /workspace/13.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.2760405687
Short name T174
Test name
Test status
Simulation time 62896835 ps
CPU time 3.46 seconds
Started Feb 25 03:00:05 PM PST 24
Finished Feb 25 03:00:09 PM PST 24
Peak memory 236600 kb
Host smart-9b7eeff4-3f89-4fff-aa72-1f9b3e007d9e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2760405687 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_intg_err.2760405687
Directory /workspace/15.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.3065684372
Short name T172
Test name
Test status
Simulation time 757510393 ps
CPU time 40.38 seconds
Started Feb 25 02:59:37 PM PST 24
Finished Feb 25 03:00:17 PM PST 24
Peak memory 240540 kb
Host smart-06e433a5-1c11-463e-ba81-b1acb28b74d4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3065684372 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_intg_err.3065684372
Directory /workspace/8.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.3571470678
Short name T131
Test name
Test status
Simulation time 6788340704 ps
CPU time 436.74 seconds
Started Feb 25 02:59:27 PM PST 24
Finished Feb 25 03:06:44 PM PST 24
Peak memory 265532 kb
Host smart-5e314532-3c61-46c9-961b-61dc5919daf5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3571470678 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shadow_reg_erro
rs.3571470678
Directory /workspace/1.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.1587652830
Short name T175
Test name
Test status
Simulation time 475856333 ps
CPU time 50.12 seconds
Started Feb 25 02:59:33 PM PST 24
Finished Feb 25 03:00:24 PM PST 24
Peak memory 239580 kb
Host smart-38bcfc16-4592-42cc-ab37-b1d0505f34d0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1587652830 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_intg_err.1587652830
Directory /workspace/1.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.1042823910
Short name T180
Test name
Test status
Simulation time 5380507708 ps
CPU time 46.14 seconds
Started Feb 25 02:59:51 PM PST 24
Finished Feb 25 03:00:37 PM PST 24
Peak memory 239512 kb
Host smart-f6a0b012-f31d-4bc6-b99e-c636aada2692
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1042823910 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_intg_err.1042823910
Directory /workspace/11.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.2463148952
Short name T162
Test name
Test status
Simulation time 70193384 ps
CPU time 2.56 seconds
Started Feb 25 02:59:29 PM PST 24
Finished Feb 25 02:59:32 PM PST 24
Peak memory 236604 kb
Host smart-64e6a183-02fe-4034-a7c2-ea3889f5b282
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2463148952 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_intg_err.2463148952
Directory /workspace/2.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.2702533733
Short name T171
Test name
Test status
Simulation time 63008335 ps
CPU time 3.99 seconds
Started Feb 25 02:59:29 PM PST 24
Finished Feb 25 02:59:34 PM PST 24
Peak memory 236976 kb
Host smart-fa37b919-cce3-43d7-b677-a380acfd7521
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2702533733 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_intg_err.2702533733
Directory /workspace/3.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.597520769
Short name T177
Test name
Test status
Simulation time 633976821 ps
CPU time 23.7 seconds
Started Feb 25 02:59:29 PM PST 24
Finished Feb 25 02:59:53 PM PST 24
Peak memory 248732 kb
Host smart-d9e4bf64-b991-4879-a80a-22e4e136d0f0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=597520769 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_intg_err.597520769
Directory /workspace/0.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.2505822811
Short name T179
Test name
Test status
Simulation time 1725432435 ps
CPU time 40.11 seconds
Started Feb 25 03:00:02 PM PST 24
Finished Feb 25 03:00:42 PM PST 24
Peak memory 236728 kb
Host smart-81e925aa-8241-4e9c-9124-bb09347ab30f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2505822811 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_intg_err.2505822811
Directory /workspace/17.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.3656852379
Short name T186
Test name
Test status
Simulation time 60281627 ps
CPU time 2.23 seconds
Started Feb 25 03:00:02 PM PST 24
Finished Feb 25 03:00:05 PM PST 24
Peak memory 236752 kb
Host smart-6341f143-bb61-438e-810b-b29944565327
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3656852379 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_intg_err.3656852379
Directory /workspace/18.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.1906992722
Short name T185
Test name
Test status
Simulation time 491982584 ps
CPU time 36.5 seconds
Started Feb 25 02:59:30 PM PST 24
Finished Feb 25 03:00:07 PM PST 24
Peak memory 239412 kb
Host smart-e1cab743-91ba-4bf1-ba7b-b9a0cc8d659e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1906992722 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_intg_err.1906992722
Directory /workspace/4.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.285042889
Short name T164
Test name
Test status
Simulation time 1052291103 ps
CPU time 74.8 seconds
Started Feb 25 02:59:29 PM PST 24
Finished Feb 25 03:00:44 PM PST 24
Peak memory 245276 kb
Host smart-d076c4bd-fd35-4d71-89bd-0fa39bac5772
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=285042889 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_intg_err.285042889
Directory /workspace/5.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.1994791972
Short name T168
Test name
Test status
Simulation time 1212720600 ps
CPU time 38.63 seconds
Started Feb 25 02:59:41 PM PST 24
Finished Feb 25 03:00:20 PM PST 24
Peak memory 248736 kb
Host smart-9600be56-2940-4f23-89c9-826e41850354
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1994791972 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_intg_err.1994791972
Directory /workspace/9.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/37.alert_handler_random_classes.2730904275
Short name T22
Test name
Test status
Simulation time 590180311 ps
CPU time 46.45 seconds
Started Feb 25 03:21:59 PM PST 24
Finished Feb 25 03:22:46 PM PST 24
Peak memory 253916 kb
Host smart-16714204-c513-4382-8429-3ad6121bbf48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27309
04275 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_classes.2730904275
Directory /workspace/37.alert_handler_random_classes/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.3887155190
Short name T724
Test name
Test status
Simulation time 1658924204 ps
CPU time 129.78 seconds
Started Feb 25 02:59:29 PM PST 24
Finished Feb 25 03:01:39 PM PST 24
Peak memory 236600 kb
Host smart-fb257e07-b20b-47e9-92d4-da88eda403b0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3887155190 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_aliasing.3887155190
Directory /workspace/0.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.2211376403
Short name T759
Test name
Test status
Simulation time 25900930469 ps
CPU time 427.63 seconds
Started Feb 25 02:59:27 PM PST 24
Finished Feb 25 03:06:34 PM PST 24
Peak memory 236672 kb
Host smart-ec403e31-8370-4e90-9114-adef766eb9be
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2211376403 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_bit_bash.2211376403
Directory /workspace/0.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.3358062372
Short name T787
Test name
Test status
Simulation time 101275960 ps
CPU time 5.16 seconds
Started Feb 25 02:59:25 PM PST 24
Finished Feb 25 02:59:30 PM PST 24
Peak memory 240580 kb
Host smart-8f655d34-2cc0-48b7-967b-ac2c8eae3a5c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3358062372 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_hw_reset.3358062372
Directory /workspace/0.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.810652499
Short name T826
Test name
Test status
Simulation time 394175655 ps
CPU time 10.23 seconds
Started Feb 25 02:59:26 PM PST 24
Finished Feb 25 02:59:36 PM PST 24
Peak memory 253480 kb
Host smart-e7ab561e-d635-486b-b6ca-d8a1339676b0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810652499 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 0.alert_handler_csr_mem_rw_with_rand_reset.810652499
Directory /workspace/0.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.3696891155
Short name T830
Test name
Test status
Simulation time 58464892 ps
CPU time 4.96 seconds
Started Feb 25 02:59:27 PM PST 24
Finished Feb 25 02:59:32 PM PST 24
Peak memory 235732 kb
Host smart-b6b12831-f709-4089-a0b3-8b91eb37fd57
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3696891155 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_rw.3696891155
Directory /workspace/0.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.2809308616
Short name T757
Test name
Test status
Simulation time 22055855 ps
CPU time 1.41 seconds
Started Feb 25 02:59:33 PM PST 24
Finished Feb 25 02:59:34 PM PST 24
Peak memory 236636 kb
Host smart-40e23d4b-37f7-40f6-bd6f-2ba684c6b0ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2809308616 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_intr_test.2809308616
Directory /workspace/0.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.1513109530
Short name T193
Test name
Test status
Simulation time 3483184875 ps
CPU time 19.31 seconds
Started Feb 25 02:59:33 PM PST 24
Finished Feb 25 02:59:52 PM PST 24
Peak memory 244876 kb
Host smart-db6d196d-0d1f-49a0-971a-7a1561415ce7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1513109530 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_same_csr_out
standing.1513109530
Directory /workspace/0.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.1507704197
Short name T147
Test name
Test status
Simulation time 17609534820 ps
CPU time 638.55 seconds
Started Feb 25 02:59:27 PM PST 24
Finished Feb 25 03:10:06 PM PST 24
Peak memory 265568 kb
Host smart-d8490adb-57fe-4524-9cc0-af36ea328edc
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507704197 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.alert_handler_shadow_reg_errors_with_csr_rw.1507704197
Directory /workspace/0.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.687890086
Short name T813
Test name
Test status
Simulation time 229876879 ps
CPU time 10.46 seconds
Started Feb 25 02:59:26 PM PST 24
Finished Feb 25 02:59:37 PM PST 24
Peak memory 248640 kb
Host smart-ee22a9d8-183e-4aba-9c1d-dbb6bebcf543
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=687890086 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_errors.687890086
Directory /workspace/0.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.3668389484
Short name T785
Test name
Test status
Simulation time 1085813480 ps
CPU time 78.5 seconds
Started Feb 25 02:59:28 PM PST 24
Finished Feb 25 03:00:46 PM PST 24
Peak memory 240584 kb
Host smart-7bbfe31a-ead5-4f52-ab59-bc884d2afafc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3668389484 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_aliasing.3668389484
Directory /workspace/1.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.4018239580
Short name T796
Test name
Test status
Simulation time 3270460753 ps
CPU time 114.86 seconds
Started Feb 25 02:59:28 PM PST 24
Finished Feb 25 03:01:23 PM PST 24
Peak memory 236708 kb
Host smart-5611ed49-50a9-431f-8d4a-5d905ccd8213
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4018239580 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_bit_bash.4018239580
Directory /workspace/1.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.122209169
Short name T232
Test name
Test status
Simulation time 149905035 ps
CPU time 6.15 seconds
Started Feb 25 02:59:25 PM PST 24
Finished Feb 25 02:59:31 PM PST 24
Peak memory 240564 kb
Host smart-e51ceb37-d4ec-466f-8187-cb88531778c0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=122209169 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_hw_reset.122209169
Directory /workspace/1.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.3888642953
Short name T831
Test name
Test status
Simulation time 130093836 ps
CPU time 9.35 seconds
Started Feb 25 02:59:23 PM PST 24
Finished Feb 25 02:59:33 PM PST 24
Peak memory 252480 kb
Host smart-1fbfcbf4-18d5-4e0a-aa3c-4b06da5a6d5e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888642953 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 1.alert_handler_csr_mem_rw_with_rand_reset.3888642953
Directory /workspace/1.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.544611508
Short name T190
Test name
Test status
Simulation time 337880969 ps
CPU time 7.11 seconds
Started Feb 25 02:59:29 PM PST 24
Finished Feb 25 02:59:37 PM PST 24
Peak memory 240492 kb
Host smart-c08b740a-2f1e-45fd-86c3-03462cbd070d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=544611508 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_rw.544611508
Directory /workspace/1.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.779922693
Short name T725
Test name
Test status
Simulation time 898987074 ps
CPU time 23.36 seconds
Started Feb 25 02:59:25 PM PST 24
Finished Feb 25 02:59:49 PM PST 24
Peak memory 240532 kb
Host smart-337ee3b1-64bc-4737-9c50-18b08f820d56
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=779922693 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_same_csr_outs
tanding.779922693
Directory /workspace/1.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.2967577408
Short name T145
Test name
Test status
Simulation time 2384188919 ps
CPU time 319.34 seconds
Started Feb 25 02:59:30 PM PST 24
Finished Feb 25 03:04:49 PM PST 24
Peak memory 265432 kb
Host smart-d575d582-e08b-4c04-8f42-80fc4ed08782
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967577408 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.alert_handler_shadow_reg_errors_with_csr_rw.2967577408
Directory /workspace/1.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.854283686
Short name T734
Test name
Test status
Simulation time 975857322 ps
CPU time 15.72 seconds
Started Feb 25 02:59:33 PM PST 24
Finished Feb 25 02:59:49 PM PST 24
Peak memory 248492 kb
Host smart-3bd34dc1-3d05-42ed-8893-68fcf0b64f37
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=854283686 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_errors.854283686
Directory /workspace/1.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.1487048534
Short name T351
Test name
Test status
Simulation time 63547839 ps
CPU time 5.12 seconds
Started Feb 25 02:59:48 PM PST 24
Finished Feb 25 02:59:54 PM PST 24
Peak memory 241728 kb
Host smart-0a0c0a2f-d414-49ea-b344-94cd1fc7e6c0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487048534 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 10.alert_handler_csr_mem_rw_with_rand_reset.1487048534
Directory /workspace/10.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.4260711535
Short name T762
Test name
Test status
Simulation time 472107397 ps
CPU time 9.7 seconds
Started Feb 25 02:59:48 PM PST 24
Finished Feb 25 02:59:58 PM PST 24
Peak memory 240532 kb
Host smart-654cdb68-cd97-46de-84e2-5f1a8d999e0d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4260711535 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_rw.4260711535
Directory /workspace/10.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.2185689567
Short name T720
Test name
Test status
Simulation time 6334909 ps
CPU time 1.5 seconds
Started Feb 25 03:00:00 PM PST 24
Finished Feb 25 03:00:02 PM PST 24
Peak memory 236608 kb
Host smart-25c1c2a0-3d8d-46d5-babc-39c94906984b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2185689567 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_intr_test.2185689567
Directory /workspace/10.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.771900978
Short name T827
Test name
Test status
Simulation time 691369717 ps
CPU time 48.26 seconds
Started Feb 25 02:59:46 PM PST 24
Finished Feb 25 03:00:34 PM PST 24
Peak memory 248720 kb
Host smart-f9b3725a-52e3-401f-be52-20036d12a8d4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=771900978 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_same_csr_out
standing.771900978
Directory /workspace/10.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.753400788
Short name T133
Test name
Test status
Simulation time 3495532955 ps
CPU time 208.7 seconds
Started Feb 25 02:59:38 PM PST 24
Finished Feb 25 03:03:07 PM PST 24
Peak memory 272816 kb
Host smart-58266a06-26a4-4a69-83a1-8dbb75f54b51
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=753400788 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shadow_reg_erro
rs.753400788
Directory /workspace/10.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.1026520461
Short name T824
Test name
Test status
Simulation time 1229215763 ps
CPU time 23.71 seconds
Started Feb 25 02:59:48 PM PST 24
Finished Feb 25 03:00:12 PM PST 24
Peak memory 248180 kb
Host smart-8e37233d-3683-4d5a-bb33-0a2ff9a483d8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1026520461 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_errors.1026520461
Directory /workspace/10.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.1946396924
Short name T350
Test name
Test status
Simulation time 133854080 ps
CPU time 6.26 seconds
Started Feb 25 02:59:42 PM PST 24
Finished Feb 25 02:59:48 PM PST 24
Peak memory 242488 kb
Host smart-de822ded-b5cb-4df0-8790-90a971e43290
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946396924 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 11.alert_handler_csr_mem_rw_with_rand_reset.1946396924
Directory /workspace/11.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.2631596163
Short name T196
Test name
Test status
Simulation time 494604316 ps
CPU time 10.1 seconds
Started Feb 25 02:59:44 PM PST 24
Finished Feb 25 02:59:54 PM PST 24
Peak memory 236608 kb
Host smart-f97afec9-5b6a-4854-8b1a-de92b27406cc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2631596163 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_rw.2631596163
Directory /workspace/11.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.2387326889
Short name T346
Test name
Test status
Simulation time 17863482 ps
CPU time 1.37 seconds
Started Feb 25 02:59:54 PM PST 24
Finished Feb 25 02:59:56 PM PST 24
Peak memory 235748 kb
Host smart-eaa70aa7-8cb0-4374-a8c0-2f69e9c24399
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2387326889 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_intr_test.2387326889
Directory /workspace/11.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.2236825289
Short name T804
Test name
Test status
Simulation time 1281538881 ps
CPU time 43.08 seconds
Started Feb 25 02:59:54 PM PST 24
Finished Feb 25 03:00:37 PM PST 24
Peak memory 244780 kb
Host smart-46ce96a7-776b-4204-bc7e-ba880b60b191
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2236825289 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_same_csr_ou
tstanding.2236825289
Directory /workspace/11.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.1711784344
Short name T150
Test name
Test status
Simulation time 13569410796 ps
CPU time 971.93 seconds
Started Feb 25 02:59:48 PM PST 24
Finished Feb 25 03:16:00 PM PST 24
Peak memory 265496 kb
Host smart-f6610688-9419-402a-b573-06938dcef11d
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711784344 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 11.alert_handler_shadow_reg_errors_with_csr_rw.1711784344
Directory /workspace/11.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.2642042981
Short name T722
Test name
Test status
Simulation time 118063926 ps
CPU time 10.96 seconds
Started Feb 25 02:59:48 PM PST 24
Finished Feb 25 02:59:59 PM PST 24
Peak memory 247888 kb
Host smart-9c980a5e-2107-4fce-8b6f-f8c73417388c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2642042981 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_errors.2642042981
Directory /workspace/11.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.3280055442
Short name T750
Test name
Test status
Simulation time 65320790 ps
CPU time 10.42 seconds
Started Feb 25 03:00:03 PM PST 24
Finished Feb 25 03:00:14 PM PST 24
Peak memory 252748 kb
Host smart-9c7bdce5-a408-4d28-9c49-1508a442f691
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280055442 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 12.alert_handler_csr_mem_rw_with_rand_reset.3280055442
Directory /workspace/12.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.4270227234
Short name T194
Test name
Test status
Simulation time 63019307 ps
CPU time 5.32 seconds
Started Feb 25 02:59:47 PM PST 24
Finished Feb 25 02:59:53 PM PST 24
Peak memory 240484 kb
Host smart-dc0e5909-2ba0-4ec5-b18f-61961aeee7aa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4270227234 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_rw.4270227234
Directory /workspace/12.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.2975543281
Short name T828
Test name
Test status
Simulation time 7742732 ps
CPU time 1.38 seconds
Started Feb 25 03:00:03 PM PST 24
Finished Feb 25 03:00:04 PM PST 24
Peak memory 235740 kb
Host smart-21e30bc5-30b5-45ff-8483-1a47bf3355e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2975543281 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_intr_test.2975543281
Directory /workspace/12.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.2069400823
Short name T730
Test name
Test status
Simulation time 359365743 ps
CPU time 23.07 seconds
Started Feb 25 03:00:01 PM PST 24
Finished Feb 25 03:00:24 PM PST 24
Peak memory 248744 kb
Host smart-1aa9d1f6-2e77-472b-ae8c-50c08d32902f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2069400823 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_same_csr_ou
tstanding.2069400823
Directory /workspace/12.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.1792362681
Short name T144
Test name
Test status
Simulation time 14215717777 ps
CPU time 251.34 seconds
Started Feb 25 02:59:43 PM PST 24
Finished Feb 25 03:03:54 PM PST 24
Peak memory 265488 kb
Host smart-7acbcd81-38d5-4208-b28e-53516fa619d3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1792362681 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shadow_reg_err
ors.1792362681
Directory /workspace/12.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.580406581
Short name T158
Test name
Test status
Simulation time 73899989289 ps
CPU time 1116 seconds
Started Feb 25 02:59:44 PM PST 24
Finished Feb 25 03:18:20 PM PST 24
Peak memory 273680 kb
Host smart-7a500675-7a63-4eed-a76c-dc4c758a0472
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580406581 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 12.alert_handler_shadow_reg_errors_with_csr_rw.580406581
Directory /workspace/12.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.2632847926
Short name T821
Test name
Test status
Simulation time 446066513 ps
CPU time 8.66 seconds
Started Feb 25 02:59:55 PM PST 24
Finished Feb 25 03:00:04 PM PST 24
Peak memory 247796 kb
Host smart-94048440-ef0f-4855-b7cb-2823fffdec59
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2632847926 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_errors.2632847926
Directory /workspace/12.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.595107091
Short name T802
Test name
Test status
Simulation time 142137417 ps
CPU time 10.25 seconds
Started Feb 25 03:00:00 PM PST 24
Finished Feb 25 03:00:11 PM PST 24
Peak memory 240548 kb
Host smart-af919df3-37c9-4b48-a2af-ec3f7053a23e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=595107091 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_rw.595107091
Directory /workspace/13.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.1371830813
Short name T736
Test name
Test status
Simulation time 15486788 ps
CPU time 1.41 seconds
Started Feb 25 03:00:05 PM PST 24
Finished Feb 25 03:00:06 PM PST 24
Peak memory 234816 kb
Host smart-3a575eb7-766f-4e41-a4f6-0a2a5b846ff8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1371830813 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_intr_test.1371830813
Directory /workspace/13.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.2352178139
Short name T745
Test name
Test status
Simulation time 176690152 ps
CPU time 13.98 seconds
Started Feb 25 03:00:01 PM PST 24
Finished Feb 25 03:00:15 PM PST 24
Peak memory 244800 kb
Host smart-2d199efe-a598-43a8-96f8-7a7b033f94bc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2352178139 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_same_csr_ou
tstanding.2352178139
Directory /workspace/13.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.2148234369
Short name T155
Test name
Test status
Simulation time 1480161059 ps
CPU time 102.15 seconds
Started Feb 25 03:00:05 PM PST 24
Finished Feb 25 03:01:47 PM PST 24
Peak memory 256548 kb
Host smart-563cd222-4a8d-4b62-9baa-e3f331c12d05
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2148234369 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shadow_reg_err
ors.2148234369
Directory /workspace/13.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.1187095975
Short name T779
Test name
Test status
Simulation time 131599288 ps
CPU time 5.55 seconds
Started Feb 25 03:00:02 PM PST 24
Finished Feb 25 03:00:08 PM PST 24
Peak memory 248848 kb
Host smart-798ea85f-326e-4b21-83ce-c3198e053345
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1187095975 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_errors.1187095975
Directory /workspace/13.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.112820640
Short name T747
Test name
Test status
Simulation time 369060694 ps
CPU time 8 seconds
Started Feb 25 03:00:04 PM PST 24
Finished Feb 25 03:00:12 PM PST 24
Peak memory 239512 kb
Host smart-e14e391b-2b92-4e6a-a30c-e5d734b8eded
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112820640 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 14.alert_handler_csr_mem_rw_with_rand_reset.112820640
Directory /workspace/14.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.160529737
Short name T819
Test name
Test status
Simulation time 161779129 ps
CPU time 5.32 seconds
Started Feb 25 02:59:59 PM PST 24
Finished Feb 25 03:00:04 PM PST 24
Peak memory 236628 kb
Host smart-ae741975-4463-4fee-afc2-3b729e1b0e85
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=160529737 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_rw.160529737
Directory /workspace/14.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.223319194
Short name T755
Test name
Test status
Simulation time 1306374621 ps
CPU time 20.14 seconds
Started Feb 25 03:00:02 PM PST 24
Finished Feb 25 03:00:22 PM PST 24
Peak memory 244792 kb
Host smart-d1d8258c-4f38-4f49-a322-370ac65c7915
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=223319194 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_same_csr_out
standing.223319194
Directory /workspace/14.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.1176183145
Short name T161
Test name
Test status
Simulation time 2397265972 ps
CPU time 224.03 seconds
Started Feb 25 02:59:59 PM PST 24
Finished Feb 25 03:03:44 PM PST 24
Peak memory 265384 kb
Host smart-4e1ec65c-04a7-4c14-8bff-44eb4623f2f1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1176183145 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shadow_reg_err
ors.1176183145
Directory /workspace/14.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.1666634203
Short name T125
Test name
Test status
Simulation time 31272779272 ps
CPU time 882.13 seconds
Started Feb 25 02:59:51 PM PST 24
Finished Feb 25 03:14:34 PM PST 24
Peak memory 273216 kb
Host smart-e8b85ff5-38ba-476a-8c81-e0b063aea517
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666634203 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 14.alert_handler_shadow_reg_errors_with_csr_rw.1666634203
Directory /workspace/14.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.4216650993
Short name T760
Test name
Test status
Simulation time 135516122 ps
CPU time 5.63 seconds
Started Feb 25 03:00:01 PM PST 24
Finished Feb 25 03:00:07 PM PST 24
Peak memory 253436 kb
Host smart-18c62619-df4a-4ff6-80cf-0b3a94338796
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4216650993 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_errors.4216650993
Directory /workspace/14.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.101244863
Short name T163
Test name
Test status
Simulation time 69257976 ps
CPU time 4.25 seconds
Started Feb 25 03:00:02 PM PST 24
Finished Feb 25 03:00:07 PM PST 24
Peak memory 237796 kb
Host smart-2c6afa04-530d-4cc1-b61b-e8867d20e3bd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=101244863 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_intg_err.101244863
Directory /workspace/14.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.338342750
Short name T775
Test name
Test status
Simulation time 504129721 ps
CPU time 10.44 seconds
Started Feb 25 02:59:58 PM PST 24
Finished Feb 25 03:00:09 PM PST 24
Peak memory 240600 kb
Host smart-ae288cde-f980-4485-8cc4-f707c6a2e259
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338342750 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 15.alert_handler_csr_mem_rw_with_rand_reset.338342750
Directory /workspace/15.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.3617174506
Short name T192
Test name
Test status
Simulation time 686069203 ps
CPU time 8.31 seconds
Started Feb 25 03:00:02 PM PST 24
Finished Feb 25 03:00:11 PM PST 24
Peak memory 235596 kb
Host smart-926c1c6e-290e-4af2-8a98-62c63b4d94ac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3617174506 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_rw.3617174506
Directory /workspace/15.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.2153211700
Short name T765
Test name
Test status
Simulation time 13272415 ps
CPU time 1.71 seconds
Started Feb 25 02:59:58 PM PST 24
Finished Feb 25 03:00:00 PM PST 24
Peak memory 235856 kb
Host smart-995a11a5-264e-43c2-a232-ef8ca1300273
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2153211700 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_intr_test.2153211700
Directory /workspace/15.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.1879113521
Short name T825
Test name
Test status
Simulation time 626198650 ps
CPU time 39.6 seconds
Started Feb 25 03:00:01 PM PST 24
Finished Feb 25 03:00:40 PM PST 24
Peak memory 243932 kb
Host smart-bf0ff734-47a2-4150-815a-d5512d688aa8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1879113521 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_same_csr_ou
tstanding.1879113521
Directory /workspace/15.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.626722797
Short name T823
Test name
Test status
Simulation time 87487641 ps
CPU time 9.23 seconds
Started Feb 25 03:00:02 PM PST 24
Finished Feb 25 03:00:11 PM PST 24
Peak memory 248748 kb
Host smart-0402b0d3-97e5-42cb-9973-21f2ffbd6ead
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=626722797 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_errors.626722797
Directory /workspace/15.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.881157179
Short name T818
Test name
Test status
Simulation time 38242307 ps
CPU time 6.13 seconds
Started Feb 25 03:00:03 PM PST 24
Finished Feb 25 03:00:09 PM PST 24
Peak memory 242532 kb
Host smart-27b93492-92a5-418f-aed6-a92b0f783003
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881157179 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 16.alert_handler_csr_mem_rw_with_rand_reset.881157179
Directory /workspace/16.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.3811058838
Short name T231
Test name
Test status
Simulation time 1695257659 ps
CPU time 8.87 seconds
Started Feb 25 03:00:03 PM PST 24
Finished Feb 25 03:00:12 PM PST 24
Peak memory 235584 kb
Host smart-9bc7f6d9-1588-4d27-bbf7-9d09265ae61d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3811058838 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_rw.3811058838
Directory /workspace/16.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.1237622467
Short name T345
Test name
Test status
Simulation time 9877894 ps
CPU time 1.39 seconds
Started Feb 25 02:59:57 PM PST 24
Finished Feb 25 02:59:59 PM PST 24
Peak memory 236756 kb
Host smart-29802ad7-c100-41bc-a8b5-8a74119eaa62
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1237622467 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_intr_test.1237622467
Directory /workspace/16.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.1896881427
Short name T732
Test name
Test status
Simulation time 108936349 ps
CPU time 12.93 seconds
Started Feb 25 03:00:00 PM PST 24
Finished Feb 25 03:00:13 PM PST 24
Peak memory 244760 kb
Host smart-62bbd501-557a-42a1-b461-a92b13d45b58
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1896881427 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_same_csr_ou
tstanding.1896881427
Directory /workspace/16.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.311380267
Short name T815
Test name
Test status
Simulation time 774069445 ps
CPU time 99.68 seconds
Started Feb 25 02:59:51 PM PST 24
Finished Feb 25 03:01:31 PM PST 24
Peak memory 265708 kb
Host smart-c3455102-fea6-4c71-9d88-ee473599bdac
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=311380267 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shadow_reg_erro
rs.311380267
Directory /workspace/16.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.3489516176
Short name T160
Test name
Test status
Simulation time 19977106985 ps
CPU time 644.93 seconds
Started Feb 25 03:00:04 PM PST 24
Finished Feb 25 03:10:49 PM PST 24
Peak memory 265628 kb
Host smart-8a2e68ee-6029-4de1-9879-0ea3ff6965ef
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489516176 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 16.alert_handler_shadow_reg_errors_with_csr_rw.3489516176
Directory /workspace/16.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.3074008633
Short name T761
Test name
Test status
Simulation time 37660187 ps
CPU time 5.59 seconds
Started Feb 25 02:59:50 PM PST 24
Finished Feb 25 02:59:55 PM PST 24
Peak memory 248808 kb
Host smart-7449fee8-93d9-4399-9684-3e30c4099c1a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3074008633 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_errors.3074008633
Directory /workspace/16.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.3881896140
Short name T822
Test name
Test status
Simulation time 39989928 ps
CPU time 5.77 seconds
Started Feb 25 03:00:00 PM PST 24
Finished Feb 25 03:00:06 PM PST 24
Peak memory 240612 kb
Host smart-cf4a92f5-1ced-4eae-90a9-a873a96462b6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881896140 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 17.alert_handler_csr_mem_rw_with_rand_reset.3881896140
Directory /workspace/17.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.835565276
Short name T728
Test name
Test status
Simulation time 36620999 ps
CPU time 5.42 seconds
Started Feb 25 03:00:06 PM PST 24
Finished Feb 25 03:00:12 PM PST 24
Peak memory 236612 kb
Host smart-0fd2239c-8636-4b5d-8d7c-7dbf999a49df
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=835565276 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_rw.835565276
Directory /workspace/17.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.571535632
Short name T348
Test name
Test status
Simulation time 18455889 ps
CPU time 1.49 seconds
Started Feb 25 03:00:02 PM PST 24
Finished Feb 25 03:00:04 PM PST 24
Peak memory 236640 kb
Host smart-e1cadd69-3462-44b2-80d5-7354739f37af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=571535632 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_intr_test.571535632
Directory /workspace/17.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.3787967399
Short name T817
Test name
Test status
Simulation time 3926170886 ps
CPU time 41.48 seconds
Started Feb 25 03:00:02 PM PST 24
Finished Feb 25 03:00:44 PM PST 24
Peak memory 248744 kb
Host smart-7d7dfb07-f738-4055-853f-b608d2916b71
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3787967399 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_same_csr_ou
tstanding.3787967399
Directory /workspace/17.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.3396291025
Short name T836
Test name
Test status
Simulation time 13597612738 ps
CPU time 93.47 seconds
Started Feb 25 03:00:05 PM PST 24
Finished Feb 25 03:01:39 PM PST 24
Peak memory 257284 kb
Host smart-9d2b3b9f-5666-452e-ae4b-beb559b2afa2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3396291025 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shadow_reg_err
ors.3396291025
Directory /workspace/17.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.2128381512
Short name T148
Test name
Test status
Simulation time 6457070322 ps
CPU time 462.81 seconds
Started Feb 25 03:00:02 PM PST 24
Finished Feb 25 03:07:45 PM PST 24
Peak memory 265468 kb
Host smart-8ff7a303-bf96-40b7-925a-f1c42687b2ee
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128381512 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 17.alert_handler_shadow_reg_errors_with_csr_rw.2128381512
Directory /workspace/17.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.2555700754
Short name T718
Test name
Test status
Simulation time 40594240 ps
CPU time 5.44 seconds
Started Feb 25 03:00:01 PM PST 24
Finished Feb 25 03:00:07 PM PST 24
Peak memory 249912 kb
Host smart-b50c2d4e-4bde-4e97-99a8-4d3d8b868f9e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2555700754 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_errors.2555700754
Directory /workspace/17.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.160140930
Short name T834
Test name
Test status
Simulation time 472994322 ps
CPU time 8.86 seconds
Started Feb 25 03:00:00 PM PST 24
Finished Feb 25 03:00:09 PM PST 24
Peak memory 240596 kb
Host smart-b27edf3c-018a-425d-ab8c-d2ee61494437
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160140930 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 18.alert_handler_csr_mem_rw_with_rand_reset.160140930
Directory /workspace/18.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.3135424761
Short name T774
Test name
Test status
Simulation time 370390241 ps
CPU time 8.17 seconds
Started Feb 25 03:00:09 PM PST 24
Finished Feb 25 03:00:18 PM PST 24
Peak memory 235724 kb
Host smart-3556b41a-ba9d-4d13-a654-b69a913d0011
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3135424761 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_rw.3135424761
Directory /workspace/18.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.3287391887
Short name T772
Test name
Test status
Simulation time 11194094 ps
CPU time 1.39 seconds
Started Feb 25 03:00:04 PM PST 24
Finished Feb 25 03:00:06 PM PST 24
Peak memory 235768 kb
Host smart-25f8cb08-224d-4f11-b09f-51c737e42ec8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3287391887 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_intr_test.3287391887
Directory /workspace/18.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.3855225514
Short name T770
Test name
Test status
Simulation time 87232201 ps
CPU time 11.19 seconds
Started Feb 25 03:00:06 PM PST 24
Finished Feb 25 03:00:18 PM PST 24
Peak memory 243920 kb
Host smart-f9fd80d7-6b36-4607-bca1-2b4f4ac0cac2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3855225514 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_same_csr_ou
tstanding.3855225514
Directory /workspace/18.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.4264592684
Short name T141
Test name
Test status
Simulation time 6284141654 ps
CPU time 471.51 seconds
Started Feb 25 03:00:04 PM PST 24
Finished Feb 25 03:07:56 PM PST 24
Peak memory 265696 kb
Host smart-43430003-c5a0-402f-ab7d-bdba3127a9d2
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264592684 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 18.alert_handler_shadow_reg_errors_with_csr_rw.4264592684
Directory /workspace/18.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.1712998182
Short name T719
Test name
Test status
Simulation time 180845450 ps
CPU time 7.21 seconds
Started Feb 25 03:00:02 PM PST 24
Finished Feb 25 03:00:10 PM PST 24
Peak memory 248952 kb
Host smart-388335e1-5266-4f39-a006-6f80b2e003ad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1712998182 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_errors.1712998182
Directory /workspace/18.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.1420835305
Short name T743
Test name
Test status
Simulation time 94639229 ps
CPU time 8.51 seconds
Started Feb 25 03:00:02 PM PST 24
Finished Feb 25 03:00:11 PM PST 24
Peak memory 253460 kb
Host smart-37fc6ee3-5735-4a81-ba3b-dd5ad4049f3b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420835305 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 19.alert_handler_csr_mem_rw_with_rand_reset.1420835305
Directory /workspace/19.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.3671891373
Short name T182
Test name
Test status
Simulation time 67789487 ps
CPU time 3.26 seconds
Started Feb 25 03:00:04 PM PST 24
Finished Feb 25 03:00:08 PM PST 24
Peak memory 235672 kb
Host smart-c076b1c4-80e0-497b-b740-41a640a3c043
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3671891373 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_rw.3671891373
Directory /workspace/19.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.2401376981
Short name T763
Test name
Test status
Simulation time 15080176 ps
CPU time 1.49 seconds
Started Feb 25 03:00:01 PM PST 24
Finished Feb 25 03:00:02 PM PST 24
Peak memory 236636 kb
Host smart-ef968203-2b5e-48a7-8b6c-a988a8d3e3eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2401376981 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_intr_test.2401376981
Directory /workspace/19.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.1522147281
Short name T788
Test name
Test status
Simulation time 1359097961 ps
CPU time 37.7 seconds
Started Feb 25 03:00:06 PM PST 24
Finished Feb 25 03:00:44 PM PST 24
Peak memory 243920 kb
Host smart-3ad0823e-7224-45ff-b3de-da61bddad54f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1522147281 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_same_csr_ou
tstanding.1522147281
Directory /workspace/19.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.698547583
Short name T143
Test name
Test status
Simulation time 2173704615 ps
CPU time 217.6 seconds
Started Feb 25 03:00:04 PM PST 24
Finished Feb 25 03:03:41 PM PST 24
Peak memory 265552 kb
Host smart-b4250157-0ecb-4282-ae12-e82668414777
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=698547583 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shadow_reg_erro
rs.698547583
Directory /workspace/19.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.2252674483
Short name T789
Test name
Test status
Simulation time 914388497 ps
CPU time 16.22 seconds
Started Feb 25 03:00:02 PM PST 24
Finished Feb 25 03:00:18 PM PST 24
Peak memory 248456 kb
Host smart-e1dd7ebe-9411-481d-b9fc-859abbd1531f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2252674483 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_errors.2252674483
Directory /workspace/19.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.997210537
Short name T776
Test name
Test status
Simulation time 602883158 ps
CPU time 67.44 seconds
Started Feb 25 02:59:29 PM PST 24
Finished Feb 25 03:00:37 PM PST 24
Peak memory 236748 kb
Host smart-9dc1071a-4499-4351-8e34-e2be72b7db67
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=997210537 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_aliasing.997210537
Directory /workspace/2.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.127305608
Short name T191
Test name
Test status
Simulation time 15004466794 ps
CPU time 220.68 seconds
Started Feb 25 02:59:23 PM PST 24
Finished Feb 25 03:03:04 PM PST 24
Peak memory 240596 kb
Host smart-ec978649-a6a5-40f3-b619-8cbcdeda7c1a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=127305608 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_bit_bash.127305608
Directory /workspace/2.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.1566101802
Short name T230
Test name
Test status
Simulation time 563883593 ps
CPU time 9.94 seconds
Started Feb 25 02:59:30 PM PST 24
Finished Feb 25 02:59:40 PM PST 24
Peak memory 240516 kb
Host smart-64a62188-55d3-4f6d-bf3b-242fb2e6640c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1566101802 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_hw_reset.1566101802
Directory /workspace/2.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.2777797911
Short name T198
Test name
Test status
Simulation time 178131452 ps
CPU time 5.96 seconds
Started Feb 25 02:59:25 PM PST 24
Finished Feb 25 02:59:31 PM PST 24
Peak memory 240728 kb
Host smart-2e4e5773-3244-401d-bad1-fa14779484f0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777797911 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 2.alert_handler_csr_mem_rw_with_rand_reset.2777797911
Directory /workspace/2.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.2174850893
Short name T764
Test name
Test status
Simulation time 96947959 ps
CPU time 5.16 seconds
Started Feb 25 02:59:27 PM PST 24
Finished Feb 25 02:59:33 PM PST 24
Peak memory 240376 kb
Host smart-b1c691cf-2e9c-4ceb-829c-75712a0c27b8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2174850893 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_rw.2174850893
Directory /workspace/2.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.189513469
Short name T833
Test name
Test status
Simulation time 6390764 ps
CPU time 1.45 seconds
Started Feb 25 02:59:27 PM PST 24
Finished Feb 25 02:59:29 PM PST 24
Peak memory 236628 kb
Host smart-d519665b-5ad5-439c-bffe-9264a2389e05
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=189513469 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_intr_test.189513469
Directory /workspace/2.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.4079034232
Short name T768
Test name
Test status
Simulation time 177107639 ps
CPU time 23.59 seconds
Started Feb 25 02:59:33 PM PST 24
Finished Feb 25 02:59:57 PM PST 24
Peak memory 245492 kb
Host smart-e1856f67-2f88-4877-b1d8-ad3052e2e2a1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4079034232 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_same_csr_out
standing.4079034232
Directory /workspace/2.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.3246199001
Short name T149
Test name
Test status
Simulation time 2027190006 ps
CPU time 158.28 seconds
Started Feb 25 02:59:28 PM PST 24
Finished Feb 25 03:02:06 PM PST 24
Peak memory 257248 kb
Host smart-d0faacc6-7e40-451e-bed6-7c85a81c5029
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3246199001 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shadow_reg_erro
rs.3246199001
Directory /workspace/2.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.1530352821
Short name T157
Test name
Test status
Simulation time 2145787740 ps
CPU time 345.26 seconds
Started Feb 25 02:59:26 PM PST 24
Finished Feb 25 03:05:11 PM PST 24
Peak memory 265432 kb
Host smart-f22f273a-4530-45d7-8bd7-fc3c69b87586
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530352821 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.alert_handler_shadow_reg_errors_with_csr_rw.1530352821
Directory /workspace/2.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.2923426162
Short name T741
Test name
Test status
Simulation time 1326842629 ps
CPU time 24 seconds
Started Feb 25 02:59:28 PM PST 24
Finished Feb 25 02:59:52 PM PST 24
Peak memory 248492 kb
Host smart-9fa3739b-f7ac-4555-84c9-41147681ef16
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2923426162 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_errors.2923426162
Directory /workspace/2.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.743914372
Short name T166
Test name
Test status
Simulation time 18653725 ps
CPU time 1.37 seconds
Started Feb 25 02:59:59 PM PST 24
Finished Feb 25 03:00:01 PM PST 24
Peak memory 234820 kb
Host smart-395fab26-4945-4087-8104-f4d4921526ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=743914372 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.alert_handler_intr_test.743914372
Directory /workspace/20.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.2051043827
Short name T784
Test name
Test status
Simulation time 18337763 ps
CPU time 1.35 seconds
Started Feb 25 03:00:06 PM PST 24
Finished Feb 25 03:00:07 PM PST 24
Peak memory 234804 kb
Host smart-5ea112bf-753b-4da4-8e60-6214fa5d38c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2051043827 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.alert_handler_intr_test.2051043827
Directory /workspace/21.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.3907597336
Short name T756
Test name
Test status
Simulation time 21984591 ps
CPU time 1.39 seconds
Started Feb 25 03:00:02 PM PST 24
Finished Feb 25 03:00:04 PM PST 24
Peak memory 235760 kb
Host smart-8a4a6776-864e-4cfa-93c9-fdf85f45c600
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3907597336 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.alert_handler_intr_test.3907597336
Directory /workspace/22.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.307712324
Short name T782
Test name
Test status
Simulation time 7737145 ps
CPU time 1.43 seconds
Started Feb 25 03:00:07 PM PST 24
Finished Feb 25 03:00:09 PM PST 24
Peak memory 236616 kb
Host smart-326626ad-59bd-42c9-b6e8-7470813b206e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=307712324 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.alert_handler_intr_test.307712324
Directory /workspace/23.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.735540524
Short name T814
Test name
Test status
Simulation time 13155983 ps
CPU time 1.42 seconds
Started Feb 25 03:00:07 PM PST 24
Finished Feb 25 03:00:09 PM PST 24
Peak memory 236616 kb
Host smart-dbe26eec-abb9-43cb-b10f-84722652d465
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=735540524 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.alert_handler_intr_test.735540524
Directory /workspace/24.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.2229576227
Short name T729
Test name
Test status
Simulation time 9566948 ps
CPU time 1.29 seconds
Started Feb 25 03:00:07 PM PST 24
Finished Feb 25 03:00:09 PM PST 24
Peak memory 235728 kb
Host smart-dda8d825-6e1f-4094-b930-ab29779702e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2229576227 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.alert_handler_intr_test.2229576227
Directory /workspace/25.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.307805414
Short name T347
Test name
Test status
Simulation time 19639914 ps
CPU time 1.4 seconds
Started Feb 25 03:00:06 PM PST 24
Finished Feb 25 03:00:07 PM PST 24
Peak memory 235828 kb
Host smart-8b0ba64f-cc0f-42e2-90ee-52147391c728
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=307805414 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.alert_handler_intr_test.307805414
Directory /workspace/26.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.1124661884
Short name T811
Test name
Test status
Simulation time 12339567 ps
CPU time 1.31 seconds
Started Feb 25 03:00:02 PM PST 24
Finished Feb 25 03:00:04 PM PST 24
Peak memory 236628 kb
Host smart-518d1ef5-01a4-4ca6-9218-4212c5d02556
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1124661884 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.alert_handler_intr_test.1124661884
Directory /workspace/27.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.1236332575
Short name T805
Test name
Test status
Simulation time 11603370 ps
CPU time 1.47 seconds
Started Feb 25 03:00:10 PM PST 24
Finished Feb 25 03:00:11 PM PST 24
Peak memory 236672 kb
Host smart-5b67f10c-ed01-4745-93b5-85e3e74b764b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1236332575 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.alert_handler_intr_test.1236332575
Directory /workspace/28.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.1505503504
Short name T781
Test name
Test status
Simulation time 12318028 ps
CPU time 1.69 seconds
Started Feb 25 03:00:10 PM PST 24
Finished Feb 25 03:00:12 PM PST 24
Peak memory 235764 kb
Host smart-966ce663-dcd4-4633-b03b-32d41884f2a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1505503504 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.alert_handler_intr_test.1505503504
Directory /workspace/29.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.1933839091
Short name T766
Test name
Test status
Simulation time 28358697365 ps
CPU time 131.02 seconds
Started Feb 25 02:59:27 PM PST 24
Finished Feb 25 03:01:39 PM PST 24
Peak memory 240604 kb
Host smart-7d90e43a-d825-47ae-b96d-0f525b0cba96
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1933839091 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_aliasing.1933839091
Directory /workspace/3.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.2536207374
Short name T737
Test name
Test status
Simulation time 98368195 ps
CPU time 10.22 seconds
Started Feb 25 02:59:29 PM PST 24
Finished Feb 25 02:59:40 PM PST 24
Peak memory 240508 kb
Host smart-e11bf385-8482-4fdf-938d-0177219802ec
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2536207374 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_hw_reset.2536207374
Directory /workspace/3.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.1574708053
Short name T786
Test name
Test status
Simulation time 117064939 ps
CPU time 5.37 seconds
Started Feb 25 02:59:24 PM PST 24
Finished Feb 25 02:59:29 PM PST 24
Peak memory 241136 kb
Host smart-d3a965b5-82cf-4818-a774-0a626612d247
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574708053 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 3.alert_handler_csr_mem_rw_with_rand_reset.1574708053
Directory /workspace/3.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.570410515
Short name T739
Test name
Test status
Simulation time 127649822 ps
CPU time 6.06 seconds
Started Feb 25 02:59:33 PM PST 24
Finished Feb 25 02:59:40 PM PST 24
Peak memory 236604 kb
Host smart-6cc107fe-b251-4731-b9fa-9331108d110b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=570410515 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_rw.570410515
Directory /workspace/3.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.472806463
Short name T803
Test name
Test status
Simulation time 18981016 ps
CPU time 1.29 seconds
Started Feb 25 02:59:29 PM PST 24
Finished Feb 25 02:59:31 PM PST 24
Peak memory 234776 kb
Host smart-7a678bd1-1eed-4bce-93b0-365814328994
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=472806463 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_intr_test.472806463
Directory /workspace/3.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.3709790934
Short name T733
Test name
Test status
Simulation time 384857136 ps
CPU time 25.19 seconds
Started Feb 25 02:59:28 PM PST 24
Finished Feb 25 02:59:54 PM PST 24
Peak memory 240328 kb
Host smart-36d94587-0453-42e5-a78a-a2ac94fd1c11
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3709790934 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_same_csr_out
standing.3709790934
Directory /workspace/3.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.261428515
Short name T799
Test name
Test status
Simulation time 43465960 ps
CPU time 6.22 seconds
Started Feb 25 02:59:29 PM PST 24
Finished Feb 25 02:59:35 PM PST 24
Peak memory 248796 kb
Host smart-332e9d53-957a-404e-8e77-03d4ce08c865
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=261428515 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_errors.261428515
Directory /workspace/3.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.2286156188
Short name T797
Test name
Test status
Simulation time 15158580 ps
CPU time 1.29 seconds
Started Feb 25 03:00:10 PM PST 24
Finished Feb 25 03:00:12 PM PST 24
Peak memory 234840 kb
Host smart-9e65dbba-e017-4365-93fd-c3a484f79ad2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2286156188 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.alert_handler_intr_test.2286156188
Directory /workspace/30.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.790137777
Short name T777
Test name
Test status
Simulation time 18677917 ps
CPU time 2 seconds
Started Feb 25 03:00:06 PM PST 24
Finished Feb 25 03:00:08 PM PST 24
Peak memory 236636 kb
Host smart-953a8f55-f2be-47ad-b03d-9004501db7d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=790137777 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.alert_handler_intr_test.790137777
Directory /workspace/31.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.3414864898
Short name T816
Test name
Test status
Simulation time 10416368 ps
CPU time 1.26 seconds
Started Feb 25 03:00:05 PM PST 24
Finished Feb 25 03:00:07 PM PST 24
Peak memory 234832 kb
Host smart-e02b7988-f51e-4c02-9d0e-298f95089c3b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3414864898 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.alert_handler_intr_test.3414864898
Directory /workspace/32.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.2686719999
Short name T801
Test name
Test status
Simulation time 7825132 ps
CPU time 1.43 seconds
Started Feb 25 03:00:12 PM PST 24
Finished Feb 25 03:00:13 PM PST 24
Peak memory 236644 kb
Host smart-f8baa6f7-4e01-4089-b3e1-a279610c4a3f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2686719999 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.alert_handler_intr_test.2686719999
Directory /workspace/33.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.805505569
Short name T226
Test name
Test status
Simulation time 11926195 ps
CPU time 1.53 seconds
Started Feb 25 03:00:11 PM PST 24
Finished Feb 25 03:00:12 PM PST 24
Peak memory 236628 kb
Host smart-ce13938c-ab51-4793-b881-e11727bf16a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=805505569 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.alert_handler_intr_test.805505569
Directory /workspace/34.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.2705274063
Short name T749
Test name
Test status
Simulation time 7522040 ps
CPU time 1.5 seconds
Started Feb 25 03:00:12 PM PST 24
Finished Feb 25 03:00:14 PM PST 24
Peak memory 235784 kb
Host smart-85946b0a-41f7-48e2-965e-a58db3fbe298
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2705274063 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.alert_handler_intr_test.2705274063
Directory /workspace/35.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.1903048876
Short name T751
Test name
Test status
Simulation time 25799163 ps
CPU time 1.5 seconds
Started Feb 25 03:00:07 PM PST 24
Finished Feb 25 03:00:09 PM PST 24
Peak memory 236520 kb
Host smart-de761d57-b9f9-467e-87f8-a10068ed587a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1903048876 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.alert_handler_intr_test.1903048876
Directory /workspace/36.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.1424606167
Short name T234
Test name
Test status
Simulation time 15901902 ps
CPU time 1.66 seconds
Started Feb 25 03:00:07 PM PST 24
Finished Feb 25 03:00:09 PM PST 24
Peak memory 235740 kb
Host smart-6e12823a-4439-46a9-9b8c-67dbed43fca4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1424606167 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.alert_handler_intr_test.1424606167
Directory /workspace/37.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.4018221991
Short name T754
Test name
Test status
Simulation time 9579075 ps
CPU time 1.28 seconds
Started Feb 25 03:00:12 PM PST 24
Finished Feb 25 03:00:13 PM PST 24
Peak memory 234696 kb
Host smart-7e23dd5f-4ab5-4010-8206-4e688af97149
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4018221991 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.alert_handler_intr_test.4018221991
Directory /workspace/38.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.1277538205
Short name T808
Test name
Test status
Simulation time 7582445 ps
CPU time 1.37 seconds
Started Feb 25 03:00:09 PM PST 24
Finished Feb 25 03:00:11 PM PST 24
Peak memory 236756 kb
Host smart-3659e50f-a8a0-49c4-8d30-09ba7af002cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1277538205 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.alert_handler_intr_test.1277538205
Directory /workspace/39.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.426221533
Short name T195
Test name
Test status
Simulation time 535087885 ps
CPU time 69.31 seconds
Started Feb 25 02:59:27 PM PST 24
Finished Feb 25 03:00:36 PM PST 24
Peak memory 236604 kb
Host smart-70f75412-17e8-4cde-9dba-a77a73679b6c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=426221533 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_aliasing.426221533
Directory /workspace/4.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.5696761
Short name T792
Test name
Test status
Simulation time 3861453815 ps
CPU time 210.48 seconds
Started Feb 25 02:59:26 PM PST 24
Finished Feb 25 03:02:57 PM PST 24
Peak memory 235676 kb
Host smart-88a87aa6-9aae-43b3-ba47-2020b9b884e7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=5696761 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_bit_bash.5696761
Directory /workspace/4.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.2281447892
Short name T783
Test name
Test status
Simulation time 58017303 ps
CPU time 5.13 seconds
Started Feb 25 02:59:28 PM PST 24
Finished Feb 25 02:59:34 PM PST 24
Peak memory 240544 kb
Host smart-d169b137-6b36-4853-9f66-be8bc3fafa55
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2281447892 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_hw_reset.2281447892
Directory /workspace/4.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.2955657597
Short name T731
Test name
Test status
Simulation time 31977448 ps
CPU time 5.43 seconds
Started Feb 25 02:59:31 PM PST 24
Finished Feb 25 02:59:37 PM PST 24
Peak memory 248448 kb
Host smart-36cb7980-2520-43b0-90fd-7d280f91a511
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955657597 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 4.alert_handler_csr_mem_rw_with_rand_reset.2955657597
Directory /workspace/4.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.1424213132
Short name T769
Test name
Test status
Simulation time 318669546 ps
CPU time 5.61 seconds
Started Feb 25 02:59:23 PM PST 24
Finished Feb 25 02:59:29 PM PST 24
Peak memory 236608 kb
Host smart-3ed4f048-28e2-4cc0-8837-905d61bbc6d1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1424213132 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_rw.1424213132
Directory /workspace/4.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.1274364537
Short name T780
Test name
Test status
Simulation time 635470318 ps
CPU time 46.37 seconds
Started Feb 25 02:59:27 PM PST 24
Finished Feb 25 03:00:13 PM PST 24
Peak memory 248740 kb
Host smart-bfcb9dba-c698-4773-83c4-f92e814cdb2b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1274364537 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_same_csr_out
standing.1274364537
Directory /workspace/4.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.1640414918
Short name T142
Test name
Test status
Simulation time 11670335434 ps
CPU time 150.6 seconds
Started Feb 25 02:59:28 PM PST 24
Finished Feb 25 03:01:59 PM PST 24
Peak memory 257300 kb
Host smart-af9d84d3-6351-418c-9dbd-258647586c8f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1640414918 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shadow_reg_erro
rs.1640414918
Directory /workspace/4.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.3422505052
Short name T832
Test name
Test status
Simulation time 229409791 ps
CPU time 18.11 seconds
Started Feb 25 02:59:31 PM PST 24
Finished Feb 25 02:59:50 PM PST 24
Peak memory 248660 kb
Host smart-381415d6-6ced-4aaa-aa63-25475e0d2a7e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3422505052 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_errors.3422505052
Directory /workspace/4.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.228292396
Short name T740
Test name
Test status
Simulation time 11950290 ps
CPU time 1.47 seconds
Started Feb 25 03:00:11 PM PST 24
Finished Feb 25 03:00:12 PM PST 24
Peak memory 236632 kb
Host smart-51039b84-d30b-41f9-8f7c-db512a6e69ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=228292396 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.alert_handler_intr_test.228292396
Directory /workspace/40.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.1372192049
Short name T752
Test name
Test status
Simulation time 9942070 ps
CPU time 1.58 seconds
Started Feb 25 03:00:16 PM PST 24
Finished Feb 25 03:00:18 PM PST 24
Peak memory 235700 kb
Host smart-aacb735e-6917-4bd9-b6f9-82ec53d630e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1372192049 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.alert_handler_intr_test.1372192049
Directory /workspace/41.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.3358526649
Short name T165
Test name
Test status
Simulation time 25296582 ps
CPU time 1.48 seconds
Started Feb 25 03:00:11 PM PST 24
Finished Feb 25 03:00:13 PM PST 24
Peak memory 235756 kb
Host smart-72908e77-ad72-4d4d-b721-a417be2cf1b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3358526649 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.alert_handler_intr_test.3358526649
Directory /workspace/42.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.1419422956
Short name T807
Test name
Test status
Simulation time 17132678 ps
CPU time 1.34 seconds
Started Feb 25 03:00:31 PM PST 24
Finished Feb 25 03:00:32 PM PST 24
Peak memory 236636 kb
Host smart-be426e18-c137-47ae-a381-cbb5f80bd927
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1419422956 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.alert_handler_intr_test.1419422956
Directory /workspace/43.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.298057544
Short name T742
Test name
Test status
Simulation time 38454813 ps
CPU time 1.27 seconds
Started Feb 25 03:00:12 PM PST 24
Finished Feb 25 03:00:14 PM PST 24
Peak memory 236384 kb
Host smart-2cd6b965-b736-43d3-abaf-b6f22e5dccaa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=298057544 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.alert_handler_intr_test.298057544
Directory /workspace/44.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.2770385670
Short name T810
Test name
Test status
Simulation time 9374267 ps
CPU time 1.38 seconds
Started Feb 25 03:00:12 PM PST 24
Finished Feb 25 03:00:13 PM PST 24
Peak memory 235632 kb
Host smart-160b33fb-6141-4f83-b098-c5fde8c415be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2770385670 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.alert_handler_intr_test.2770385670
Directory /workspace/45.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.2571773442
Short name T735
Test name
Test status
Simulation time 10785921 ps
CPU time 1.37 seconds
Started Feb 25 03:00:13 PM PST 24
Finished Feb 25 03:00:14 PM PST 24
Peak memory 235748 kb
Host smart-78d5b422-31ba-4e5a-9088-9ef4c741a129
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2571773442 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.alert_handler_intr_test.2571773442
Directory /workspace/46.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.2728635303
Short name T721
Test name
Test status
Simulation time 8013692 ps
CPU time 1.44 seconds
Started Feb 25 03:00:10 PM PST 24
Finished Feb 25 03:00:12 PM PST 24
Peak memory 236612 kb
Host smart-239f18a9-8c7c-4155-adff-d250f720e343
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2728635303 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.alert_handler_intr_test.2728635303
Directory /workspace/47.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.3963358056
Short name T829
Test name
Test status
Simulation time 13967315 ps
CPU time 1.33 seconds
Started Feb 25 03:00:11 PM PST 24
Finished Feb 25 03:00:12 PM PST 24
Peak memory 234772 kb
Host smart-e3e56c2d-ba1f-46ae-b3aa-132c06251cd2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3963358056 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.alert_handler_intr_test.3963358056
Directory /workspace/48.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.506724353
Short name T820
Test name
Test status
Simulation time 22658587 ps
CPU time 1.44 seconds
Started Feb 25 03:00:16 PM PST 24
Finished Feb 25 03:00:18 PM PST 24
Peak memory 235748 kb
Host smart-6440f4a5-443a-4701-b6e4-68d6977fcbd4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=506724353 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.alert_handler_intr_test.506724353
Directory /workspace/49.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.592050761
Short name T767
Test name
Test status
Simulation time 63966201 ps
CPU time 5.46 seconds
Started Feb 25 02:59:40 PM PST 24
Finished Feb 25 02:59:46 PM PST 24
Peak memory 256952 kb
Host smart-3dfaa777-bff6-408f-a4c5-41b873b0e01c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592050761 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 5.alert_handler_csr_mem_rw_with_rand_reset.592050761
Directory /workspace/5.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.3528267917
Short name T727
Test name
Test status
Simulation time 50650450 ps
CPU time 4.81 seconds
Started Feb 25 02:59:26 PM PST 24
Finished Feb 25 02:59:31 PM PST 24
Peak memory 239464 kb
Host smart-0b7512f0-c4c4-4408-92df-6d078d706c78
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3528267917 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_rw.3528267917
Directory /workspace/5.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.874077160
Short name T809
Test name
Test status
Simulation time 10763914 ps
CPU time 1.55 seconds
Started Feb 25 02:59:25 PM PST 24
Finished Feb 25 02:59:26 PM PST 24
Peak memory 235760 kb
Host smart-adaa285b-2537-4508-aee7-5453f4ef2681
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=874077160 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_intr_test.874077160
Directory /workspace/5.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.2278382535
Short name T791
Test name
Test status
Simulation time 456865748 ps
CPU time 11.03 seconds
Started Feb 25 02:59:41 PM PST 24
Finished Feb 25 02:59:53 PM PST 24
Peak memory 243920 kb
Host smart-b720a5f9-7954-474c-9f28-85407ea4e0cc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2278382535 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_same_csr_out
standing.2278382535
Directory /workspace/5.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.25732698
Short name T152
Test name
Test status
Simulation time 819194660 ps
CPU time 113.18 seconds
Started Feb 25 02:59:28 PM PST 24
Finished Feb 25 03:01:21 PM PST 24
Peak memory 264668 kb
Host smart-e2fbaf52-c307-4b81-8190-30323b1940e4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=25732698 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shadow_reg_errors
.25732698
Directory /workspace/5.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.627304511
Short name T129
Test name
Test status
Simulation time 7541120231 ps
CPU time 521.38 seconds
Started Feb 25 02:59:28 PM PST 24
Finished Feb 25 03:08:10 PM PST 24
Peak memory 269216 kb
Host smart-aba00c48-7723-4a9c-bdfc-dbc9efe201a3
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627304511 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.alert_handler_shadow_reg_errors_with_csr_rw.627304511
Directory /workspace/5.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.1110460505
Short name T738
Test name
Test status
Simulation time 61265485 ps
CPU time 7.72 seconds
Started Feb 25 02:59:32 PM PST 24
Finished Feb 25 02:59:40 PM PST 24
Peak memory 248532 kb
Host smart-f6c71ee1-57d7-4a65-8520-6b3992280c63
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1110460505 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_errors.1110460505
Directory /workspace/5.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.1960642280
Short name T798
Test name
Test status
Simulation time 604867845 ps
CPU time 5.53 seconds
Started Feb 25 02:59:48 PM PST 24
Finished Feb 25 02:59:54 PM PST 24
Peak memory 250268 kb
Host smart-86f556ab-ae70-43c8-8cb3-ad9c3d8f8bcf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960642280 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 6.alert_handler_csr_mem_rw_with_rand_reset.1960642280
Directory /workspace/6.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.696351994
Short name T771
Test name
Test status
Simulation time 39245727 ps
CPU time 5.68 seconds
Started Feb 25 02:59:40 PM PST 24
Finished Feb 25 02:59:46 PM PST 24
Peak memory 235580 kb
Host smart-6bfc26b1-91b4-4fa9-8648-62b87f1ab60d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=696351994 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_rw.696351994
Directory /workspace/6.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.598190628
Short name T795
Test name
Test status
Simulation time 27789557 ps
CPU time 2.18 seconds
Started Feb 25 02:59:42 PM PST 24
Finished Feb 25 02:59:44 PM PST 24
Peak memory 236624 kb
Host smart-ed609c67-4344-4c03-9a20-9f19092cc101
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=598190628 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_intr_test.598190628
Directory /workspace/6.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.3668020887
Short name T812
Test name
Test status
Simulation time 253323869 ps
CPU time 20.48 seconds
Started Feb 25 02:59:40 PM PST 24
Finished Feb 25 03:00:00 PM PST 24
Peak memory 240540 kb
Host smart-74a8fd9e-81bd-4681-8157-fc05b2467e66
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3668020887 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_same_csr_out
standing.3668020887
Directory /workspace/6.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.3255218178
Short name T753
Test name
Test status
Simulation time 65695179 ps
CPU time 8.65 seconds
Started Feb 25 02:59:40 PM PST 24
Finished Feb 25 02:59:49 PM PST 24
Peak memory 248800 kb
Host smart-0de61cb9-130a-4163-8c02-9bf6f40947cd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3255218178 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_errors.3255218178
Directory /workspace/6.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.1497534038
Short name T793
Test name
Test status
Simulation time 500522668 ps
CPU time 8.78 seconds
Started Feb 25 02:59:40 PM PST 24
Finished Feb 25 02:59:48 PM PST 24
Peak memory 240560 kb
Host smart-cf716c1a-8ba9-4295-a35f-06bf3aa3e9e4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497534038 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 7.alert_handler_csr_mem_rw_with_rand_reset.1497534038
Directory /workspace/7.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.276543110
Short name T726
Test name
Test status
Simulation time 19372335 ps
CPU time 3.74 seconds
Started Feb 25 02:59:40 PM PST 24
Finished Feb 25 02:59:44 PM PST 24
Peak memory 235740 kb
Host smart-c5dafe35-1dcc-4980-8661-37eb70c93220
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=276543110 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_rw.276543110
Directory /workspace/7.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.1698900555
Short name T800
Test name
Test status
Simulation time 13251864 ps
CPU time 1.65 seconds
Started Feb 25 02:59:43 PM PST 24
Finished Feb 25 02:59:45 PM PST 24
Peak memory 236632 kb
Host smart-f8c736e0-d516-4e5a-aefb-88debea43817
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1698900555 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_intr_test.1698900555
Directory /workspace/7.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.2489300017
Short name T748
Test name
Test status
Simulation time 168520240 ps
CPU time 23.82 seconds
Started Feb 25 02:59:48 PM PST 24
Finished Feb 25 03:00:12 PM PST 24
Peak memory 244672 kb
Host smart-03c1c7a8-68cf-4b9c-aaf7-558f20ebe955
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2489300017 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_same_csr_out
standing.2489300017
Directory /workspace/7.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.4182184047
Short name T723
Test name
Test status
Simulation time 285323141 ps
CPU time 22.05 seconds
Started Feb 25 02:59:43 PM PST 24
Finished Feb 25 03:00:05 PM PST 24
Peak memory 253468 kb
Host smart-afb1dc2e-87b3-4d5a-9589-e1f718498420
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4182184047 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_errors.4182184047
Directory /workspace/7.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.3043633191
Short name T806
Test name
Test status
Simulation time 591250290 ps
CPU time 21.14 seconds
Started Feb 25 02:59:39 PM PST 24
Finished Feb 25 03:00:00 PM PST 24
Peak memory 248752 kb
Host smart-04222afe-cccb-45df-a616-6b4065f63892
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3043633191 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_intg_err.3043633191
Directory /workspace/7.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.1479008270
Short name T794
Test name
Test status
Simulation time 108581822 ps
CPU time 9.5 seconds
Started Feb 25 02:59:44 PM PST 24
Finished Feb 25 02:59:53 PM PST 24
Peak memory 239648 kb
Host smart-4db9e309-4b6b-405e-a767-2b3012dca489
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479008270 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 8.alert_handler_csr_mem_rw_with_rand_reset.1479008270
Directory /workspace/8.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.3963898536
Short name T183
Test name
Test status
Simulation time 402083924 ps
CPU time 4.87 seconds
Started Feb 25 02:59:44 PM PST 24
Finished Feb 25 02:59:49 PM PST 24
Peak memory 240480 kb
Host smart-b77d4416-431a-4d9c-9af7-2723c6331aa6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3963898536 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_rw.3963898536
Directory /workspace/8.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.560625853
Short name T790
Test name
Test status
Simulation time 10592098 ps
CPU time 1.26 seconds
Started Feb 25 02:59:37 PM PST 24
Finished Feb 25 02:59:38 PM PST 24
Peak memory 234852 kb
Host smart-ea23f93e-3e06-4131-bff2-49abf0e04607
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=560625853 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_intr_test.560625853
Directory /workspace/8.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.379216494
Short name T758
Test name
Test status
Simulation time 822537056 ps
CPU time 19.98 seconds
Started Feb 25 02:59:39 PM PST 24
Finished Feb 25 02:59:59 PM PST 24
Peak memory 244792 kb
Host smart-0f8e359d-1ad2-484e-bc9f-d00549683d8c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=379216494 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_same_csr_outs
tanding.379216494
Directory /workspace/8.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.3373136791
Short name T778
Test name
Test status
Simulation time 898618498 ps
CPU time 16 seconds
Started Feb 25 02:59:43 PM PST 24
Finished Feb 25 02:59:59 PM PST 24
Peak memory 252872 kb
Host smart-069152b0-2307-4e8d-9481-fde5e7e65825
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3373136791 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_errors.3373136791
Directory /workspace/8.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.4009563553
Short name T773
Test name
Test status
Simulation time 441843009 ps
CPU time 8.29 seconds
Started Feb 25 02:59:43 PM PST 24
Finished Feb 25 02:59:51 PM PST 24
Peak memory 239448 kb
Host smart-73b5f160-7a23-4499-abc5-bf9b60f78377
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009563553 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 9.alert_handler_csr_mem_rw_with_rand_reset.4009563553
Directory /workspace/9.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.2612399969
Short name T349
Test name
Test status
Simulation time 52422938 ps
CPU time 5.35 seconds
Started Feb 25 02:59:39 PM PST 24
Finished Feb 25 02:59:44 PM PST 24
Peak memory 236600 kb
Host smart-0d257718-9680-4799-955c-c731b7a1a58a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2612399969 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_rw.2612399969
Directory /workspace/9.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.220217
Short name T835
Test name
Test status
Simulation time 12151425 ps
CPU time 1.31 seconds
Started Feb 25 02:59:43 PM PST 24
Finished Feb 25 02:59:44 PM PST 24
Peak memory 236644 kb
Host smart-66e85e4b-afed-451c-be64-bd8246362395
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=220217 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_intr_test.220217
Directory /workspace/9.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.3613614507
Short name T744
Test name
Test status
Simulation time 1234683995 ps
CPU time 23.93 seconds
Started Feb 25 02:59:40 PM PST 24
Finished Feb 25 03:00:04 PM PST 24
Peak memory 240444 kb
Host smart-b3011fb6-b139-4d6f-80a2-6c21a4a78a58
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3613614507 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_same_csr_out
standing.3613614507
Directory /workspace/9.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.2296984273
Short name T130
Test name
Test status
Simulation time 9339344111 ps
CPU time 155.07 seconds
Started Feb 25 02:59:40 PM PST 24
Finished Feb 25 03:02:15 PM PST 24
Peak memory 265480 kb
Host smart-7ee3f4d9-bd71-44cc-bcf5-ae37e02dfd59
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2296984273 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shadow_reg_erro
rs.2296984273
Directory /workspace/9.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.1607350089
Short name T146
Test name
Test status
Simulation time 8648920632 ps
CPU time 572.64 seconds
Started Feb 25 02:59:43 PM PST 24
Finished Feb 25 03:09:15 PM PST 24
Peak memory 265508 kb
Host smart-2beaf154-d83d-4d36-b170-01b9a3488ffe
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607350089 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.alert_handler_shadow_reg_errors_with_csr_rw.1607350089
Directory /workspace/9.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.1655943271
Short name T746
Test name
Test status
Simulation time 192724800 ps
CPU time 14.2 seconds
Started Feb 25 02:59:38 PM PST 24
Finished Feb 25 02:59:53 PM PST 24
Peak memory 248664 kb
Host smart-a733d4cd-0b1d-4c2b-9e31-ebcd8732ea7c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1655943271 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_errors.1655943271
Directory /workspace/9.alert_handler_tl_errors/latest

Test location /workspace/coverage/default/0.alert_handler_entropy.1486618998
Short name T107
Test name
Test status
Simulation time 41076074106 ps
CPU time 871.29 seconds
Started Feb 25 03:19:56 PM PST 24
Finished Feb 25 03:34:28 PM PST 24
Peak memory 272332 kb
Host smart-4a17a414-7841-4674-831e-695298f22f3a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486618998 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy.1486618998
Directory /workspace/0.alert_handler_entropy/latest

Test location /workspace/coverage/default/0.alert_handler_entropy_stress.364561706
Short name T492
Test name
Test status
Simulation time 1034270234 ps
CPU time 22.28 seconds
Started Feb 25 03:19:51 PM PST 24
Finished Feb 25 03:20:14 PM PST 24
Peak memory 240012 kb
Host smart-a1f5b429-fc29-40b2-b5b3-d54b71dd8d20
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=364561706 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy_stress.364561706
Directory /workspace/0.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/0.alert_handler_esc_alert_accum.1840145065
Short name T353
Test name
Test status
Simulation time 9032655274 ps
CPU time 137.15 seconds
Started Feb 25 03:20:03 PM PST 24
Finished Feb 25 03:22:20 PM PST 24
Peak memory 247828 kb
Host smart-e3823f74-6159-40dd-98bd-e1a0a4092532
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18401
45065 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_alert_accum.1840145065
Directory /workspace/0.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/0.alert_handler_esc_intr_timeout.3883400282
Short name T509
Test name
Test status
Simulation time 389482827 ps
CPU time 30.7 seconds
Started Feb 25 03:19:48 PM PST 24
Finished Feb 25 03:20:19 PM PST 24
Peak memory 254520 kb
Host smart-968439e3-7d1f-46f3-9e82-25d78ef5ade3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38834
00282 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_intr_timeout.3883400282
Directory /workspace/0.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_lpg_stub_clk.2356374319
Short name T118
Test name
Test status
Simulation time 21539516074 ps
CPU time 1538.02 seconds
Started Feb 25 03:19:54 PM PST 24
Finished Feb 25 03:45:32 PM PST 24
Peak memory 272888 kb
Host smart-e2b24214-3a4f-4674-9808-344d46c2a8c5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356374319 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg_stub_clk.2356374319
Directory /workspace/0.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/0.alert_handler_ping_timeout.3134675392
Short name T291
Test name
Test status
Simulation time 7120646057 ps
CPU time 267.25 seconds
Started Feb 25 03:19:51 PM PST 24
Finished Feb 25 03:24:19 PM PST 24
Peak memory 247180 kb
Host smart-1c266318-b4f7-457f-9467-19dbace08c35
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134675392 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_ping_timeout.3134675392
Directory /workspace/0.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_random_alerts.1315846840
Short name T690
Test name
Test status
Simulation time 2539900975 ps
CPU time 40.81 seconds
Started Feb 25 03:19:46 PM PST 24
Finished Feb 25 03:20:27 PM PST 24
Peak memory 248288 kb
Host smart-5d6540e8-e9a1-4e77-bbcb-2ca68c7b0119
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13158
46840 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_alerts.1315846840
Directory /workspace/0.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/0.alert_handler_random_classes.495653018
Short name T546
Test name
Test status
Simulation time 819921427 ps
CPU time 53.07 seconds
Started Feb 25 03:19:57 PM PST 24
Finished Feb 25 03:20:51 PM PST 24
Peak memory 255052 kb
Host smart-9f542bfc-168c-42e6-9503-70c0a05c6608
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49565
3018 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_classes.495653018
Directory /workspace/0.alert_handler_random_classes/latest

Test location /workspace/coverage/default/0.alert_handler_sig_int_fail.34182636
Short name T678
Test name
Test status
Simulation time 3022372738 ps
CPU time 42.27 seconds
Started Feb 25 03:19:46 PM PST 24
Finished Feb 25 03:20:29 PM PST 24
Peak memory 254736 kb
Host smart-febd0daf-7147-4fbf-abd0-3d0db6128f39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34182
636 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sig_int_fail.34182636
Directory /workspace/0.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/0.alert_handler_smoke.3175391258
Short name T704
Test name
Test status
Simulation time 4205470776 ps
CPU time 48.69 seconds
Started Feb 25 03:19:45 PM PST 24
Finished Feb 25 03:20:35 PM PST 24
Peak memory 248432 kb
Host smart-ed86f533-96d8-4809-a669-b0fd9775ad36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31753
91258 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_smoke.3175391258
Directory /workspace/0.alert_handler_smoke/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all.1835130501
Short name T245
Test name
Test status
Simulation time 4734538985 ps
CPU time 264.64 seconds
Started Feb 25 03:19:48 PM PST 24
Finished Feb 25 03:24:13 PM PST 24
Peak memory 255900 kb
Host smart-4358ff53-cfa9-4c14-81f0-986991b78c64
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835130501 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_han
dler_stress_all.1835130501
Directory /workspace/0.alert_handler_stress_all/latest

Test location /workspace/coverage/default/1.alert_handler_entropy.1136181598
Short name T551
Test name
Test status
Simulation time 65607391243 ps
CPU time 1825.16 seconds
Started Feb 25 03:19:58 PM PST 24
Finished Feb 25 03:50:24 PM PST 24
Peak memory 272828 kb
Host smart-f6d40fb1-a33b-4419-af5b-a0fcf6af125e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1136181598 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy.1136181598
Directory /workspace/1.alert_handler_entropy/latest

Test location /workspace/coverage/default/1.alert_handler_entropy_stress.3663588213
Short name T503
Test name
Test status
Simulation time 212189223 ps
CPU time 12.44 seconds
Started Feb 25 03:20:19 PM PST 24
Finished Feb 25 03:20:32 PM PST 24
Peak memory 248220 kb
Host smart-0fb556a1-ef28-4831-8671-900e34d77862
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3663588213 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy_stress.3663588213
Directory /workspace/1.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/1.alert_handler_esc_alert_accum.2747609580
Short name T427
Test name
Test status
Simulation time 14029533519 ps
CPU time 214.71 seconds
Started Feb 25 03:20:17 PM PST 24
Finished Feb 25 03:23:52 PM PST 24
Peak memory 255516 kb
Host smart-3c6ffc03-ff46-4596-b92a-69746ede4c09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27476
09580 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_alert_accum.2747609580
Directory /workspace/1.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/1.alert_handler_esc_intr_timeout.2910668786
Short name T81
Test name
Test status
Simulation time 1585330326 ps
CPU time 28.07 seconds
Started Feb 25 03:20:13 PM PST 24
Finished Feb 25 03:20:42 PM PST 24
Peak memory 253924 kb
Host smart-9d0f3e3a-737c-4c0e-b9a9-8513400cd338
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29106
68786 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_intr_timeout.2910668786
Directory /workspace/1.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_lpg.1154494786
Short name T339
Test name
Test status
Simulation time 74536425425 ps
CPU time 1650.02 seconds
Started Feb 25 03:19:59 PM PST 24
Finished Feb 25 03:47:29 PM PST 24
Peak memory 270428 kb
Host smart-3a5e6d67-401d-4577-9df5-b966d9ac8547
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1154494786 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg.1154494786
Directory /workspace/1.alert_handler_lpg/latest

Test location /workspace/coverage/default/1.alert_handler_lpg_stub_clk.3374720245
Short name T380
Test name
Test status
Simulation time 49546419919 ps
CPU time 712.31 seconds
Started Feb 25 03:20:04 PM PST 24
Finished Feb 25 03:31:57 PM PST 24
Peak memory 264292 kb
Host smart-80469b28-5fe9-4fb9-b08f-12e394e12149
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3374720245 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg_stub_clk.3374720245
Directory /workspace/1.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/1.alert_handler_ping_timeout.1275207743
Short name T220
Test name
Test status
Simulation time 16075122702 ps
CPU time 655.03 seconds
Started Feb 25 03:20:11 PM PST 24
Finished Feb 25 03:31:07 PM PST 24
Peak memory 246264 kb
Host smart-ad1155c0-d5af-49c2-a4ed-24311587e26d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275207743 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_ping_timeout.1275207743
Directory /workspace/1.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_random_alerts.1438963365
Short name T586
Test name
Test status
Simulation time 820120812 ps
CPU time 49.5 seconds
Started Feb 25 03:20:00 PM PST 24
Finished Feb 25 03:20:50 PM PST 24
Peak memory 248220 kb
Host smart-7d6d50e9-012e-4729-97fc-a699562517c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14389
63365 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_alerts.1438963365
Directory /workspace/1.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/1.alert_handler_random_classes.1270088119
Short name T616
Test name
Test status
Simulation time 681400372 ps
CPU time 28.5 seconds
Started Feb 25 03:19:48 PM PST 24
Finished Feb 25 03:20:17 PM PST 24
Peak memory 254228 kb
Host smart-6a5766da-994c-43b6-a156-7c6f21764b23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12700
88119 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_classes.1270088119
Directory /workspace/1.alert_handler_random_classes/latest

Test location /workspace/coverage/default/1.alert_handler_sec_cm.3552652619
Short name T32
Test name
Test status
Simulation time 2164089320 ps
CPU time 48.3 seconds
Started Feb 25 03:20:02 PM PST 24
Finished Feb 25 03:20:51 PM PST 24
Peak memory 269748 kb
Host smart-aba375b7-35fe-4ced-af98-eb76a2a4340c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3552652619 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sec_cm.3552652619
Directory /workspace/1.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/1.alert_handler_smoke.1858395008
Short name T565
Test name
Test status
Simulation time 108895748 ps
CPU time 7.84 seconds
Started Feb 25 03:19:51 PM PST 24
Finished Feb 25 03:19:59 PM PST 24
Peak memory 248232 kb
Host smart-3b86bf2a-cd25-4c87-ac8e-b00c84d96ca0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18583
95008 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_smoke.1858395008
Directory /workspace/1.alert_handler_smoke/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all.2721200286
Short name T423
Test name
Test status
Simulation time 37901415077 ps
CPU time 1730.97 seconds
Started Feb 25 03:20:13 PM PST 24
Finished Feb 25 03:49:06 PM PST 24
Peak memory 272896 kb
Host smart-b6bc11f8-dbf2-4de4-90c4-7172f556b45e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721200286 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_han
dler_stress_all.2721200286
Directory /workspace/1.alert_handler_stress_all/latest

Test location /workspace/coverage/default/10.alert_handler_alert_accum_saturation.87587457
Short name T200
Test name
Test status
Simulation time 103187356 ps
CPU time 2.94 seconds
Started Feb 25 03:20:37 PM PST 24
Finished Feb 25 03:20:40 PM PST 24
Peak memory 248524 kb
Host smart-df67d4b3-ad85-4654-b418-c8e1f4a4a40c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=87587457 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_alert_accum_saturation.87587457
Directory /workspace/10.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/10.alert_handler_entropy.2272432884
Short name T460
Test name
Test status
Simulation time 8610837735 ps
CPU time 801.14 seconds
Started Feb 25 03:20:41 PM PST 24
Finished Feb 25 03:34:02 PM PST 24
Peak memory 264692 kb
Host smart-26ee8517-2b13-4b25-bc70-ac4eb57e6f21
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272432884 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy.2272432884
Directory /workspace/10.alert_handler_entropy/latest

Test location /workspace/coverage/default/10.alert_handler_entropy_stress.2304927284
Short name T571
Test name
Test status
Simulation time 95831636 ps
CPU time 6.13 seconds
Started Feb 25 03:20:34 PM PST 24
Finished Feb 25 03:20:40 PM PST 24
Peak memory 240032 kb
Host smart-33d9d9b6-3108-45fd-930d-dec174b1f46a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2304927284 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy_stress.2304927284
Directory /workspace/10.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/10.alert_handler_esc_alert_accum.1832203665
Short name T44
Test name
Test status
Simulation time 1774016733 ps
CPU time 146.03 seconds
Started Feb 25 03:20:34 PM PST 24
Finished Feb 25 03:23:00 PM PST 24
Peak memory 255696 kb
Host smart-043dd681-3a9d-4ae1-ab6a-0dd63a6c4938
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18322
03665 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_alert_accum.1832203665
Directory /workspace/10.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/10.alert_handler_esc_intr_timeout.4291754457
Short name T402
Test name
Test status
Simulation time 2075325550 ps
CPU time 34.23 seconds
Started Feb 25 03:20:21 PM PST 24
Finished Feb 25 03:20:56 PM PST 24
Peak memory 254688 kb
Host smart-8bf6c1a0-d65d-4122-a678-d413d6d1960c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42917
54457 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_intr_timeout.4291754457
Directory /workspace/10.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_lpg_stub_clk.1484752624
Short name T578
Test name
Test status
Simulation time 27078201295 ps
CPU time 1642.03 seconds
Started Feb 25 03:20:28 PM PST 24
Finished Feb 25 03:47:51 PM PST 24
Peak memory 264292 kb
Host smart-41a98296-3095-4cf7-bf91-7b89754e8957
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484752624 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg_stub_clk.1484752624
Directory /workspace/10.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/10.alert_handler_ping_timeout.2753909748
Short name T303
Test name
Test status
Simulation time 19006134581 ps
CPU time 376.9 seconds
Started Feb 25 03:20:28 PM PST 24
Finished Feb 25 03:26:45 PM PST 24
Peak memory 247160 kb
Host smart-1858a9da-9923-4ac5-843a-c116b60fd541
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753909748 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_ping_timeout.2753909748
Directory /workspace/10.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_random_alerts.2315766340
Short name T388
Test name
Test status
Simulation time 255597174 ps
CPU time 15 seconds
Started Feb 25 03:20:30 PM PST 24
Finished Feb 25 03:20:45 PM PST 24
Peak memory 248248 kb
Host smart-c84d5b21-62ad-40ba-a767-612f90edbbaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23157
66340 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_alerts.2315766340
Directory /workspace/10.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/10.alert_handler_random_classes.2235415429
Short name T464
Test name
Test status
Simulation time 951814679 ps
CPU time 57.16 seconds
Started Feb 25 03:20:35 PM PST 24
Finished Feb 25 03:21:32 PM PST 24
Peak memory 254716 kb
Host smart-c8b0184f-5420-4e67-9b07-e2b78e1c393c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22354
15429 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_classes.2235415429
Directory /workspace/10.alert_handler_random_classes/latest

Test location /workspace/coverage/default/10.alert_handler_sig_int_fail.1953480498
Short name T517
Test name
Test status
Simulation time 471619179 ps
CPU time 17.28 seconds
Started Feb 25 03:20:28 PM PST 24
Finished Feb 25 03:20:45 PM PST 24
Peak memory 248232 kb
Host smart-c0262da7-c101-47b0-8f95-c5c135340a23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19534
80498 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_sig_int_fail.1953480498
Directory /workspace/10.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/10.alert_handler_smoke.3892252519
Short name T648
Test name
Test status
Simulation time 1064585545 ps
CPU time 18.31 seconds
Started Feb 25 03:20:23 PM PST 24
Finished Feb 25 03:20:41 PM PST 24
Peak memory 248268 kb
Host smart-cf0089db-3fb7-402c-830e-35257a261006
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38922
52519 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_smoke.3892252519
Directory /workspace/10.alert_handler_smoke/latest

Test location /workspace/coverage/default/11.alert_handler_entropy.716405735
Short name T699
Test name
Test status
Simulation time 58474668649 ps
CPU time 679.64 seconds
Started Feb 25 03:20:32 PM PST 24
Finished Feb 25 03:31:52 PM PST 24
Peak memory 264788 kb
Host smart-e08cbc4c-e733-4a76-b23b-471a1d2eac28
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716405735 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy.716405735
Directory /workspace/11.alert_handler_entropy/latest

Test location /workspace/coverage/default/11.alert_handler_entropy_stress.2715248476
Short name T714
Test name
Test status
Simulation time 922698477 ps
CPU time 13.26 seconds
Started Feb 25 03:20:32 PM PST 24
Finished Feb 25 03:20:46 PM PST 24
Peak memory 248236 kb
Host smart-7d8ae658-0afe-4ec4-8788-395ac67c98ad
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2715248476 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy_stress.2715248476
Directory /workspace/11.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/11.alert_handler_esc_alert_accum.621286340
Short name T599
Test name
Test status
Simulation time 10107788925 ps
CPU time 286.18 seconds
Started Feb 25 03:20:41 PM PST 24
Finished Feb 25 03:25:27 PM PST 24
Peak memory 255620 kb
Host smart-e77a9ca1-8c01-42b0-9f1e-a44a3e17ea9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62128
6340 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_alert_accum.621286340
Directory /workspace/11.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/11.alert_handler_esc_intr_timeout.820017430
Short name T532
Test name
Test status
Simulation time 532878372 ps
CPU time 33.02 seconds
Started Feb 25 03:20:35 PM PST 24
Finished Feb 25 03:21:08 PM PST 24
Peak memory 254308 kb
Host smart-8baee765-bb24-4887-a8a7-b75c4c2e5420
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82001
7430 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_intr_timeout.820017430
Directory /workspace/11.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_lpg_stub_clk.2835693226
Short name T398
Test name
Test status
Simulation time 103435508836 ps
CPU time 1607.07 seconds
Started Feb 25 03:20:33 PM PST 24
Finished Feb 25 03:47:20 PM PST 24
Peak memory 271900 kb
Host smart-1230c0b8-7bdf-4833-9560-50fc584a6573
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835693226 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg_stub_clk.2835693226
Directory /workspace/11.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/11.alert_handler_ping_timeout.3175360419
Short name T309
Test name
Test status
Simulation time 2241370339 ps
CPU time 90.22 seconds
Started Feb 25 03:20:30 PM PST 24
Finished Feb 25 03:22:00 PM PST 24
Peak memory 247084 kb
Host smart-530676ed-a651-4f58-9f1c-4694621fb72e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175360419 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_ping_timeout.3175360419
Directory /workspace/11.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_random_alerts.964044043
Short name T466
Test name
Test status
Simulation time 391734004 ps
CPU time 9.46 seconds
Started Feb 25 03:20:29 PM PST 24
Finished Feb 25 03:20:38 PM PST 24
Peak memory 248292 kb
Host smart-9f25234a-a74c-49ed-a518-f15b49e29fda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96404
4043 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_alerts.964044043
Directory /workspace/11.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/11.alert_handler_random_classes.580136506
Short name T93
Test name
Test status
Simulation time 1136571942 ps
CPU time 30.54 seconds
Started Feb 25 03:20:29 PM PST 24
Finished Feb 25 03:21:00 PM PST 24
Peak memory 254532 kb
Host smart-be687a05-e08f-4ed2-9706-ff6a6571aa77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58013
6506 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_classes.580136506
Directory /workspace/11.alert_handler_random_classes/latest

Test location /workspace/coverage/default/11.alert_handler_sig_int_fail.1556637449
Short name T501
Test name
Test status
Simulation time 167817699 ps
CPU time 14.91 seconds
Started Feb 25 03:20:32 PM PST 24
Finished Feb 25 03:20:47 PM PST 24
Peak memory 248200 kb
Host smart-316a0c0b-9fcc-4741-92d5-a11c2d6bae42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15566
37449 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_sig_int_fail.1556637449
Directory /workspace/11.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/11.alert_handler_smoke.2992727492
Short name T711
Test name
Test status
Simulation time 2978220149 ps
CPU time 48.77 seconds
Started Feb 25 03:20:35 PM PST 24
Finished Feb 25 03:21:24 PM PST 24
Peak memory 255276 kb
Host smart-814525a2-fcee-4588-b3d5-e74c7f75af63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29927
27492 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_smoke.2992727492
Directory /workspace/11.alert_handler_smoke/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all.3057645101
Short name T615
Test name
Test status
Simulation time 128498283 ps
CPU time 15.22 seconds
Started Feb 25 03:20:26 PM PST 24
Finished Feb 25 03:20:41 PM PST 24
Peak memory 255112 kb
Host smart-68b2c2f4-f170-4617-9c3f-88724411a716
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057645101 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_ha
ndler_stress_all.3057645101
Directory /workspace/11.alert_handler_stress_all/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all_with_rand_reset.3110200986
Short name T83
Test name
Test status
Simulation time 285906892187 ps
CPU time 6431.27 seconds
Started Feb 25 03:20:31 PM PST 24
Finished Feb 25 05:07:43 PM PST 24
Peak memory 370660 kb
Host smart-26788e2f-4c99-4f43-bc1f-3321f737523d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110200986 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 11.alert_handler_stress_all_with_rand_reset.3110200986
Directory /workspace/11.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.alert_handler_alert_accum_saturation.1021608109
Short name T207
Test name
Test status
Simulation time 162931459 ps
CPU time 2.48 seconds
Started Feb 25 03:20:33 PM PST 24
Finished Feb 25 03:20:35 PM PST 24
Peak memory 248528 kb
Host smart-db29f738-5cc0-42ee-a955-62eee175c9fa
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1021608109 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_alert_accum_saturation.1021608109
Directory /workspace/12.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/12.alert_handler_entropy.324000850
Short name T688
Test name
Test status
Simulation time 13524050871 ps
CPU time 1329.11 seconds
Started Feb 25 03:20:42 PM PST 24
Finished Feb 25 03:42:51 PM PST 24
Peak memory 284140 kb
Host smart-7126b344-abaf-4265-a6ce-cf42e1778d81
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324000850 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy.324000850
Directory /workspace/12.alert_handler_entropy/latest

Test location /workspace/coverage/default/12.alert_handler_esc_alert_accum.2529689451
Short name T657
Test name
Test status
Simulation time 39507998675 ps
CPU time 195.77 seconds
Started Feb 25 03:20:33 PM PST 24
Finished Feb 25 03:23:49 PM PST 24
Peak memory 256476 kb
Host smart-6d24cf73-2391-4ef5-b185-b80fbb7854e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25296
89451 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_alert_accum.2529689451
Directory /workspace/12.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/12.alert_handler_esc_intr_timeout.790364955
Short name T361
Test name
Test status
Simulation time 2844879119 ps
CPU time 57.56 seconds
Started Feb 25 03:20:32 PM PST 24
Finished Feb 25 03:21:29 PM PST 24
Peak memory 254772 kb
Host smart-d3523a0d-eff4-4e5d-88d9-3aeafb3cb246
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79036
4955 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_intr_timeout.790364955
Directory /workspace/12.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_lpg.2226971037
Short name T342
Test name
Test status
Simulation time 44454059237 ps
CPU time 1022.32 seconds
Started Feb 25 03:20:30 PM PST 24
Finished Feb 25 03:37:32 PM PST 24
Peak memory 272676 kb
Host smart-d6bdb5b0-87dd-4369-ae96-f1e202156264
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226971037 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg.2226971037
Directory /workspace/12.alert_handler_lpg/latest

Test location /workspace/coverage/default/12.alert_handler_lpg_stub_clk.2426928036
Short name T647
Test name
Test status
Simulation time 273994813699 ps
CPU time 1342.28 seconds
Started Feb 25 03:20:29 PM PST 24
Finished Feb 25 03:42:51 PM PST 24
Peak memory 288340 kb
Host smart-216cb768-bd2f-4bce-b64a-fa398d60ff28
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2426928036 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg_stub_clk.2426928036
Directory /workspace/12.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/12.alert_handler_ping_timeout.3894652254
Short name T11
Test name
Test status
Simulation time 24246257301 ps
CPU time 156.39 seconds
Started Feb 25 03:20:30 PM PST 24
Finished Feb 25 03:23:07 PM PST 24
Peak memory 247116 kb
Host smart-db7f5169-6b56-450c-96a2-3398da3d1312
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894652254 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_ping_timeout.3894652254
Directory /workspace/12.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_random_alerts.3163462496
Short name T23
Test name
Test status
Simulation time 268039240 ps
CPU time 27.54 seconds
Started Feb 25 03:20:32 PM PST 24
Finished Feb 25 03:21:00 PM PST 24
Peak memory 248220 kb
Host smart-fa2367c9-c19a-4ae4-9993-182ce76e22bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31634
62496 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_alerts.3163462496
Directory /workspace/12.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/12.alert_handler_random_classes.1774758755
Short name T580
Test name
Test status
Simulation time 297858959 ps
CPU time 26.15 seconds
Started Feb 25 03:20:30 PM PST 24
Finished Feb 25 03:20:56 PM PST 24
Peak memory 254084 kb
Host smart-da50e415-0e5b-4d78-8c03-690d5a67a898
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17747
58755 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_classes.1774758755
Directory /workspace/12.alert_handler_random_classes/latest

Test location /workspace/coverage/default/12.alert_handler_sig_int_fail.2655308550
Short name T528
Test name
Test status
Simulation time 760028538 ps
CPU time 27.93 seconds
Started Feb 25 03:20:30 PM PST 24
Finished Feb 25 03:20:58 PM PST 24
Peak memory 254644 kb
Host smart-60e8c550-db11-41df-8b5a-140da366b2a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26553
08550 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_sig_int_fail.2655308550
Directory /workspace/12.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/12.alert_handler_smoke.6472204
Short name T422
Test name
Test status
Simulation time 643468732 ps
CPU time 40.49 seconds
Started Feb 25 03:20:34 PM PST 24
Finished Feb 25 03:21:15 PM PST 24
Peak memory 255112 kb
Host smart-21100607-8adf-494a-8e57-55621f599740
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64722
04 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_smoke.6472204
Directory /workspace/12.alert_handler_smoke/latest

Test location /workspace/coverage/default/13.alert_handler_entropy.1837079794
Short name T49
Test name
Test status
Simulation time 39583369543 ps
CPU time 2417.54 seconds
Started Feb 25 03:20:28 PM PST 24
Finished Feb 25 04:00:46 PM PST 24
Peak memory 270824 kb
Host smart-3f08377b-1e87-44d8-90c2-4822791db203
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837079794 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy.1837079794
Directory /workspace/13.alert_handler_entropy/latest

Test location /workspace/coverage/default/13.alert_handler_entropy_stress.3176774031
Short name T470
Test name
Test status
Simulation time 3416532730 ps
CPU time 45.05 seconds
Started Feb 25 03:20:41 PM PST 24
Finished Feb 25 03:21:26 PM PST 24
Peak memory 240104 kb
Host smart-4a01ea39-5510-497c-b5ca-83572b82b348
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3176774031 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy_stress.3176774031
Directory /workspace/13.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/13.alert_handler_esc_alert_accum.1417362666
Short name T604
Test name
Test status
Simulation time 2304295992 ps
CPU time 89.95 seconds
Started Feb 25 03:20:41 PM PST 24
Finished Feb 25 03:22:12 PM PST 24
Peak memory 255552 kb
Host smart-8be6d61b-ec75-4085-8be4-7f87fae73aa9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14173
62666 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_alert_accum.1417362666
Directory /workspace/13.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/13.alert_handler_esc_intr_timeout.1206260065
Short name T440
Test name
Test status
Simulation time 327087443 ps
CPU time 33.61 seconds
Started Feb 25 03:20:28 PM PST 24
Finished Feb 25 03:21:02 PM PST 24
Peak memory 254664 kb
Host smart-e7d054db-48dd-419c-ba21-2653f6e3bff1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12062
60065 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_intr_timeout.1206260065
Directory /workspace/13.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_lpg.3644840029
Short name T707
Test name
Test status
Simulation time 116083251394 ps
CPU time 3087.32 seconds
Started Feb 25 03:20:30 PM PST 24
Finished Feb 25 04:11:58 PM PST 24
Peak memory 288232 kb
Host smart-71b46aa4-42cc-472e-b4a8-ba1a33afc0e3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3644840029 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg.3644840029
Directory /workspace/13.alert_handler_lpg/latest

Test location /workspace/coverage/default/13.alert_handler_lpg_stub_clk.1970837794
Short name T277
Test name
Test status
Simulation time 218650865537 ps
CPU time 3060.09 seconds
Started Feb 25 03:20:28 PM PST 24
Finished Feb 25 04:11:28 PM PST 24
Peak memory 288728 kb
Host smart-ad9d1bfa-896c-4762-9749-7f2e9a5fd0c7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970837794 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg_stub_clk.1970837794
Directory /workspace/13.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/13.alert_handler_random_alerts.2242053948
Short name T216
Test name
Test status
Simulation time 910377452 ps
CPU time 15.41 seconds
Started Feb 25 03:20:30 PM PST 24
Finished Feb 25 03:20:45 PM PST 24
Peak memory 248340 kb
Host smart-70b6abad-a5a6-485c-bbcf-72f69a0e0e2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22420
53948 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_alerts.2242053948
Directory /workspace/13.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/13.alert_handler_random_classes.380825196
Short name T259
Test name
Test status
Simulation time 414332183 ps
CPU time 29.59 seconds
Started Feb 25 03:20:33 PM PST 24
Finished Feb 25 03:21:03 PM PST 24
Peak memory 246528 kb
Host smart-dd13076e-8b9d-4184-a57a-c208aaea8f8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38082
5196 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_classes.380825196
Directory /workspace/13.alert_handler_random_classes/latest

Test location /workspace/coverage/default/13.alert_handler_sig_int_fail.1665056266
Short name T261
Test name
Test status
Simulation time 214923961 ps
CPU time 20.09 seconds
Started Feb 25 03:20:36 PM PST 24
Finished Feb 25 03:20:56 PM PST 24
Peak memory 255004 kb
Host smart-38494c8b-7721-4ca2-8ba1-e7ea2320c956
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16650
56266 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_sig_int_fail.1665056266
Directory /workspace/13.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/13.alert_handler_smoke.823191847
Short name T710
Test name
Test status
Simulation time 2386757179 ps
CPU time 33.72 seconds
Started Feb 25 03:20:42 PM PST 24
Finished Feb 25 03:21:15 PM PST 24
Peak memory 256460 kb
Host smart-c335c4e6-b327-429c-b471-f9d31dd1a68b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82319
1847 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_smoke.823191847
Directory /workspace/13.alert_handler_smoke/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all.2756868685
Short name T272
Test name
Test status
Simulation time 50234276064 ps
CPU time 540.26 seconds
Started Feb 25 03:20:40 PM PST 24
Finished Feb 25 03:29:40 PM PST 24
Peak memory 264688 kb
Host smart-d1490b09-e566-43cd-8133-614a08a53fb0
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756868685 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_ha
ndler_stress_all.2756868685
Directory /workspace/13.alert_handler_stress_all/latest

Test location /workspace/coverage/default/14.alert_handler_alert_accum_saturation.4286987239
Short name T199
Test name
Test status
Simulation time 164017181 ps
CPU time 3.04 seconds
Started Feb 25 03:20:34 PM PST 24
Finished Feb 25 03:20:37 PM PST 24
Peak memory 248516 kb
Host smart-6df87a77-b4ce-4d87-b632-dbede327f26f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4286987239 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_alert_accum_saturation.4286987239
Directory /workspace/14.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/14.alert_handler_entropy.2414746446
Short name T98
Test name
Test status
Simulation time 141712672442 ps
CPU time 3243.44 seconds
Started Feb 25 03:20:40 PM PST 24
Finished Feb 25 04:14:44 PM PST 24
Peak memory 288840 kb
Host smart-c5af0107-4715-4455-95b4-46f3c54c63ad
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2414746446 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy.2414746446
Directory /workspace/14.alert_handler_entropy/latest

Test location /workspace/coverage/default/14.alert_handler_entropy_stress.2139019197
Short name T448
Test name
Test status
Simulation time 263030907 ps
CPU time 14.55 seconds
Started Feb 25 03:20:32 PM PST 24
Finished Feb 25 03:20:46 PM PST 24
Peak memory 240032 kb
Host smart-a7323317-f077-45ee-986f-7d68372bd8d4
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2139019197 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy_stress.2139019197
Directory /workspace/14.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/14.alert_handler_esc_alert_accum.68464436
Short name T431
Test name
Test status
Simulation time 437827868 ps
CPU time 18.72 seconds
Started Feb 25 03:20:31 PM PST 24
Finished Feb 25 03:20:50 PM PST 24
Peak memory 254904 kb
Host smart-f7c94f7d-991e-4b8c-9a57-39fd968e474a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68464
436 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_alert_accum.68464436
Directory /workspace/14.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/14.alert_handler_esc_intr_timeout.601605260
Short name T481
Test name
Test status
Simulation time 6126768531 ps
CPU time 49.89 seconds
Started Feb 25 03:20:33 PM PST 24
Finished Feb 25 03:21:23 PM PST 24
Peak memory 254912 kb
Host smart-1bd6c384-20e6-4da6-881f-f83008c57cbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60160
5260 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_intr_timeout.601605260
Directory /workspace/14.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_lpg.3011606876
Short name T287
Test name
Test status
Simulation time 21332501039 ps
CPU time 929.23 seconds
Started Feb 25 03:20:31 PM PST 24
Finished Feb 25 03:36:00 PM PST 24
Peak memory 272428 kb
Host smart-4688bebe-a7c7-46f6-b608-9cf95185772a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011606876 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg.3011606876
Directory /workspace/14.alert_handler_lpg/latest

Test location /workspace/coverage/default/14.alert_handler_lpg_stub_clk.2367363287
Short name T672
Test name
Test status
Simulation time 92497151300 ps
CPU time 2520.23 seconds
Started Feb 25 03:20:31 PM PST 24
Finished Feb 25 04:02:32 PM PST 24
Peak memory 288632 kb
Host smart-c1df0961-2250-4f03-9cc3-9dd29e45ae92
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367363287 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg_stub_clk.2367363287
Directory /workspace/14.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/14.alert_handler_ping_timeout.3299720906
Short name T316
Test name
Test status
Simulation time 12602312597 ps
CPU time 510.91 seconds
Started Feb 25 03:20:35 PM PST 24
Finished Feb 25 03:29:06 PM PST 24
Peak memory 246964 kb
Host smart-6a474605-80a9-4d43-993f-8dea909b0a5c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299720906 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_ping_timeout.3299720906
Directory /workspace/14.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_random_alerts.1432084271
Short name T656
Test name
Test status
Simulation time 314194552 ps
CPU time 23.13 seconds
Started Feb 25 03:20:41 PM PST 24
Finished Feb 25 03:21:04 PM PST 24
Peak memory 253956 kb
Host smart-ff155dd6-0838-45b6-8f75-70b951944728
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14320
84271 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_alerts.1432084271
Directory /workspace/14.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/14.alert_handler_random_classes.1292860717
Short name T549
Test name
Test status
Simulation time 515075629 ps
CPU time 27.63 seconds
Started Feb 25 03:20:30 PM PST 24
Finished Feb 25 03:20:57 PM PST 24
Peak memory 246504 kb
Host smart-2ad5fb14-c5e4-491f-82d4-17baeff13a7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12928
60717 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_classes.1292860717
Directory /workspace/14.alert_handler_random_classes/latest

Test location /workspace/coverage/default/14.alert_handler_sig_int_fail.426296444
Short name T415
Test name
Test status
Simulation time 557707208 ps
CPU time 11.67 seconds
Started Feb 25 03:20:31 PM PST 24
Finished Feb 25 03:20:43 PM PST 24
Peak memory 253688 kb
Host smart-a31562e7-3787-4e71-b16c-4182a41074a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42629
6444 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_sig_int_fail.426296444
Directory /workspace/14.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/14.alert_handler_smoke.603662171
Short name T475
Test name
Test status
Simulation time 254664928 ps
CPU time 20.64 seconds
Started Feb 25 03:20:30 PM PST 24
Finished Feb 25 03:20:51 PM PST 24
Peak memory 256368 kb
Host smart-db3bd800-065e-4265-9821-3ff948b0365e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60366
2171 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_smoke.603662171
Directory /workspace/14.alert_handler_smoke/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all.1270185230
Short name T99
Test name
Test status
Simulation time 157270833019 ps
CPU time 2396.8 seconds
Started Feb 25 03:20:35 PM PST 24
Finished Feb 25 04:00:32 PM PST 24
Peak memory 289268 kb
Host smart-e7b7d29e-5d48-4d56-a1a0-a00650f9c675
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270185230 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_ha
ndler_stress_all.1270185230
Directory /workspace/14.alert_handler_stress_all/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all_with_rand_reset.538037359
Short name T262
Test name
Test status
Simulation time 50914251758 ps
CPU time 3555.7 seconds
Started Feb 25 03:20:27 PM PST 24
Finished Feb 25 04:19:44 PM PST 24
Peak memory 304548 kb
Host smart-7b2844ac-1891-4079-9e03-a5aab8dad3da
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538037359 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 14.alert_handler_stress_all_with_rand_reset.538037359
Directory /workspace/14.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.alert_handler_alert_accum_saturation.2961259854
Short name T208
Test name
Test status
Simulation time 230328320 ps
CPU time 3.74 seconds
Started Feb 25 03:20:35 PM PST 24
Finished Feb 25 03:20:38 PM PST 24
Peak memory 248528 kb
Host smart-92a57b23-157a-42ab-9367-fc4df639d3b5
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2961259854 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_alert_accum_saturation.2961259854
Directory /workspace/15.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/15.alert_handler_entropy.851226303
Short name T437
Test name
Test status
Simulation time 27553893403 ps
CPU time 1822.19 seconds
Started Feb 25 03:20:40 PM PST 24
Finished Feb 25 03:51:02 PM PST 24
Peak memory 272692 kb
Host smart-5edc056c-aab2-4e24-98e9-e2f82bc37603
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851226303 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy.851226303
Directory /workspace/15.alert_handler_entropy/latest

Test location /workspace/coverage/default/15.alert_handler_entropy_stress.3897261450
Short name T227
Test name
Test status
Simulation time 886980921 ps
CPU time 39.79 seconds
Started Feb 25 03:20:36 PM PST 24
Finished Feb 25 03:21:16 PM PST 24
Peak memory 248244 kb
Host smart-b5545538-b6b6-4093-9117-c2338685b4db
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3897261450 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy_stress.3897261450
Directory /workspace/15.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/15.alert_handler_esc_alert_accum.1029427087
Short name T577
Test name
Test status
Simulation time 22715099660 ps
CPU time 367.5 seconds
Started Feb 25 03:20:36 PM PST 24
Finished Feb 25 03:26:43 PM PST 24
Peak memory 250348 kb
Host smart-8b53a8b0-4fcb-4ab9-8ebe-7ad5b78e31e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10294
27087 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_alert_accum.1029427087
Directory /workspace/15.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/15.alert_handler_esc_intr_timeout.1320720177
Short name T365
Test name
Test status
Simulation time 438406595 ps
CPU time 4.86 seconds
Started Feb 25 03:20:32 PM PST 24
Finished Feb 25 03:20:37 PM PST 24
Peak memory 238328 kb
Host smart-72c8baaa-262b-4cf7-a028-f665abc2d5f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13207
20177 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_intr_timeout.1320720177
Directory /workspace/15.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_lpg.1607473796
Short name T496
Test name
Test status
Simulation time 36621927700 ps
CPU time 928.63 seconds
Started Feb 25 03:20:33 PM PST 24
Finished Feb 25 03:36:02 PM PST 24
Peak memory 272328 kb
Host smart-d1c817bd-c83c-4d6d-83f5-c412ad303979
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607473796 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg.1607473796
Directory /workspace/15.alert_handler_lpg/latest

Test location /workspace/coverage/default/15.alert_handler_lpg_stub_clk.3960549353
Short name T555
Test name
Test status
Simulation time 50503569978 ps
CPU time 2903.28 seconds
Started Feb 25 03:20:39 PM PST 24
Finished Feb 25 04:09:03 PM PST 24
Peak memory 289208 kb
Host smart-cf1a15b3-a378-4e21-8bfa-8f6e795e3b13
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960549353 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg_stub_clk.3960549353
Directory /workspace/15.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/15.alert_handler_random_alerts.3029139834
Short name T553
Test name
Test status
Simulation time 504037450 ps
CPU time 17.41 seconds
Started Feb 25 03:20:29 PM PST 24
Finished Feb 25 03:20:46 PM PST 24
Peak memory 248228 kb
Host smart-bcc9f466-a543-4fc4-a4d4-10734509d0c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30291
39834 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_alerts.3029139834
Directory /workspace/15.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/15.alert_handler_sig_int_fail.2954958468
Short name T610
Test name
Test status
Simulation time 224243389 ps
CPU time 24.47 seconds
Started Feb 25 03:20:32 PM PST 24
Finished Feb 25 03:20:56 PM PST 24
Peak memory 246496 kb
Host smart-5c1e208f-1c4c-473e-b390-beb98aac8bb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29549
58468 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_sig_int_fail.2954958468
Directory /workspace/15.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/15.alert_handler_smoke.1925511563
Short name T414
Test name
Test status
Simulation time 189052870 ps
CPU time 18.29 seconds
Started Feb 25 03:20:31 PM PST 24
Finished Feb 25 03:20:50 PM PST 24
Peak memory 248236 kb
Host smart-c498c400-3023-45de-8d7c-1ea9fcd38259
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19255
11563 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_smoke.1925511563
Directory /workspace/15.alert_handler_smoke/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all_with_rand_reset.2761540471
Short name T474
Test name
Test status
Simulation time 13021518241 ps
CPU time 1415.41 seconds
Started Feb 25 03:20:32 PM PST 24
Finished Feb 25 03:44:08 PM PST 24
Peak memory 289200 kb
Host smart-d04b7dd5-5705-4ae0-8cff-a3f154c2c0f0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761540471 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.alert_handler_stress_all_with_rand_reset.2761540471
Directory /workspace/15.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.alert_handler_alert_accum_saturation.3916326962
Short name T210
Test name
Test status
Simulation time 190074249 ps
CPU time 4.28 seconds
Started Feb 25 03:20:47 PM PST 24
Finished Feb 25 03:20:51 PM PST 24
Peak memory 248516 kb
Host smart-ec97f6e7-68a2-42f2-b8b8-974f2ee7acc7
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3916326962 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_alert_accum_saturation.3916326962
Directory /workspace/16.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/16.alert_handler_entropy.2038332830
Short name T97
Test name
Test status
Simulation time 44259747231 ps
CPU time 2493.62 seconds
Started Feb 25 03:20:35 PM PST 24
Finished Feb 25 04:02:09 PM PST 24
Peak memory 288712 kb
Host smart-dd7045fe-4869-49d7-bebf-157400b22184
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038332830 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy.2038332830
Directory /workspace/16.alert_handler_entropy/latest

Test location /workspace/coverage/default/16.alert_handler_entropy_stress.259005316
Short name T473
Test name
Test status
Simulation time 387063887 ps
CPU time 10.96 seconds
Started Feb 25 03:20:40 PM PST 24
Finished Feb 25 03:20:52 PM PST 24
Peak memory 240044 kb
Host smart-078ab143-c6d0-4747-ab90-4106de108526
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=259005316 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy_stress.259005316
Directory /workspace/16.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/16.alert_handler_esc_alert_accum.4159636353
Short name T367
Test name
Test status
Simulation time 25311511543 ps
CPU time 286.76 seconds
Started Feb 25 03:20:43 PM PST 24
Finished Feb 25 03:25:31 PM PST 24
Peak memory 256044 kb
Host smart-5cda383e-b3cf-4a54-b384-bd2ee15e6d12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41596
36353 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_alert_accum.4159636353
Directory /workspace/16.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/16.alert_handler_esc_intr_timeout.3096168642
Short name T582
Test name
Test status
Simulation time 1699441788 ps
CPU time 16.08 seconds
Started Feb 25 03:20:40 PM PST 24
Finished Feb 25 03:20:56 PM PST 24
Peak memory 255272 kb
Host smart-08ab74c7-83e5-4ab6-9582-19950e660919
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30961
68642 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_intr_timeout.3096168642
Directory /workspace/16.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_lpg.4137852035
Short name T336
Test name
Test status
Simulation time 50971400522 ps
CPU time 1366.5 seconds
Started Feb 25 03:20:41 PM PST 24
Finished Feb 25 03:43:27 PM PST 24
Peak memory 286104 kb
Host smart-86aa7803-4ff4-4842-84fd-eea312c220af
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137852035 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg.4137852035
Directory /workspace/16.alert_handler_lpg/latest

Test location /workspace/coverage/default/16.alert_handler_lpg_stub_clk.981493716
Short name T659
Test name
Test status
Simulation time 32982924991 ps
CPU time 1356.86 seconds
Started Feb 25 03:20:52 PM PST 24
Finished Feb 25 03:43:29 PM PST 24
Peak memory 271996 kb
Host smart-3497a3ff-c766-4d43-a31a-661afdda4aec
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981493716 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg_stub_clk.981493716
Directory /workspace/16.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/16.alert_handler_random_alerts.2552743892
Short name T445
Test name
Test status
Simulation time 378659196 ps
CPU time 31.49 seconds
Started Feb 25 03:20:39 PM PST 24
Finished Feb 25 03:21:11 PM PST 24
Peak memory 254836 kb
Host smart-457ce9ce-8ed3-4ac9-804d-64fcf9698841
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25527
43892 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_alerts.2552743892
Directory /workspace/16.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/16.alert_handler_random_classes.2324988375
Short name T677
Test name
Test status
Simulation time 1693511683 ps
CPU time 44.9 seconds
Started Feb 25 03:20:46 PM PST 24
Finished Feb 25 03:21:31 PM PST 24
Peak memory 246804 kb
Host smart-3d0ac32f-a7cc-45a0-8105-118f855a252a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23249
88375 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_classes.2324988375
Directory /workspace/16.alert_handler_random_classes/latest

Test location /workspace/coverage/default/16.alert_handler_smoke.2242661936
Short name T527
Test name
Test status
Simulation time 32038065 ps
CPU time 3.9 seconds
Started Feb 25 03:20:50 PM PST 24
Finished Feb 25 03:20:54 PM PST 24
Peak memory 240028 kb
Host smart-a105435e-c974-4bd1-8ade-2c3f7ac5dc55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22426
61936 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_smoke.2242661936
Directory /workspace/16.alert_handler_smoke/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all.2802536080
Short name T293
Test name
Test status
Simulation time 111520605205 ps
CPU time 1908.6 seconds
Started Feb 25 03:20:38 PM PST 24
Finished Feb 25 03:52:27 PM PST 24
Peak memory 289252 kb
Host smart-e93fc00a-46fc-408a-a30c-fe8da5e45fd6
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802536080 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_ha
ndler_stress_all.2802536080
Directory /workspace/16.alert_handler_stress_all/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all_with_rand_reset.3753335448
Short name T90
Test name
Test status
Simulation time 29117553145 ps
CPU time 817.31 seconds
Started Feb 25 03:20:43 PM PST 24
Finished Feb 25 03:34:21 PM PST 24
Peak memory 282312 kb
Host smart-b2465009-e017-4ca7-8e46-ddb1ec042a05
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753335448 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 16.alert_handler_stress_all_with_rand_reset.3753335448
Directory /workspace/16.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.alert_handler_alert_accum_saturation.2882766753
Short name T87
Test name
Test status
Simulation time 53995372 ps
CPU time 2.67 seconds
Started Feb 25 03:20:37 PM PST 24
Finished Feb 25 03:20:40 PM PST 24
Peak memory 248528 kb
Host smart-aef8b3db-261e-4fe9-aad8-c46ab89e7d68
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2882766753 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_alert_accum_saturation.2882766753
Directory /workspace/17.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/17.alert_handler_entropy.168286267
Short name T635
Test name
Test status
Simulation time 47279087093 ps
CPU time 2108.78 seconds
Started Feb 25 03:21:00 PM PST 24
Finished Feb 25 03:56:10 PM PST 24
Peak memory 272360 kb
Host smart-f2a934f6-552e-4cc4-98bd-cea6b2e1f341
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=168286267 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy.168286267
Directory /workspace/17.alert_handler_entropy/latest

Test location /workspace/coverage/default/17.alert_handler_entropy_stress.1017873062
Short name T447
Test name
Test status
Simulation time 528698988 ps
CPU time 15.3 seconds
Started Feb 25 03:20:46 PM PST 24
Finished Feb 25 03:21:01 PM PST 24
Peak memory 240044 kb
Host smart-00a35f95-7eec-48e1-94a7-0b92c3b35ac7
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1017873062 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy_stress.1017873062
Directory /workspace/17.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/17.alert_handler_esc_alert_accum.149740314
Short name T392
Test name
Test status
Simulation time 919071517 ps
CPU time 56.25 seconds
Started Feb 25 03:20:47 PM PST 24
Finished Feb 25 03:21:43 PM PST 24
Peak memory 254976 kb
Host smart-51756b5f-276d-44ac-aa13-318ae7192e15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14974
0314 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_alert_accum.149740314
Directory /workspace/17.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/17.alert_handler_esc_intr_timeout.491408164
Short name T408
Test name
Test status
Simulation time 594091421 ps
CPU time 27.92 seconds
Started Feb 25 03:20:38 PM PST 24
Finished Feb 25 03:21:06 PM PST 24
Peak memory 254012 kb
Host smart-8196a971-38f4-4c28-8931-df37e236b188
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49140
8164 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_intr_timeout.491408164
Directory /workspace/17.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_lpg.67016067
Short name T338
Test name
Test status
Simulation time 26948916573 ps
CPU time 1516.74 seconds
Started Feb 25 03:20:43 PM PST 24
Finished Feb 25 03:46:01 PM PST 24
Peak memory 272264 kb
Host smart-5237157f-8de0-4879-b293-43090200d330
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67016067 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg.67016067
Directory /workspace/17.alert_handler_lpg/latest

Test location /workspace/coverage/default/17.alert_handler_lpg_stub_clk.1576166742
Short name T449
Test name
Test status
Simulation time 10239404765 ps
CPU time 874.52 seconds
Started Feb 25 03:20:38 PM PST 24
Finished Feb 25 03:35:13 PM PST 24
Peak memory 281800 kb
Host smart-0ac48786-f983-4c5e-a395-9e9da8403919
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1576166742 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg_stub_clk.1576166742
Directory /workspace/17.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/17.alert_handler_ping_timeout.2335153685
Short name T487
Test name
Test status
Simulation time 3817239446 ps
CPU time 169.93 seconds
Started Feb 25 03:20:40 PM PST 24
Finished Feb 25 03:23:30 PM PST 24
Peak memory 247200 kb
Host smart-d3edbc33-632f-4146-a20a-15a22d5f00ce
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335153685 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_ping_timeout.2335153685
Directory /workspace/17.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_random_alerts.723850369
Short name T225
Test name
Test status
Simulation time 6290559382 ps
CPU time 47.89 seconds
Started Feb 25 03:20:39 PM PST 24
Finished Feb 25 03:21:27 PM PST 24
Peak memory 248288 kb
Host smart-c37bba48-274e-4c59-a28b-35a2a295d86e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72385
0369 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_alerts.723850369
Directory /workspace/17.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/17.alert_handler_random_classes.2829790114
Short name T435
Test name
Test status
Simulation time 1173260556 ps
CPU time 17.13 seconds
Started Feb 25 03:20:39 PM PST 24
Finished Feb 25 03:20:56 PM PST 24
Peak memory 253088 kb
Host smart-95fdc1a5-23bd-4d2a-b0ef-e0fd30d4e6e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28297
90114 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_classes.2829790114
Directory /workspace/17.alert_handler_random_classes/latest

Test location /workspace/coverage/default/17.alert_handler_sig_int_fail.3085462299
Short name T706
Test name
Test status
Simulation time 127720802 ps
CPU time 17.51 seconds
Started Feb 25 03:20:43 PM PST 24
Finished Feb 25 03:21:01 PM PST 24
Peak memory 255780 kb
Host smart-3830cd95-8082-41d5-abf2-e54963152a2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30854
62299 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_sig_int_fail.3085462299
Directory /workspace/17.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/17.alert_handler_smoke.3980391335
Short name T451
Test name
Test status
Simulation time 422533637 ps
CPU time 18.12 seconds
Started Feb 25 03:20:43 PM PST 24
Finished Feb 25 03:21:02 PM PST 24
Peak memory 253744 kb
Host smart-48b243ba-31f1-45d3-af65-7047d4b02f83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39803
91335 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_smoke.3980391335
Directory /workspace/17.alert_handler_smoke/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all.3739696478
Short name T612
Test name
Test status
Simulation time 52494120642 ps
CPU time 1379.1 seconds
Started Feb 25 03:20:40 PM PST 24
Finished Feb 25 03:43:40 PM PST 24
Peak memory 268064 kb
Host smart-ed5a30c8-4dcf-4bda-9838-99212fd53d64
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739696478 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_ha
ndler_stress_all.3739696478
Directory /workspace/17.alert_handler_stress_all/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all_with_rand_reset.1022559900
Short name T54
Test name
Test status
Simulation time 58113588072 ps
CPU time 3328.84 seconds
Started Feb 25 03:20:43 PM PST 24
Finished Feb 25 04:16:13 PM PST 24
Peak memory 321404 kb
Host smart-abadb1ea-d924-4dd9-a920-dfafeadfc868
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022559900 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 17.alert_handler_stress_all_with_rand_reset.1022559900
Directory /workspace/17.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.alert_handler_alert_accum_saturation.244347406
Short name T211
Test name
Test status
Simulation time 102413454 ps
CPU time 3.02 seconds
Started Feb 25 03:20:43 PM PST 24
Finished Feb 25 03:20:47 PM PST 24
Peak memory 248516 kb
Host smart-9f81c08e-3da7-494d-adc4-673e4709f27b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=244347406 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_alert_accum_saturation.244347406
Directory /workspace/18.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/18.alert_handler_entropy_stress.3210169532
Short name T584
Test name
Test status
Simulation time 393087960 ps
CPU time 7.18 seconds
Started Feb 25 03:20:40 PM PST 24
Finished Feb 25 03:20:47 PM PST 24
Peak memory 240024 kb
Host smart-b8887b59-2aeb-46c1-91b2-33814cad9af2
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3210169532 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy_stress.3210169532
Directory /workspace/18.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/18.alert_handler_esc_alert_accum.1169998254
Short name T652
Test name
Test status
Simulation time 5249716753 ps
CPU time 312.78 seconds
Started Feb 25 03:20:39 PM PST 24
Finished Feb 25 03:25:52 PM PST 24
Peak memory 256020 kb
Host smart-06d78170-31b6-42dc-ad73-b5d11a4efa4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11699
98254 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_alert_accum.1169998254
Directory /workspace/18.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/18.alert_handler_esc_intr_timeout.163832178
Short name T35
Test name
Test status
Simulation time 386526799 ps
CPU time 31.05 seconds
Started Feb 25 03:20:44 PM PST 24
Finished Feb 25 03:21:15 PM PST 24
Peak memory 254504 kb
Host smart-9bc30035-8b0c-4f96-b901-3fb454fb9c3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16383
2178 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_intr_timeout.163832178
Directory /workspace/18.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_lpg_stub_clk.2277811322
Short name T355
Test name
Test status
Simulation time 25460168356 ps
CPU time 1371.3 seconds
Started Feb 25 03:20:41 PM PST 24
Finished Feb 25 03:43:32 PM PST 24
Peak memory 268116 kb
Host smart-1e5337af-152e-4dda-9cf2-14ae3493de64
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277811322 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg_stub_clk.2277811322
Directory /workspace/18.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/18.alert_handler_ping_timeout.553256255
Short name T40
Test name
Test status
Simulation time 10209542376 ps
CPU time 207.49 seconds
Started Feb 25 03:20:43 PM PST 24
Finished Feb 25 03:24:11 PM PST 24
Peak memory 247068 kb
Host smart-122ee2dc-ade0-45cb-87ac-08a1b2faea8b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553256255 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_ping_timeout.553256255
Directory /workspace/18.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_random_alerts.1798348918
Short name T489
Test name
Test status
Simulation time 1052991803 ps
CPU time 21.08 seconds
Started Feb 25 03:20:43 PM PST 24
Finished Feb 25 03:21:05 PM PST 24
Peak memory 248200 kb
Host smart-d0c2f975-acb1-47a4-98ab-e28713ba38c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17983
48918 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_alerts.1798348918
Directory /workspace/18.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/18.alert_handler_random_classes.1205197022
Short name T115
Test name
Test status
Simulation time 740428471 ps
CPU time 19.72 seconds
Started Feb 25 03:20:39 PM PST 24
Finished Feb 25 03:20:59 PM PST 24
Peak memory 254328 kb
Host smart-c00aa34e-e28f-4d4d-aabe-3369657bec6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12051
97022 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_classes.1205197022
Directory /workspace/18.alert_handler_random_classes/latest

Test location /workspace/coverage/default/18.alert_handler_smoke.3255851119
Short name T357
Test name
Test status
Simulation time 1773704425 ps
CPU time 27.08 seconds
Started Feb 25 03:20:35 PM PST 24
Finished Feb 25 03:21:02 PM PST 24
Peak memory 248212 kb
Host smart-19c8cb36-1071-4320-9756-d72910332875
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32558
51119 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_smoke.3255851119
Directory /workspace/18.alert_handler_smoke/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all.14578675
Short name T478
Test name
Test status
Simulation time 1381566950 ps
CPU time 49.83 seconds
Started Feb 25 03:20:45 PM PST 24
Finished Feb 25 03:21:35 PM PST 24
Peak memory 255196 kb
Host smart-94d7e789-4dc2-4ffe-af4d-d9cc7674395a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14578675 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_hand
ler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_hand
ler_stress_all.14578675
Directory /workspace/18.alert_handler_stress_all/latest

Test location /workspace/coverage/default/19.alert_handler_alert_accum_saturation.2225626998
Short name T212
Test name
Test status
Simulation time 73803965 ps
CPU time 2.95 seconds
Started Feb 25 03:20:45 PM PST 24
Finished Feb 25 03:20:48 PM PST 24
Peak memory 248516 kb
Host smart-b62e3728-9086-4a73-bba2-0783f0233c2d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2225626998 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_alert_accum_saturation.2225626998
Directory /workspace/19.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/19.alert_handler_entropy.1374545604
Short name T702
Test name
Test status
Simulation time 52741009148 ps
CPU time 1883.16 seconds
Started Feb 25 03:20:45 PM PST 24
Finished Feb 25 03:52:14 PM PST 24
Peak memory 281080 kb
Host smart-b9d6887f-069f-403c-9b80-beaf9c320339
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374545604 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy.1374545604
Directory /workspace/19.alert_handler_entropy/latest

Test location /workspace/coverage/default/19.alert_handler_entropy_stress.526658553
Short name T16
Test name
Test status
Simulation time 151751835 ps
CPU time 9.64 seconds
Started Feb 25 03:20:47 PM PST 24
Finished Feb 25 03:20:57 PM PST 24
Peak memory 240016 kb
Host smart-8d974353-313e-48c5-8420-e1da64a61325
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=526658553 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy_stress.526658553
Directory /workspace/19.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/19.alert_handler_esc_alert_accum.2301351391
Short name T239
Test name
Test status
Simulation time 23765137019 ps
CPU time 330.32 seconds
Started Feb 25 03:20:56 PM PST 24
Finished Feb 25 03:26:26 PM PST 24
Peak memory 255920 kb
Host smart-4acd6c00-116a-4929-a5ec-aec6e6faaeb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23013
51391 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_alert_accum.2301351391
Directory /workspace/19.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/19.alert_handler_esc_intr_timeout.732164708
Short name T430
Test name
Test status
Simulation time 1210467724 ps
CPU time 25.96 seconds
Started Feb 25 03:20:38 PM PST 24
Finished Feb 25 03:21:04 PM PST 24
Peak memory 254504 kb
Host smart-a8da6f96-15e7-4685-a9cd-91f5e52afc48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73216
4708 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_intr_timeout.732164708
Directory /workspace/19.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_lpg.3553124318
Short name T567
Test name
Test status
Simulation time 17776286517 ps
CPU time 1419.79 seconds
Started Feb 25 03:20:43 PM PST 24
Finished Feb 25 03:44:24 PM PST 24
Peak memory 284596 kb
Host smart-de1782ba-4b17-4637-b6e4-dc7baa1c6d54
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553124318 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg.3553124318
Directory /workspace/19.alert_handler_lpg/latest

Test location /workspace/coverage/default/19.alert_handler_lpg_stub_clk.843553188
Short name T712
Test name
Test status
Simulation time 8681808300 ps
CPU time 819.77 seconds
Started Feb 25 03:20:47 PM PST 24
Finished Feb 25 03:34:27 PM PST 24
Peak memory 272876 kb
Host smart-a74caf54-f08f-43b6-8860-425dbd89ba73
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843553188 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg_stub_clk.843553188
Directory /workspace/19.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/19.alert_handler_random_alerts.3278644407
Short name T544
Test name
Test status
Simulation time 61164084 ps
CPU time 5.38 seconds
Started Feb 25 03:20:44 PM PST 24
Finished Feb 25 03:20:49 PM PST 24
Peak memory 240036 kb
Host smart-7e621102-d81f-4d5b-8975-8997eb853a24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32786
44407 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_alerts.3278644407
Directory /workspace/19.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/19.alert_handler_random_classes.3190686051
Short name T455
Test name
Test status
Simulation time 509425352 ps
CPU time 18.89 seconds
Started Feb 25 03:20:44 PM PST 24
Finished Feb 25 03:21:03 PM PST 24
Peak memory 252728 kb
Host smart-a1f9358c-e0ed-40a9-9bfa-d79ca682f100
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31906
86051 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_classes.3190686051
Directory /workspace/19.alert_handler_random_classes/latest

Test location /workspace/coverage/default/19.alert_handler_sig_int_fail.846408725
Short name T377
Test name
Test status
Simulation time 2797615345 ps
CPU time 59.51 seconds
Started Feb 25 03:20:37 PM PST 24
Finished Feb 25 03:21:37 PM PST 24
Peak memory 254744 kb
Host smart-04158ee6-e0a0-4498-984c-bcca4c5031f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84640
8725 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_sig_int_fail.846408725
Directory /workspace/19.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/19.alert_handler_smoke.3693553289
Short name T376
Test name
Test status
Simulation time 951037463 ps
CPU time 21.61 seconds
Started Feb 25 03:20:39 PM PST 24
Finished Feb 25 03:21:01 PM PST 24
Peak memory 254628 kb
Host smart-7841697c-c3ea-4c0a-8a68-8b7a5246bed1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36935
53289 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_smoke.3693553289
Directory /workspace/19.alert_handler_smoke/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all.2672406789
Short name T569
Test name
Test status
Simulation time 33814043674 ps
CPU time 2088.34 seconds
Started Feb 25 03:20:54 PM PST 24
Finished Feb 25 03:55:43 PM PST 24
Peak memory 289260 kb
Host smart-d892e58f-fa24-417a-9691-07bc9627f79e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672406789 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_ha
ndler_stress_all.2672406789
Directory /workspace/19.alert_handler_stress_all/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all_with_rand_reset.3270622980
Short name T84
Test name
Test status
Simulation time 323307323173 ps
CPU time 5674.25 seconds
Started Feb 25 03:20:39 PM PST 24
Finished Feb 25 04:55:14 PM PST 24
Peak memory 321780 kb
Host smart-588fc9f2-2939-413b-8390-f9f31e6d89a5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270622980 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 19.alert_handler_stress_all_with_rand_reset.3270622980
Directory /workspace/19.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.alert_handler_alert_accum_saturation.2671305263
Short name T202
Test name
Test status
Simulation time 47540499 ps
CPU time 3.73 seconds
Started Feb 25 03:20:28 PM PST 24
Finished Feb 25 03:20:32 PM PST 24
Peak memory 248524 kb
Host smart-c5a5f796-4e68-4566-8acb-2526e10d8651
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2671305263 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_alert_accum_saturation.2671305263
Directory /workspace/2.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/2.alert_handler_entropy.3116206770
Short name T17
Test name
Test status
Simulation time 76398179709 ps
CPU time 1778.68 seconds
Started Feb 25 03:20:06 PM PST 24
Finished Feb 25 03:49:45 PM PST 24
Peak memory 288644 kb
Host smart-23126b61-81c6-47ab-829f-f82e0c5f43c4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116206770 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy.3116206770
Directory /workspace/2.alert_handler_entropy/latest

Test location /workspace/coverage/default/2.alert_handler_entropy_stress.3433632929
Short name T397
Test name
Test status
Simulation time 148498735 ps
CPU time 9.06 seconds
Started Feb 25 03:20:22 PM PST 24
Finished Feb 25 03:20:32 PM PST 24
Peak memory 240028 kb
Host smart-387211d5-64a6-4744-8a4d-a7654e8d68a2
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3433632929 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy_stress.3433632929
Directory /workspace/2.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/2.alert_handler_esc_alert_accum.2147390484
Short name T393
Test name
Test status
Simulation time 216338229 ps
CPU time 15.03 seconds
Started Feb 25 03:19:56 PM PST 24
Finished Feb 25 03:20:11 PM PST 24
Peak memory 254152 kb
Host smart-a2a84a62-2923-43e2-b977-8686b6eed993
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21473
90484 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_alert_accum.2147390484
Directory /workspace/2.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/2.alert_handler_esc_intr_timeout.2847122242
Short name T530
Test name
Test status
Simulation time 4705891729 ps
CPU time 60.37 seconds
Started Feb 25 03:19:55 PM PST 24
Finished Feb 25 03:20:56 PM PST 24
Peak memory 255528 kb
Host smart-e1b0badb-bc12-47d9-a83c-577092599159
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28471
22242 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_intr_timeout.2847122242
Directory /workspace/2.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_lpg.1215068154
Short name T307
Test name
Test status
Simulation time 35849031070 ps
CPU time 2322.56 seconds
Started Feb 25 03:20:03 PM PST 24
Finished Feb 25 03:58:46 PM PST 24
Peak memory 288532 kb
Host smart-7e1c5714-a0c3-4c25-9e54-b73069e6593e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1215068154 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg.1215068154
Directory /workspace/2.alert_handler_lpg/latest

Test location /workspace/coverage/default/2.alert_handler_ping_timeout.2263036180
Short name T305
Test name
Test status
Simulation time 30987952867 ps
CPU time 290.2 seconds
Started Feb 25 03:20:05 PM PST 24
Finished Feb 25 03:24:56 PM PST 24
Peak memory 247200 kb
Host smart-9460a5b8-73a4-472b-af6f-514cc22f1d94
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263036180 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_ping_timeout.2263036180
Directory /workspace/2.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_random_alerts.2243721319
Short name T6
Test name
Test status
Simulation time 4552330673 ps
CPU time 53.4 seconds
Started Feb 25 03:20:21 PM PST 24
Finished Feb 25 03:21:15 PM PST 24
Peak memory 248304 kb
Host smart-9fd9a2e2-4ccd-4905-ad4e-f4c887b3d7ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22437
21319 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_alerts.2243721319
Directory /workspace/2.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/2.alert_handler_random_classes.799962148
Short name T574
Test name
Test status
Simulation time 493950873 ps
CPU time 18.52 seconds
Started Feb 25 03:20:17 PM PST 24
Finished Feb 25 03:20:35 PM PST 24
Peak memory 254696 kb
Host smart-4acd7167-aa40-4e9b-b0bf-71bfa31de676
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79996
2148 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_classes.799962148
Directory /workspace/2.alert_handler_random_classes/latest

Test location /workspace/coverage/default/2.alert_handler_sig_int_fail.2269645865
Short name T411
Test name
Test status
Simulation time 225918216 ps
CPU time 13.24 seconds
Started Feb 25 03:20:14 PM PST 24
Finished Feb 25 03:20:28 PM PST 24
Peak memory 254084 kb
Host smart-d6c4639b-d30c-44dd-ba9f-2ca23c588d53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22696
45865 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sig_int_fail.2269645865
Directory /workspace/2.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/2.alert_handler_smoke.1874569261
Short name T401
Test name
Test status
Simulation time 8818108768 ps
CPU time 54.11 seconds
Started Feb 25 03:20:08 PM PST 24
Finished Feb 25 03:21:02 PM PST 24
Peak memory 248364 kb
Host smart-6b173137-9453-4b00-805a-ed66fe926d68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18745
69261 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_smoke.1874569261
Directory /workspace/2.alert_handler_smoke/latest

Test location /workspace/coverage/default/20.alert_handler_entropy.4103398854
Short name T413
Test name
Test status
Simulation time 29913199674 ps
CPU time 741.12 seconds
Started Feb 25 03:20:41 PM PST 24
Finished Feb 25 03:33:02 PM PST 24
Peak memory 272224 kb
Host smart-2c27a4e3-15b6-4b93-be05-d8e5251ac4dc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103398854 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_entropy.4103398854
Directory /workspace/20.alert_handler_entropy/latest

Test location /workspace/coverage/default/20.alert_handler_esc_alert_accum.1437006328
Short name T562
Test name
Test status
Simulation time 2322422986 ps
CPU time 39.78 seconds
Started Feb 25 03:20:41 PM PST 24
Finished Feb 25 03:21:21 PM PST 24
Peak memory 247828 kb
Host smart-9d3f970f-9e49-4f6d-9514-25ce0b0bcb40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14370
06328 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_alert_accum.1437006328
Directory /workspace/20.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/20.alert_handler_esc_intr_timeout.1342973919
Short name T105
Test name
Test status
Simulation time 1987281166 ps
CPU time 61.74 seconds
Started Feb 25 03:20:39 PM PST 24
Finished Feb 25 03:21:41 PM PST 24
Peak memory 253848 kb
Host smart-68fe9bf8-5b93-4849-abc6-ffe68f94f8af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13429
73919 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_intr_timeout.1342973919
Directory /workspace/20.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_lpg.1099523893
Short name T284
Test name
Test status
Simulation time 35316330052 ps
CPU time 2142.52 seconds
Started Feb 25 03:20:41 PM PST 24
Finished Feb 25 03:56:23 PM PST 24
Peak memory 272624 kb
Host smart-7ed35e1f-a15f-4528-8975-289843f65326
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099523893 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg.1099523893
Directory /workspace/20.alert_handler_lpg/latest

Test location /workspace/coverage/default/20.alert_handler_lpg_stub_clk.1630981623
Short name T537
Test name
Test status
Simulation time 80817942183 ps
CPU time 1236.83 seconds
Started Feb 25 03:20:40 PM PST 24
Finished Feb 25 03:41:17 PM PST 24
Peak memory 288416 kb
Host smart-213d391b-c6d4-4b59-90a5-3a2806ee4dfc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630981623 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg_stub_clk.1630981623
Directory /workspace/20.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/20.alert_handler_random_alerts.1753960466
Short name T632
Test name
Test status
Simulation time 1046913854 ps
CPU time 15.66 seconds
Started Feb 25 03:20:38 PM PST 24
Finished Feb 25 03:20:54 PM PST 24
Peak memory 248232 kb
Host smart-fdba20c2-769c-45cb-8f1a-b94eab02eb23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17539
60466 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_alerts.1753960466
Directory /workspace/20.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/20.alert_handler_random_classes.3078063022
Short name T122
Test name
Test status
Simulation time 1783590321 ps
CPU time 30.06 seconds
Started Feb 25 03:20:40 PM PST 24
Finished Feb 25 03:21:10 PM PST 24
Peak memory 254712 kb
Host smart-64cc63c2-ed17-4e6c-bc6e-b2634fa553aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30780
63022 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_classes.3078063022
Directory /workspace/20.alert_handler_random_classes/latest

Test location /workspace/coverage/default/20.alert_handler_sig_int_fail.1766257028
Short name T251
Test name
Test status
Simulation time 243307808 ps
CPU time 16.66 seconds
Started Feb 25 03:20:42 PM PST 24
Finished Feb 25 03:20:58 PM PST 24
Peak memory 253664 kb
Host smart-1ba8889d-a41b-4095-9180-11c3d9eca1b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17662
57028 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_sig_int_fail.1766257028
Directory /workspace/20.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/20.alert_handler_smoke.38707959
Short name T222
Test name
Test status
Simulation time 237422637 ps
CPU time 23.2 seconds
Started Feb 25 03:20:40 PM PST 24
Finished Feb 25 03:21:03 PM PST 24
Peak memory 254848 kb
Host smart-ddf75652-2459-4ec3-942c-09a575e224db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38707
959 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_smoke.38707959
Directory /workspace/20.alert_handler_smoke/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all.2866741496
Short name T476
Test name
Test status
Simulation time 242989956 ps
CPU time 23.59 seconds
Started Feb 25 03:20:41 PM PST 24
Finished Feb 25 03:21:05 PM PST 24
Peak memory 254388 kb
Host smart-2a0eacde-8ff3-48db-bf2f-26923c255e70
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866741496 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_ha
ndler_stress_all.2866741496
Directory /workspace/20.alert_handler_stress_all/latest

Test location /workspace/coverage/default/21.alert_handler_entropy.1285951962
Short name T568
Test name
Test status
Simulation time 61543893920 ps
CPU time 3353.73 seconds
Started Feb 25 03:20:45 PM PST 24
Finished Feb 25 04:16:39 PM PST 24
Peak memory 289076 kb
Host smart-08437855-4a12-4ce2-bcbc-812a66d3df9b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285951962 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_entropy.1285951962
Directory /workspace/21.alert_handler_entropy/latest

Test location /workspace/coverage/default/21.alert_handler_esc_alert_accum.2044422029
Short name T217
Test name
Test status
Simulation time 8415194696 ps
CPU time 117.63 seconds
Started Feb 25 03:20:49 PM PST 24
Finished Feb 25 03:22:47 PM PST 24
Peak memory 255760 kb
Host smart-33c64313-7442-45a7-9309-32b01096d5b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20444
22029 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_alert_accum.2044422029
Directory /workspace/21.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/21.alert_handler_esc_intr_timeout.1836151250
Short name T541
Test name
Test status
Simulation time 32891510 ps
CPU time 3.19 seconds
Started Feb 25 03:20:47 PM PST 24
Finished Feb 25 03:20:51 PM PST 24
Peak memory 238148 kb
Host smart-c9dd0b5a-2026-452a-8129-6646a423c5b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18361
51250 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_intr_timeout.1836151250
Directory /workspace/21.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_lpg.3386919637
Short name T595
Test name
Test status
Simulation time 98118808953 ps
CPU time 1407.34 seconds
Started Feb 25 03:21:04 PM PST 24
Finished Feb 25 03:44:32 PM PST 24
Peak memory 281504 kb
Host smart-8459de66-7035-4563-aeab-a856663945df
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386919637 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg.3386919637
Directory /workspace/21.alert_handler_lpg/latest

Test location /workspace/coverage/default/21.alert_handler_lpg_stub_clk.4138645528
Short name T358
Test name
Test status
Simulation time 36655187272 ps
CPU time 1456.05 seconds
Started Feb 25 03:21:11 PM PST 24
Finished Feb 25 03:45:27 PM PST 24
Peak memory 288484 kb
Host smart-06a746cb-065c-4ffb-9a4d-18056d345b5c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138645528 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg_stub_clk.4138645528
Directory /workspace/21.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/21.alert_handler_random_alerts.3111475503
Short name T276
Test name
Test status
Simulation time 1760496979 ps
CPU time 48.77 seconds
Started Feb 25 03:21:05 PM PST 24
Finished Feb 25 03:21:54 PM PST 24
Peak memory 248232 kb
Host smart-46b6ebb8-0548-4922-a5e1-eea14c4f87ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31114
75503 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_alerts.3111475503
Directory /workspace/21.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/21.alert_handler_random_classes.1999015553
Short name T641
Test name
Test status
Simulation time 1087445881 ps
CPU time 62.23 seconds
Started Feb 25 03:20:48 PM PST 24
Finished Feb 25 03:21:50 PM PST 24
Peak memory 247584 kb
Host smart-6279ccce-9ada-4d81-afd9-e7ef41f22d35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19990
15553 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_classes.1999015553
Directory /workspace/21.alert_handler_random_classes/latest

Test location /workspace/coverage/default/21.alert_handler_sig_int_fail.1113142789
Short name T368
Test name
Test status
Simulation time 620874092 ps
CPU time 9.52 seconds
Started Feb 25 03:20:46 PM PST 24
Finished Feb 25 03:20:56 PM PST 24
Peak memory 246480 kb
Host smart-d35fc51d-a19e-4f01-82e1-eb61daff59dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11131
42789 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_sig_int_fail.1113142789
Directory /workspace/21.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/21.alert_handler_smoke.594062881
Short name T634
Test name
Test status
Simulation time 1546692651 ps
CPU time 27.09 seconds
Started Feb 25 03:20:40 PM PST 24
Finished Feb 25 03:21:08 PM PST 24
Peak memory 248148 kb
Host smart-e1801883-57f2-4641-8f52-8dae1e74c221
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59406
2881 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_smoke.594062881
Directory /workspace/21.alert_handler_smoke/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all.3696539497
Short name T547
Test name
Test status
Simulation time 20979103395 ps
CPU time 848.28 seconds
Started Feb 25 03:21:04 PM PST 24
Finished Feb 25 03:35:12 PM PST 24
Peak memory 269628 kb
Host smart-5199f6cb-4985-4d33-8f05-ef4c833b613a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696539497 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_ha
ndler_stress_all.3696539497
Directory /workspace/21.alert_handler_stress_all/latest

Test location /workspace/coverage/default/22.alert_handler_entropy.2236398028
Short name T649
Test name
Test status
Simulation time 171843389766 ps
CPU time 2378.18 seconds
Started Feb 25 03:20:50 PM PST 24
Finished Feb 25 04:00:28 PM PST 24
Peak memory 283084 kb
Host smart-28a4fdfb-fc31-410f-bcd4-86f8356e2069
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236398028 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_entropy.2236398028
Directory /workspace/22.alert_handler_entropy/latest

Test location /workspace/coverage/default/22.alert_handler_esc_alert_accum.3775359002
Short name T676
Test name
Test status
Simulation time 9966096848 ps
CPU time 296.99 seconds
Started Feb 25 03:20:48 PM PST 24
Finished Feb 25 03:25:45 PM PST 24
Peak memory 255836 kb
Host smart-e143c709-13b3-48fe-8f88-9146108fea34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37753
59002 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_alert_accum.3775359002
Directory /workspace/22.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/22.alert_handler_esc_intr_timeout.2384737499
Short name T500
Test name
Test status
Simulation time 2897086768 ps
CPU time 49.06 seconds
Started Feb 25 03:21:06 PM PST 24
Finished Feb 25 03:21:56 PM PST 24
Peak memory 254024 kb
Host smart-412945e9-f289-4dc2-949e-bcf37abca59f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23847
37499 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_intr_timeout.2384737499
Directory /workspace/22.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_lpg.1811378590
Short name T340
Test name
Test status
Simulation time 115318668870 ps
CPU time 1697.33 seconds
Started Feb 25 03:20:57 PM PST 24
Finished Feb 25 03:49:15 PM PST 24
Peak memory 272220 kb
Host smart-7ec1aefc-9a0c-4e16-a89d-97fef4e85ae6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811378590 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg.1811378590
Directory /workspace/22.alert_handler_lpg/latest

Test location /workspace/coverage/default/22.alert_handler_lpg_stub_clk.2601393349
Short name T275
Test name
Test status
Simulation time 331561247624 ps
CPU time 2295.87 seconds
Started Feb 25 03:20:59 PM PST 24
Finished Feb 25 03:59:16 PM PST 24
Peak memory 288624 kb
Host smart-352370f2-566e-49f5-bf33-bfa5af1ddaae
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601393349 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg_stub_clk.2601393349
Directory /workspace/22.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/22.alert_handler_ping_timeout.2488521380
Short name T573
Test name
Test status
Simulation time 9893334427 ps
CPU time 192.31 seconds
Started Feb 25 03:20:45 PM PST 24
Finished Feb 25 03:23:57 PM PST 24
Peak memory 246156 kb
Host smart-594a07d9-3078-492b-8cac-87b452568e3a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488521380 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_ping_timeout.2488521380
Directory /workspace/22.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_random_alerts.3724572139
Short name T606
Test name
Test status
Simulation time 436910973 ps
CPU time 32.48 seconds
Started Feb 25 03:21:01 PM PST 24
Finished Feb 25 03:21:34 PM PST 24
Peak memory 248480 kb
Host smart-fbd6ed7d-abdc-4ace-8c96-58849c0b2064
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37245
72139 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_alerts.3724572139
Directory /workspace/22.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/22.alert_handler_random_classes.1974072421
Short name T400
Test name
Test status
Simulation time 5200178411 ps
CPU time 81.26 seconds
Started Feb 25 03:20:56 PM PST 24
Finished Feb 25 03:22:17 PM PST 24
Peak memory 254792 kb
Host smart-18f6bdb9-39c4-4f3d-b429-fb4cf0229164
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19740
72421 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_classes.1974072421
Directory /workspace/22.alert_handler_random_classes/latest

Test location /workspace/coverage/default/22.alert_handler_smoke.143143062
Short name T713
Test name
Test status
Simulation time 236326113 ps
CPU time 19.73 seconds
Started Feb 25 03:20:55 PM PST 24
Finished Feb 25 03:21:14 PM PST 24
Peak memory 248284 kb
Host smart-0f2336ba-273f-4f1a-887a-69b8f250658b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14314
3062 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_smoke.143143062
Directory /workspace/22.alert_handler_smoke/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all.366894673
Short name T24
Test name
Test status
Simulation time 5896394009 ps
CPU time 177.17 seconds
Started Feb 25 03:21:04 PM PST 24
Finished Feb 25 03:24:02 PM PST 24
Peak memory 256492 kb
Host smart-1f137705-a9be-4bab-8c94-1dfec2e2f198
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366894673 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_han
dler_stress_all.366894673
Directory /workspace/22.alert_handler_stress_all/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all_with_rand_reset.2719404797
Short name T457
Test name
Test status
Simulation time 150200014744 ps
CPU time 2506.33 seconds
Started Feb 25 03:20:48 PM PST 24
Finished Feb 25 04:02:35 PM PST 24
Peak memory 297608 kb
Host smart-a0592c6e-795d-422e-8ed5-db01597da32e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719404797 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 22.alert_handler_stress_all_with_rand_reset.2719404797
Directory /workspace/22.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.alert_handler_entropy.87274506
Short name T461
Test name
Test status
Simulation time 67629213246 ps
CPU time 1897.46 seconds
Started Feb 25 03:20:55 PM PST 24
Finished Feb 25 03:52:32 PM PST 24
Peak memory 272868 kb
Host smart-e483a339-ccb8-4906-8fab-308db4e9b0af
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87274506 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_entropy.87274506
Directory /workspace/23.alert_handler_entropy/latest

Test location /workspace/coverage/default/23.alert_handler_esc_alert_accum.4077973189
Short name T1
Test name
Test status
Simulation time 21876661568 ps
CPU time 229.85 seconds
Started Feb 25 03:20:58 PM PST 24
Finished Feb 25 03:24:48 PM PST 24
Peak memory 256484 kb
Host smart-190ccf2c-c109-4098-99a1-63baa7f8068e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40779
73189 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_alert_accum.4077973189
Directory /workspace/23.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/23.alert_handler_esc_intr_timeout.3367543036
Short name T535
Test name
Test status
Simulation time 1505753365 ps
CPU time 14.97 seconds
Started Feb 25 03:21:06 PM PST 24
Finished Feb 25 03:21:21 PM PST 24
Peak memory 252880 kb
Host smart-75afd1d1-99f3-446b-ae68-9caabffc4fde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33675
43036 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_intr_timeout.3367543036
Directory /workspace/23.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_lpg.1275828962
Short name T327
Test name
Test status
Simulation time 334528966583 ps
CPU time 1970.25 seconds
Started Feb 25 03:21:08 PM PST 24
Finished Feb 25 03:53:59 PM PST 24
Peak memory 272148 kb
Host smart-dcf69e90-68ed-4713-b514-4c23b6890dce
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275828962 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg.1275828962
Directory /workspace/23.alert_handler_lpg/latest

Test location /workspace/coverage/default/23.alert_handler_lpg_stub_clk.1341865043
Short name T66
Test name
Test status
Simulation time 32102991519 ps
CPU time 1366.52 seconds
Started Feb 25 03:20:55 PM PST 24
Finished Feb 25 03:43:41 PM PST 24
Peak memory 288476 kb
Host smart-1a27b35e-508f-4085-96ad-6ef185f7d47a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341865043 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg_stub_clk.1341865043
Directory /workspace/23.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/23.alert_handler_ping_timeout.673179264
Short name T10
Test name
Test status
Simulation time 8271826991 ps
CPU time 359.04 seconds
Started Feb 25 03:21:04 PM PST 24
Finished Feb 25 03:27:03 PM PST 24
Peak memory 248292 kb
Host smart-b7270a0d-0a88-4bb6-8081-34f2e077cff3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673179264 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_ping_timeout.673179264
Directory /workspace/23.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_random_alerts.1738033173
Short name T459
Test name
Test status
Simulation time 2058789649 ps
CPU time 13.45 seconds
Started Feb 25 03:21:02 PM PST 24
Finished Feb 25 03:21:16 PM PST 24
Peak memory 253756 kb
Host smart-3c9c4d80-1474-49f4-bb26-010717473c21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17380
33173 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_alerts.1738033173
Directory /workspace/23.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/23.alert_handler_random_classes.395082869
Short name T384
Test name
Test status
Simulation time 2282243593 ps
CPU time 32.49 seconds
Started Feb 25 03:20:54 PM PST 24
Finished Feb 25 03:21:27 PM PST 24
Peak memory 254460 kb
Host smart-c9eaebf5-50d3-4007-9793-e9fb59bc74a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39508
2869 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_classes.395082869
Directory /workspace/23.alert_handler_random_classes/latest

Test location /workspace/coverage/default/23.alert_handler_sig_int_fail.2516080275
Short name T258
Test name
Test status
Simulation time 1708368543 ps
CPU time 50.65 seconds
Started Feb 25 03:20:51 PM PST 24
Finished Feb 25 03:21:42 PM PST 24
Peak memory 253708 kb
Host smart-92d6288c-2320-49ec-aa63-203fa6abcace
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25160
80275 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_sig_int_fail.2516080275
Directory /workspace/23.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/23.alert_handler_smoke.372787834
Short name T689
Test name
Test status
Simulation time 380149125 ps
CPU time 20.01 seconds
Started Feb 25 03:20:58 PM PST 24
Finished Feb 25 03:21:19 PM PST 24
Peak memory 253856 kb
Host smart-57fe9cee-b035-4869-8efd-101c5fdcf19c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37278
7834 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_smoke.372787834
Directory /workspace/23.alert_handler_smoke/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all.4127900080
Short name T683
Test name
Test status
Simulation time 38292718391 ps
CPU time 1805.97 seconds
Started Feb 25 03:21:04 PM PST 24
Finished Feb 25 03:51:10 PM PST 24
Peak memory 288820 kb
Host smart-5b442a88-cd2a-487a-a2ec-3aeb01382f7f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127900080 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_ha
ndler_stress_all.4127900080
Directory /workspace/23.alert_handler_stress_all/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all_with_rand_reset.3300607587
Short name T117
Test name
Test status
Simulation time 19181977925 ps
CPU time 1323.28 seconds
Started Feb 25 03:21:01 PM PST 24
Finished Feb 25 03:43:05 PM PST 24
Peak memory 272484 kb
Host smart-fa54b378-3dea-4de6-a395-c1aa2eb4889a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300607587 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 23.alert_handler_stress_all_with_rand_reset.3300607587
Directory /workspace/23.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.alert_handler_entropy.3877552260
Short name T91
Test name
Test status
Simulation time 20599764993 ps
CPU time 1293.94 seconds
Started Feb 25 03:21:00 PM PST 24
Finished Feb 25 03:42:34 PM PST 24
Peak memory 272524 kb
Host smart-c483977d-43dd-4324-b521-669048257b40
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877552260 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_entropy.3877552260
Directory /workspace/24.alert_handler_entropy/latest

Test location /workspace/coverage/default/24.alert_handler_esc_alert_accum.4016829178
Short name T238
Test name
Test status
Simulation time 15283986091 ps
CPU time 206.73 seconds
Started Feb 25 03:20:45 PM PST 24
Finished Feb 25 03:24:12 PM PST 24
Peak memory 256216 kb
Host smart-f2bed78b-9173-40c0-8976-3682e8daf0e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40168
29178 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_alert_accum.4016829178
Directory /workspace/24.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/24.alert_handler_esc_intr_timeout.2816987733
Short name T416
Test name
Test status
Simulation time 1198256872 ps
CPU time 26.12 seconds
Started Feb 25 03:20:55 PM PST 24
Finished Feb 25 03:21:21 PM PST 24
Peak memory 253880 kb
Host smart-d1dade7b-1622-4202-abd4-3caa67310961
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28169
87733 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_intr_timeout.2816987733
Directory /workspace/24.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_lpg.2737486552
Short name T285
Test name
Test status
Simulation time 48749012258 ps
CPU time 1145.93 seconds
Started Feb 25 03:20:58 PM PST 24
Finished Feb 25 03:40:04 PM PST 24
Peak memory 272192 kb
Host smart-f3215d50-3e8f-435f-b688-46dcbf5c6418
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2737486552 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg.2737486552
Directory /workspace/24.alert_handler_lpg/latest

Test location /workspace/coverage/default/24.alert_handler_lpg_stub_clk.570024275
Short name T587
Test name
Test status
Simulation time 29373529735 ps
CPU time 1896.78 seconds
Started Feb 25 03:21:05 PM PST 24
Finished Feb 25 03:52:42 PM PST 24
Peak memory 281080 kb
Host smart-3a07bd22-31a5-4d79-be9c-3e7af2006ed5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570024275 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg_stub_clk.570024275
Directory /workspace/24.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/24.alert_handler_ping_timeout.475257978
Short name T590
Test name
Test status
Simulation time 8610031807 ps
CPU time 178.94 seconds
Started Feb 25 03:21:05 PM PST 24
Finished Feb 25 03:24:04 PM PST 24
Peak memory 247188 kb
Host smart-f02363d9-0652-4ea6-b814-771ba6010d14
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475257978 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_ping_timeout.475257978
Directory /workspace/24.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_random_alerts.3962665556
Short name T685
Test name
Test status
Simulation time 267830972 ps
CPU time 28.36 seconds
Started Feb 25 03:20:45 PM PST 24
Finished Feb 25 03:21:14 PM PST 24
Peak memory 248232 kb
Host smart-a123b1c8-3885-43e6-a15e-d4801eda353c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39626
65556 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_alerts.3962665556
Directory /workspace/24.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/24.alert_handler_random_classes.551851906
Short name T106
Test name
Test status
Simulation time 1551957063 ps
CPU time 44.63 seconds
Started Feb 25 03:20:55 PM PST 24
Finished Feb 25 03:21:40 PM PST 24
Peak memory 254520 kb
Host smart-baf085ce-fd3d-48be-96d9-a3da46982a65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55185
1906 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_classes.551851906
Directory /workspace/24.alert_handler_random_classes/latest

Test location /workspace/coverage/default/24.alert_handler_sig_int_fail.3280438760
Short name T505
Test name
Test status
Simulation time 2341351694 ps
CPU time 34.33 seconds
Started Feb 25 03:20:47 PM PST 24
Finished Feb 25 03:21:21 PM PST 24
Peak memory 248316 kb
Host smart-06587f58-7e1b-49a8-bfb5-22d9fe863952
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32804
38760 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_sig_int_fail.3280438760
Directory /workspace/24.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/24.alert_handler_smoke.349571036
Short name T588
Test name
Test status
Simulation time 62719182 ps
CPU time 5.23 seconds
Started Feb 25 03:20:53 PM PST 24
Finished Feb 25 03:20:59 PM PST 24
Peak memory 240020 kb
Host smart-bb7af340-a68e-4cfa-a23b-d65d9233e2df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34957
1036 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_smoke.349571036
Directory /workspace/24.alert_handler_smoke/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all.1278519067
Short name T53
Test name
Test status
Simulation time 62341735965 ps
CPU time 1506.51 seconds
Started Feb 25 03:21:04 PM PST 24
Finished Feb 25 03:46:11 PM PST 24
Peak memory 289260 kb
Host smart-2de143b9-27ad-4be3-9487-2849b6103d55
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278519067 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_ha
ndler_stress_all.1278519067
Directory /workspace/24.alert_handler_stress_all/latest

Test location /workspace/coverage/default/25.alert_handler_entropy.480357671
Short name T638
Test name
Test status
Simulation time 136075800919 ps
CPU time 1865.53 seconds
Started Feb 25 03:21:06 PM PST 24
Finished Feb 25 03:52:12 PM PST 24
Peak memory 282092 kb
Host smart-2a4318a8-e397-4bab-a406-574c4f4a079a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480357671 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_entropy.480357671
Directory /workspace/25.alert_handler_entropy/latest

Test location /workspace/coverage/default/25.alert_handler_esc_alert_accum.3219907518
Short name T698
Test name
Test status
Simulation time 3126445625 ps
CPU time 202.58 seconds
Started Feb 25 03:21:08 PM PST 24
Finished Feb 25 03:24:31 PM PST 24
Peak memory 249332 kb
Host smart-e38bc0ad-9ee8-48d5-ae75-166d20600fd2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32199
07518 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_alert_accum.3219907518
Directory /workspace/25.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/25.alert_handler_esc_intr_timeout.992095467
Short name T463
Test name
Test status
Simulation time 1726309187 ps
CPU time 56.9 seconds
Started Feb 25 03:21:10 PM PST 24
Finished Feb 25 03:22:07 PM PST 24
Peak memory 254060 kb
Host smart-135fcb6f-69bb-4304-97da-643864bf44ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99209
5467 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_intr_timeout.992095467
Directory /workspace/25.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_lpg.2241100304
Short name T524
Test name
Test status
Simulation time 162437987045 ps
CPU time 2429.78 seconds
Started Feb 25 03:21:11 PM PST 24
Finished Feb 25 04:01:42 PM PST 24
Peak memory 288716 kb
Host smart-976b1017-2ead-4590-90b3-3370d31c9c4a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2241100304 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg.2241100304
Directory /workspace/25.alert_handler_lpg/latest

Test location /workspace/coverage/default/25.alert_handler_lpg_stub_clk.1348887348
Short name T529
Test name
Test status
Simulation time 24283307621 ps
CPU time 1227.49 seconds
Started Feb 25 03:21:07 PM PST 24
Finished Feb 25 03:41:35 PM PST 24
Peak memory 272816 kb
Host smart-ab4f96e4-bd43-456d-a4ba-f7b822be67bd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348887348 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg_stub_clk.1348887348
Directory /workspace/25.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/25.alert_handler_ping_timeout.3528854790
Short name T651
Test name
Test status
Simulation time 23624216534 ps
CPU time 249.86 seconds
Started Feb 25 03:21:08 PM PST 24
Finished Feb 25 03:25:19 PM PST 24
Peak memory 247188 kb
Host smart-64e5e8e1-5e1e-4995-b02e-920ad07c1cac
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528854790 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_ping_timeout.3528854790
Directory /workspace/25.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_random_alerts.642303398
Short name T26
Test name
Test status
Simulation time 1713427506 ps
CPU time 30.5 seconds
Started Feb 25 03:21:17 PM PST 24
Finished Feb 25 03:21:48 PM PST 24
Peak memory 248252 kb
Host smart-c6e5bf8a-c355-462c-a595-843a2439f08f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64230
3398 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_alerts.642303398
Directory /workspace/25.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/25.alert_handler_random_classes.2109204211
Short name T620
Test name
Test status
Simulation time 727025266 ps
CPU time 28.16 seconds
Started Feb 25 03:21:09 PM PST 24
Finished Feb 25 03:21:37 PM PST 24
Peak memory 254536 kb
Host smart-3e47dc0d-593c-4f8a-b17a-93cbbffcb6be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21092
04211 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_classes.2109204211
Directory /workspace/25.alert_handler_random_classes/latest

Test location /workspace/coverage/default/25.alert_handler_sig_int_fail.1048494601
Short name T82
Test name
Test status
Simulation time 728534709 ps
CPU time 56.86 seconds
Started Feb 25 03:21:18 PM PST 24
Finished Feb 25 03:22:15 PM PST 24
Peak memory 254644 kb
Host smart-ca964227-870e-4096-b423-8dd35bf7e1db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10484
94601 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_sig_int_fail.1048494601
Directory /workspace/25.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/25.alert_handler_smoke.2954290653
Short name T420
Test name
Test status
Simulation time 3968002228 ps
CPU time 28.87 seconds
Started Feb 25 03:21:04 PM PST 24
Finished Feb 25 03:21:33 PM PST 24
Peak memory 248300 kb
Host smart-8ef0c82c-c1e4-4284-ad46-0065015c4e66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29542
90653 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_smoke.2954290653
Directory /workspace/25.alert_handler_smoke/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all.1252905095
Short name T701
Test name
Test status
Simulation time 66221215583 ps
CPU time 1526.71 seconds
Started Feb 25 03:21:06 PM PST 24
Finished Feb 25 03:46:33 PM PST 24
Peak memory 289052 kb
Host smart-65567c7b-70c2-455e-be21-969594f166af
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252905095 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_ha
ndler_stress_all.1252905095
Directory /workspace/25.alert_handler_stress_all/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all_with_rand_reset.181535547
Short name T62
Test name
Test status
Simulation time 328579063158 ps
CPU time 6588.35 seconds
Started Feb 25 03:21:18 PM PST 24
Finished Feb 25 05:11:07 PM PST 24
Peak memory 338100 kb
Host smart-a7e66f65-3f04-40e6-aeb0-66ea98fccea0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181535547 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 25.alert_handler_stress_all_with_rand_reset.181535547
Directory /workspace/25.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.alert_handler_entropy.573479619
Short name T533
Test name
Test status
Simulation time 60753724919 ps
CPU time 787 seconds
Started Feb 25 03:21:11 PM PST 24
Finished Feb 25 03:34:18 PM PST 24
Peak memory 271928 kb
Host smart-3f963f9a-8782-4725-a446-bbc336ea5b0f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573479619 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_entropy.573479619
Directory /workspace/26.alert_handler_entropy/latest

Test location /workspace/coverage/default/26.alert_handler_esc_alert_accum.140457374
Short name T516
Test name
Test status
Simulation time 2230124030 ps
CPU time 129.15 seconds
Started Feb 25 03:21:06 PM PST 24
Finished Feb 25 03:23:15 PM PST 24
Peak memory 249236 kb
Host smart-138e1af3-27e8-476b-94b4-09a85cc3d675
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14045
7374 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_alert_accum.140457374
Directory /workspace/26.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/26.alert_handler_esc_intr_timeout.1974889874
Short name T570
Test name
Test status
Simulation time 3726681750 ps
CPU time 62.9 seconds
Started Feb 25 03:21:13 PM PST 24
Finished Feb 25 03:22:16 PM PST 24
Peak memory 254756 kb
Host smart-8bfd8a1c-139c-4704-b914-f55db303c770
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19748
89874 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_intr_timeout.1974889874
Directory /workspace/26.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_lpg.3735373156
Short name T329
Test name
Test status
Simulation time 9061671275 ps
CPU time 945.89 seconds
Started Feb 25 03:21:07 PM PST 24
Finished Feb 25 03:36:53 PM PST 24
Peak memory 272744 kb
Host smart-03faea5c-7071-449f-909b-11a6af830dfc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3735373156 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg.3735373156
Directory /workspace/26.alert_handler_lpg/latest

Test location /workspace/coverage/default/26.alert_handler_lpg_stub_clk.411373061
Short name T611
Test name
Test status
Simulation time 27158059842 ps
CPU time 1289.11 seconds
Started Feb 25 03:21:18 PM PST 24
Finished Feb 25 03:42:47 PM PST 24
Peak memory 281096 kb
Host smart-24828d52-99c2-4783-8a4e-9c6be0822240
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411373061 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg_stub_clk.411373061
Directory /workspace/26.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/26.alert_handler_ping_timeout.2160359692
Short name T318
Test name
Test status
Simulation time 22942219142 ps
CPU time 493.37 seconds
Started Feb 25 03:21:11 PM PST 24
Finished Feb 25 03:29:25 PM PST 24
Peak memory 245868 kb
Host smart-926a8033-02dc-4ddf-a19f-5f0c5131e00e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160359692 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_ping_timeout.2160359692
Directory /workspace/26.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_random_alerts.2987784218
Short name T520
Test name
Test status
Simulation time 1021612872 ps
CPU time 59.27 seconds
Started Feb 25 03:20:56 PM PST 24
Finished Feb 25 03:21:56 PM PST 24
Peak memory 248232 kb
Host smart-82d2e213-1b1b-49df-94d8-3f256dc07dce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29877
84218 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_alerts.2987784218
Directory /workspace/26.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/26.alert_handler_random_classes.1316716957
Short name T622
Test name
Test status
Simulation time 768476025 ps
CPU time 19.6 seconds
Started Feb 25 03:21:11 PM PST 24
Finished Feb 25 03:21:31 PM PST 24
Peak memory 254140 kb
Host smart-9f5c152e-05c5-43e8-844f-752a0a802d63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13167
16957 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_classes.1316716957
Directory /workspace/26.alert_handler_random_classes/latest

Test location /workspace/coverage/default/26.alert_handler_sig_int_fail.2929709794
Short name T560
Test name
Test status
Simulation time 3004262349 ps
CPU time 52.72 seconds
Started Feb 25 03:20:56 PM PST 24
Finished Feb 25 03:21:49 PM PST 24
Peak memory 246756 kb
Host smart-68087ba3-396a-48d7-8345-e0981e9ea1c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29297
09794 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_sig_int_fail.2929709794
Directory /workspace/26.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/26.alert_handler_smoke.1197238226
Short name T405
Test name
Test status
Simulation time 195347744 ps
CPU time 18.84 seconds
Started Feb 25 03:21:02 PM PST 24
Finished Feb 25 03:21:21 PM PST 24
Peak memory 248220 kb
Host smart-d4ff200d-5217-4459-9141-67cf1b4617b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11972
38226 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_smoke.1197238226
Directory /workspace/26.alert_handler_smoke/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all.2959279700
Short name T123
Test name
Test status
Simulation time 179587141631 ps
CPU time 2381.1 seconds
Started Feb 25 03:21:06 PM PST 24
Finished Feb 25 04:00:48 PM PST 24
Peak memory 288248 kb
Host smart-bbaeb44d-3816-43c5-8d89-e79740301c4f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959279700 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_ha
ndler_stress_all.2959279700
Directory /workspace/26.alert_handler_stress_all/latest

Test location /workspace/coverage/default/27.alert_handler_entropy.1418484354
Short name T72
Test name
Test status
Simulation time 9157614777 ps
CPU time 666.58 seconds
Started Feb 25 03:21:10 PM PST 24
Finished Feb 25 03:32:17 PM PST 24
Peak memory 265728 kb
Host smart-2aa5287a-71c4-4dee-9670-eb35bf4cb530
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418484354 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_entropy.1418484354
Directory /workspace/27.alert_handler_entropy/latest

Test location /workspace/coverage/default/27.alert_handler_esc_alert_accum.4137407947
Short name T583
Test name
Test status
Simulation time 2180217467 ps
CPU time 42.18 seconds
Started Feb 25 03:21:19 PM PST 24
Finished Feb 25 03:22:02 PM PST 24
Peak memory 255592 kb
Host smart-c875865b-dd6c-4cbf-8ab4-151e7be9f009
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41374
07947 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_alert_accum.4137407947
Directory /workspace/27.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/27.alert_handler_esc_intr_timeout.3789107078
Short name T526
Test name
Test status
Simulation time 355404903 ps
CPU time 23.97 seconds
Started Feb 25 03:21:05 PM PST 24
Finished Feb 25 03:21:29 PM PST 24
Peak memory 254764 kb
Host smart-8f07e1b9-f013-47a4-b25b-e7d527754dea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37891
07078 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_intr_timeout.3789107078
Directory /workspace/27.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_lpg.4156022216
Short name T319
Test name
Test status
Simulation time 44612207535 ps
CPU time 2467.94 seconds
Started Feb 25 03:21:11 PM PST 24
Finished Feb 25 04:02:20 PM PST 24
Peak memory 288500 kb
Host smart-422ec6e6-ef64-4ced-8203-f4e205776d93
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156022216 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg.4156022216
Directory /workspace/27.alert_handler_lpg/latest

Test location /workspace/coverage/default/27.alert_handler_lpg_stub_clk.3393052297
Short name T566
Test name
Test status
Simulation time 46582411263 ps
CPU time 1818.99 seconds
Started Feb 25 03:21:09 PM PST 24
Finished Feb 25 03:51:29 PM PST 24
Peak memory 283980 kb
Host smart-099a205e-92b7-464a-a278-ffcaef3d247f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393052297 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg_stub_clk.3393052297
Directory /workspace/27.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/27.alert_handler_ping_timeout.4094556447
Short name T292
Test name
Test status
Simulation time 10998148296 ps
CPU time 172.68 seconds
Started Feb 25 03:21:15 PM PST 24
Finished Feb 25 03:24:08 PM PST 24
Peak memory 246464 kb
Host smart-c64a1cec-f1a6-496b-b3be-256f886357f4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094556447 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_ping_timeout.4094556447
Directory /workspace/27.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_random_alerts.489129454
Short name T266
Test name
Test status
Simulation time 121190231 ps
CPU time 7.85 seconds
Started Feb 25 03:21:10 PM PST 24
Finished Feb 25 03:21:18 PM PST 24
Peak memory 248228 kb
Host smart-a82690b4-45e4-4d34-9d4f-c74361279fe3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48912
9454 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_alerts.489129454
Directory /workspace/27.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/27.alert_handler_random_classes.4074631863
Short name T221
Test name
Test status
Simulation time 984217497 ps
CPU time 62.68 seconds
Started Feb 25 03:21:11 PM PST 24
Finished Feb 25 03:22:14 PM PST 24
Peak memory 254780 kb
Host smart-d1d0bdd4-ae66-44a2-a198-e76378d35e12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40746
31863 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_classes.4074631863
Directory /workspace/27.alert_handler_random_classes/latest

Test location /workspace/coverage/default/27.alert_handler_sig_int_fail.187974939
Short name T75
Test name
Test status
Simulation time 524083281 ps
CPU time 31.75 seconds
Started Feb 25 03:21:09 PM PST 24
Finished Feb 25 03:21:42 PM PST 24
Peak memory 246888 kb
Host smart-91628934-8932-4690-99e9-d478d634fcaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18797
4939 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_sig_int_fail.187974939
Directory /workspace/27.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/27.alert_handler_smoke.940697016
Short name T113
Test name
Test status
Simulation time 9727848900 ps
CPU time 52.42 seconds
Started Feb 25 03:21:11 PM PST 24
Finished Feb 25 03:22:04 PM PST 24
Peak memory 255172 kb
Host smart-d664f7a3-0d2f-4c33-a7ac-4bfddfd3e4f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94069
7016 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_smoke.940697016
Directory /workspace/27.alert_handler_smoke/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all.496677841
Short name T61
Test name
Test status
Simulation time 84567353730 ps
CPU time 2847.19 seconds
Started Feb 25 03:21:03 PM PST 24
Finished Feb 25 04:08:31 PM PST 24
Peak memory 288488 kb
Host smart-4ea54578-40a6-45a4-9496-88709b3131ec
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496677841 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_han
dler_stress_all.496677841
Directory /workspace/27.alert_handler_stress_all/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all_with_rand_reset.3044188503
Short name T446
Test name
Test status
Simulation time 52696700393 ps
CPU time 3521.76 seconds
Started Feb 25 03:21:19 PM PST 24
Finished Feb 25 04:20:01 PM PST 24
Peak memory 305672 kb
Host smart-b3a8a176-2730-4c36-83f5-a350b3533bd4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044188503 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.alert_handler_stress_all_with_rand_reset.3044188503
Directory /workspace/27.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.alert_handler_entropy.1197916418
Short name T114
Test name
Test status
Simulation time 53075707683 ps
CPU time 1548.16 seconds
Started Feb 25 03:21:13 PM PST 24
Finished Feb 25 03:47:02 PM PST 24
Peak memory 288712 kb
Host smart-c9da83a9-24e7-47e2-bae9-94f989e3d5e7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197916418 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_entropy.1197916418
Directory /workspace/28.alert_handler_entropy/latest

Test location /workspace/coverage/default/28.alert_handler_esc_alert_accum.3577950696
Short name T86
Test name
Test status
Simulation time 3508977792 ps
CPU time 22.81 seconds
Started Feb 25 03:21:19 PM PST 24
Finished Feb 25 03:21:42 PM PST 24
Peak memory 254772 kb
Host smart-1dd43a00-1e0f-4e27-8aa6-1913beb2934b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35779
50696 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_alert_accum.3577950696
Directory /workspace/28.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/28.alert_handler_esc_intr_timeout.2687016604
Short name T21
Test name
Test status
Simulation time 948201293 ps
CPU time 12.66 seconds
Started Feb 25 03:21:17 PM PST 24
Finished Feb 25 03:21:30 PM PST 24
Peak memory 247840 kb
Host smart-4c5f5f67-c115-483a-9885-e3077c8f847e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26870
16604 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_intr_timeout.2687016604
Directory /workspace/28.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_lpg.2899048034
Short name T283
Test name
Test status
Simulation time 72372674808 ps
CPU time 1343.57 seconds
Started Feb 25 03:21:19 PM PST 24
Finished Feb 25 03:43:43 PM PST 24
Peak memory 285828 kb
Host smart-532115e8-f049-470f-bd35-ed8fb1e43e0d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899048034 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg.2899048034
Directory /workspace/28.alert_handler_lpg/latest

Test location /workspace/coverage/default/28.alert_handler_lpg_stub_clk.986507411
Short name T646
Test name
Test status
Simulation time 217526212306 ps
CPU time 2574.43 seconds
Started Feb 25 03:21:07 PM PST 24
Finished Feb 25 04:04:02 PM PST 24
Peak memory 282924 kb
Host smart-0d8dfaf7-11ee-4998-8fa4-ae0cc7a94cb8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986507411 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg_stub_clk.986507411
Directory /workspace/28.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/28.alert_handler_random_alerts.642122828
Short name T387
Test name
Test status
Simulation time 53413047 ps
CPU time 2.59 seconds
Started Feb 25 03:21:13 PM PST 24
Finished Feb 25 03:21:16 PM PST 24
Peak memory 240032 kb
Host smart-8d3bba02-c20d-47d4-bcd2-cce8426b332f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64212
2828 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_alerts.642122828
Directory /workspace/28.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/28.alert_handler_random_classes.1171851954
Short name T703
Test name
Test status
Simulation time 674640544 ps
CPU time 32.64 seconds
Started Feb 25 03:21:16 PM PST 24
Finished Feb 25 03:21:49 PM PST 24
Peak memory 254728 kb
Host smart-ff5ec943-cfc7-4a8f-9567-85fd374889b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11718
51954 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_classes.1171851954
Directory /workspace/28.alert_handler_random_classes/latest

Test location /workspace/coverage/default/28.alert_handler_sig_int_fail.1993817787
Short name T497
Test name
Test status
Simulation time 964054348 ps
CPU time 30.55 seconds
Started Feb 25 03:21:19 PM PST 24
Finished Feb 25 03:21:50 PM PST 24
Peak memory 253984 kb
Host smart-e52e9ed5-28b4-4903-ac3c-8a45a418ef19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19938
17787 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_sig_int_fail.1993817787
Directory /workspace/28.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/28.alert_handler_smoke.3366425825
Short name T417
Test name
Test status
Simulation time 114533612 ps
CPU time 8.84 seconds
Started Feb 25 03:21:18 PM PST 24
Finished Feb 25 03:21:27 PM PST 24
Peak memory 248224 kb
Host smart-80e4b61d-b3ab-4bdd-a178-de784bae5cc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33664
25825 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_smoke.3366425825
Directory /workspace/28.alert_handler_smoke/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all.4208764047
Short name T394
Test name
Test status
Simulation time 1086737047 ps
CPU time 91.92 seconds
Started Feb 25 03:21:15 PM PST 24
Finished Feb 25 03:22:47 PM PST 24
Peak memory 249812 kb
Host smart-1d7e1ca2-72a9-4f83-accd-c6bc7e5a82b9
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208764047 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_ha
ndler_stress_all.4208764047
Directory /workspace/28.alert_handler_stress_all/latest

Test location /workspace/coverage/default/29.alert_handler_entropy.282282458
Short name T479
Test name
Test status
Simulation time 14872044920 ps
CPU time 1366.02 seconds
Started Feb 25 03:21:21 PM PST 24
Finished Feb 25 03:44:07 PM PST 24
Peak memory 286412 kb
Host smart-5899aca3-a225-4239-90f0-8efc19f533ee
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=282282458 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_entropy.282282458
Directory /workspace/29.alert_handler_entropy/latest

Test location /workspace/coverage/default/29.alert_handler_esc_alert_accum.2625527975
Short name T453
Test name
Test status
Simulation time 3768236580 ps
CPU time 129.54 seconds
Started Feb 25 03:21:17 PM PST 24
Finished Feb 25 03:23:27 PM PST 24
Peak memory 255872 kb
Host smart-3579c0c9-8362-4890-99b3-37a2ec1bb3d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26255
27975 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_alert_accum.2625527975
Directory /workspace/29.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/29.alert_handler_esc_intr_timeout.4078764318
Short name T223
Test name
Test status
Simulation time 310273526 ps
CPU time 20.07 seconds
Started Feb 25 03:21:22 PM PST 24
Finished Feb 25 03:21:42 PM PST 24
Peak memory 247752 kb
Host smart-dad85cff-af8e-4f83-9c04-99ea180a7cc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40787
64318 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_intr_timeout.4078764318
Directory /workspace/29.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_lpg.3694076121
Short name T286
Test name
Test status
Simulation time 10909183762 ps
CPU time 1159.99 seconds
Started Feb 25 03:21:17 PM PST 24
Finished Feb 25 03:40:38 PM PST 24
Peak memory 288616 kb
Host smart-37d354ef-fa79-474b-895f-db1aa4d89d79
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694076121 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg.3694076121
Directory /workspace/29.alert_handler_lpg/latest

Test location /workspace/coverage/default/29.alert_handler_lpg_stub_clk.1261092907
Short name T521
Test name
Test status
Simulation time 15622964121 ps
CPU time 1136.64 seconds
Started Feb 25 03:21:08 PM PST 24
Finished Feb 25 03:40:05 PM PST 24
Peak memory 272876 kb
Host smart-8f96e284-b05f-4780-99ce-9d53881c69ee
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1261092907 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg_stub_clk.1261092907
Directory /workspace/29.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/29.alert_handler_ping_timeout.3956687630
Short name T538
Test name
Test status
Simulation time 13386875114 ps
CPU time 586.54 seconds
Started Feb 25 03:21:18 PM PST 24
Finished Feb 25 03:31:05 PM PST 24
Peak memory 246144 kb
Host smart-9bc782a2-9f27-4e38-8bec-f6defea60b9a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956687630 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_ping_timeout.3956687630
Directory /workspace/29.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_random_alerts.6673276
Short name T523
Test name
Test status
Simulation time 212946075 ps
CPU time 14.92 seconds
Started Feb 25 03:21:08 PM PST 24
Finished Feb 25 03:21:23 PM PST 24
Peak memory 254060 kb
Host smart-27fba2a9-641e-4708-a031-0c16886f97e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66732
76 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_alerts.6673276
Directory /workspace/29.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/29.alert_handler_random_classes.3104447222
Short name T511
Test name
Test status
Simulation time 1026516445 ps
CPU time 9.53 seconds
Started Feb 25 03:21:09 PM PST 24
Finished Feb 25 03:21:19 PM PST 24
Peak memory 252168 kb
Host smart-d183c35d-82b3-4897-bd0d-a91287352427
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31044
47222 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_classes.3104447222
Directory /workspace/29.alert_handler_random_classes/latest

Test location /workspace/coverage/default/29.alert_handler_sig_int_fail.2038355958
Short name T243
Test name
Test status
Simulation time 1132179846 ps
CPU time 42.45 seconds
Started Feb 25 03:21:18 PM PST 24
Finished Feb 25 03:22:00 PM PST 24
Peak memory 254516 kb
Host smart-029c195d-7b83-4f7e-9603-b6b8fb2c4061
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20383
55958 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_sig_int_fail.2038355958
Directory /workspace/29.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/29.alert_handler_smoke.2645980145
Short name T581
Test name
Test status
Simulation time 326683023 ps
CPU time 36.92 seconds
Started Feb 25 03:21:18 PM PST 24
Finished Feb 25 03:21:55 PM PST 24
Peak memory 248184 kb
Host smart-0f507f2d-5b1c-4821-abdc-e09b2869932b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26459
80145 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_smoke.2645980145
Directory /workspace/29.alert_handler_smoke/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all.3317554457
Short name T57
Test name
Test status
Simulation time 89105102077 ps
CPU time 709.87 seconds
Started Feb 25 03:21:22 PM PST 24
Finished Feb 25 03:33:12 PM PST 24
Peak memory 264784 kb
Host smart-35e0439f-be31-46e7-a5d8-609a41ffb61e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317554457 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_ha
ndler_stress_all.3317554457
Directory /workspace/29.alert_handler_stress_all/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all_with_rand_reset.1090210812
Short name T59
Test name
Test status
Simulation time 55650625566 ps
CPU time 3395.4 seconds
Started Feb 25 03:21:18 PM PST 24
Finished Feb 25 04:17:54 PM PST 24
Peak memory 297612 kb
Host smart-980d4fe2-5071-4fec-b008-d1929c798777
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090210812 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.alert_handler_stress_all_with_rand_reset.1090210812
Directory /workspace/29.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.alert_handler_alert_accum_saturation.1258946116
Short name T204
Test name
Test status
Simulation time 190105992 ps
CPU time 2.28 seconds
Started Feb 25 03:20:12 PM PST 24
Finished Feb 25 03:20:15 PM PST 24
Peak memory 248528 kb
Host smart-e6df2ab1-0834-48c8-81ae-deea3dbf2576
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1258946116 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_alert_accum_saturation.1258946116
Directory /workspace/3.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/3.alert_handler_entropy.1373464874
Short name T626
Test name
Test status
Simulation time 57694036437 ps
CPU time 1130.3 seconds
Started Feb 25 03:20:14 PM PST 24
Finished Feb 25 03:39:06 PM PST 24
Peak memory 288652 kb
Host smart-46fcbf36-4ff0-490b-b42b-e808c6a6a92f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1373464874 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy.1373464874
Directory /workspace/3.alert_handler_entropy/latest

Test location /workspace/coverage/default/3.alert_handler_entropy_stress.2017882477
Short name T371
Test name
Test status
Simulation time 1772680140 ps
CPU time 24.07 seconds
Started Feb 25 03:20:12 PM PST 24
Finished Feb 25 03:20:37 PM PST 24
Peak memory 240056 kb
Host smart-4f059beb-a2b6-41df-be03-01f7212f4cc7
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2017882477 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy_stress.2017882477
Directory /workspace/3.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/3.alert_handler_esc_alert_accum.3954361848
Short name T662
Test name
Test status
Simulation time 117828173 ps
CPU time 8.82 seconds
Started Feb 25 03:20:08 PM PST 24
Finished Feb 25 03:20:17 PM PST 24
Peak memory 247904 kb
Host smart-f0a29ac4-316d-432d-b8f6-519212bdb5eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39543
61848 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_alert_accum.3954361848
Directory /workspace/3.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/3.alert_handler_esc_intr_timeout.190401602
Short name T374
Test name
Test status
Simulation time 376172347 ps
CPU time 10.26 seconds
Started Feb 25 03:20:07 PM PST 24
Finished Feb 25 03:20:17 PM PST 24
Peak memory 254160 kb
Host smart-fac63154-53c2-4a72-a370-47e231fd1a0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19040
1602 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_intr_timeout.190401602
Directory /workspace/3.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_lpg.2246499293
Short name T265
Test name
Test status
Simulation time 25124914588 ps
CPU time 1522.92 seconds
Started Feb 25 03:20:13 PM PST 24
Finished Feb 25 03:45:37 PM PST 24
Peak memory 267760 kb
Host smart-da973575-4a72-4b1e-8b99-b8c86ea3fcf9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246499293 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg.2246499293
Directory /workspace/3.alert_handler_lpg/latest

Test location /workspace/coverage/default/3.alert_handler_lpg_stub_clk.347839276
Short name T289
Test name
Test status
Simulation time 6759586276 ps
CPU time 667.04 seconds
Started Feb 25 03:20:19 PM PST 24
Finished Feb 25 03:31:26 PM PST 24
Peak memory 266776 kb
Host smart-cbb4a57f-d8cd-45eb-89a2-07274bb441c6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347839276 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg_stub_clk.347839276
Directory /workspace/3.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/3.alert_handler_random_alerts.1898984068
Short name T119
Test name
Test status
Simulation time 5250648414 ps
CPU time 57.54 seconds
Started Feb 25 03:20:04 PM PST 24
Finished Feb 25 03:21:07 PM PST 24
Peak memory 248296 kb
Host smart-7bac7a8e-6bf1-4933-ab95-71423b63bc79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18989
84068 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_alerts.1898984068
Directory /workspace/3.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/3.alert_handler_random_classes.759727984
Short name T629
Test name
Test status
Simulation time 1630808766 ps
CPU time 38.84 seconds
Started Feb 25 03:19:57 PM PST 24
Finished Feb 25 03:20:36 PM PST 24
Peak memory 246532 kb
Host smart-6aedd04f-208a-484f-9d2a-885d5a74374d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75972
7984 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_classes.759727984
Directory /workspace/3.alert_handler_random_classes/latest

Test location /workspace/coverage/default/3.alert_handler_sec_cm.1728272460
Short name T13
Test name
Test status
Simulation time 1764826557 ps
CPU time 27.3 seconds
Started Feb 25 03:20:14 PM PST 24
Finished Feb 25 03:20:43 PM PST 24
Peak memory 269280 kb
Host smart-d9322d85-4db5-47da-a2ab-61d1f7a471c5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1728272460 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sec_cm.1728272460
Directory /workspace/3.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/3.alert_handler_smoke.3718688373
Short name T603
Test name
Test status
Simulation time 7284152277 ps
CPU time 28.16 seconds
Started Feb 25 03:20:17 PM PST 24
Finished Feb 25 03:20:45 PM PST 24
Peak memory 248288 kb
Host smart-220022ba-0733-4e03-9afb-098df0ae9982
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37186
88373 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_smoke.3718688373
Directory /workspace/3.alert_handler_smoke/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all.928496893
Short name T661
Test name
Test status
Simulation time 40423423 ps
CPU time 4.99 seconds
Started Feb 25 03:20:07 PM PST 24
Finished Feb 25 03:20:12 PM PST 24
Peak memory 248212 kb
Host smart-ee0863d7-f27f-4a79-89d3-d928e0f7aeef
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928496893 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_hand
ler_stress_all.928496893
Directory /workspace/3.alert_handler_stress_all/latest

Test location /workspace/coverage/default/30.alert_handler_entropy.4037276002
Short name T628
Test name
Test status
Simulation time 115479505285 ps
CPU time 1308.97 seconds
Started Feb 25 03:21:21 PM PST 24
Finished Feb 25 03:43:11 PM PST 24
Peak memory 281072 kb
Host smart-d2ca8388-7ee2-4848-b51e-690118870254
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037276002 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_entropy.4037276002
Directory /workspace/30.alert_handler_entropy/latest

Test location /workspace/coverage/default/30.alert_handler_esc_alert_accum.2833050341
Short name T269
Test name
Test status
Simulation time 6989132216 ps
CPU time 53.2 seconds
Started Feb 25 03:21:22 PM PST 24
Finished Feb 25 03:22:15 PM PST 24
Peak memory 255348 kb
Host smart-3a93396f-9495-4be3-9be6-96adc3dad084
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28330
50341 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_alert_accum.2833050341
Directory /workspace/30.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/30.alert_handler_esc_intr_timeout.3121136448
Short name T506
Test name
Test status
Simulation time 1091929711 ps
CPU time 41.05 seconds
Started Feb 25 03:21:18 PM PST 24
Finished Feb 25 03:21:59 PM PST 24
Peak memory 254532 kb
Host smart-2dc5ae35-304b-48b6-b210-8a09d0a9777d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31211
36448 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_intr_timeout.3121136448
Directory /workspace/30.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_lpg_stub_clk.1755035343
Short name T709
Test name
Test status
Simulation time 33322913566 ps
CPU time 1433.06 seconds
Started Feb 25 03:21:23 PM PST 24
Finished Feb 25 03:45:17 PM PST 24
Peak memory 286680 kb
Host smart-8d7a8d5b-b216-40a1-bad7-3fbefa56dcf5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1755035343 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg_stub_clk.1755035343
Directory /workspace/30.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/30.alert_handler_ping_timeout.599856480
Short name T313
Test name
Test status
Simulation time 10820495921 ps
CPU time 115.22 seconds
Started Feb 25 03:21:20 PM PST 24
Finished Feb 25 03:23:16 PM PST 24
Peak memory 246968 kb
Host smart-c4358f24-3f23-4913-8c77-c7008b303f71
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599856480 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_ping_timeout.599856480
Directory /workspace/30.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_random_alerts.4276663356
Short name T601
Test name
Test status
Simulation time 1567270812 ps
CPU time 35.87 seconds
Started Feb 25 03:21:13 PM PST 24
Finished Feb 25 03:21:50 PM PST 24
Peak memory 255152 kb
Host smart-bc9fd913-6277-4d6c-93c6-89e0ba805b36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42766
63356 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_alerts.4276663356
Directory /workspace/30.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/30.alert_handler_random_classes.2089110170
Short name T224
Test name
Test status
Simulation time 1113470345 ps
CPU time 79.52 seconds
Started Feb 25 03:21:18 PM PST 24
Finished Feb 25 03:22:38 PM PST 24
Peak memory 254664 kb
Host smart-d177c25a-421c-462f-83a0-0d07e1caf432
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20891
10170 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_classes.2089110170
Directory /workspace/30.alert_handler_random_classes/latest

Test location /workspace/coverage/default/30.alert_handler_sig_int_fail.2968337883
Short name T490
Test name
Test status
Simulation time 188607405 ps
CPU time 24.43 seconds
Started Feb 25 03:21:24 PM PST 24
Finished Feb 25 03:21:49 PM PST 24
Peak memory 254676 kb
Host smart-c60fbdd4-ac88-42d3-900c-13510cc7ba4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29683
37883 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_sig_int_fail.2968337883
Directory /workspace/30.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/30.alert_handler_smoke.2379479962
Short name T519
Test name
Test status
Simulation time 331412456 ps
CPU time 30.1 seconds
Started Feb 25 03:21:17 PM PST 24
Finished Feb 25 03:21:47 PM PST 24
Peak memory 248232 kb
Host smart-5f9795a4-ea4c-401f-8e68-be4ac0588eff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23794
79962 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_smoke.2379479962
Directory /workspace/30.alert_handler_smoke/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all.351431284
Short name T100
Test name
Test status
Simulation time 14883103409 ps
CPU time 1280.69 seconds
Started Feb 25 03:21:20 PM PST 24
Finished Feb 25 03:42:42 PM PST 24
Peak memory 288912 kb
Host smart-f9bb9d24-15b9-4126-96f6-c9b7ecd83c76
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351431284 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_han
dler_stress_all.351431284
Directory /workspace/30.alert_handler_stress_all/latest

Test location /workspace/coverage/default/31.alert_handler_entropy.2139599439
Short name T2
Test name
Test status
Simulation time 18638819715 ps
CPU time 1128.49 seconds
Started Feb 25 03:21:22 PM PST 24
Finished Feb 25 03:40:11 PM PST 24
Peak memory 272740 kb
Host smart-efecbb03-31c4-474f-9982-9b5b97a1a90b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2139599439 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_entropy.2139599439
Directory /workspace/31.alert_handler_entropy/latest

Test location /workspace/coverage/default/31.alert_handler_esc_alert_accum.2335002891
Short name T399
Test name
Test status
Simulation time 2398246907 ps
CPU time 180.33 seconds
Started Feb 25 03:21:23 PM PST 24
Finished Feb 25 03:24:23 PM PST 24
Peak memory 255580 kb
Host smart-16e4fcb7-af23-4466-81d1-2e915d78bf08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23350
02891 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_alert_accum.2335002891
Directory /workspace/31.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/31.alert_handler_esc_intr_timeout.3659927608
Short name T600
Test name
Test status
Simulation time 959059479 ps
CPU time 34.06 seconds
Started Feb 25 03:21:23 PM PST 24
Finished Feb 25 03:21:57 PM PST 24
Peak memory 254640 kb
Host smart-fa68e3d0-aece-43f0-a453-5261f9a5da9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36599
27608 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_intr_timeout.3659927608
Directory /workspace/31.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_lpg.1660878857
Short name T591
Test name
Test status
Simulation time 24582646362 ps
CPU time 1530.47 seconds
Started Feb 25 03:21:22 PM PST 24
Finished Feb 25 03:46:53 PM PST 24
Peak memory 272224 kb
Host smart-2632193a-25a5-4261-81ad-97f451ddd8cb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660878857 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg.1660878857
Directory /workspace/31.alert_handler_lpg/latest

Test location /workspace/coverage/default/31.alert_handler_lpg_stub_clk.3864394351
Short name T425
Test name
Test status
Simulation time 190390192232 ps
CPU time 1344.77 seconds
Started Feb 25 03:21:33 PM PST 24
Finished Feb 25 03:43:58 PM PST 24
Peak memory 264712 kb
Host smart-25407ee7-9698-4208-80f3-f55345ef14e6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3864394351 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg_stub_clk.3864394351
Directory /workspace/31.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/31.alert_handler_ping_timeout.4094973656
Short name T317
Test name
Test status
Simulation time 13619664315 ps
CPU time 244.43 seconds
Started Feb 25 03:21:20 PM PST 24
Finished Feb 25 03:25:25 PM PST 24
Peak memory 246160 kb
Host smart-ee1e1e8b-3730-4b66-9ff7-3cd21a7e383e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094973656 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_ping_timeout.4094973656
Directory /workspace/31.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_random_alerts.2765791555
Short name T717
Test name
Test status
Simulation time 48721498 ps
CPU time 4.65 seconds
Started Feb 25 03:21:28 PM PST 24
Finished Feb 25 03:21:33 PM PST 24
Peak memory 240048 kb
Host smart-cb46d51d-1f91-4cbc-bb30-c4ad6cdcfe2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27657
91555 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_alerts.2765791555
Directory /workspace/31.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/31.alert_handler_random_classes.957333825
Short name T518
Test name
Test status
Simulation time 3256287236 ps
CPU time 22.07 seconds
Started Feb 25 03:21:20 PM PST 24
Finished Feb 25 03:21:43 PM PST 24
Peak memory 246992 kb
Host smart-f5ce8686-99db-43de-91c5-ba43b70508d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95733
3825 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_classes.957333825
Directory /workspace/31.alert_handler_random_classes/latest

Test location /workspace/coverage/default/31.alert_handler_sig_int_fail.4043040858
Short name T556
Test name
Test status
Simulation time 136270756 ps
CPU time 10.53 seconds
Started Feb 25 03:21:23 PM PST 24
Finished Feb 25 03:21:33 PM PST 24
Peak memory 253076 kb
Host smart-2867f17f-0db2-4e40-9139-f1a03185badd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40430
40858 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_sig_int_fail.4043040858
Directory /workspace/31.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/31.alert_handler_smoke.4189048037
Short name T426
Test name
Test status
Simulation time 1164549169 ps
CPU time 26.38 seconds
Started Feb 25 03:21:30 PM PST 24
Finished Feb 25 03:21:57 PM PST 24
Peak memory 248236 kb
Host smart-d32555c4-0d84-459e-8245-b65a9c1cb294
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41890
48037 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_smoke.4189048037
Directory /workspace/31.alert_handler_smoke/latest

Test location /workspace/coverage/default/32.alert_handler_entropy.1408376228
Short name T71
Test name
Test status
Simulation time 40605658581 ps
CPU time 2482.58 seconds
Started Feb 25 03:21:35 PM PST 24
Finished Feb 25 04:02:58 PM PST 24
Peak memory 288500 kb
Host smart-46a43c22-c4f7-4663-b349-8396c3373ece
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408376228 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_entropy.1408376228
Directory /workspace/32.alert_handler_entropy/latest

Test location /workspace/coverage/default/32.alert_handler_esc_alert_accum.192990887
Short name T441
Test name
Test status
Simulation time 5140328030 ps
CPU time 275.69 seconds
Started Feb 25 03:21:22 PM PST 24
Finished Feb 25 03:25:58 PM PST 24
Peak memory 250316 kb
Host smart-9649e545-3832-4c5f-bb34-ee39f742d2b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19299
0887 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_alert_accum.192990887
Directory /workspace/32.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/32.alert_handler_esc_intr_timeout.4282465904
Short name T369
Test name
Test status
Simulation time 2151615562 ps
CPU time 29.73 seconds
Started Feb 25 03:21:21 PM PST 24
Finished Feb 25 03:21:51 PM PST 24
Peak memory 254796 kb
Host smart-0d756eca-869b-4880-8b88-79652e7688cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42824
65904 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_intr_timeout.4282465904
Directory /workspace/32.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_lpg.2549230427
Short name T328
Test name
Test status
Simulation time 772983227784 ps
CPU time 3146.21 seconds
Started Feb 25 03:21:35 PM PST 24
Finished Feb 25 04:14:02 PM PST 24
Peak memory 289052 kb
Host smart-a0fe07ba-88ce-4fd2-a78e-5733e76c86d2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2549230427 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg.2549230427
Directory /workspace/32.alert_handler_lpg/latest

Test location /workspace/coverage/default/32.alert_handler_lpg_stub_clk.3992585189
Short name T575
Test name
Test status
Simulation time 5332439041 ps
CPU time 629.82 seconds
Started Feb 25 03:21:30 PM PST 24
Finished Feb 25 03:32:01 PM PST 24
Peak memory 264296 kb
Host smart-edac637d-7b00-4125-9970-dc7c65ea4c9e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992585189 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg_stub_clk.3992585189
Directory /workspace/32.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/32.alert_handler_ping_timeout.3164624645
Short name T539
Test name
Test status
Simulation time 47013741847 ps
CPU time 466.71 seconds
Started Feb 25 03:21:31 PM PST 24
Finished Feb 25 03:29:18 PM PST 24
Peak memory 247144 kb
Host smart-2338cd3f-eda5-4284-b5be-db1a829e85ab
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164624645 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_ping_timeout.3164624645
Directory /workspace/32.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_random_alerts.1854090786
Short name T522
Test name
Test status
Simulation time 753084810 ps
CPU time 17.28 seconds
Started Feb 25 03:21:23 PM PST 24
Finished Feb 25 03:21:41 PM PST 24
Peak memory 248248 kb
Host smart-12b53595-854a-409b-b619-d999338bf592
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18540
90786 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_alerts.1854090786
Directory /workspace/32.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/32.alert_handler_random_classes.4136803868
Short name T508
Test name
Test status
Simulation time 1473939005 ps
CPU time 33.99 seconds
Started Feb 25 03:21:29 PM PST 24
Finished Feb 25 03:22:03 PM PST 24
Peak memory 254008 kb
Host smart-b624aa0d-5000-4c58-b061-55ceafed7ba2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41368
03868 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_classes.4136803868
Directory /workspace/32.alert_handler_random_classes/latest

Test location /workspace/coverage/default/32.alert_handler_sig_int_fail.1659246505
Short name T644
Test name
Test status
Simulation time 58684026 ps
CPU time 5.21 seconds
Started Feb 25 03:21:31 PM PST 24
Finished Feb 25 03:21:36 PM PST 24
Peak memory 238176 kb
Host smart-01a6ac62-99cf-4a05-b10f-5e5ac911e4d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16592
46505 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_sig_int_fail.1659246505
Directory /workspace/32.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/32.alert_handler_smoke.1656106324
Short name T545
Test name
Test status
Simulation time 512236995 ps
CPU time 10.84 seconds
Started Feb 25 03:21:24 PM PST 24
Finished Feb 25 03:21:36 PM PST 24
Peak memory 253920 kb
Host smart-f9c20528-1d27-4ba8-8767-6ad291c033be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16561
06324 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_smoke.1656106324
Directory /workspace/32.alert_handler_smoke/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all.1003427688
Short name T58
Test name
Test status
Simulation time 24271242221 ps
CPU time 1277.1 seconds
Started Feb 25 03:21:33 PM PST 24
Finished Feb 25 03:42:51 PM PST 24
Peak memory 288816 kb
Host smart-115e4b93-e58e-4321-bd3e-6ea0905d378f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003427688 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_ha
ndler_stress_all.1003427688
Directory /workspace/32.alert_handler_stress_all/latest

Test location /workspace/coverage/default/33.alert_handler_entropy.1426319252
Short name T410
Test name
Test status
Simulation time 176170963718 ps
CPU time 2290.69 seconds
Started Feb 25 03:21:29 PM PST 24
Finished Feb 25 03:59:40 PM PST 24
Peak memory 283588 kb
Host smart-d4be0ed4-f777-4efe-ba4e-6647c2634ce8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426319252 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_entropy.1426319252
Directory /workspace/33.alert_handler_entropy/latest

Test location /workspace/coverage/default/33.alert_handler_esc_alert_accum.305173789
Short name T77
Test name
Test status
Simulation time 1611284764 ps
CPU time 31.93 seconds
Started Feb 25 03:21:30 PM PST 24
Finished Feb 25 03:22:02 PM PST 24
Peak memory 255088 kb
Host smart-27aa0922-52f2-47e7-adb8-eae085937912
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30517
3789 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_alert_accum.305173789
Directory /workspace/33.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/33.alert_handler_esc_intr_timeout.2462030629
Short name T658
Test name
Test status
Simulation time 834547229 ps
CPU time 22.02 seconds
Started Feb 25 03:21:32 PM PST 24
Finished Feb 25 03:21:54 PM PST 24
Peak memory 253884 kb
Host smart-dcc7b495-0139-40a8-853b-5bf883c93160
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24620
30629 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_intr_timeout.2462030629
Directory /workspace/33.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_lpg.125144661
Short name T326
Test name
Test status
Simulation time 20467766289 ps
CPU time 1556.12 seconds
Started Feb 25 03:21:32 PM PST 24
Finished Feb 25 03:47:28 PM PST 24
Peak memory 287040 kb
Host smart-633d0b87-e0f5-4710-8649-23717b6c66d9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=125144661 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg.125144661
Directory /workspace/33.alert_handler_lpg/latest

Test location /workspace/coverage/default/33.alert_handler_lpg_stub_clk.3449704566
Short name T621
Test name
Test status
Simulation time 23896926597 ps
CPU time 1052.32 seconds
Started Feb 25 03:21:35 PM PST 24
Finished Feb 25 03:39:08 PM PST 24
Peak memory 270808 kb
Host smart-58677b84-3831-4a15-ad64-09c9c1be45c5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449704566 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg_stub_clk.3449704566
Directory /workspace/33.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/33.alert_handler_ping_timeout.2596653321
Short name T715
Test name
Test status
Simulation time 27059618880 ps
CPU time 280.29 seconds
Started Feb 25 03:21:35 PM PST 24
Finished Feb 25 03:26:16 PM PST 24
Peak memory 248188 kb
Host smart-e9d9cd93-0cd1-4564-9f37-5e47e1a55665
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596653321 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_ping_timeout.2596653321
Directory /workspace/33.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_random_alerts.1457638557
Short name T390
Test name
Test status
Simulation time 722731404 ps
CPU time 34.27 seconds
Started Feb 25 03:21:35 PM PST 24
Finished Feb 25 03:22:10 PM PST 24
Peak memory 256324 kb
Host smart-51528ac2-97d1-4e54-8fcc-3824f727a3f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14576
38557 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_alerts.1457638557
Directory /workspace/33.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/33.alert_handler_random_classes.3209199369
Short name T43
Test name
Test status
Simulation time 449861095 ps
CPU time 33.57 seconds
Started Feb 25 03:21:30 PM PST 24
Finished Feb 25 03:22:04 PM PST 24
Peak memory 254968 kb
Host smart-46cd15d7-1624-4ff1-86ba-3b4588907ecc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32091
99369 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_classes.3209199369
Directory /workspace/33.alert_handler_random_classes/latest

Test location /workspace/coverage/default/33.alert_handler_sig_int_fail.888880090
Short name T249
Test name
Test status
Simulation time 190739997 ps
CPU time 6.32 seconds
Started Feb 25 03:21:31 PM PST 24
Finished Feb 25 03:21:37 PM PST 24
Peak memory 252216 kb
Host smart-00dac778-6c0d-41a5-9f90-a81c0c33c625
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88888
0090 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_sig_int_fail.888880090
Directory /workspace/33.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/33.alert_handler_smoke.2148510847
Short name T673
Test name
Test status
Simulation time 28237919 ps
CPU time 4.82 seconds
Started Feb 25 03:21:32 PM PST 24
Finished Feb 25 03:21:37 PM PST 24
Peak memory 240040 kb
Host smart-536d6f0c-61dc-4165-b464-96b8d525763b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21485
10847 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_smoke.2148510847
Directory /workspace/33.alert_handler_smoke/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all.642769840
Short name T92
Test name
Test status
Simulation time 434006769941 ps
CPU time 1819.75 seconds
Started Feb 25 03:21:33 PM PST 24
Finished Feb 25 03:51:53 PM PST 24
Peak memory 281072 kb
Host smart-cce5977b-54b2-44b4-a0c1-78fb930a6cae
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642769840 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_han
dler_stress_all.642769840
Directory /workspace/33.alert_handler_stress_all/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all_with_rand_reset.3498461620
Short name T187
Test name
Test status
Simulation time 19412179444 ps
CPU time 1324 seconds
Started Feb 25 03:21:31 PM PST 24
Finished Feb 25 03:43:36 PM PST 24
Peak memory 272484 kb
Host smart-773cca3c-e2f4-4e00-a881-6a87af42da98
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498461620 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 33.alert_handler_stress_all_with_rand_reset.3498461620
Directory /workspace/33.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.alert_handler_entropy.3167716886
Short name T279
Test name
Test status
Simulation time 130088878049 ps
CPU time 2321.42 seconds
Started Feb 25 03:21:34 PM PST 24
Finished Feb 25 04:00:15 PM PST 24
Peak memory 284000 kb
Host smart-a053b098-acaf-40b7-8c3f-f0b9128d5ea1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3167716886 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_entropy.3167716886
Directory /workspace/34.alert_handler_entropy/latest

Test location /workspace/coverage/default/34.alert_handler_esc_alert_accum.1616343751
Short name T558
Test name
Test status
Simulation time 3599070405 ps
CPU time 93.76 seconds
Started Feb 25 03:21:30 PM PST 24
Finished Feb 25 03:23:04 PM PST 24
Peak memory 256448 kb
Host smart-c64c54fc-a106-4934-a78e-47749a01d7cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16163
43751 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_alert_accum.1616343751
Directory /workspace/34.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/34.alert_handler_esc_intr_timeout.3135285741
Short name T674
Test name
Test status
Simulation time 524510450 ps
CPU time 39.13 seconds
Started Feb 25 03:21:31 PM PST 24
Finished Feb 25 03:22:10 PM PST 24
Peak memory 254544 kb
Host smart-14158533-c92a-4f23-b074-dcc20dd95f5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31352
85741 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_intr_timeout.3135285741
Directory /workspace/34.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_lpg.2058506033
Short name T609
Test name
Test status
Simulation time 42948216959 ps
CPU time 1383.02 seconds
Started Feb 25 03:21:30 PM PST 24
Finished Feb 25 03:44:33 PM PST 24
Peak memory 264660 kb
Host smart-49a175ed-6b32-49eb-9c82-d302b2abe482
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058506033 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg.2058506033
Directory /workspace/34.alert_handler_lpg/latest

Test location /workspace/coverage/default/34.alert_handler_lpg_stub_clk.722953887
Short name T561
Test name
Test status
Simulation time 11781730391 ps
CPU time 944.43 seconds
Started Feb 25 03:21:31 PM PST 24
Finished Feb 25 03:37:16 PM PST 24
Peak memory 270848 kb
Host smart-c210dcc1-3d4c-4053-ba11-2de879194248
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722953887 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg_stub_clk.722953887
Directory /workspace/34.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/34.alert_handler_ping_timeout.899944929
Short name T300
Test name
Test status
Simulation time 8025526461 ps
CPU time 83.78 seconds
Started Feb 25 03:21:36 PM PST 24
Finished Feb 25 03:23:00 PM PST 24
Peak memory 246940 kb
Host smart-485b4492-0b6d-48ea-a92c-7ffe291b0ee7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899944929 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_ping_timeout.899944929
Directory /workspace/34.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_random_alerts.3622676985
Short name T102
Test name
Test status
Simulation time 401429022 ps
CPU time 31.74 seconds
Started Feb 25 03:21:36 PM PST 24
Finished Feb 25 03:22:08 PM PST 24
Peak memory 248076 kb
Host smart-cca37444-6aaf-4dcc-a4b9-74fc6a8c36ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36226
76985 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_alerts.3622676985
Directory /workspace/34.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/34.alert_handler_random_classes.1132492786
Short name T442
Test name
Test status
Simulation time 595490077 ps
CPU time 21.54 seconds
Started Feb 25 03:21:34 PM PST 24
Finished Feb 25 03:21:55 PM PST 24
Peak memory 253796 kb
Host smart-ab8ba811-d17c-4edb-b529-006fec6d3012
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11324
92786 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_classes.1132492786
Directory /workspace/34.alert_handler_random_classes/latest

Test location /workspace/coverage/default/34.alert_handler_sig_int_fail.3527938808
Short name T386
Test name
Test status
Simulation time 185130270 ps
CPU time 13.72 seconds
Started Feb 25 03:21:29 PM PST 24
Finished Feb 25 03:21:43 PM PST 24
Peak memory 248224 kb
Host smart-70e9cbb6-6632-4ab7-a49e-0d0433572847
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35279
38808 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_sig_int_fail.3527938808
Directory /workspace/34.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/34.alert_handler_smoke.504288508
Short name T389
Test name
Test status
Simulation time 1111285396 ps
CPU time 31.74 seconds
Started Feb 25 03:21:30 PM PST 24
Finished Feb 25 03:22:02 PM PST 24
Peak memory 256400 kb
Host smart-10c9077e-57a0-482a-bb5c-972e92198574
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50428
8508 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_smoke.504288508
Directory /workspace/34.alert_handler_smoke/latest

Test location /workspace/coverage/default/35.alert_handler_entropy.1499522299
Short name T89
Test name
Test status
Simulation time 75882940522 ps
CPU time 1635.25 seconds
Started Feb 25 03:21:50 PM PST 24
Finished Feb 25 03:49:06 PM PST 24
Peak memory 288752 kb
Host smart-7b2e4509-68c4-49bf-bbde-8d9cb87302b1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1499522299 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_entropy.1499522299
Directory /workspace/35.alert_handler_entropy/latest

Test location /workspace/coverage/default/35.alert_handler_esc_alert_accum.2979585928
Short name T653
Test name
Test status
Simulation time 13392668481 ps
CPU time 186.5 seconds
Started Feb 25 03:21:30 PM PST 24
Finished Feb 25 03:24:37 PM PST 24
Peak memory 256088 kb
Host smart-8e7b048b-5be3-4fc7-8d0f-88b6f09f337d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29795
85928 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_alert_accum.2979585928
Directory /workspace/35.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/35.alert_handler_esc_intr_timeout.4111077645
Short name T608
Test name
Test status
Simulation time 2015332353 ps
CPU time 37.33 seconds
Started Feb 25 03:21:30 PM PST 24
Finished Feb 25 03:22:07 PM PST 24
Peak memory 254024 kb
Host smart-c4116dd0-e9f1-433d-918a-ecbe6d58f788
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41110
77645 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_intr_timeout.4111077645
Directory /workspace/35.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_lpg.703470405
Short name T324
Test name
Test status
Simulation time 18243304429 ps
CPU time 1446.31 seconds
Started Feb 25 03:21:59 PM PST 24
Finished Feb 25 03:46:06 PM PST 24
Peak memory 288544 kb
Host smart-c74b952a-d666-4772-b15b-95b83e3c3eca
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703470405 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg.703470405
Directory /workspace/35.alert_handler_lpg/latest

Test location /workspace/coverage/default/35.alert_handler_lpg_stub_clk.3081943995
Short name T110
Test name
Test status
Simulation time 156726360234 ps
CPU time 2278.71 seconds
Started Feb 25 03:22:00 PM PST 24
Finished Feb 25 03:59:59 PM PST 24
Peak memory 272888 kb
Host smart-619baa11-f03e-4964-aaa4-728e504fb8d2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081943995 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg_stub_clk.3081943995
Directory /workspace/35.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/35.alert_handler_ping_timeout.1534191381
Short name T302
Test name
Test status
Simulation time 14910128051 ps
CPU time 167.96 seconds
Started Feb 25 03:21:48 PM PST 24
Finished Feb 25 03:24:36 PM PST 24
Peak memory 246956 kb
Host smart-f3053f36-6cbf-4608-910b-6a09fad2c5a6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534191381 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_ping_timeout.1534191381
Directory /workspace/35.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_random_alerts.1507286702
Short name T20
Test name
Test status
Simulation time 2266728187 ps
CPU time 66.98 seconds
Started Feb 25 03:21:33 PM PST 24
Finished Feb 25 03:22:40 PM PST 24
Peak memory 255152 kb
Host smart-004504cf-f6a2-4f77-9ec8-4c466f9a03ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15072
86702 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_alerts.1507286702
Directory /workspace/35.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/35.alert_handler_random_classes.632246557
Short name T596
Test name
Test status
Simulation time 1089277845 ps
CPU time 26.29 seconds
Started Feb 25 03:21:36 PM PST 24
Finished Feb 25 03:22:02 PM PST 24
Peak memory 255560 kb
Host smart-af1bc261-6f3d-4a78-baa8-6c4b748d924b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63224
6557 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_classes.632246557
Directory /workspace/35.alert_handler_random_classes/latest

Test location /workspace/coverage/default/35.alert_handler_sig_int_fail.3974931317
Short name T79
Test name
Test status
Simulation time 386930985 ps
CPU time 28.96 seconds
Started Feb 25 03:21:31 PM PST 24
Finished Feb 25 03:22:00 PM PST 24
Peak memory 247128 kb
Host smart-546a3676-7d9f-4cac-b18c-8c454afb37ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39749
31317 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_sig_int_fail.3974931317
Directory /workspace/35.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/35.alert_handler_smoke.1705966752
Short name T418
Test name
Test status
Simulation time 522607310 ps
CPU time 34.63 seconds
Started Feb 25 03:21:31 PM PST 24
Finished Feb 25 03:22:06 PM PST 24
Peak memory 248220 kb
Host smart-a78ad39a-f065-483b-827e-ae58364e4f2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17059
66752 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_smoke.1705966752
Directory /workspace/35.alert_handler_smoke/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all.1004825650
Short name T38
Test name
Test status
Simulation time 37892623332 ps
CPU time 1633.34 seconds
Started Feb 25 03:21:59 PM PST 24
Finished Feb 25 03:49:12 PM PST 24
Peak memory 289204 kb
Host smart-1d07e6d2-39f9-43da-9c8f-66f80123b349
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004825650 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_ha
ndler_stress_all.1004825650
Directory /workspace/35.alert_handler_stress_all/latest

Test location /workspace/coverage/default/36.alert_handler_entropy.3114750965
Short name T48
Test name
Test status
Simulation time 63013459729 ps
CPU time 3568.59 seconds
Started Feb 25 03:21:50 PM PST 24
Finished Feb 25 04:21:19 PM PST 24
Peak memory 288880 kb
Host smart-ffc0847a-c3b2-4db1-9f02-e3b60d81d0c7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3114750965 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_entropy.3114750965
Directory /workspace/36.alert_handler_entropy/latest

Test location /workspace/coverage/default/36.alert_handler_esc_alert_accum.4267694496
Short name T564
Test name
Test status
Simulation time 7835639519 ps
CPU time 233.52 seconds
Started Feb 25 03:22:01 PM PST 24
Finished Feb 25 03:25:55 PM PST 24
Peak memory 255936 kb
Host smart-1ed753b2-4bdd-4f5b-84b2-ba2d61c5e120
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42676
94496 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_alert_accum.4267694496
Directory /workspace/36.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/36.alert_handler_esc_intr_timeout.2402587071
Short name T378
Test name
Test status
Simulation time 13133835929 ps
CPU time 51.22 seconds
Started Feb 25 03:21:49 PM PST 24
Finished Feb 25 03:22:40 PM PST 24
Peak memory 254768 kb
Host smart-a9992f5d-8586-45bd-be6b-8b92c163e2dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24025
87071 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_intr_timeout.2402587071
Directory /workspace/36.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_lpg.3907770985
Short name T330
Test name
Test status
Simulation time 12069380875 ps
CPU time 952.2 seconds
Started Feb 25 03:21:50 PM PST 24
Finished Feb 25 03:37:42 PM PST 24
Peak memory 272268 kb
Host smart-31a6aca2-bfbf-4c9a-933c-a990112adcea
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907770985 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg.3907770985
Directory /workspace/36.alert_handler_lpg/latest

Test location /workspace/coverage/default/36.alert_handler_lpg_stub_clk.2334067014
Short name T559
Test name
Test status
Simulation time 245267394408 ps
CPU time 2577.68 seconds
Started Feb 25 03:21:48 PM PST 24
Finished Feb 25 04:04:46 PM PST 24
Peak memory 282636 kb
Host smart-f8963c3e-f9ef-41b7-88e6-186911ac4a79
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334067014 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg_stub_clk.2334067014
Directory /workspace/36.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/36.alert_handler_ping_timeout.583921075
Short name T320
Test name
Test status
Simulation time 8985031525 ps
CPU time 396.04 seconds
Started Feb 25 03:21:58 PM PST 24
Finished Feb 25 03:28:34 PM PST 24
Peak memory 247208 kb
Host smart-a31503fc-5841-40c2-993d-5a73a496069f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583921075 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_ping_timeout.583921075
Directory /workspace/36.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_random_alerts.187195718
Short name T264
Test name
Test status
Simulation time 339754649 ps
CPU time 31.3 seconds
Started Feb 25 03:21:48 PM PST 24
Finished Feb 25 03:22:20 PM PST 24
Peak memory 248228 kb
Host smart-0e4b8994-cef7-4856-9dc7-a85985e0a1fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18719
5718 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_alerts.187195718
Directory /workspace/36.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/36.alert_handler_random_classes.3877653368
Short name T642
Test name
Test status
Simulation time 1210098520 ps
CPU time 69.78 seconds
Started Feb 25 03:21:49 PM PST 24
Finished Feb 25 03:22:58 PM PST 24
Peak memory 247828 kb
Host smart-4109da6b-499b-4b07-b46e-9cbc61a84dd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38776
53368 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_classes.3877653368
Directory /workspace/36.alert_handler_random_classes/latest

Test location /workspace/coverage/default/36.alert_handler_sig_int_fail.2290510283
Short name T491
Test name
Test status
Simulation time 799556881 ps
CPU time 24.47 seconds
Started Feb 25 03:21:48 PM PST 24
Finished Feb 25 03:22:12 PM PST 24
Peak memory 246656 kb
Host smart-cb61cbd5-8d55-4046-a762-c1dddde0b6fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22905
10283 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_sig_int_fail.2290510283
Directory /workspace/36.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/36.alert_handler_smoke.2307393435
Short name T469
Test name
Test status
Simulation time 168533424 ps
CPU time 4.85 seconds
Started Feb 25 03:21:53 PM PST 24
Finished Feb 25 03:21:57 PM PST 24
Peak memory 240040 kb
Host smart-e38080a6-5606-4a29-a521-279244d89e77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23073
93435 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_smoke.2307393435
Directory /workspace/36.alert_handler_smoke/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all.1742478838
Short name T693
Test name
Test status
Simulation time 97799341649 ps
CPU time 2890.07 seconds
Started Feb 25 03:21:58 PM PST 24
Finished Feb 25 04:10:09 PM PST 24
Peak memory 286932 kb
Host smart-4b41fdcb-0e7b-4bd7-8fbd-8441ac6e3af6
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742478838 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_ha
ndler_stress_all.1742478838
Directory /workspace/36.alert_handler_stress_all/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all_with_rand_reset.2810892355
Short name T116
Test name
Test status
Simulation time 60703862842 ps
CPU time 5113.83 seconds
Started Feb 25 03:22:02 PM PST 24
Finished Feb 25 04:47:17 PM PST 24
Peak memory 321856 kb
Host smart-67b9ea24-7870-490d-aebd-8bf03fd522b3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810892355 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 36.alert_handler_stress_all_with_rand_reset.2810892355
Directory /workspace/36.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.alert_handler_entropy.2966223993
Short name T366
Test name
Test status
Simulation time 98293687090 ps
CPU time 1264.48 seconds
Started Feb 25 03:21:49 PM PST 24
Finished Feb 25 03:42:54 PM PST 24
Peak memory 271884 kb
Host smart-a163357a-ec3a-4ef7-9cfd-ab067ac34387
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2966223993 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_entropy.2966223993
Directory /workspace/37.alert_handler_entropy/latest

Test location /workspace/coverage/default/37.alert_handler_esc_alert_accum.250558183
Short name T477
Test name
Test status
Simulation time 1877290763 ps
CPU time 99.27 seconds
Started Feb 25 03:22:01 PM PST 24
Finished Feb 25 03:23:40 PM PST 24
Peak memory 255864 kb
Host smart-5f04f96a-9b8f-4e20-aa11-25d30093559c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25055
8183 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_alert_accum.250558183
Directory /workspace/37.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/37.alert_handler_esc_intr_timeout.4149305399
Short name T536
Test name
Test status
Simulation time 837285205 ps
CPU time 29.75 seconds
Started Feb 25 03:21:50 PM PST 24
Finished Feb 25 03:22:20 PM PST 24
Peak memory 253020 kb
Host smart-e7ec3098-90c3-4e01-ba75-b58d067a7484
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41493
05399 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_intr_timeout.4149305399
Directory /workspace/37.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_lpg.2651501983
Short name T332
Test name
Test status
Simulation time 118052633931 ps
CPU time 1739.38 seconds
Started Feb 25 03:21:49 PM PST 24
Finished Feb 25 03:50:49 PM PST 24
Peak memory 272624 kb
Host smart-3dba6e16-1b62-4302-ac0a-2e799f80e303
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651501983 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg.2651501983
Directory /workspace/37.alert_handler_lpg/latest

Test location /workspace/coverage/default/37.alert_handler_lpg_stub_clk.3491420891
Short name T472
Test name
Test status
Simulation time 65766238718 ps
CPU time 1920.65 seconds
Started Feb 25 03:21:48 PM PST 24
Finished Feb 25 03:53:49 PM PST 24
Peak memory 286052 kb
Host smart-17e529ca-0724-4a3a-821c-86c92be698f7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3491420891 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg_stub_clk.3491420891
Directory /workspace/37.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/37.alert_handler_ping_timeout.1125951361
Short name T607
Test name
Test status
Simulation time 41040588476 ps
CPU time 450.44 seconds
Started Feb 25 03:22:03 PM PST 24
Finished Feb 25 03:29:34 PM PST 24
Peak memory 246976 kb
Host smart-b0a0b1e8-8130-4867-a48f-382b666df335
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125951361 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_ping_timeout.1125951361
Directory /workspace/37.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_random_alerts.2131527313
Short name T30
Test name
Test status
Simulation time 407416962 ps
CPU time 36.42 seconds
Started Feb 25 03:21:51 PM PST 24
Finished Feb 25 03:22:27 PM PST 24
Peak memory 248228 kb
Host smart-44c691fe-be61-41c9-9524-94ad79113220
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21315
27313 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_alerts.2131527313
Directory /workspace/37.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/37.alert_handler_sig_int_fail.4023700855
Short name T50
Test name
Test status
Simulation time 245347000 ps
CPU time 30.09 seconds
Started Feb 25 03:21:53 PM PST 24
Finished Feb 25 03:22:23 PM PST 24
Peak memory 246380 kb
Host smart-c6e7e552-dfa8-46bd-978d-72b9b56ae72a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40237
00855 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_sig_int_fail.4023700855
Directory /workspace/37.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/37.alert_handler_smoke.3411152540
Short name T403
Test name
Test status
Simulation time 156920909 ps
CPU time 8.87 seconds
Started Feb 25 03:21:50 PM PST 24
Finished Feb 25 03:21:59 PM PST 24
Peak memory 256404 kb
Host smart-5c4b2b96-56a8-4367-af4e-be01b8277f96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34111
52540 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_smoke.3411152540
Directory /workspace/37.alert_handler_smoke/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all.1565322234
Short name T444
Test name
Test status
Simulation time 9499001193 ps
CPU time 295.21 seconds
Started Feb 25 03:21:56 PM PST 24
Finished Feb 25 03:26:51 PM PST 24
Peak memory 256492 kb
Host smart-4cd8c622-be56-428f-bd78-6df4a0aa73fb
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565322234 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_ha
ndler_stress_all.1565322234
Directory /workspace/37.alert_handler_stress_all/latest

Test location /workspace/coverage/default/38.alert_handler_entropy.3286792229
Short name T294
Test name
Test status
Simulation time 52449888813 ps
CPU time 1841.17 seconds
Started Feb 25 03:22:03 PM PST 24
Finished Feb 25 03:52:45 PM PST 24
Peak memory 281064 kb
Host smart-9748594a-95f5-4d5a-a32e-853b4212606a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286792229 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_entropy.3286792229
Directory /workspace/38.alert_handler_entropy/latest

Test location /workspace/coverage/default/38.alert_handler_esc_alert_accum.3901827026
Short name T680
Test name
Test status
Simulation time 563814364 ps
CPU time 30.53 seconds
Started Feb 25 03:22:02 PM PST 24
Finished Feb 25 03:22:33 PM PST 24
Peak memory 255704 kb
Host smart-fd488a43-d525-4ac3-a99b-ca52d4d863b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39018
27026 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_alert_accum.3901827026
Directory /workspace/38.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/38.alert_handler_esc_intr_timeout.305342414
Short name T700
Test name
Test status
Simulation time 278688462 ps
CPU time 25.18 seconds
Started Feb 25 03:22:07 PM PST 24
Finished Feb 25 03:22:32 PM PST 24
Peak memory 253960 kb
Host smart-e0b21269-b364-4e7c-bd28-865913665e32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30534
2414 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_intr_timeout.305342414
Directory /workspace/38.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_lpg_stub_clk.2276773162
Short name T507
Test name
Test status
Simulation time 38915465702 ps
CPU time 2327.11 seconds
Started Feb 25 03:22:04 PM PST 24
Finished Feb 25 04:00:52 PM PST 24
Peak memory 288724 kb
Host smart-3172e6ce-4bdf-4583-8d6a-b3b7a0237db3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276773162 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg_stub_clk.2276773162
Directory /workspace/38.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/38.alert_handler_random_alerts.2012344548
Short name T428
Test name
Test status
Simulation time 968596345 ps
CPU time 52.66 seconds
Started Feb 25 03:21:57 PM PST 24
Finished Feb 25 03:22:50 PM PST 24
Peak memory 255140 kb
Host smart-b77e2880-0bd5-4b8a-88f3-09bb8e389ab3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20123
44548 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_alerts.2012344548
Directory /workspace/38.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/38.alert_handler_random_classes.1832479329
Short name T274
Test name
Test status
Simulation time 2616235835 ps
CPU time 41.43 seconds
Started Feb 25 03:21:59 PM PST 24
Finished Feb 25 03:22:40 PM PST 24
Peak memory 254764 kb
Host smart-8f6d28f5-0368-4d6c-b145-fbe609c8850f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18324
79329 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_classes.1832479329
Directory /workspace/38.alert_handler_random_classes/latest

Test location /workspace/coverage/default/38.alert_handler_sig_int_fail.3689793633
Short name T281
Test name
Test status
Simulation time 723195253 ps
CPU time 44.99 seconds
Started Feb 25 03:22:06 PM PST 24
Finished Feb 25 03:22:51 PM PST 24
Peak memory 246688 kb
Host smart-c8992342-3f75-4daf-b6d3-f3394057bd13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36897
93633 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_sig_int_fail.3689793633
Directory /workspace/38.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/38.alert_handler_smoke.1839375351
Short name T540
Test name
Test status
Simulation time 960035081 ps
CPU time 47.84 seconds
Started Feb 25 03:21:57 PM PST 24
Finished Feb 25 03:22:45 PM PST 24
Peak memory 255044 kb
Host smart-280a8283-f78c-4f6b-bddc-7ee0208f6532
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18393
75351 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_smoke.1839375351
Directory /workspace/38.alert_handler_smoke/latest

Test location /workspace/coverage/default/39.alert_handler_entropy.148927691
Short name T579
Test name
Test status
Simulation time 38983276251 ps
CPU time 1093.73 seconds
Started Feb 25 03:22:03 PM PST 24
Finished Feb 25 03:40:17 PM PST 24
Peak memory 272660 kb
Host smart-f8840bc1-36b2-45db-83c5-b00ca31ebab5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148927691 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_entropy.148927691
Directory /workspace/39.alert_handler_entropy/latest

Test location /workspace/coverage/default/39.alert_handler_esc_alert_accum.931257406
Short name T660
Test name
Test status
Simulation time 31197481592 ps
CPU time 124.29 seconds
Started Feb 25 03:21:59 PM PST 24
Finished Feb 25 03:24:03 PM PST 24
Peak memory 248156 kb
Host smart-a7d5a78b-781f-40a0-bc67-1b7d7f7dd1ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93125
7406 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_alert_accum.931257406
Directory /workspace/39.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/39.alert_handler_esc_intr_timeout.3032079862
Short name T557
Test name
Test status
Simulation time 182032483 ps
CPU time 16.55 seconds
Started Feb 25 03:21:57 PM PST 24
Finished Feb 25 03:22:14 PM PST 24
Peak memory 254000 kb
Host smart-1334b441-8326-4cf7-857a-bf9f7e76adf9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30320
79862 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_intr_timeout.3032079862
Directory /workspace/39.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_lpg.3748191951
Short name T308
Test name
Test status
Simulation time 30156259670 ps
CPU time 1664.11 seconds
Started Feb 25 03:22:00 PM PST 24
Finished Feb 25 03:49:44 PM PST 24
Peak memory 272476 kb
Host smart-73f3344d-87a1-4435-8a69-48dfa7a9051b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748191951 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg.3748191951
Directory /workspace/39.alert_handler_lpg/latest

Test location /workspace/coverage/default/39.alert_handler_lpg_stub_clk.2673254576
Short name T667
Test name
Test status
Simulation time 34228032517 ps
CPU time 689.74 seconds
Started Feb 25 03:22:02 PM PST 24
Finished Feb 25 03:33:32 PM PST 24
Peak memory 272620 kb
Host smart-8e7bcd5f-de44-44df-bb45-502b1451f99a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673254576 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg_stub_clk.2673254576
Directory /workspace/39.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/39.alert_handler_ping_timeout.69436184
Short name T301
Test name
Test status
Simulation time 36351629408 ps
CPU time 407.47 seconds
Started Feb 25 03:22:01 PM PST 24
Finished Feb 25 03:28:48 PM PST 24
Peak memory 247184 kb
Host smart-13ddef66-5f08-47c5-aa47-ab9fb56f6ecb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69436184 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_ping_timeout.69436184
Directory /workspace/39.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_random_alerts.3426601951
Short name T482
Test name
Test status
Simulation time 366064566 ps
CPU time 16.61 seconds
Started Feb 25 03:22:01 PM PST 24
Finished Feb 25 03:22:18 PM PST 24
Peak memory 256416 kb
Host smart-06059551-b3a4-4797-b43f-7548d7655609
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34266
01951 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_alerts.3426601951
Directory /workspace/39.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/39.alert_handler_random_classes.701566632
Short name T531
Test name
Test status
Simulation time 242542078 ps
CPU time 8.36 seconds
Started Feb 25 03:21:53 PM PST 24
Finished Feb 25 03:22:02 PM PST 24
Peak memory 248952 kb
Host smart-4f62e7a5-d58f-4783-8918-4e71775baf79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70156
6632 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_classes.701566632
Directory /workspace/39.alert_handler_random_classes/latest

Test location /workspace/coverage/default/39.alert_handler_sig_int_fail.2070489298
Short name T694
Test name
Test status
Simulation time 159213459 ps
CPU time 4.91 seconds
Started Feb 25 03:21:53 PM PST 24
Finished Feb 25 03:21:58 PM PST 24
Peak memory 248748 kb
Host smart-59135335-8ec1-4034-aa79-7596a083ea69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20704
89298 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_sig_int_fail.2070489298
Directory /workspace/39.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/39.alert_handler_smoke.2614189425
Short name T69
Test name
Test status
Simulation time 101959718 ps
CPU time 4.17 seconds
Started Feb 25 03:22:07 PM PST 24
Finished Feb 25 03:22:11 PM PST 24
Peak memory 248220 kb
Host smart-83dc40d1-c028-418e-b06f-f73abd9b9fec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26141
89425 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_smoke.2614189425
Directory /workspace/39.alert_handler_smoke/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all.2934787364
Short name T480
Test name
Test status
Simulation time 56889195494 ps
CPU time 248.97 seconds
Started Feb 25 03:21:58 PM PST 24
Finished Feb 25 03:26:07 PM PST 24
Peak memory 256416 kb
Host smart-30b15532-ab71-4e4a-8f65-39187e332149
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934787364 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_ha
ndler_stress_all.2934787364
Directory /workspace/39.alert_handler_stress_all/latest

Test location /workspace/coverage/default/4.alert_handler_alert_accum_saturation.615632507
Short name T203
Test name
Test status
Simulation time 13297753 ps
CPU time 2.44 seconds
Started Feb 25 03:20:28 PM PST 24
Finished Feb 25 03:20:31 PM PST 24
Peak memory 248516 kb
Host smart-271bdc83-8b36-41a9-bc19-c0a6ef440176
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=615632507 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_alert_accum_saturation.615632507
Directory /workspace/4.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/4.alert_handler_entropy.4265743785
Short name T495
Test name
Test status
Simulation time 67831145891 ps
CPU time 2272.12 seconds
Started Feb 25 03:20:14 PM PST 24
Finished Feb 25 03:58:07 PM PST 24
Peak memory 288720 kb
Host smart-17490918-d6d2-4d81-9f03-ae472628f400
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265743785 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy.4265743785
Directory /workspace/4.alert_handler_entropy/latest

Test location /workspace/coverage/default/4.alert_handler_entropy_stress.4205839768
Short name T456
Test name
Test status
Simulation time 16510591563 ps
CPU time 121.73 seconds
Started Feb 25 03:20:27 PM PST 24
Finished Feb 25 03:22:29 PM PST 24
Peak memory 248308 kb
Host smart-4b74c087-dee5-4f1c-bfdf-0c2d829a114a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4205839768 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy_stress.4205839768
Directory /workspace/4.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/4.alert_handler_esc_alert_accum.2203804613
Short name T434
Test name
Test status
Simulation time 5013442099 ps
CPU time 165.78 seconds
Started Feb 25 03:20:24 PM PST 24
Finished Feb 25 03:23:10 PM PST 24
Peak memory 256380 kb
Host smart-b4b79019-1882-4604-b254-14f361002bbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22038
04613 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_alert_accum.2203804613
Directory /workspace/4.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/4.alert_handler_esc_intr_timeout.3096490330
Short name T256
Test name
Test status
Simulation time 1428099691 ps
CPU time 53.74 seconds
Started Feb 25 03:20:10 PM PST 24
Finished Feb 25 03:21:04 PM PST 24
Peak memory 254660 kb
Host smart-2f235fa8-a8c8-439a-8b55-e643be1fd139
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30964
90330 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_intr_timeout.3096490330
Directory /workspace/4.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_lpg.3192019736
Short name T343
Test name
Test status
Simulation time 26028812439 ps
CPU time 1120.58 seconds
Started Feb 25 03:20:14 PM PST 24
Finished Feb 25 03:38:56 PM PST 24
Peak memory 281560 kb
Host smart-32884917-d0b7-4dd2-ae2f-70a491e54729
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192019736 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg.3192019736
Directory /workspace/4.alert_handler_lpg/latest

Test location /workspace/coverage/default/4.alert_handler_lpg_stub_clk.1014706622
Short name T534
Test name
Test status
Simulation time 29954121555 ps
CPU time 836.35 seconds
Started Feb 25 03:20:24 PM PST 24
Finished Feb 25 03:34:21 PM PST 24
Peak memory 272076 kb
Host smart-2a63489b-953c-408c-9b12-e87fa3580ec5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014706622 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg_stub_clk.1014706622
Directory /workspace/4.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/4.alert_handler_ping_timeout.1262154538
Short name T321
Test name
Test status
Simulation time 19129446078 ps
CPU time 390.58 seconds
Started Feb 25 03:20:10 PM PST 24
Finished Feb 25 03:26:42 PM PST 24
Peak memory 247192 kb
Host smart-215a989d-563c-4e68-816c-3b741298b9a8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262154538 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_ping_timeout.1262154538
Directory /workspace/4.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_random_alerts.805619577
Short name T381
Test name
Test status
Simulation time 292304850 ps
CPU time 9.24 seconds
Started Feb 25 03:20:14 PM PST 24
Finished Feb 25 03:20:25 PM PST 24
Peak memory 248252 kb
Host smart-f11b818d-c16f-411d-b5c4-ed38f319ddfe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80561
9577 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_alerts.805619577
Directory /workspace/4.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/4.alert_handler_random_classes.4109332659
Short name T666
Test name
Test status
Simulation time 552097075 ps
CPU time 37.66 seconds
Started Feb 25 03:20:13 PM PST 24
Finished Feb 25 03:20:52 PM PST 24
Peak memory 254512 kb
Host smart-0111c66f-8792-4caf-87a7-c6e2d55edc33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41093
32659 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_classes.4109332659
Directory /workspace/4.alert_handler_random_classes/latest

Test location /workspace/coverage/default/4.alert_handler_sec_cm.1066052857
Short name T33
Test name
Test status
Simulation time 853560049 ps
CPU time 33.99 seconds
Started Feb 25 03:20:29 PM PST 24
Finished Feb 25 03:21:03 PM PST 24
Peak memory 268280 kb
Host smart-3b6878cf-3a89-4664-9c34-e0bbdb049000
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1066052857 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sec_cm.1066052857
Directory /workspace/4.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/4.alert_handler_sig_int_fail.2475886012
Short name T498
Test name
Test status
Simulation time 1295083353 ps
CPU time 38.51 seconds
Started Feb 25 03:20:09 PM PST 24
Finished Feb 25 03:20:48 PM PST 24
Peak memory 255168 kb
Host smart-7f3e63ff-db63-4176-973d-a7ad49fabbac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24758
86012 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sig_int_fail.2475886012
Directory /workspace/4.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/4.alert_handler_smoke.1241935523
Short name T623
Test name
Test status
Simulation time 1744456156 ps
CPU time 19.93 seconds
Started Feb 25 03:20:11 PM PST 24
Finished Feb 25 03:20:32 PM PST 24
Peak memory 248224 kb
Host smart-e5a9bf3a-4a03-4e4e-b645-f9356fc36032
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12419
35523 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_smoke.1241935523
Directory /workspace/4.alert_handler_smoke/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all.207962798
Short name T363
Test name
Test status
Simulation time 858164184 ps
CPU time 40.28 seconds
Started Feb 25 03:20:10 PM PST 24
Finished Feb 25 03:20:52 PM PST 24
Peak memory 254600 kb
Host smart-669ca047-7717-45f5-9153-a2e12509a5f5
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207962798 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_hand
ler_stress_all.207962798
Directory /workspace/4.alert_handler_stress_all/latest

Test location /workspace/coverage/default/40.alert_handler_esc_alert_accum.501598155
Short name T443
Test name
Test status
Simulation time 466401620 ps
CPU time 29.23 seconds
Started Feb 25 03:22:01 PM PST 24
Finished Feb 25 03:22:30 PM PST 24
Peak memory 247756 kb
Host smart-1f06f278-581d-4a2c-8f29-e9cdc56aae5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50159
8155 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_alert_accum.501598155
Directory /workspace/40.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/40.alert_handler_esc_intr_timeout.3567047535
Short name T514
Test name
Test status
Simulation time 1001872302 ps
CPU time 20.98 seconds
Started Feb 25 03:22:02 PM PST 24
Finished Feb 25 03:22:23 PM PST 24
Peak memory 254324 kb
Host smart-baced5fb-c020-4a77-befb-b54c8688ae80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35670
47535 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_intr_timeout.3567047535
Directory /workspace/40.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_lpg.2753866727
Short name T4
Test name
Test status
Simulation time 9763263889 ps
CPU time 867.87 seconds
Started Feb 25 03:22:01 PM PST 24
Finished Feb 25 03:36:29 PM PST 24
Peak memory 264640 kb
Host smart-9bb96dbe-b358-486c-9192-eece53da66e6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753866727 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg.2753866727
Directory /workspace/40.alert_handler_lpg/latest

Test location /workspace/coverage/default/40.alert_handler_lpg_stub_clk.863148913
Short name T630
Test name
Test status
Simulation time 7852923945 ps
CPU time 880.24 seconds
Started Feb 25 03:22:03 PM PST 24
Finished Feb 25 03:36:43 PM PST 24
Peak memory 268760 kb
Host smart-435e92f8-2011-47dd-b358-0642c0f4b6a9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863148913 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg_stub_clk.863148913
Directory /workspace/40.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/40.alert_handler_ping_timeout.1149528331
Short name T691
Test name
Test status
Simulation time 7995176865 ps
CPU time 316.24 seconds
Started Feb 25 03:22:00 PM PST 24
Finished Feb 25 03:27:16 PM PST 24
Peak memory 246180 kb
Host smart-5586a072-d0b5-4aab-9ce8-59ccb57c96be
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149528331 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_ping_timeout.1149528331
Directory /workspace/40.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_random_alerts.435482731
Short name T458
Test name
Test status
Simulation time 5077534831 ps
CPU time 46.47 seconds
Started Feb 25 03:22:03 PM PST 24
Finished Feb 25 03:22:49 PM PST 24
Peak memory 255168 kb
Host smart-fccdda40-c460-465c-b63c-95ee97f1da11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43548
2731 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_alerts.435482731
Directory /workspace/40.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/40.alert_handler_random_classes.684081245
Short name T406
Test name
Test status
Simulation time 256031395 ps
CPU time 25.18 seconds
Started Feb 25 03:22:08 PM PST 24
Finished Feb 25 03:22:34 PM PST 24
Peak memory 246536 kb
Host smart-28c87a2b-a129-4874-84fd-a0d0e4f1c93c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68408
1245 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_classes.684081245
Directory /workspace/40.alert_handler_random_classes/latest

Test location /workspace/coverage/default/40.alert_handler_sig_int_fail.2719064292
Short name T112
Test name
Test status
Simulation time 242711509 ps
CPU time 31.48 seconds
Started Feb 25 03:22:02 PM PST 24
Finished Feb 25 03:22:33 PM PST 24
Peak memory 246568 kb
Host smart-830d7fc6-12fa-4bba-8f7e-0e8073c04162
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27190
64292 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_sig_int_fail.2719064292
Directory /workspace/40.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/40.alert_handler_smoke.483654508
Short name T104
Test name
Test status
Simulation time 235665961 ps
CPU time 22.65 seconds
Started Feb 25 03:22:03 PM PST 24
Finished Feb 25 03:22:26 PM PST 24
Peak memory 254972 kb
Host smart-6f832fa9-9626-469f-a735-e0c2cf087cf4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48365
4508 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_smoke.483654508
Directory /workspace/40.alert_handler_smoke/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all.763682513
Short name T485
Test name
Test status
Simulation time 8702281886 ps
CPU time 312.47 seconds
Started Feb 25 03:22:02 PM PST 24
Finished Feb 25 03:27:15 PM PST 24
Peak memory 256492 kb
Host smart-8ce20dd1-891f-4d27-ba59-8e938959efe1
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763682513 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_han
dler_stress_all.763682513
Directory /workspace/40.alert_handler_stress_all/latest

Test location /workspace/coverage/default/41.alert_handler_entropy.2723658303
Short name T665
Test name
Test status
Simulation time 60046808814 ps
CPU time 1263.65 seconds
Started Feb 25 03:22:03 PM PST 24
Finished Feb 25 03:43:07 PM PST 24
Peak memory 289272 kb
Host smart-5e4c7186-244e-4b1a-b1a8-3bde7a360f69
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723658303 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_entropy.2723658303
Directory /workspace/41.alert_handler_entropy/latest

Test location /workspace/coverage/default/41.alert_handler_esc_alert_accum.1135328184
Short name T429
Test name
Test status
Simulation time 11313871370 ps
CPU time 164.93 seconds
Started Feb 25 03:22:01 PM PST 24
Finished Feb 25 03:24:46 PM PST 24
Peak memory 256464 kb
Host smart-5a544e09-b854-4289-aa9c-afea7022c633
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11353
28184 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_alert_accum.1135328184
Directory /workspace/41.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/41.alert_handler_esc_intr_timeout.3366402779
Short name T391
Test name
Test status
Simulation time 227828323 ps
CPU time 15 seconds
Started Feb 25 03:22:03 PM PST 24
Finished Feb 25 03:22:18 PM PST 24
Peak memory 247880 kb
Host smart-2abaaee9-2895-4f81-8b49-c3ff9eee8e52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33664
02779 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_intr_timeout.3366402779
Directory /workspace/41.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_lpg.752002925
Short name T341
Test name
Test status
Simulation time 30580790964 ps
CPU time 1794.72 seconds
Started Feb 25 03:22:10 PM PST 24
Finished Feb 25 03:52:05 PM PST 24
Peak memory 281752 kb
Host smart-8db43105-c507-4abb-9de0-a128c4b4e92c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=752002925 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg.752002925
Directory /workspace/41.alert_handler_lpg/latest

Test location /workspace/coverage/default/41.alert_handler_lpg_stub_clk.3667194494
Short name T278
Test name
Test status
Simulation time 59462035620 ps
CPU time 1859.12 seconds
Started Feb 25 03:22:11 PM PST 24
Finished Feb 25 03:53:10 PM PST 24
Peak memory 272324 kb
Host smart-1675cb90-66a8-4671-b198-aba0806de79b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667194494 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg_stub_clk.3667194494
Directory /workspace/41.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/41.alert_handler_ping_timeout.50636141
Short name T311
Test name
Test status
Simulation time 10065111565 ps
CPU time 415.84 seconds
Started Feb 25 03:22:14 PM PST 24
Finished Feb 25 03:29:10 PM PST 24
Peak memory 247200 kb
Host smart-870043e9-a5d1-4030-ad13-85e458c83b08
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50636141 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_ping_timeout.50636141
Directory /workspace/41.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_random_alerts.2520550875
Short name T450
Test name
Test status
Simulation time 6665161500 ps
CPU time 45.4 seconds
Started Feb 25 03:22:04 PM PST 24
Finished Feb 25 03:22:50 PM PST 24
Peak memory 248300 kb
Host smart-6a76810b-a4c1-4892-ac27-bf6f737350e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25205
50875 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_alerts.2520550875
Directory /workspace/41.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/41.alert_handler_random_classes.3944975034
Short name T663
Test name
Test status
Simulation time 538995968 ps
CPU time 11.12 seconds
Started Feb 25 03:22:01 PM PST 24
Finished Feb 25 03:22:12 PM PST 24
Peak memory 250024 kb
Host smart-18028d1b-0c90-4d5c-b4ee-a370c3b2adb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39449
75034 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_classes.3944975034
Directory /workspace/41.alert_handler_random_classes/latest

Test location /workspace/coverage/default/41.alert_handler_sig_int_fail.2050776128
Short name T617
Test name
Test status
Simulation time 397597692 ps
CPU time 24.69 seconds
Started Feb 25 03:22:02 PM PST 24
Finished Feb 25 03:22:27 PM PST 24
Peak memory 253932 kb
Host smart-11f5665c-72db-44b2-bf84-19c3fae5d5c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20507
76128 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_sig_int_fail.2050776128
Directory /workspace/41.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/41.alert_handler_smoke.800617010
Short name T484
Test name
Test status
Simulation time 1219044647 ps
CPU time 35.88 seconds
Started Feb 25 03:22:08 PM PST 24
Finished Feb 25 03:22:45 PM PST 24
Peak memory 248212 kb
Host smart-27434a2d-2fab-47d2-8cd6-dcd5f269e138
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80061
7010 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_smoke.800617010
Directory /workspace/41.alert_handler_smoke/latest

Test location /workspace/coverage/default/42.alert_handler_entropy.3760629945
Short name T625
Test name
Test status
Simulation time 62030250696 ps
CPU time 1836.23 seconds
Started Feb 25 03:22:15 PM PST 24
Finished Feb 25 03:52:52 PM PST 24
Peak memory 266748 kb
Host smart-31aa88a5-9bcd-4351-886e-e9d88127b60e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3760629945 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_entropy.3760629945
Directory /workspace/42.alert_handler_entropy/latest

Test location /workspace/coverage/default/42.alert_handler_esc_alert_accum.397450409
Short name T395
Test name
Test status
Simulation time 10034008401 ps
CPU time 193.33 seconds
Started Feb 25 03:22:14 PM PST 24
Finished Feb 25 03:25:28 PM PST 24
Peak memory 255924 kb
Host smart-29cc0e0c-60d6-4642-accd-0c1daf1a1bee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39745
0409 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_alert_accum.397450409
Directory /workspace/42.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/42.alert_handler_esc_intr_timeout.113818091
Short name T664
Test name
Test status
Simulation time 30211236 ps
CPU time 4.75 seconds
Started Feb 25 03:22:06 PM PST 24
Finished Feb 25 03:22:11 PM PST 24
Peak memory 249764 kb
Host smart-21f47aaf-00ef-423f-ac25-59a4143274c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11381
8091 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_intr_timeout.113818091
Directory /workspace/42.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_lpg_stub_clk.2918861703
Short name T640
Test name
Test status
Simulation time 105328682866 ps
CPU time 1720.21 seconds
Started Feb 25 03:22:14 PM PST 24
Finished Feb 25 03:50:55 PM PST 24
Peak memory 281440 kb
Host smart-17e98179-4949-461c-b6aa-22cad4b25252
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918861703 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg_stub_clk.2918861703
Directory /workspace/42.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/42.alert_handler_ping_timeout.1461531449
Short name T9
Test name
Test status
Simulation time 25258913505 ps
CPU time 278.7 seconds
Started Feb 25 03:22:13 PM PST 24
Finished Feb 25 03:26:52 PM PST 24
Peak memory 246972 kb
Host smart-72bc2009-83c0-40b4-9b4d-48be11c81051
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461531449 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_ping_timeout.1461531449
Directory /workspace/42.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_random_alerts.2546206922
Short name T696
Test name
Test status
Simulation time 247765930 ps
CPU time 27.6 seconds
Started Feb 25 03:22:14 PM PST 24
Finished Feb 25 03:22:43 PM PST 24
Peak memory 248200 kb
Host smart-2571782c-8600-4002-bdba-8754baadcde8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25462
06922 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_alerts.2546206922
Directory /workspace/42.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/42.alert_handler_random_classes.4084976478
Short name T468
Test name
Test status
Simulation time 176988914 ps
CPU time 12.38 seconds
Started Feb 25 03:22:12 PM PST 24
Finished Feb 25 03:22:24 PM PST 24
Peak memory 246384 kb
Host smart-acf38344-b64f-4692-b1e2-a5ec7be1abb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40849
76478 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_classes.4084976478
Directory /workspace/42.alert_handler_random_classes/latest

Test location /workspace/coverage/default/42.alert_handler_sig_int_fail.941736810
Short name T80
Test name
Test status
Simulation time 272916745 ps
CPU time 23.43 seconds
Started Feb 25 03:22:13 PM PST 24
Finished Feb 25 03:22:37 PM PST 24
Peak memory 246888 kb
Host smart-47a7641c-0ba2-4a3e-8067-3317fc4908a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94173
6810 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_sig_int_fail.941736810
Directory /workspace/42.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/42.alert_handler_smoke.1535194486
Short name T359
Test name
Test status
Simulation time 383920348 ps
CPU time 24.84 seconds
Started Feb 25 03:22:11 PM PST 24
Finished Feb 25 03:22:36 PM PST 24
Peak memory 255064 kb
Host smart-ba121023-f3c0-445b-a5b0-e4d6062ff4ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15351
94486 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_smoke.1535194486
Directory /workspace/42.alert_handler_smoke/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all.1846556848
Short name T633
Test name
Test status
Simulation time 52542758914 ps
CPU time 1661.11 seconds
Started Feb 25 03:22:14 PM PST 24
Finished Feb 25 03:49:55 PM PST 24
Peak memory 288596 kb
Host smart-dcb608e7-47cc-4983-97ad-1cafebc2e444
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846556848 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_ha
ndler_stress_all.1846556848
Directory /workspace/42.alert_handler_stress_all/latest

Test location /workspace/coverage/default/43.alert_handler_entropy.4156767845
Short name T684
Test name
Test status
Simulation time 443037546515 ps
CPU time 2362.38 seconds
Started Feb 25 03:22:15 PM PST 24
Finished Feb 25 04:01:38 PM PST 24
Peak memory 288616 kb
Host smart-0a1aa906-2195-4dab-8a65-0d9fd99138bc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156767845 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_entropy.4156767845
Directory /workspace/43.alert_handler_entropy/latest

Test location /workspace/coverage/default/43.alert_handler_esc_alert_accum.1121443978
Short name T412
Test name
Test status
Simulation time 223526590 ps
CPU time 8.92 seconds
Started Feb 25 03:22:22 PM PST 24
Finished Feb 25 03:22:31 PM PST 24
Peak memory 239504 kb
Host smart-9c2b5616-300a-41a8-8632-a700315906b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11214
43978 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_alert_accum.1121443978
Directory /workspace/43.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/43.alert_handler_esc_intr_timeout.4015163268
Short name T356
Test name
Test status
Simulation time 165300778 ps
CPU time 11.47 seconds
Started Feb 25 03:22:07 PM PST 24
Finished Feb 25 03:22:19 PM PST 24
Peak memory 252824 kb
Host smart-6a009a42-7987-48ab-8295-f48d4ff51193
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40151
63268 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_intr_timeout.4015163268
Directory /workspace/43.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_lpg.1698758818
Short name T288
Test name
Test status
Simulation time 16193103791 ps
CPU time 678.49 seconds
Started Feb 25 03:22:17 PM PST 24
Finished Feb 25 03:33:36 PM PST 24
Peak memory 269928 kb
Host smart-2c636c97-71a9-4776-94e1-f78515a3ee9b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698758818 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg.1698758818
Directory /workspace/43.alert_handler_lpg/latest

Test location /workspace/coverage/default/43.alert_handler_lpg_stub_clk.4218308816
Short name T686
Test name
Test status
Simulation time 105262771512 ps
CPU time 1694.82 seconds
Started Feb 25 03:22:21 PM PST 24
Finished Feb 25 03:50:36 PM PST 24
Peak memory 272252 kb
Host smart-d9a75c2c-67a8-4bec-9cf4-ffe45c62147b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218308816 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg_stub_clk.4218308816
Directory /workspace/43.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/43.alert_handler_ping_timeout.480633382
Short name T631
Test name
Test status
Simulation time 32181104256 ps
CPU time 303.37 seconds
Started Feb 25 03:22:22 PM PST 24
Finished Feb 25 03:27:25 PM PST 24
Peak memory 247028 kb
Host smart-38016ccf-8e0d-4883-8689-6b64ae6f9fc7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480633382 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_ping_timeout.480633382
Directory /workspace/43.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_random_alerts.1013043829
Short name T515
Test name
Test status
Simulation time 136086730 ps
CPU time 17.02 seconds
Started Feb 25 03:22:10 PM PST 24
Finished Feb 25 03:22:27 PM PST 24
Peak memory 255096 kb
Host smart-c9daaf72-9831-4d9b-8357-cb7334d3d1e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10130
43829 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_alerts.1013043829
Directory /workspace/43.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/43.alert_handler_random_classes.154446286
Short name T513
Test name
Test status
Simulation time 369074801 ps
CPU time 18.5 seconds
Started Feb 25 03:22:15 PM PST 24
Finished Feb 25 03:22:34 PM PST 24
Peak memory 254852 kb
Host smart-da0f4943-68bf-4324-82d4-6f444ebb700f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15444
6286 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_classes.154446286
Directory /workspace/43.alert_handler_random_classes/latest

Test location /workspace/coverage/default/43.alert_handler_sig_int_fail.3852685891
Short name T421
Test name
Test status
Simulation time 713178961 ps
CPU time 12.01 seconds
Started Feb 25 03:22:21 PM PST 24
Finished Feb 25 03:22:33 PM PST 24
Peak memory 246348 kb
Host smart-1382455b-607b-4f4d-b507-c8b417c32e24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38526
85891 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_sig_int_fail.3852685891
Directory /workspace/43.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/43.alert_handler_smoke.155807857
Short name T572
Test name
Test status
Simulation time 862085194 ps
CPU time 33.7 seconds
Started Feb 25 03:22:14 PM PST 24
Finished Feb 25 03:22:48 PM PST 24
Peak memory 248232 kb
Host smart-aed6495d-41bb-4234-ba8a-a01f8266370a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15580
7857 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_smoke.155807857
Directory /workspace/43.alert_handler_smoke/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all.61299907
Short name T619
Test name
Test status
Simulation time 132759287928 ps
CPU time 2189.95 seconds
Started Feb 25 03:22:20 PM PST 24
Finished Feb 25 03:58:50 PM PST 24
Peak memory 285044 kb
Host smart-61f82474-4c86-4041-b982-84fcf60696ad
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61299907 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_hand
ler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_hand
ler_stress_all.61299907
Directory /workspace/43.alert_handler_stress_all/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all_with_rand_reset.1452391218
Short name T60
Test name
Test status
Simulation time 358720633611 ps
CPU time 4981.55 seconds
Started Feb 25 03:22:13 PM PST 24
Finished Feb 25 04:45:15 PM PST 24
Peak memory 297616 kb
Host smart-18a02c07-c76f-44a6-8b37-b3113fbb304d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452391218 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 43.alert_handler_stress_all_with_rand_reset.1452391218
Directory /workspace/43.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.alert_handler_entropy.1064237782
Short name T618
Test name
Test status
Simulation time 40167569124 ps
CPU time 2327.61 seconds
Started Feb 25 03:22:21 PM PST 24
Finished Feb 25 04:01:10 PM PST 24
Peak memory 281092 kb
Host smart-e04540c3-8123-4be9-885a-e5ede905b7f1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064237782 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_entropy.1064237782
Directory /workspace/44.alert_handler_entropy/latest

Test location /workspace/coverage/default/44.alert_handler_esc_alert_accum.1890971005
Short name T585
Test name
Test status
Simulation time 19139406765 ps
CPU time 250.45 seconds
Started Feb 25 03:22:20 PM PST 24
Finished Feb 25 03:26:31 PM PST 24
Peak memory 256496 kb
Host smart-a59516ac-4d3c-4d34-b944-9d088b3e0b56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18909
71005 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_alert_accum.1890971005
Directory /workspace/44.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/44.alert_handler_esc_intr_timeout.3872119169
Short name T432
Test name
Test status
Simulation time 524254793 ps
CPU time 23.02 seconds
Started Feb 25 03:22:17 PM PST 24
Finished Feb 25 03:22:40 PM PST 24
Peak memory 253408 kb
Host smart-4c511ba1-0bbf-448d-b86f-9f8d4795bcb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38721
19169 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_intr_timeout.3872119169
Directory /workspace/44.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_lpg.1479584396
Short name T668
Test name
Test status
Simulation time 18812046024 ps
CPU time 1514.32 seconds
Started Feb 25 03:22:17 PM PST 24
Finished Feb 25 03:47:32 PM PST 24
Peak memory 288240 kb
Host smart-1fc3231c-b938-4a6f-bb8d-6ceb1690876d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479584396 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg.1479584396
Directory /workspace/44.alert_handler_lpg/latest

Test location /workspace/coverage/default/44.alert_handler_lpg_stub_clk.2598729385
Short name T37
Test name
Test status
Simulation time 17995594331 ps
CPU time 750.86 seconds
Started Feb 25 03:22:25 PM PST 24
Finished Feb 25 03:34:57 PM PST 24
Peak memory 264696 kb
Host smart-d21d7014-52f5-4801-85dd-014cf23a5d29
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598729385 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg_stub_clk.2598729385
Directory /workspace/44.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/44.alert_handler_ping_timeout.399663708
Short name T297
Test name
Test status
Simulation time 84521900112 ps
CPU time 357.83 seconds
Started Feb 25 03:22:22 PM PST 24
Finished Feb 25 03:28:20 PM PST 24
Peak memory 246772 kb
Host smart-f498f310-910d-4509-b79c-45b074e13e5f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399663708 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_ping_timeout.399663708
Directory /workspace/44.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_random_alerts.2963603190
Short name T504
Test name
Test status
Simulation time 31316657 ps
CPU time 4.76 seconds
Started Feb 25 03:22:16 PM PST 24
Finished Feb 25 03:22:21 PM PST 24
Peak memory 247424 kb
Host smart-d8d0a771-382b-4e7b-a1b6-8d754293cadb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29636
03190 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_alerts.2963603190
Directory /workspace/44.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/44.alert_handler_random_classes.1685762535
Short name T467
Test name
Test status
Simulation time 833713218 ps
CPU time 33.41 seconds
Started Feb 25 03:22:16 PM PST 24
Finished Feb 25 03:22:49 PM PST 24
Peak memory 245908 kb
Host smart-4f7cad2c-1a1f-4a72-b0a0-1563a878be4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16857
62535 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_classes.1685762535
Directory /workspace/44.alert_handler_random_classes/latest

Test location /workspace/coverage/default/44.alert_handler_sig_int_fail.1712384790
Short name T246
Test name
Test status
Simulation time 259203232 ps
CPU time 35.19 seconds
Started Feb 25 03:22:18 PM PST 24
Finished Feb 25 03:22:53 PM PST 24
Peak memory 254380 kb
Host smart-1d46ec26-cae4-447a-a508-6c56f8599de4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17123
84790 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_sig_int_fail.1712384790
Directory /workspace/44.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/44.alert_handler_smoke.2767241197
Short name T669
Test name
Test status
Simulation time 342386094 ps
CPU time 28.71 seconds
Started Feb 25 03:22:13 PM PST 24
Finished Feb 25 03:22:42 PM PST 24
Peak memory 256416 kb
Host smart-be24e354-c79e-4f8a-80f6-00152622ed42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27672
41197 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_smoke.2767241197
Directory /workspace/44.alert_handler_smoke/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all.535381899
Short name T605
Test name
Test status
Simulation time 10797036861 ps
CPU time 1216.87 seconds
Started Feb 25 03:22:23 PM PST 24
Finished Feb 25 03:42:41 PM PST 24
Peak memory 286780 kb
Host smart-05167730-5f6a-46b0-bc9c-e5d13fff3526
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535381899 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_han
dler_stress_all.535381899
Directory /workspace/44.alert_handler_stress_all/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all_with_rand_reset.2660779526
Short name T624
Test name
Test status
Simulation time 124085537269 ps
CPU time 10771.3 seconds
Started Feb 25 03:22:27 PM PST 24
Finished Feb 25 06:22:00 PM PST 24
Peak memory 394500 kb
Host smart-14e3b1e0-95c5-456c-9ef1-3a20cbfa2f97
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660779526 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 44.alert_handler_stress_all_with_rand_reset.2660779526
Directory /workspace/44.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.alert_handler_esc_alert_accum.2809449189
Short name T639
Test name
Test status
Simulation time 268479373 ps
CPU time 20.66 seconds
Started Feb 25 03:22:23 PM PST 24
Finished Feb 25 03:22:44 PM PST 24
Peak memory 247888 kb
Host smart-ac388ca0-3627-4774-b3c9-e9f62614c79f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28094
49189 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_alert_accum.2809449189
Directory /workspace/45.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/45.alert_handler_esc_intr_timeout.420222540
Short name T592
Test name
Test status
Simulation time 1010218131 ps
CPU time 46.94 seconds
Started Feb 25 03:22:23 PM PST 24
Finished Feb 25 03:23:10 PM PST 24
Peak memory 254684 kb
Host smart-e67e43c6-02b4-4ae6-98b3-31056d519d56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42022
2540 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_intr_timeout.420222540
Directory /workspace/45.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_lpg.2339058816
Short name T325
Test name
Test status
Simulation time 24257530729 ps
CPU time 1210.71 seconds
Started Feb 25 03:22:24 PM PST 24
Finished Feb 25 03:42:35 PM PST 24
Peak memory 288876 kb
Host smart-b59a25af-8ebc-40f2-b253-4e573e73fc0f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339058816 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg.2339058816
Directory /workspace/45.alert_handler_lpg/latest

Test location /workspace/coverage/default/45.alert_handler_lpg_stub_clk.3870819371
Short name T594
Test name
Test status
Simulation time 187154328425 ps
CPU time 2767.99 seconds
Started Feb 25 03:22:24 PM PST 24
Finished Feb 25 04:08:32 PM PST 24
Peak memory 285060 kb
Host smart-dc084927-cfe2-488a-8495-598674dab2d4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870819371 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg_stub_clk.3870819371
Directory /workspace/45.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/45.alert_handler_ping_timeout.315201871
Short name T637
Test name
Test status
Simulation time 37729202159 ps
CPU time 377.62 seconds
Started Feb 25 03:22:28 PM PST 24
Finished Feb 25 03:28:46 PM PST 24
Peak memory 247136 kb
Host smart-909c24b9-04c8-4c43-a446-ad975a326407
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315201871 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_ping_timeout.315201871
Directory /workspace/45.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_random_alerts.482083122
Short name T379
Test name
Test status
Simulation time 37980969 ps
CPU time 5.33 seconds
Started Feb 25 03:22:28 PM PST 24
Finished Feb 25 03:22:34 PM PST 24
Peak memory 248228 kb
Host smart-8b8af5fc-d3b9-4b02-a664-7df04f6cbfbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48208
3122 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_alerts.482083122
Directory /workspace/45.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/45.alert_handler_random_classes.817417254
Short name T101
Test name
Test status
Simulation time 4375009896 ps
CPU time 77.96 seconds
Started Feb 25 03:22:31 PM PST 24
Finished Feb 25 03:23:49 PM PST 24
Peak memory 254612 kb
Host smart-588c8601-9c6f-44b0-868c-b42f88d25974
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81741
7254 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_classes.817417254
Directory /workspace/45.alert_handler_random_classes/latest

Test location /workspace/coverage/default/45.alert_handler_sig_int_fail.2832871493
Short name T254
Test name
Test status
Simulation time 288114114 ps
CPU time 40.37 seconds
Started Feb 25 03:22:28 PM PST 24
Finished Feb 25 03:23:09 PM PST 24
Peak memory 246648 kb
Host smart-d4509afa-3ba7-4403-96a8-bdc62d0fbc3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28328
71493 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_sig_int_fail.2832871493
Directory /workspace/45.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/45.alert_handler_smoke.501385946
Short name T409
Test name
Test status
Simulation time 145504762 ps
CPU time 10.27 seconds
Started Feb 25 03:22:28 PM PST 24
Finished Feb 25 03:22:39 PM PST 24
Peak memory 248172 kb
Host smart-ec433328-40ac-4958-b701-46ebcc3bda01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50138
5946 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_smoke.501385946
Directory /workspace/45.alert_handler_smoke/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all.2865215143
Short name T270
Test name
Test status
Simulation time 99646146931 ps
CPU time 1415.33 seconds
Started Feb 25 03:22:26 PM PST 24
Finished Feb 25 03:46:02 PM PST 24
Peak memory 289068 kb
Host smart-f964d634-e1d8-4cf1-9fdd-eefe4cbbbe53
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865215143 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_ha
ndler_stress_all.2865215143
Directory /workspace/45.alert_handler_stress_all/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all_with_rand_reset.1783077500
Short name T188
Test name
Test status
Simulation time 355650978506 ps
CPU time 6157.28 seconds
Started Feb 25 03:22:24 PM PST 24
Finished Feb 25 05:05:02 PM PST 24
Peak memory 371272 kb
Host smart-8c3631a9-33c1-410f-810e-3fe0b1711234
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783077500 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 45.alert_handler_stress_all_with_rand_reset.1783077500
Directory /workspace/45.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.alert_handler_entropy.2232128354
Short name T396
Test name
Test status
Simulation time 33128385652 ps
CPU time 1906.28 seconds
Started Feb 25 03:22:30 PM PST 24
Finished Feb 25 03:54:17 PM PST 24
Peak memory 271912 kb
Host smart-57066551-db6c-4a9a-b7f7-caa6471c7907
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232128354 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_entropy.2232128354
Directory /workspace/46.alert_handler_entropy/latest

Test location /workspace/coverage/default/46.alert_handler_esc_alert_accum.1956552880
Short name T280
Test name
Test status
Simulation time 1427623623 ps
CPU time 89.88 seconds
Started Feb 25 03:22:32 PM PST 24
Finished Feb 25 03:24:02 PM PST 24
Peak memory 255812 kb
Host smart-3c436856-3a7d-4b30-9888-f9e8605d57c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19565
52880 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_alert_accum.1956552880
Directory /workspace/46.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/46.alert_handler_esc_intr_timeout.2291614233
Short name T452
Test name
Test status
Simulation time 716439046 ps
CPU time 40.17 seconds
Started Feb 25 03:22:27 PM PST 24
Finished Feb 25 03:23:08 PM PST 24
Peak memory 247848 kb
Host smart-5475db98-413d-44e5-922f-bc04c68836a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22916
14233 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_intr_timeout.2291614233
Directory /workspace/46.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_lpg.2449256763
Short name T271
Test name
Test status
Simulation time 34840831702 ps
CPU time 1762.53 seconds
Started Feb 25 03:22:30 PM PST 24
Finished Feb 25 03:51:53 PM PST 24
Peak memory 271616 kb
Host smart-321cd669-1d68-466b-babb-cd564efad160
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449256763 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg.2449256763
Directory /workspace/46.alert_handler_lpg/latest

Test location /workspace/coverage/default/46.alert_handler_lpg_stub_clk.3731030721
Short name T716
Test name
Test status
Simulation time 7092202958 ps
CPU time 607.34 seconds
Started Feb 25 03:22:31 PM PST 24
Finished Feb 25 03:32:39 PM PST 24
Peak memory 264356 kb
Host smart-f7127f58-8e74-4107-82e7-7aad8c72eaf8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731030721 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg_stub_clk.3731030721
Directory /workspace/46.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/46.alert_handler_ping_timeout.2116326771
Short name T304
Test name
Test status
Simulation time 57064491115 ps
CPU time 388.88 seconds
Started Feb 25 03:22:34 PM PST 24
Finished Feb 25 03:29:04 PM PST 24
Peak memory 246964 kb
Host smart-961872b0-2db3-4136-bde7-fe626bd16e90
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116326771 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_ping_timeout.2116326771
Directory /workspace/46.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_random_alerts.634366402
Short name T486
Test name
Test status
Simulation time 2189052693 ps
CPU time 40.56 seconds
Started Feb 25 03:22:26 PM PST 24
Finished Feb 25 03:23:07 PM PST 24
Peak memory 254820 kb
Host smart-e17e994a-628d-4881-808b-11e37e4dea32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63436
6402 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_alerts.634366402
Directory /workspace/46.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/46.alert_handler_random_classes.3342801374
Short name T34
Test name
Test status
Simulation time 1563506804 ps
CPU time 21.51 seconds
Started Feb 25 03:22:25 PM PST 24
Finished Feb 25 03:22:47 PM PST 24
Peak memory 253876 kb
Host smart-f113ac97-56ef-41fd-8569-216db46c538b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33428
01374 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_classes.3342801374
Directory /workspace/46.alert_handler_random_classes/latest

Test location /workspace/coverage/default/46.alert_handler_sig_int_fail.4289349799
Short name T247
Test name
Test status
Simulation time 2282654035 ps
CPU time 40.07 seconds
Started Feb 25 03:22:31 PM PST 24
Finished Feb 25 03:23:12 PM PST 24
Peak memory 254804 kb
Host smart-49496d99-38ee-4e79-9c68-abd00d3ccee9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42893
49799 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_sig_int_fail.4289349799
Directory /workspace/46.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/46.alert_handler_smoke.667699547
Short name T70
Test name
Test status
Simulation time 889484389 ps
CPU time 51.88 seconds
Started Feb 25 03:22:26 PM PST 24
Finished Feb 25 03:23:18 PM PST 24
Peak memory 254996 kb
Host smart-59d97661-ec2c-4b14-8cde-82575ea617ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66769
9547 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_smoke.667699547
Directory /workspace/46.alert_handler_smoke/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all.1064964722
Short name T282
Test name
Test status
Simulation time 90561515313 ps
CPU time 1784.32 seconds
Started Feb 25 03:22:31 PM PST 24
Finished Feb 25 03:52:15 PM PST 24
Peak memory 283460 kb
Host smart-91dc396a-1ea9-4861-8f57-9974100cc30b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064964722 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_ha
ndler_stress_all.1064964722
Directory /workspace/46.alert_handler_stress_all/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all_with_rand_reset.156326689
Short name T613
Test name
Test status
Simulation time 155384181664 ps
CPU time 3499.66 seconds
Started Feb 25 03:22:32 PM PST 24
Finished Feb 25 04:20:52 PM PST 24
Peak memory 321536 kb
Host smart-666283f1-8080-4103-b217-cea5d39e7882
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156326689 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 46.alert_handler_stress_all_with_rand_reset.156326689
Directory /workspace/46.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.alert_handler_entropy.2824635726
Short name T95
Test name
Test status
Simulation time 76651564463 ps
CPU time 2226.58 seconds
Started Feb 25 03:22:46 PM PST 24
Finished Feb 25 03:59:54 PM PST 24
Peak memory 282380 kb
Host smart-825e12a4-23cd-4d3d-ab9c-60c67da97a50
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824635726 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_entropy.2824635726
Directory /workspace/47.alert_handler_entropy/latest

Test location /workspace/coverage/default/47.alert_handler_esc_alert_accum.1819992590
Short name T45
Test name
Test status
Simulation time 831958332 ps
CPU time 48.63 seconds
Started Feb 25 03:22:44 PM PST 24
Finished Feb 25 03:23:33 PM PST 24
Peak memory 255844 kb
Host smart-f8f1f785-e84f-4876-9a8b-bc373485129e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18199
92590 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_alert_accum.1819992590
Directory /workspace/47.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/47.alert_handler_esc_intr_timeout.2203523156
Short name T255
Test name
Test status
Simulation time 4731866789 ps
CPU time 70.42 seconds
Started Feb 25 03:22:34 PM PST 24
Finished Feb 25 03:23:45 PM PST 24
Peak memory 254760 kb
Host smart-8c732950-48ad-4433-b402-0f67df19358d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22035
23156 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_intr_timeout.2203523156
Directory /workspace/47.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_lpg.2226200553
Short name T670
Test name
Test status
Simulation time 22929807436 ps
CPU time 1537.78 seconds
Started Feb 25 03:22:47 PM PST 24
Finished Feb 25 03:48:26 PM PST 24
Peak memory 281080 kb
Host smart-abe138d1-9aae-4d89-9993-8c39537ab8e2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226200553 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg.2226200553
Directory /workspace/47.alert_handler_lpg/latest

Test location /workspace/coverage/default/47.alert_handler_lpg_stub_clk.3875231485
Short name T645
Test name
Test status
Simulation time 41154811628 ps
CPU time 2441.87 seconds
Started Feb 25 03:22:46 PM PST 24
Finished Feb 25 04:03:29 PM PST 24
Peak memory 288544 kb
Host smart-404a4485-b576-4e1f-aaa7-dad50782f55a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875231485 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg_stub_clk.3875231485
Directory /workspace/47.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/47.alert_handler_ping_timeout.3181686327
Short name T548
Test name
Test status
Simulation time 8693106487 ps
CPU time 96.73 seconds
Started Feb 25 03:22:45 PM PST 24
Finished Feb 25 03:24:23 PM PST 24
Peak memory 247096 kb
Host smart-b2045784-903e-4704-8bc2-22ab659d6636
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181686327 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_ping_timeout.3181686327
Directory /workspace/47.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_random_alerts.1842059693
Short name T364
Test name
Test status
Simulation time 653583195 ps
CPU time 36.97 seconds
Started Feb 25 03:22:33 PM PST 24
Finished Feb 25 03:23:10 PM PST 24
Peak memory 255112 kb
Host smart-973d0751-b26d-4287-b25b-47af51c9c0a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18420
59693 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_alerts.1842059693
Directory /workspace/47.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/47.alert_handler_random_classes.913928660
Short name T439
Test name
Test status
Simulation time 115594317 ps
CPU time 7.96 seconds
Started Feb 25 03:22:30 PM PST 24
Finished Feb 25 03:22:38 PM PST 24
Peak memory 249692 kb
Host smart-9e7dda41-6515-4d62-bfd3-ac0ed69862cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91392
8660 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_classes.913928660
Directory /workspace/47.alert_handler_random_classes/latest

Test location /workspace/coverage/default/47.alert_handler_sig_int_fail.2666785163
Short name T383
Test name
Test status
Simulation time 3498542155 ps
CPU time 38.18 seconds
Started Feb 25 03:22:44 PM PST 24
Finished Feb 25 03:23:24 PM PST 24
Peak memory 255592 kb
Host smart-598c2ca3-9ace-402c-82bb-a6e37dc6b430
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26667
85163 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_sig_int_fail.2666785163
Directory /workspace/47.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/47.alert_handler_smoke.1052233378
Short name T385
Test name
Test status
Simulation time 1266078214 ps
CPU time 27.09 seconds
Started Feb 25 03:22:32 PM PST 24
Finished Feb 25 03:22:59 PM PST 24
Peak memory 248224 kb
Host smart-3afb7030-5c6a-43e5-90cb-052a8e866863
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10522
33378 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_smoke.1052233378
Directory /workspace/47.alert_handler_smoke/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all_with_rand_reset.1618918318
Short name T705
Test name
Test status
Simulation time 154617558536 ps
CPU time 2587.32 seconds
Started Feb 25 03:22:46 PM PST 24
Finished Feb 25 04:05:54 PM PST 24
Peak memory 289056 kb
Host smart-c91433be-e122-4262-85d2-6c2909e39d13
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618918318 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 47.alert_handler_stress_all_with_rand_reset.1618918318
Directory /workspace/47.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.alert_handler_entropy.1698999674
Short name T682
Test name
Test status
Simulation time 55018175575 ps
CPU time 3166.21 seconds
Started Feb 25 03:22:50 PM PST 24
Finished Feb 25 04:15:37 PM PST 24
Peak memory 289140 kb
Host smart-664a90dd-356d-445e-9a7b-b62e3a5d6f12
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698999674 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_entropy.1698999674
Directory /workspace/48.alert_handler_entropy/latest

Test location /workspace/coverage/default/48.alert_handler_esc_alert_accum.2897797211
Short name T462
Test name
Test status
Simulation time 6440764336 ps
CPU time 43.96 seconds
Started Feb 25 03:22:44 PM PST 24
Finished Feb 25 03:23:29 PM PST 24
Peak memory 255000 kb
Host smart-cb89b9bb-501d-4241-9442-d134925fd08f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28977
97211 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_alert_accum.2897797211
Directory /workspace/48.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/48.alert_handler_esc_intr_timeout.1233347926
Short name T692
Test name
Test status
Simulation time 713537708 ps
CPU time 59.17 seconds
Started Feb 25 03:22:43 PM PST 24
Finished Feb 25 03:23:43 PM PST 24
Peak memory 254580 kb
Host smart-a0e7b50b-4516-42a3-9d58-eed9fad5e132
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12333
47926 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_intr_timeout.1233347926
Directory /workspace/48.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_lpg.2325612421
Short name T337
Test name
Test status
Simulation time 70051113391 ps
CPU time 2110.45 seconds
Started Feb 25 03:22:44 PM PST 24
Finished Feb 25 03:57:55 PM PST 24
Peak memory 272328 kb
Host smart-f4642b34-b8d9-406b-896e-3755c06c5afa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325612421 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg.2325612421
Directory /workspace/48.alert_handler_lpg/latest

Test location /workspace/coverage/default/48.alert_handler_lpg_stub_clk.3125299483
Short name T499
Test name
Test status
Simulation time 26543920686 ps
CPU time 1202.97 seconds
Started Feb 25 03:22:46 PM PST 24
Finished Feb 25 03:42:50 PM PST 24
Peak memory 281088 kb
Host smart-118c6420-6f44-4920-a6d1-69ce6d8a86c6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125299483 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg_stub_clk.3125299483
Directory /workspace/48.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/48.alert_handler_ping_timeout.1269995727
Short name T299
Test name
Test status
Simulation time 43313369106 ps
CPU time 454.4 seconds
Started Feb 25 03:22:45 PM PST 24
Finished Feb 25 03:30:20 PM PST 24
Peak memory 247184 kb
Host smart-513d2111-26fc-44c0-ae47-33dc8d82ef29
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269995727 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_ping_timeout.1269995727
Directory /workspace/48.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_random_alerts.1865953524
Short name T56
Test name
Test status
Simulation time 142623543 ps
CPU time 9.6 seconds
Started Feb 25 03:22:50 PM PST 24
Finished Feb 25 03:23:00 PM PST 24
Peak memory 248244 kb
Host smart-082f6187-782d-4332-9595-c021813eb766
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18659
53524 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_alerts.1865953524
Directory /workspace/48.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/48.alert_handler_random_classes.3877384505
Short name T362
Test name
Test status
Simulation time 629845374 ps
CPU time 26.94 seconds
Started Feb 25 03:22:44 PM PST 24
Finished Feb 25 03:23:12 PM PST 24
Peak memory 253520 kb
Host smart-354a9c62-ccdf-4346-aae7-7ce4a28531c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38773
84505 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_classes.3877384505
Directory /workspace/48.alert_handler_random_classes/latest

Test location /workspace/coverage/default/48.alert_handler_sig_int_fail.3892324115
Short name T268
Test name
Test status
Simulation time 156207126 ps
CPU time 23.42 seconds
Started Feb 25 03:22:43 PM PST 24
Finished Feb 25 03:23:08 PM PST 24
Peak memory 246564 kb
Host smart-97679196-603f-4988-bc5b-08e31caeeda3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38923
24115 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_sig_int_fail.3892324115
Directory /workspace/48.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/48.alert_handler_smoke.2421644085
Short name T263
Test name
Test status
Simulation time 585558440 ps
CPU time 41.28 seconds
Started Feb 25 03:22:45 PM PST 24
Finished Feb 25 03:23:27 PM PST 24
Peak memory 254808 kb
Host smart-33c2173f-66a9-459d-bc59-6d3b43867c1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24216
44085 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_smoke.2421644085
Directory /workspace/48.alert_handler_smoke/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all.2273245268
Short name T681
Test name
Test status
Simulation time 53214661358 ps
CPU time 2949.2 seconds
Started Feb 25 03:22:44 PM PST 24
Finished Feb 25 04:11:54 PM PST 24
Peak memory 288920 kb
Host smart-2ac6bde8-d7af-4090-8b4a-293e0cc62118
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273245268 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_ha
ndler_stress_all.2273245268
Directory /workspace/48.alert_handler_stress_all/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all_with_rand_reset.2533427947
Short name T242
Test name
Test status
Simulation time 323392847675 ps
CPU time 6436.66 seconds
Started Feb 25 03:22:47 PM PST 24
Finished Feb 25 05:10:05 PM PST 24
Peak memory 354000 kb
Host smart-8fba3a76-e053-4d4f-a468-d5788bd5e090
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533427947 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 48.alert_handler_stress_all_with_rand_reset.2533427947
Directory /workspace/48.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.alert_handler_entropy.3406892929
Short name T636
Test name
Test status
Simulation time 56932047306 ps
CPU time 1530.72 seconds
Started Feb 25 03:22:56 PM PST 24
Finished Feb 25 03:48:27 PM PST 24
Peak memory 272816 kb
Host smart-a2355669-9044-4a61-8edc-12767643acec
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406892929 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_entropy.3406892929
Directory /workspace/49.alert_handler_entropy/latest

Test location /workspace/coverage/default/49.alert_handler_esc_alert_accum.2624883249
Short name T602
Test name
Test status
Simulation time 4705248558 ps
CPU time 248.44 seconds
Started Feb 25 03:22:56 PM PST 24
Finished Feb 25 03:27:05 PM PST 24
Peak memory 254776 kb
Host smart-51c867de-b320-4b39-b7a0-424dd52e01ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26248
83249 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_alert_accum.2624883249
Directory /workspace/49.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/49.alert_handler_esc_intr_timeout.2307610859
Short name T512
Test name
Test status
Simulation time 401362918 ps
CPU time 13.46 seconds
Started Feb 25 03:22:57 PM PST 24
Finished Feb 25 03:23:10 PM PST 24
Peak memory 254020 kb
Host smart-8073c469-58c7-40c5-a0a8-5781627f9d99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23076
10859 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_intr_timeout.2307610859
Directory /workspace/49.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_lpg_stub_clk.2522299684
Short name T121
Test name
Test status
Simulation time 57598557182 ps
CPU time 999.29 seconds
Started Feb 25 03:22:57 PM PST 24
Finished Feb 25 03:39:36 PM PST 24
Peak memory 272252 kb
Host smart-6cae3206-8be0-48e0-a1e4-ff62c8a1806c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522299684 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg_stub_clk.2522299684
Directory /workspace/49.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/49.alert_handler_ping_timeout.586576752
Short name T563
Test name
Test status
Simulation time 57475105795 ps
CPU time 598.06 seconds
Started Feb 25 03:22:53 PM PST 24
Finished Feb 25 03:32:51 PM PST 24
Peak memory 247232 kb
Host smart-67f94aba-ff69-455e-9d66-266d492b1f84
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=586576752 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_ping_timeout.586576752
Directory /workspace/49.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_random_alerts.3849146081
Short name T354
Test name
Test status
Simulation time 1281462092 ps
CPU time 45.7 seconds
Started Feb 25 03:22:55 PM PST 24
Finished Feb 25 03:23:41 PM PST 24
Peak memory 248224 kb
Host smart-db06f799-1831-4b25-bbb1-0c277f80174a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38491
46081 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_alerts.3849146081
Directory /workspace/49.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/49.alert_handler_random_classes.3023866226
Short name T74
Test name
Test status
Simulation time 5234438863 ps
CPU time 69.47 seconds
Started Feb 25 03:22:58 PM PST 24
Finished Feb 25 03:24:08 PM PST 24
Peak memory 254884 kb
Host smart-32bc4ea6-2e5a-4668-9492-6aeb87416e2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30238
66226 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_classes.3023866226
Directory /workspace/49.alert_handler_random_classes/latest

Test location /workspace/coverage/default/49.alert_handler_sig_int_fail.3811357368
Short name T465
Test name
Test status
Simulation time 59135624 ps
CPU time 9.54 seconds
Started Feb 25 03:22:56 PM PST 24
Finished Feb 25 03:23:06 PM PST 24
Peak memory 253376 kb
Host smart-306c45cb-c4c4-477b-9ce5-716411d74815
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38113
57368 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_sig_int_fail.3811357368
Directory /workspace/49.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/49.alert_handler_smoke.1152090771
Short name T419
Test name
Test status
Simulation time 393008348 ps
CPU time 38.51 seconds
Started Feb 25 03:22:59 PM PST 24
Finished Feb 25 03:23:38 PM PST 24
Peak memory 255100 kb
Host smart-7c0b428b-f265-442f-b38e-fd543a39fd6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11520
90771 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_smoke.1152090771
Directory /workspace/49.alert_handler_smoke/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all.3721208120
Short name T614
Test name
Test status
Simulation time 60343895375 ps
CPU time 1842.97 seconds
Started Feb 25 03:23:03 PM PST 24
Finished Feb 25 03:53:47 PM PST 24
Peak memory 272880 kb
Host smart-d9aa896c-4f24-498f-9563-d262e4ca833b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721208120 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_ha
ndler_stress_all.3721208120
Directory /workspace/49.alert_handler_stress_all/latest

Test location /workspace/coverage/default/5.alert_handler_alert_accum_saturation.255982619
Short name T213
Test name
Test status
Simulation time 142962279 ps
CPU time 3.57 seconds
Started Feb 25 03:20:24 PM PST 24
Finished Feb 25 03:20:28 PM PST 24
Peak memory 248516 kb
Host smart-425e9fef-29f8-4b10-9cba-c134bf74dfc2
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=255982619 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_alert_accum_saturation.255982619
Directory /workspace/5.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/5.alert_handler_entropy.3967803608
Short name T502
Test name
Test status
Simulation time 109628369538 ps
CPU time 1859.15 seconds
Started Feb 25 03:20:21 PM PST 24
Finished Feb 25 03:51:21 PM PST 24
Peak memory 284904 kb
Host smart-9a69e97b-7e03-4c90-8443-50c815112af1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967803608 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy.3967803608
Directory /workspace/5.alert_handler_entropy/latest

Test location /workspace/coverage/default/5.alert_handler_entropy_stress.2323969095
Short name T433
Test name
Test status
Simulation time 531319422 ps
CPU time 14.12 seconds
Started Feb 25 03:20:26 PM PST 24
Finished Feb 25 03:20:40 PM PST 24
Peak memory 252032 kb
Host smart-fa5924bb-ca19-45b9-b006-c7122c55077c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2323969095 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy_stress.2323969095
Directory /workspace/5.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/5.alert_handler_esc_alert_accum.441365215
Short name T550
Test name
Test status
Simulation time 1512342411 ps
CPU time 48.99 seconds
Started Feb 25 03:20:19 PM PST 24
Finished Feb 25 03:21:08 PM PST 24
Peak memory 255608 kb
Host smart-83a68da2-02f2-41a8-ab17-be71f65b8739
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44136
5215 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_alert_accum.441365215
Directory /workspace/5.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/5.alert_handler_esc_intr_timeout.4143088110
Short name T47
Test name
Test status
Simulation time 972286303 ps
CPU time 49.78 seconds
Started Feb 25 03:20:29 PM PST 24
Finished Feb 25 03:21:18 PM PST 24
Peak memory 253920 kb
Host smart-81444e66-7e58-4d48-899e-8b95d403633d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41430
88110 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_intr_timeout.4143088110
Directory /workspace/5.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_lpg.1720895710
Short name T597
Test name
Test status
Simulation time 34108712542 ps
CPU time 736.43 seconds
Started Feb 25 03:20:34 PM PST 24
Finished Feb 25 03:32:51 PM PST 24
Peak memory 264688 kb
Host smart-3ca6ebbb-ab69-436d-ae89-5306eb11e8c3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1720895710 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg.1720895710
Directory /workspace/5.alert_handler_lpg/latest

Test location /workspace/coverage/default/5.alert_handler_lpg_stub_clk.171192540
Short name T697
Test name
Test status
Simulation time 129583985725 ps
CPU time 2070.97 seconds
Started Feb 25 03:20:21 PM PST 24
Finished Feb 25 03:54:52 PM PST 24
Peak memory 268048 kb
Host smart-5f5801ba-7a9b-4ec5-af9d-4ca27aecea02
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171192540 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg_stub_clk.171192540
Directory /workspace/5.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/5.alert_handler_random_alerts.2158650791
Short name T424
Test name
Test status
Simulation time 72390111 ps
CPU time 4.6 seconds
Started Feb 25 03:20:29 PM PST 24
Finished Feb 25 03:20:34 PM PST 24
Peak memory 240040 kb
Host smart-58ae821a-eece-4dcf-a919-e07163e4e176
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21586
50791 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_alerts.2158650791
Directory /workspace/5.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/5.alert_handler_random_classes.2136153991
Short name T436
Test name
Test status
Simulation time 1344650620 ps
CPU time 26.49 seconds
Started Feb 25 03:20:34 PM PST 24
Finished Feb 25 03:21:01 PM PST 24
Peak memory 246612 kb
Host smart-ec279342-7770-49e0-8c82-75bc9e5691fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21361
53991 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_classes.2136153991
Directory /workspace/5.alert_handler_random_classes/latest

Test location /workspace/coverage/default/5.alert_handler_sig_int_fail.3455181594
Short name T253
Test name
Test status
Simulation time 1493630580 ps
CPU time 54.25 seconds
Started Feb 25 03:20:23 PM PST 24
Finished Feb 25 03:21:18 PM PST 24
Peak memory 254504 kb
Host smart-6f76b9f6-699c-4de2-94ec-7ff26cc61756
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34551
81594 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_sig_int_fail.3455181594
Directory /workspace/5.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/5.alert_handler_smoke.1047764564
Short name T552
Test name
Test status
Simulation time 1190290744 ps
CPU time 15.37 seconds
Started Feb 25 03:20:14 PM PST 24
Finished Feb 25 03:20:31 PM PST 24
Peak memory 248212 kb
Host smart-b0c2b4b8-e164-43f8-93d9-65180bf4b604
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10477
64564 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_smoke.1047764564
Directory /workspace/5.alert_handler_smoke/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all.3893153887
Short name T41
Test name
Test status
Simulation time 67182063408 ps
CPU time 1447.73 seconds
Started Feb 25 03:20:23 PM PST 24
Finished Feb 25 03:44:31 PM PST 24
Peak memory 288824 kb
Host smart-a0dcdcc2-17b9-4a6e-9bcc-39eeddb856f1
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893153887 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_han
dler_stress_all.3893153887
Directory /workspace/5.alert_handler_stress_all/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all_with_rand_reset.769273774
Short name T229
Test name
Test status
Simulation time 589615485010 ps
CPU time 8149.05 seconds
Started Feb 25 03:20:16 PM PST 24
Finished Feb 25 05:36:06 PM PST 24
Peak memory 333860 kb
Host smart-f4a58d78-d1f5-48ca-8ffb-3692075d03d6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769273774 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 5.alert_handler_stress_all_with_rand_reset.769273774
Directory /workspace/5.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.alert_handler_alert_accum_saturation.1324673701
Short name T64
Test name
Test status
Simulation time 20406342 ps
CPU time 2.46 seconds
Started Feb 25 03:20:24 PM PST 24
Finished Feb 25 03:20:27 PM PST 24
Peak memory 248520 kb
Host smart-230c13da-1132-4d6c-8b39-1092c58c4c9d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1324673701 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_alert_accum_saturation.1324673701
Directory /workspace/6.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/6.alert_handler_entropy.232983581
Short name T493
Test name
Test status
Simulation time 86380953392 ps
CPU time 1007.56 seconds
Started Feb 25 03:20:22 PM PST 24
Finished Feb 25 03:37:10 PM PST 24
Peak memory 272656 kb
Host smart-0313789c-b9f6-4b6c-abde-6e5f0d7e9065
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=232983581 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy.232983581
Directory /workspace/6.alert_handler_entropy/latest

Test location /workspace/coverage/default/6.alert_handler_entropy_stress.1153372646
Short name T695
Test name
Test status
Simulation time 777079880 ps
CPU time 34.47 seconds
Started Feb 25 03:20:30 PM PST 24
Finished Feb 25 03:21:05 PM PST 24
Peak memory 240028 kb
Host smart-856d5596-38d1-4302-bfb0-5b63cf898152
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1153372646 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy_stress.1153372646
Directory /workspace/6.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/6.alert_handler_esc_alert_accum.1670102119
Short name T510
Test name
Test status
Simulation time 1452153228 ps
CPU time 90.94 seconds
Started Feb 25 03:20:23 PM PST 24
Finished Feb 25 03:21:54 PM PST 24
Peak memory 255524 kb
Host smart-2c59d558-b99f-4e64-b520-297d67875b16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16701
02119 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_alert_accum.1670102119
Directory /workspace/6.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/6.alert_handler_esc_intr_timeout.2908227842
Short name T687
Test name
Test status
Simulation time 1058344132 ps
CPU time 20.83 seconds
Started Feb 25 03:20:29 PM PST 24
Finished Feb 25 03:20:50 PM PST 24
Peak memory 247880 kb
Host smart-d6d551dc-d756-4917-896c-e46126983b04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29082
27842 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_intr_timeout.2908227842
Directory /workspace/6.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_lpg_stub_clk.805801270
Short name T483
Test name
Test status
Simulation time 934097466314 ps
CPU time 2975.81 seconds
Started Feb 25 03:20:16 PM PST 24
Finished Feb 25 04:09:53 PM PST 24
Peak memory 288404 kb
Host smart-26d55b50-4079-4129-a6ac-147a7a6595e2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805801270 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg_stub_clk.805801270
Directory /workspace/6.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/6.alert_handler_ping_timeout.3830712916
Short name T296
Test name
Test status
Simulation time 50380012640 ps
CPU time 468.45 seconds
Started Feb 25 03:20:21 PM PST 24
Finished Feb 25 03:28:10 PM PST 24
Peak memory 247052 kb
Host smart-92c92d33-d55c-43fc-b879-c17b152a5d03
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830712916 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_ping_timeout.3830712916
Directory /workspace/6.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_random_alerts.2909714934
Short name T382
Test name
Test status
Simulation time 268519215 ps
CPU time 24.26 seconds
Started Feb 25 03:20:16 PM PST 24
Finished Feb 25 03:20:41 PM PST 24
Peak memory 256404 kb
Host smart-c201fab7-8af0-43aa-aaa9-9ffa7755390b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29097
14934 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_alerts.2909714934
Directory /workspace/6.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/6.alert_handler_random_classes.1603967307
Short name T554
Test name
Test status
Simulation time 1743289929 ps
CPU time 59.85 seconds
Started Feb 25 03:20:28 PM PST 24
Finished Feb 25 03:21:28 PM PST 24
Peak memory 255128 kb
Host smart-410dea62-7c5f-49e6-a452-0b22e36742c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16039
67307 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_classes.1603967307
Directory /workspace/6.alert_handler_random_classes/latest

Test location /workspace/coverage/default/6.alert_handler_sig_int_fail.256785941
Short name T252
Test name
Test status
Simulation time 3116052463 ps
CPU time 29.77 seconds
Started Feb 25 03:20:30 PM PST 24
Finished Feb 25 03:21:00 PM PST 24
Peak memory 246428 kb
Host smart-6d4968d0-d5d0-4c36-9730-d88a9ef8c3c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25678
5941 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_sig_int_fail.256785941
Directory /workspace/6.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/6.alert_handler_smoke.777378681
Short name T576
Test name
Test status
Simulation time 1751598928 ps
CPU time 48.94 seconds
Started Feb 25 03:20:27 PM PST 24
Finished Feb 25 03:21:16 PM PST 24
Peak memory 248240 kb
Host smart-16856b42-d887-489b-ae9a-c52960f9266d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77737
8681 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_smoke.777378681
Directory /workspace/6.alert_handler_smoke/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all.436141928
Short name T671
Test name
Test status
Simulation time 121656639625 ps
CPU time 1794.48 seconds
Started Feb 25 03:20:32 PM PST 24
Finished Feb 25 03:50:26 PM PST 24
Peak memory 272284 kb
Host smart-aed99bcc-aac0-494d-ba93-bf9f0b47ceb4
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436141928 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_hand
ler_stress_all.436141928
Directory /workspace/6.alert_handler_stress_all/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all_with_rand_reset.2532454798
Short name T627
Test name
Test status
Simulation time 113031040587 ps
CPU time 3313.77 seconds
Started Feb 25 03:20:23 PM PST 24
Finished Feb 25 04:15:37 PM PST 24
Peak memory 280712 kb
Host smart-f7886c26-15fd-4bdc-88c0-5ae2d25daf3a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532454798 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 6.alert_handler_stress_all_with_rand_reset.2532454798
Directory /workspace/6.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.alert_handler_alert_accum_saturation.2168571763
Short name T214
Test name
Test status
Simulation time 293825669 ps
CPU time 3.74 seconds
Started Feb 25 03:20:31 PM PST 24
Finished Feb 25 03:20:35 PM PST 24
Peak memory 248536 kb
Host smart-b439df03-be71-4fcf-94c2-d9e632c17341
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2168571763 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_alert_accum_saturation.2168571763
Directory /workspace/7.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/7.alert_handler_entropy.2541261620
Short name T525
Test name
Test status
Simulation time 44572226875 ps
CPU time 2640.62 seconds
Started Feb 25 03:20:22 PM PST 24
Finished Feb 25 04:04:23 PM PST 24
Peak memory 288876 kb
Host smart-d022e2ec-fe14-4f53-95b3-bd6aa196bc4d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541261620 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy.2541261620
Directory /workspace/7.alert_handler_entropy/latest

Test location /workspace/coverage/default/7.alert_handler_entropy_stress.865648099
Short name T454
Test name
Test status
Simulation time 2686036501 ps
CPU time 12.83 seconds
Started Feb 25 03:20:29 PM PST 24
Finished Feb 25 03:20:42 PM PST 24
Peak memory 252192 kb
Host smart-376fbfe0-42d3-4f7b-a5b0-9627922830da
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=865648099 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy_stress.865648099
Directory /workspace/7.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/7.alert_handler_esc_alert_accum.4178305622
Short name T675
Test name
Test status
Simulation time 6921044487 ps
CPU time 222.29 seconds
Started Feb 25 03:20:35 PM PST 24
Finished Feb 25 03:24:17 PM PST 24
Peak memory 255820 kb
Host smart-5e4c8000-24ac-43f2-8677-cee10037d1d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41783
05622 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_alert_accum.4178305622
Directory /workspace/7.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/7.alert_handler_esc_intr_timeout.2199221043
Short name T372
Test name
Test status
Simulation time 1138217747 ps
CPU time 63.81 seconds
Started Feb 25 03:20:31 PM PST 24
Finished Feb 25 03:21:35 PM PST 24
Peak memory 254084 kb
Host smart-d5cec83f-c7f5-4f8f-8e22-008a4951e63e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21992
21043 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_intr_timeout.2199221043
Directory /workspace/7.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_lpg.619328866
Short name T39
Test name
Test status
Simulation time 53458461688 ps
CPU time 1373.08 seconds
Started Feb 25 03:20:31 PM PST 24
Finished Feb 25 03:43:24 PM PST 24
Peak memory 288712 kb
Host smart-94cb5f04-1b5a-469d-a229-504445649aac
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=619328866 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg.619328866
Directory /workspace/7.alert_handler_lpg/latest

Test location /workspace/coverage/default/7.alert_handler_lpg_stub_clk.3114817328
Short name T404
Test name
Test status
Simulation time 105082261413 ps
CPU time 1344.3 seconds
Started Feb 25 03:20:30 PM PST 24
Finished Feb 25 03:42:55 PM PST 24
Peak memory 264288 kb
Host smart-48187092-cd3a-4f79-9165-7fbc7bc04843
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3114817328 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg_stub_clk.3114817328
Directory /workspace/7.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/7.alert_handler_ping_timeout.2573454898
Short name T67
Test name
Test status
Simulation time 15936477905 ps
CPU time 339.41 seconds
Started Feb 25 03:20:27 PM PST 24
Finished Feb 25 03:26:07 PM PST 24
Peak memory 246960 kb
Host smart-3df10b4c-dbbd-4d3f-8972-1572120fd275
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573454898 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_ping_timeout.2573454898
Directory /workspace/7.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_random_alerts.858091139
Short name T598
Test name
Test status
Simulation time 320956011 ps
CPU time 27.32 seconds
Started Feb 25 03:20:35 PM PST 24
Finished Feb 25 03:21:02 PM PST 24
Peak memory 255032 kb
Host smart-4fe27cfc-6a64-4086-85e9-2ef1a7b240eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85809
1139 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_alerts.858091139
Directory /workspace/7.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/7.alert_handler_random_classes.4149728396
Short name T655
Test name
Test status
Simulation time 2759924706 ps
CPU time 45.9 seconds
Started Feb 25 03:20:30 PM PST 24
Finished Feb 25 03:21:16 PM PST 24
Peak memory 254928 kb
Host smart-361a1edf-5ff8-49c5-822a-1606b4a3cffd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41497
28396 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_classes.4149728396
Directory /workspace/7.alert_handler_random_classes/latest

Test location /workspace/coverage/default/7.alert_handler_sig_int_fail.2784979477
Short name T679
Test name
Test status
Simulation time 1360297744 ps
CPU time 24.03 seconds
Started Feb 25 03:20:34 PM PST 24
Finished Feb 25 03:20:58 PM PST 24
Peak memory 254980 kb
Host smart-21f858f8-5ba9-4727-a00c-d59424702cf5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27849
79477 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_sig_int_fail.2784979477
Directory /workspace/7.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/7.alert_handler_smoke.3035503086
Short name T488
Test name
Test status
Simulation time 383740529 ps
CPU time 8.16 seconds
Started Feb 25 03:20:26 PM PST 24
Finished Feb 25 03:20:35 PM PST 24
Peak memory 240248 kb
Host smart-28a180f9-8a1b-451c-ad0a-636bbd9a12fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30355
03086 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_smoke.3035503086
Directory /workspace/7.alert_handler_smoke/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all.2410100909
Short name T218
Test name
Test status
Simulation time 37898329824 ps
CPU time 1483.53 seconds
Started Feb 25 03:20:31 PM PST 24
Finished Feb 25 03:45:14 PM PST 24
Peak memory 288980 kb
Host smart-91e79abf-8125-48d1-90bd-10f0e0d0cac4
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410100909 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_han
dler_stress_all.2410100909
Directory /workspace/7.alert_handler_stress_all/latest

Test location /workspace/coverage/default/8.alert_handler_alert_accum_saturation.3484702988
Short name T209
Test name
Test status
Simulation time 50592926 ps
CPU time 4.29 seconds
Started Feb 25 03:20:29 PM PST 24
Finished Feb 25 03:20:34 PM PST 24
Peak memory 248516 kb
Host smart-936e36ad-c1ef-43c9-846e-dd6a261daf27
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3484702988 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_alert_accum_saturation.3484702988
Directory /workspace/8.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/8.alert_handler_entropy.3827132383
Short name T88
Test name
Test status
Simulation time 64075196715 ps
CPU time 1362.26 seconds
Started Feb 25 03:20:22 PM PST 24
Finished Feb 25 03:43:05 PM PST 24
Peak memory 289052 kb
Host smart-a90be90a-fb71-46c4-be78-ddf87c928548
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3827132383 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy.3827132383
Directory /workspace/8.alert_handler_entropy/latest

Test location /workspace/coverage/default/8.alert_handler_entropy_stress.4115124582
Short name T407
Test name
Test status
Simulation time 484853698 ps
CPU time 7.91 seconds
Started Feb 25 03:20:21 PM PST 24
Finished Feb 25 03:20:29 PM PST 24
Peak memory 240020 kb
Host smart-d44f368f-4c4e-405c-b259-61979b9e69c6
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4115124582 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy_stress.4115124582
Directory /workspace/8.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/8.alert_handler_esc_alert_accum.3860674149
Short name T438
Test name
Test status
Simulation time 2134007937 ps
CPU time 97.18 seconds
Started Feb 25 03:20:28 PM PST 24
Finished Feb 25 03:22:05 PM PST 24
Peak memory 255720 kb
Host smart-cc66b5b9-c58c-496e-a473-47ad8f236828
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38606
74149 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_alert_accum.3860674149
Directory /workspace/8.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/8.alert_handler_esc_intr_timeout.3752515997
Short name T237
Test name
Test status
Simulation time 705205108 ps
CPU time 32.36 seconds
Started Feb 25 03:20:28 PM PST 24
Finished Feb 25 03:21:01 PM PST 24
Peak memory 253720 kb
Host smart-e85aef12-65c0-4f68-917a-192d5614d581
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37525
15997 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_intr_timeout.3752515997
Directory /workspace/8.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_lpg_stub_clk.2962271231
Short name T352
Test name
Test status
Simulation time 29716559495 ps
CPU time 1625.57 seconds
Started Feb 25 03:20:31 PM PST 24
Finished Feb 25 03:47:37 PM PST 24
Peak memory 272748 kb
Host smart-965f09c4-0828-4da7-9666-0023eced6c81
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962271231 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg_stub_clk.2962271231
Directory /workspace/8.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/8.alert_handler_ping_timeout.363719488
Short name T103
Test name
Test status
Simulation time 19623846866 ps
CPU time 203.37 seconds
Started Feb 25 03:20:28 PM PST 24
Finished Feb 25 03:23:51 PM PST 24
Peak memory 246176 kb
Host smart-f507fb2d-c8ee-4706-83f8-98c3cc80352a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363719488 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_ping_timeout.363719488
Directory /workspace/8.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_random_alerts.2908929524
Short name T55
Test name
Test status
Simulation time 838767684 ps
CPU time 55.57 seconds
Started Feb 25 03:20:29 PM PST 24
Finished Feb 25 03:21:25 PM PST 24
Peak memory 248236 kb
Host smart-c1f1f878-d7a7-420b-aaaf-6814fcefb6fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29089
29524 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_alerts.2908929524
Directory /workspace/8.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/8.alert_handler_random_classes.3332666255
Short name T373
Test name
Test status
Simulation time 640461870 ps
CPU time 14.15 seconds
Started Feb 25 03:20:29 PM PST 24
Finished Feb 25 03:20:43 PM PST 24
Peak memory 252132 kb
Host smart-e5290901-a65d-4ac0-a1fd-0c53c8c5cc08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33326
66255 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_classes.3332666255
Directory /workspace/8.alert_handler_random_classes/latest

Test location /workspace/coverage/default/8.alert_handler_sig_int_fail.3091103625
Short name T643
Test name
Test status
Simulation time 119082099 ps
CPU time 14.34 seconds
Started Feb 25 03:20:33 PM PST 24
Finished Feb 25 03:20:47 PM PST 24
Peak memory 248240 kb
Host smart-f575af48-4f6a-413a-a996-9a470696bd54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30911
03625 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_sig_int_fail.3091103625
Directory /workspace/8.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/8.alert_handler_smoke.3194616357
Short name T650
Test name
Test status
Simulation time 1460660321 ps
CPU time 21.58 seconds
Started Feb 25 03:20:30 PM PST 24
Finished Feb 25 03:20:51 PM PST 24
Peak memory 248192 kb
Host smart-cd4fc02e-d658-4587-a4fb-36561df0f95a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31946
16357 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_smoke.3194616357
Directory /workspace/8.alert_handler_smoke/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all_with_rand_reset.2654913955
Short name T228
Test name
Test status
Simulation time 132367794391 ps
CPU time 1233.76 seconds
Started Feb 25 03:20:30 PM PST 24
Finished Feb 25 03:41:04 PM PST 24
Peak memory 281184 kb
Host smart-5ffb0998-0d55-4251-a9be-f38a0c65e889
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654913955 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 8.alert_handler_stress_all_with_rand_reset.2654913955
Directory /workspace/8.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.alert_handler_alert_accum_saturation.3363633615
Short name T206
Test name
Test status
Simulation time 33278001 ps
CPU time 2.6 seconds
Started Feb 25 03:20:25 PM PST 24
Finished Feb 25 03:20:28 PM PST 24
Peak memory 248516 kb
Host smart-f82b6264-e497-4f66-a824-1616b2c1e70c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3363633615 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_alert_accum_saturation.3363633615
Directory /workspace/9.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/9.alert_handler_entropy.4264020907
Short name T543
Test name
Test status
Simulation time 100468031707 ps
CPU time 2229.3 seconds
Started Feb 25 03:20:24 PM PST 24
Finished Feb 25 03:57:33 PM PST 24
Peak memory 282596 kb
Host smart-519e1338-ef1e-4f74-bc62-d0f363e1dc93
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264020907 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy.4264020907
Directory /workspace/9.alert_handler_entropy/latest

Test location /workspace/coverage/default/9.alert_handler_entropy_stress.3665339821
Short name T708
Test name
Test status
Simulation time 926620912 ps
CPU time 38.47 seconds
Started Feb 25 03:20:36 PM PST 24
Finished Feb 25 03:21:14 PM PST 24
Peak memory 240036 kb
Host smart-1f5178b0-9786-4d73-a7ea-02a7a46140e5
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3665339821 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy_stress.3665339821
Directory /workspace/9.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/9.alert_handler_esc_alert_accum.3173341287
Short name T370
Test name
Test status
Simulation time 4935596756 ps
CPU time 267.77 seconds
Started Feb 25 03:20:28 PM PST 24
Finished Feb 25 03:24:56 PM PST 24
Peak memory 255820 kb
Host smart-70d103f8-1cb2-4518-9ee7-5e166fd8fc78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31733
41287 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_alert_accum.3173341287
Directory /workspace/9.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/9.alert_handler_esc_intr_timeout.1857890180
Short name T76
Test name
Test status
Simulation time 736095908 ps
CPU time 17.17 seconds
Started Feb 25 03:20:26 PM PST 24
Finished Feb 25 03:20:43 PM PST 24
Peak memory 254920 kb
Host smart-e270a9f1-633c-41e3-8579-791c33783dbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18578
90180 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_intr_timeout.1857890180
Directory /workspace/9.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_lpg.4064959558
Short name T333
Test name
Test status
Simulation time 43261720730 ps
CPU time 1090.13 seconds
Started Feb 25 03:20:27 PM PST 24
Finished Feb 25 03:38:38 PM PST 24
Peak memory 280936 kb
Host smart-62f95ef6-733c-46e5-aa8a-0691ecfc543b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064959558 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg.4064959558
Directory /workspace/9.alert_handler_lpg/latest

Test location /workspace/coverage/default/9.alert_handler_lpg_stub_clk.1639130727
Short name T654
Test name
Test status
Simulation time 34588177096 ps
CPU time 987.49 seconds
Started Feb 25 03:20:27 PM PST 24
Finished Feb 25 03:36:55 PM PST 24
Peak memory 288404 kb
Host smart-39716f10-2fdb-4ed0-975b-bd449c6e77a9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639130727 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg_stub_clk.1639130727
Directory /workspace/9.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/9.alert_handler_ping_timeout.3460724769
Short name T312
Test name
Test status
Simulation time 68925232908 ps
CPU time 764.3 seconds
Started Feb 25 03:20:22 PM PST 24
Finished Feb 25 03:33:06 PM PST 24
Peak memory 247084 kb
Host smart-2da5dc55-616f-48dd-bcd9-15e6aa2f2742
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460724769 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_ping_timeout.3460724769
Directory /workspace/9.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_random_alerts.1925359521
Short name T360
Test name
Test status
Simulation time 397868018 ps
CPU time 20.99 seconds
Started Feb 25 03:20:30 PM PST 24
Finished Feb 25 03:20:51 PM PST 24
Peak memory 248480 kb
Host smart-f9c16c14-50e6-47bf-a468-1b509eb03238
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19253
59521 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_alerts.1925359521
Directory /workspace/9.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/9.alert_handler_random_classes.1607138739
Short name T471
Test name
Test status
Simulation time 1693077831 ps
CPU time 28.16 seconds
Started Feb 25 03:20:30 PM PST 24
Finished Feb 25 03:20:58 PM PST 24
Peak memory 254024 kb
Host smart-e5c544ad-8d1b-4b64-94f8-4fb0bbd25787
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16071
38739 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_classes.1607138739
Directory /workspace/9.alert_handler_random_classes/latest

Test location /workspace/coverage/default/9.alert_handler_sig_int_fail.2649378010
Short name T375
Test name
Test status
Simulation time 829413658 ps
CPU time 26.65 seconds
Started Feb 25 03:20:28 PM PST 24
Finished Feb 25 03:20:55 PM PST 24
Peak memory 255064 kb
Host smart-946eb465-04ca-43a5-bd57-2cfc2121afc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26493
78010 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_sig_int_fail.2649378010
Directory /workspace/9.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/9.alert_handler_smoke.1732053636
Short name T78
Test name
Test status
Simulation time 311133222 ps
CPU time 21.65 seconds
Started Feb 25 03:20:22 PM PST 24
Finished Feb 25 03:20:43 PM PST 24
Peak memory 256388 kb
Host smart-291cae2f-3a3e-45e5-9024-65117b2a393e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17320
53636 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_smoke.1732053636
Directory /workspace/9.alert_handler_smoke/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all.2584647667
Short name T240
Test name
Test status
Simulation time 24304086234 ps
CPU time 935.17 seconds
Started Feb 25 03:20:28 PM PST 24
Finished Feb 25 03:36:03 PM PST 24
Peak memory 281428 kb
Host smart-15495c2e-509f-4886-89fd-16cf6ca79f8a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584647667 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_han
dler_stress_all.2584647667
Directory /workspace/9.alert_handler_stress_all/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all_with_rand_reset.4022582201
Short name T494
Test name
Test status
Simulation time 24594125523 ps
CPU time 1715.92 seconds
Started Feb 25 03:20:23 PM PST 24
Finished Feb 25 03:48:59 PM PST 24
Peak memory 281172 kb
Host smart-1eac7c53-7522-4d9e-9f5d-1092a2e82f3a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022582201 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 9.alert_handler_stress_all_with_rand_reset.4022582201
Directory /workspace/9.alert_handler_stress_all_with_rand_reset/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%